clang  3.9.0
CodeGen/TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "TargetInfo.h"
16 #include "ABIInfo.h"
17 #include "CGCXXABI.h"
18 #include "CGValue.h"
19 #include "CodeGenFunction.h"
20 #include "clang/AST/RecordLayout.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <algorithm> // std::sort
30 
31 using namespace clang;
32 using namespace CodeGen;
33 
35  llvm::Value *Array,
37  unsigned FirstIndex,
38  unsigned LastIndex) {
39  // Alternatively, we could emit this as a loop in the source.
40  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
41  llvm::Value *Cell =
42  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
43  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
44  }
45 }
46 
50 }
51 
53 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
54  llvm::Type *Padding) const {
55  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
56  ByRef, Realign, Padding);
57 }
58 
61  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
62  /*ByRef*/ false, Realign);
63 }
64 
66  QualType Ty) const {
67  return Address::invalid();
68 }
69 
71 
72 /// Does the given lowering require more than the given number of
73 /// registers when expanded?
74 ///
75 /// This is intended to be the basis of a reasonable basic implementation
76 /// of should{Pass,Return}IndirectlyForSwift.
77 ///
78 /// For most targets, a limit of four total registers is reasonable; this
79 /// limits the amount of code required in order to move around the value
80 /// in case it wasn't produced immediately prior to the call by the caller
81 /// (or wasn't produced in exactly the right registers) or isn't used
82 /// immediately within the callee. But some targets may need to further
83 /// limit the register count due to an inability to support that many
84 /// return registers.
85 static bool occupiesMoreThan(CodeGenTypes &cgt,
86  ArrayRef<llvm::Type*> scalarTypes,
87  unsigned maxAllRegisters) {
88  unsigned intCount = 0, fpCount = 0;
89  for (llvm::Type *type : scalarTypes) {
90  if (type->isPointerTy()) {
91  intCount++;
92  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
93  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
94  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
95  } else {
96  assert(type->isVectorTy() || type->isFloatingPointTy());
97  fpCount++;
98  }
99  }
100 
101  return (intCount + fpCount > maxAllRegisters);
102 }
103 
105  llvm::Type *eltTy,
106  unsigned numElts) const {
107  // The default implementation of this assumes that the target guarantees
108  // 128-bit SIMD support but nothing more.
109  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
110 }
111 
113  CGCXXABI &CXXABI) {
114  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
115  if (!RD)
116  return CGCXXABI::RAA_Default;
117  return CXXABI.getRecordArgABI(RD);
118 }
119 
121  CGCXXABI &CXXABI) {
122  const RecordType *RT = T->getAs<RecordType>();
123  if (!RT)
124  return CGCXXABI::RAA_Default;
125  return getRecordArgABI(RT, CXXABI);
126 }
127 
128 /// Pass transparent unions as if they were the type of the first element. Sema
129 /// should ensure that all elements of the union have the same "machine type".
131  if (const RecordType *UT = Ty->getAsUnionType()) {
132  const RecordDecl *UD = UT->getDecl();
133  if (UD->hasAttr<TransparentUnionAttr>()) {
134  assert(!UD->field_empty() && "sema created an empty transparent union");
135  return UD->field_begin()->getType();
136  }
137  }
138  return Ty;
139 }
140 
142  return CGT.getCXXABI();
143 }
144 
146  return CGT.getContext();
147 }
148 
149 llvm::LLVMContext &ABIInfo::getVMContext() const {
150  return CGT.getLLVMContext();
151 }
152 
153 const llvm::DataLayout &ABIInfo::getDataLayout() const {
154  return CGT.getDataLayout();
155 }
156 
158  return CGT.getTarget();
159 }
160 
161 bool ABIInfo:: isAndroid() const { return getTarget().getTriple().isAndroid(); }
162 
164  return false;
165 }
166 
168  uint64_t Members) const {
169  return false;
170 }
171 
173  return false;
174 }
175 
176 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
177  raw_ostream &OS = llvm::errs();
178  OS << "(ABIArgInfo Kind=";
179  switch (TheKind) {
180  case Direct:
181  OS << "Direct Type=";
182  if (llvm::Type *Ty = getCoerceToType())
183  Ty->print(OS);
184  else
185  OS << "null";
186  break;
187  case Extend:
188  OS << "Extend";
189  break;
190  case Ignore:
191  OS << "Ignore";
192  break;
193  case InAlloca:
194  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
195  break;
196  case Indirect:
197  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
198  << " ByVal=" << getIndirectByVal()
199  << " Realign=" << getIndirectRealign();
200  break;
201  case Expand:
202  OS << "Expand";
203  break;
204  case CoerceAndExpand:
205  OS << "CoerceAndExpand Type=";
206  getCoerceAndExpandType()->print(OS);
207  break;
208  }
209  OS << ")\n";
210 }
211 
212 // Dynamically round a pointer up to a multiple of the given alignment.
214  llvm::Value *Ptr,
215  CharUnits Align) {
216  llvm::Value *PtrAsInt = Ptr;
217  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
218  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
219  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
220  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
221  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
222  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
223  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
224  Ptr->getType(),
225  Ptr->getName() + ".aligned");
226  return PtrAsInt;
227 }
228 
229 /// Emit va_arg for a platform using the common void* representation,
230 /// where arguments are simply emitted in an array of slots on the stack.
231 ///
232 /// This version implements the core direct-value passing rules.
233 ///
234 /// \param SlotSize - The size and alignment of a stack slot.
235 /// Each argument will be allocated to a multiple of this number of
236 /// slots, and all the slots will be aligned to this value.
237 /// \param AllowHigherAlign - The slot alignment is not a cap;
238 /// an argument type with an alignment greater than the slot size
239 /// will be emitted on a higher-alignment address, potentially
240 /// leaving one or more empty slots behind as padding. If this
241 /// is false, the returned address might be less-aligned than
242 /// DirectAlign.
244  Address VAListAddr,
245  llvm::Type *DirectTy,
246  CharUnits DirectSize,
247  CharUnits DirectAlign,
248  CharUnits SlotSize,
249  bool AllowHigherAlign) {
250  // Cast the element type to i8* if necessary. Some platforms define
251  // va_list as a struct containing an i8* instead of just an i8*.
252  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
253  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
254 
255  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
256 
257  // If the CC aligns values higher than the slot size, do so if needed.
258  Address Addr = Address::invalid();
259  if (AllowHigherAlign && DirectAlign > SlotSize) {
260  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
261  DirectAlign);
262  } else {
263  Addr = Address(Ptr, SlotSize);
264  }
265 
266  // Advance the pointer past the argument, then store that back.
267  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
268  llvm::Value *NextPtr =
269  CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
270  "argp.next");
271  CGF.Builder.CreateStore(NextPtr, VAListAddr);
272 
273  // If the argument is smaller than a slot, and this is a big-endian
274  // target, the argument will be right-adjusted in its slot.
275  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
276  !DirectTy->isStructTy()) {
277  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
278  }
279 
280  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
281  return Addr;
282 }
283 
284 /// Emit va_arg for a platform using the common void* representation,
285 /// where arguments are simply emitted in an array of slots on the stack.
286 ///
287 /// \param IsIndirect - Values of this type are passed indirectly.
288 /// \param ValueInfo - The size and alignment of this type, generally
289 /// computed with getContext().getTypeInfoInChars(ValueTy).
290 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
291 /// Each argument will be allocated to a multiple of this number of
292 /// slots, and all the slots will be aligned to this value.
293 /// \param AllowHigherAlign - The slot alignment is not a cap;
294 /// an argument type with an alignment greater than the slot size
295 /// will be emitted on a higher-alignment address, potentially
296 /// leaving one or more empty slots behind as padding.
298  QualType ValueTy, bool IsIndirect,
299  std::pair<CharUnits, CharUnits> ValueInfo,
300  CharUnits SlotSizeAndAlign,
301  bool AllowHigherAlign) {
302  // The size and alignment of the value that was passed directly.
303  CharUnits DirectSize, DirectAlign;
304  if (IsIndirect) {
305  DirectSize = CGF.getPointerSize();
306  DirectAlign = CGF.getPointerAlign();
307  } else {
308  DirectSize = ValueInfo.first;
309  DirectAlign = ValueInfo.second;
310  }
311 
312  // Cast the address we've calculated to the right type.
313  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
314  if (IsIndirect)
315  DirectTy = DirectTy->getPointerTo(0);
316 
317  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
318  DirectSize, DirectAlign,
319  SlotSizeAndAlign,
320  AllowHigherAlign);
321 
322  if (IsIndirect) {
323  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
324  }
325 
326  return Addr;
327 
328 }
329 
331  Address Addr1, llvm::BasicBlock *Block1,
332  Address Addr2, llvm::BasicBlock *Block2,
333  const llvm::Twine &Name = "") {
334  assert(Addr1.getType() == Addr2.getType());
335  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
336  PHI->addIncoming(Addr1.getPointer(), Block1);
337  PHI->addIncoming(Addr2.getPointer(), Block2);
338  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
339  return Address(PHI, Align);
340 }
341 
343 
344 // If someone can figure out a general rule for this, that would be great.
345 // It's probably just doomed to be platform-dependent, though.
347  // Verified for:
348  // x86-64 FreeBSD, Linux, Darwin
349  // x86-32 FreeBSD, Linux, Darwin
350  // PowerPC Linux, Darwin
351  // ARM Darwin (*not* EABI)
352  // AArch64 Linux
353  return 32;
354 }
355 
357  const FunctionNoProtoType *fnType) const {
358  // The following conventions are known to require this to be false:
359  // x86_stdcall
360  // MIPS
361  // For everything else, we just prefer false unless we opt out.
362  return false;
363 }
364 
365 void
367  llvm::SmallString<24> &Opt) const {
368  // This assumes the user is passing a library name like "rt" instead of a
369  // filename like "librt.a/so", and that they don't care whether it's static or
370  // dynamic.
371  Opt = "-l";
372  Opt += Lib;
373 }
374 
376  return llvm::CallingConv::C;
377 }
378 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
379 
380 /// isEmptyField - Return true iff a the field is "empty", that is it
381 /// is an unnamed bit-field or an (array of) empty record(s).
382 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
383  bool AllowArrays) {
384  if (FD->isUnnamedBitfield())
385  return true;
386 
387  QualType FT = FD->getType();
388 
389  // Constant arrays of empty records count as empty, strip them off.
390  // Constant arrays of zero length always count as empty.
391  if (AllowArrays)
392  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
393  if (AT->getSize() == 0)
394  return true;
395  FT = AT->getElementType();
396  }
397 
398  const RecordType *RT = FT->getAs<RecordType>();
399  if (!RT)
400  return false;
401 
402  // C++ record fields are never empty, at least in the Itanium ABI.
403  //
404  // FIXME: We should use a predicate for whether this behavior is true in the
405  // current ABI.
406  if (isa<CXXRecordDecl>(RT->getDecl()))
407  return false;
408 
409  return isEmptyRecord(Context, FT, AllowArrays);
410 }
411 
412 /// isEmptyRecord - Return true iff a structure contains only empty
413 /// fields. Note that a structure with a flexible array member is not
414 /// considered empty.
415 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
416  const RecordType *RT = T->getAs<RecordType>();
417  if (!RT)
418  return false;
419  const RecordDecl *RD = RT->getDecl();
420  if (RD->hasFlexibleArrayMember())
421  return false;
422 
423  // If this is a C++ record, check the bases first.
424  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
425  for (const auto &I : CXXRD->bases())
426  if (!isEmptyRecord(Context, I.getType(), true))
427  return false;
428 
429  for (const auto *I : RD->fields())
430  if (!isEmptyField(Context, I, AllowArrays))
431  return false;
432  return true;
433 }
434 
435 /// isSingleElementStruct - Determine if a structure is a "single
436 /// element struct", i.e. it has exactly one non-empty field or
437 /// exactly one field which is itself a single element
438 /// struct. Structures with flexible array members are never
439 /// considered single element structs.
440 ///
441 /// \return The field declaration for the single non-empty field, if
442 /// it exists.
444  const RecordType *RT = T->getAs<RecordType>();
445  if (!RT)
446  return nullptr;
447 
448  const RecordDecl *RD = RT->getDecl();
449  if (RD->hasFlexibleArrayMember())
450  return nullptr;
451 
452  const Type *Found = nullptr;
453 
454  // If this is a C++ record, check the bases first.
455  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
456  for (const auto &I : CXXRD->bases()) {
457  // Ignore empty records.
458  if (isEmptyRecord(Context, I.getType(), true))
459  continue;
460 
461  // If we already found an element then this isn't a single-element struct.
462  if (Found)
463  return nullptr;
464 
465  // If this is non-empty and not a single element struct, the composite
466  // cannot be a single element struct.
467  Found = isSingleElementStruct(I.getType(), Context);
468  if (!Found)
469  return nullptr;
470  }
471  }
472 
473  // Check for single element.
474  for (const auto *FD : RD->fields()) {
475  QualType FT = FD->getType();
476 
477  // Ignore empty fields.
478  if (isEmptyField(Context, FD, true))
479  continue;
480 
481  // If we already found an element then this isn't a single-element
482  // struct.
483  if (Found)
484  return nullptr;
485 
486  // Treat single element arrays as the element.
487  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
488  if (AT->getSize().getZExtValue() != 1)
489  break;
490  FT = AT->getElementType();
491  }
492 
493  if (!isAggregateTypeForABI(FT)) {
494  Found = FT.getTypePtr();
495  } else {
496  Found = isSingleElementStruct(FT, Context);
497  if (!Found)
498  return nullptr;
499  }
500  }
501 
502  // We don't consider a struct a single-element struct if it has
503  // padding beyond the element type.
504  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
505  return nullptr;
506 
507  return Found;
508 }
509 
510 namespace {
511 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
512  const ABIArgInfo &AI) {
513  // This default implementation defers to the llvm backend's va_arg
514  // instruction. It can handle only passing arguments directly
515  // (typically only handled in the backend for primitive types), or
516  // aggregates passed indirectly by pointer (NOTE: if the "byval"
517  // flag has ABI impact in the callee, this implementation cannot
518  // work.)
519 
520  // Only a few cases are covered here at the moment -- those needed
521  // by the default abi.
522  llvm::Value *Val;
523 
524  if (AI.isIndirect()) {
525  assert(!AI.getPaddingType() &&
526  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
527  assert(
528  !AI.getIndirectRealign() &&
529  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
530 
531  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
532  CharUnits TyAlignForABI = TyInfo.second;
533 
534  llvm::Type *BaseTy =
535  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
536  llvm::Value *Addr =
537  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
538  return Address(Addr, TyAlignForABI);
539  } else {
540  assert((AI.isDirect() || AI.isExtend()) &&
541  "Unexpected ArgInfo Kind in generic VAArg emitter!");
542 
543  assert(!AI.getInReg() &&
544  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
545  assert(!AI.getPaddingType() &&
546  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
547  assert(!AI.getDirectOffset() &&
548  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
549  assert(!AI.getCoerceToType() &&
550  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
551 
552  Address Temp = CGF.CreateMemTemp(Ty, "varet");
553  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
554  CGF.Builder.CreateStore(Val, Temp);
555  return Temp;
556  }
557 }
558 
559 /// DefaultABIInfo - The default implementation for ABI specific
560 /// details. This implementation provides information which results in
561 /// self-consistent and sensible LLVM IR generation, but does not
562 /// conform to any particular ABI.
563 class DefaultABIInfo : public ABIInfo {
564 public:
565  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
566 
569 
570  void computeInfo(CGFunctionInfo &FI) const override {
571  if (!getCXXABI().classifyReturnType(FI))
573  for (auto &I : FI.arguments())
574  I.info = classifyArgumentType(I.type);
575  }
576 
577  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
578  QualType Ty) const override {
579  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
580  }
581 };
582 
583 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
584 public:
585  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
586  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
587 };
588 
591 
592  if (isAggregateTypeForABI(Ty)) {
593  // Records with non-trivial destructors/copy-constructors should not be
594  // passed by value.
595  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
596  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
597 
598  return getNaturalAlignIndirect(Ty);
599  }
600 
601  // Treat an enum type as its underlying type.
602  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
603  Ty = EnumTy->getDecl()->getIntegerType();
604 
605  return (Ty->isPromotableIntegerType() ?
606  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
607 }
608 
610  if (RetTy->isVoidType())
611  return ABIArgInfo::getIgnore();
612 
613  if (isAggregateTypeForABI(RetTy))
614  return getNaturalAlignIndirect(RetTy);
615 
616  // Treat an enum type as its underlying type.
617  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
618  RetTy = EnumTy->getDecl()->getIntegerType();
619 
620  return (RetTy->isPromotableIntegerType() ?
621  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
622 }
623 
624 //===----------------------------------------------------------------------===//
625 // WebAssembly ABI Implementation
626 //
627 // This is a very simple ABI that relies a lot on DefaultABIInfo.
628 //===----------------------------------------------------------------------===//
629 
630 class WebAssemblyABIInfo final : public DefaultABIInfo {
631 public:
632  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
633  : DefaultABIInfo(CGT) {}
634 
635 private:
638 
639  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
640  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
641  // overload them.
642  void computeInfo(CGFunctionInfo &FI) const override {
643  if (!getCXXABI().classifyReturnType(FI))
645  for (auto &Arg : FI.arguments())
646  Arg.info = classifyArgumentType(Arg.type);
647  }
648 
649  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
650  QualType Ty) const override;
651 };
652 
653 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
654 public:
655  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
656  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
657 };
658 
659 /// \brief Classify argument of given type \p Ty.
662 
663  if (isAggregateTypeForABI(Ty)) {
664  // Records with non-trivial destructors/copy-constructors should not be
665  // passed by value.
666  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
667  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
668  // Ignore empty structs/unions.
669  if (isEmptyRecord(getContext(), Ty, true))
670  return ABIArgInfo::getIgnore();
671  // Lower single-element structs to just pass a regular value. TODO: We
672  // could do reasonable-size multiple-element structs too, using getExpand(),
673  // though watch out for things like bitfields.
674  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
675  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
676  }
677 
678  // Otherwise just do the default thing.
680 }
681 
683  if (isAggregateTypeForABI(RetTy)) {
684  // Records with non-trivial destructors/copy-constructors should not be
685  // returned by value.
686  if (!getRecordArgABI(RetTy, getCXXABI())) {
687  // Ignore empty structs/unions.
688  if (isEmptyRecord(getContext(), RetTy, true))
689  return ABIArgInfo::getIgnore();
690  // Lower single-element structs to just return a regular value. TODO: We
691  // could do reasonable-size multiple-element structs too, using
692  // ABIArgInfo::getDirect().
693  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
694  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
695  }
696  }
697 
698  // Otherwise just do the default thing.
700 }
701 
702 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
703  QualType Ty) const {
704  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
705  getContext().getTypeInfoInChars(Ty),
707  /*AllowHigherAlign=*/ true);
708 }
709 
710 //===----------------------------------------------------------------------===//
711 // le32/PNaCl bitcode ABI Implementation
712 //
713 // This is a simplified version of the x86_32 ABI. Arguments and return values
714 // are always passed on the stack.
715 //===----------------------------------------------------------------------===//
716 
717 class PNaClABIInfo : public ABIInfo {
718  public:
719  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
720 
723 
724  void computeInfo(CGFunctionInfo &FI) const override;
725  Address EmitVAArg(CodeGenFunction &CGF,
726  Address VAListAddr, QualType Ty) const override;
727 };
728 
729 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
730  public:
731  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
732  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
733 };
734 
735 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
736  if (!getCXXABI().classifyReturnType(FI))
738 
739  for (auto &I : FI.arguments())
740  I.info = classifyArgumentType(I.type);
741 }
742 
743 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
744  QualType Ty) const {
745  // The PNaCL ABI is a bit odd, in that varargs don't use normal
746  // function classification. Structs get passed directly for varargs
747  // functions, through a rewriting transform in
748  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
749  // this target to actually support a va_arg instructions with an
750  // aggregate type, unlike other targets.
751  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
752 }
753 
754 /// \brief Classify argument of given type \p Ty.
756  if (isAggregateTypeForABI(Ty)) {
757  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
758  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
759  return getNaturalAlignIndirect(Ty);
760  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
761  // Treat an enum type as its underlying type.
762  Ty = EnumTy->getDecl()->getIntegerType();
763  } else if (Ty->isFloatingType()) {
764  // Floating-point types don't go inreg.
765  return ABIArgInfo::getDirect();
766  }
767 
768  return (Ty->isPromotableIntegerType() ?
769  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
770 }
771 
773  if (RetTy->isVoidType())
774  return ABIArgInfo::getIgnore();
775 
776  // In the PNaCl ABI we always return records/structures on the stack.
777  if (isAggregateTypeForABI(RetTy))
778  return getNaturalAlignIndirect(RetTy);
779 
780  // Treat an enum type as its underlying type.
781  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
782  RetTy = EnumTy->getDecl()->getIntegerType();
783 
784  return (RetTy->isPromotableIntegerType() ?
785  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
786 }
787 
788 /// IsX86_MMXType - Return true if this is an MMX type.
789 bool IsX86_MMXType(llvm::Type *IRType) {
790  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
791  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
792  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
793  IRType->getScalarSizeInBits() != 64;
794 }
795 
796 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
797  StringRef Constraint,
798  llvm::Type* Ty) {
799  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
800  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
801  // Invalid MMX constraint
802  return nullptr;
803  }
804 
805  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
806  }
807 
808  // No operation needed
809  return Ty;
810 }
811 
812 /// Returns true if this type can be passed in SSE registers with the
813 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
814 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
815  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
816  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half)
817  return true;
818  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
819  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
820  // registers specially.
821  unsigned VecSize = Context.getTypeSize(VT);
822  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
823  return true;
824  }
825  return false;
826 }
827 
828 /// Returns true if this aggregate is small enough to be passed in SSE registers
829 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
830 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
831  return NumMembers <= 4;
832 }
833 
834 //===----------------------------------------------------------------------===//
835 // X86-32 ABI Implementation
836 //===----------------------------------------------------------------------===//
837 
838 /// \brief Similar to llvm::CCState, but for Clang.
839 struct CCState {
840  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
841 
842  unsigned CC;
843  unsigned FreeRegs;
844  unsigned FreeSSERegs;
845 };
846 
847 /// X86_32ABIInfo - The X86-32 ABI information.
848 class X86_32ABIInfo : public SwiftABIInfo {
849  enum Class {
850  Integer,
851  Float
852  };
853 
854  static const unsigned MinABIStackAlignInBytes = 4;
855 
856  bool IsDarwinVectorABI;
857  bool IsRetSmallStructInRegABI;
858  bool IsWin32StructABI;
859  bool IsSoftFloatABI;
860  bool IsMCUABI;
861  unsigned DefaultNumRegisterParameters;
862 
863  static bool isRegisterSize(unsigned Size) {
864  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
865  }
866 
867  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
868  // FIXME: Assumes vectorcall is in use.
869  return isX86VectorTypeForVectorCall(getContext(), Ty);
870  }
871 
872  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
873  uint64_t NumMembers) const override {
874  // FIXME: Assumes vectorcall is in use.
875  return isX86VectorCallAggregateSmallEnough(NumMembers);
876  }
877 
878  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
879 
880  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
881  /// such that the argument will be passed in memory.
882  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
883 
884  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
885 
886  /// \brief Return the alignment to use for the given type on the stack.
887  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
888 
889  Class classify(QualType Ty) const;
890  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
891  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
892  /// \brief Updates the number of available free registers, returns
893  /// true if any registers were allocated.
894  bool updateFreeRegs(QualType Ty, CCState &State) const;
895 
896  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
897  bool &NeedsPadding) const;
898  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
899 
900  bool canExpandIndirectArgument(QualType Ty) const;
901 
902  /// \brief Rewrite the function info so that all memory arguments use
903  /// inalloca.
904  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
905 
906  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
907  CharUnits &StackOffset, ABIArgInfo &Info,
908  QualType Type) const;
909 
910 public:
911 
912  void computeInfo(CGFunctionInfo &FI) const override;
913  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
914  QualType Ty) const override;
915 
916  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
917  bool RetSmallStructInRegABI, bool Win32StructABI,
918  unsigned NumRegisterParameters, bool SoftFloatABI)
919  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
920  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
921  IsWin32StructABI(Win32StructABI),
922  IsSoftFloatABI(SoftFloatABI),
923  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
924  DefaultNumRegisterParameters(NumRegisterParameters) {}
925 
926  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
927  ArrayRef<llvm::Type*> scalars,
928  bool asReturnValue) const override {
929  // LLVM's x86-32 lowering currently only assigns up to three
930  // integer registers and three fp registers. Oddly, it'll use up to
931  // four vector registers for vectors, but those can overlap with the
932  // scalar registers.
933  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
934  }
935 };
936 
937 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
938 public:
939  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
940  bool RetSmallStructInRegABI, bool Win32StructABI,
941  unsigned NumRegisterParameters, bool SoftFloatABI)
942  : TargetCodeGenInfo(new X86_32ABIInfo(
943  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
944  NumRegisterParameters, SoftFloatABI)) {}
945 
946  static bool isStructReturnInRegABI(
947  const llvm::Triple &Triple, const CodeGenOptions &Opts);
948 
949  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
950  CodeGen::CodeGenModule &CGM) const override;
951 
952  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
953  // Darwin uses different dwarf register numbers for EH.
954  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
955  return 4;
956  }
957 
958  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
959  llvm::Value *Address) const override;
960 
961  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
962  StringRef Constraint,
963  llvm::Type* Ty) const override {
964  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
965  }
966 
967  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
968  std::string &Constraints,
969  std::vector<llvm::Type *> &ResultRegTypes,
970  std::vector<llvm::Type *> &ResultTruncRegTypes,
971  std::vector<LValue> &ResultRegDests,
972  std::string &AsmString,
973  unsigned NumOutputs) const override;
974 
975  llvm::Constant *
976  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
977  unsigned Sig = (0xeb << 0) | // jmp rel8
978  (0x06 << 8) | // .+0x08
979  ('F' << 16) |
980  ('T' << 24);
981  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
982  }
983 
984  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
985  return "movl\t%ebp, %ebp"
986  "\t\t## marker for objc_retainAutoreleaseReturnValue";
987  }
988 };
989 
990 }
991 
992 /// Rewrite input constraint references after adding some output constraints.
993 /// In the case where there is one output and one input and we add one output,
994 /// we need to replace all operand references greater than or equal to 1:
995 /// mov $0, $1
996 /// mov eax, $1
997 /// The result will be:
998 /// mov $0, $2
999 /// mov eax, $2
1000 static void rewriteInputConstraintReferences(unsigned FirstIn,
1001  unsigned NumNewOuts,
1002  std::string &AsmString) {
1003  std::string Buf;
1004  llvm::raw_string_ostream OS(Buf);
1005  size_t Pos = 0;
1006  while (Pos < AsmString.size()) {
1007  size_t DollarStart = AsmString.find('$', Pos);
1008  if (DollarStart == std::string::npos)
1009  DollarStart = AsmString.size();
1010  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1011  if (DollarEnd == std::string::npos)
1012  DollarEnd = AsmString.size();
1013  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1014  Pos = DollarEnd;
1015  size_t NumDollars = DollarEnd - DollarStart;
1016  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1017  // We have an operand reference.
1018  size_t DigitStart = Pos;
1019  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1020  if (DigitEnd == std::string::npos)
1021  DigitEnd = AsmString.size();
1022  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1023  unsigned OperandIndex;
1024  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1025  if (OperandIndex >= FirstIn)
1026  OperandIndex += NumNewOuts;
1027  OS << OperandIndex;
1028  } else {
1029  OS << OperandStr;
1030  }
1031  Pos = DigitEnd;
1032  }
1033  }
1034  AsmString = std::move(OS.str());
1035 }
1036 
1037 /// Add output constraints for EAX:EDX because they are return registers.
1038 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1039  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1040  std::vector<llvm::Type *> &ResultRegTypes,
1041  std::vector<llvm::Type *> &ResultTruncRegTypes,
1042  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1043  unsigned NumOutputs) const {
1044  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1045 
1046  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1047  // larger.
1048  if (!Constraints.empty())
1049  Constraints += ',';
1050  if (RetWidth <= 32) {
1051  Constraints += "={eax}";
1052  ResultRegTypes.push_back(CGF.Int32Ty);
1053  } else {
1054  // Use the 'A' constraint for EAX:EDX.
1055  Constraints += "=A";
1056  ResultRegTypes.push_back(CGF.Int64Ty);
1057  }
1058 
1059  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1060  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1061  ResultTruncRegTypes.push_back(CoerceTy);
1062 
1063  // Coerce the integer by bitcasting the return slot pointer.
1064  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1065  CoerceTy->getPointerTo()));
1066  ResultRegDests.push_back(ReturnSlot);
1067 
1068  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1069 }
1070 
1071 /// shouldReturnTypeInRegister - Determine if the given type should be
1072 /// returned in a register (for the Darwin and MCU ABI).
1073 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1074  ASTContext &Context) const {
1075  uint64_t Size = Context.getTypeSize(Ty);
1076 
1077  // For i386, type must be register sized.
1078  // For the MCU ABI, it only needs to be <= 8-byte
1079  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1080  return false;
1081 
1082  if (Ty->isVectorType()) {
1083  // 64- and 128- bit vectors inside structures are not returned in
1084  // registers.
1085  if (Size == 64 || Size == 128)
1086  return false;
1087 
1088  return true;
1089  }
1090 
1091  // If this is a builtin, pointer, enum, complex type, member pointer, or
1092  // member function pointer it is ok.
1093  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1094  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1095  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1096  return true;
1097 
1098  // Arrays are treated like records.
1099  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1100  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1101 
1102  // Otherwise, it must be a record type.
1103  const RecordType *RT = Ty->getAs<RecordType>();
1104  if (!RT) return false;
1105 
1106  // FIXME: Traverse bases here too.
1107 
1108  // Structure types are passed in register if all fields would be
1109  // passed in a register.
1110  for (const auto *FD : RT->getDecl()->fields()) {
1111  // Empty fields are ignored.
1112  if (isEmptyField(Context, FD, true))
1113  continue;
1114 
1115  // Check fields recursively.
1116  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1117  return false;
1118  }
1119  return true;
1120 }
1121 
1122 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1123  // Treat complex types as the element type.
1124  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1125  Ty = CTy->getElementType();
1126 
1127  // Check for a type which we know has a simple scalar argument-passing
1128  // convention without any padding. (We're specifically looking for 32
1129  // and 64-bit integer and integer-equivalents, float, and double.)
1130  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1131  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1132  return false;
1133 
1134  uint64_t Size = Context.getTypeSize(Ty);
1135  return Size == 32 || Size == 64;
1136 }
1137 
1138 /// Test whether an argument type which is to be passed indirectly (on the
1139 /// stack) would have the equivalent layout if it was expanded into separate
1140 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1141 /// optimizations.
1142 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1143  // We can only expand structure types.
1144  const RecordType *RT = Ty->getAs<RecordType>();
1145  if (!RT)
1146  return false;
1147  const RecordDecl *RD = RT->getDecl();
1148  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1149  if (!IsWin32StructABI ) {
1150  // On non-Windows, we have to conservatively match our old bitcode
1151  // prototypes in order to be ABI-compatible at the bitcode level.
1152  if (!CXXRD->isCLike())
1153  return false;
1154  } else {
1155  // Don't do this for dynamic classes.
1156  if (CXXRD->isDynamicClass())
1157  return false;
1158  // Don't do this if there are any non-empty bases.
1159  for (const CXXBaseSpecifier &Base : CXXRD->bases()) {
1160  if (!isEmptyRecord(getContext(), Base.getType(), /*AllowArrays=*/true))
1161  return false;
1162  }
1163  }
1164  }
1165 
1166  uint64_t Size = 0;
1167 
1168  for (const auto *FD : RD->fields()) {
1169  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1170  // argument is smaller than 32-bits, expanding the struct will create
1171  // alignment padding.
1172  if (!is32Or64BitBasicType(FD->getType(), getContext()))
1173  return false;
1174 
1175  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1176  // how to expand them yet, and the predicate for telling if a bitfield still
1177  // counts as "basic" is more complicated than what we were doing previously.
1178  if (FD->isBitField())
1179  return false;
1180 
1181  Size += getContext().getTypeSize(FD->getType());
1182  }
1183 
1184  // We can do this if there was no alignment padding.
1185  return Size == getContext().getTypeSize(Ty);
1186 }
1187 
1188 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1189  // If the return value is indirect, then the hidden argument is consuming one
1190  // integer register.
1191  if (State.FreeRegs) {
1192  --State.FreeRegs;
1193  if (!IsMCUABI)
1194  return getNaturalAlignIndirectInReg(RetTy);
1195  }
1196  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1197 }
1198 
1200  CCState &State) const {
1201  if (RetTy->isVoidType())
1202  return ABIArgInfo::getIgnore();
1203 
1204  const Type *Base = nullptr;
1205  uint64_t NumElts = 0;
1206  if (State.CC == llvm::CallingConv::X86_VectorCall &&
1207  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1208  // The LLVM struct type for such an aggregate should lower properly.
1209  return ABIArgInfo::getDirect();
1210  }
1211 
1212  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1213  // On Darwin, some vectors are returned in registers.
1214  if (IsDarwinVectorABI) {
1215  uint64_t Size = getContext().getTypeSize(RetTy);
1216 
1217  // 128-bit vectors are a special case; they are returned in
1218  // registers and we need to make sure to pick a type the LLVM
1219  // backend will like.
1220  if (Size == 128)
1221  return ABIArgInfo::getDirect(llvm::VectorType::get(
1222  llvm::Type::getInt64Ty(getVMContext()), 2));
1223 
1224  // Always return in register if it fits in a general purpose
1225  // register, or if it is 64 bits and has a single element.
1226  if ((Size == 8 || Size == 16 || Size == 32) ||
1227  (Size == 64 && VT->getNumElements() == 1))
1228  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1229  Size));
1230 
1231  return getIndirectReturnResult(RetTy, State);
1232  }
1233 
1234  return ABIArgInfo::getDirect();
1235  }
1236 
1237  if (isAggregateTypeForABI(RetTy)) {
1238  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1239  // Structures with flexible arrays are always indirect.
1240  if (RT->getDecl()->hasFlexibleArrayMember())
1241  return getIndirectReturnResult(RetTy, State);
1242  }
1243 
1244  // If specified, structs and unions are always indirect.
1245  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1246  return getIndirectReturnResult(RetTy, State);
1247 
1248  // Ignore empty structs/unions.
1249  if (isEmptyRecord(getContext(), RetTy, true))
1250  return ABIArgInfo::getIgnore();
1251 
1252  // Small structures which are register sized are generally returned
1253  // in a register.
1254  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1255  uint64_t Size = getContext().getTypeSize(RetTy);
1256 
1257  // As a special-case, if the struct is a "single-element" struct, and
1258  // the field is of type "float" or "double", return it in a
1259  // floating-point register. (MSVC does not apply this special case.)
1260  // We apply a similar transformation for pointer types to improve the
1261  // quality of the generated IR.
1262  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1263  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1264  || SeltTy->hasPointerRepresentation())
1265  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1266 
1267  // FIXME: We should be able to narrow this integer in cases with dead
1268  // padding.
1269  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1270  }
1271 
1272  return getIndirectReturnResult(RetTy, State);
1273  }
1274 
1275  // Treat an enum type as its underlying type.
1276  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1277  RetTy = EnumTy->getDecl()->getIntegerType();
1278 
1279  return (RetTy->isPromotableIntegerType() ?
1280  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
1281 }
1282 
1283 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1284  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1285 }
1286 
1287 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1288  const RecordType *RT = Ty->getAs<RecordType>();
1289  if (!RT)
1290  return 0;
1291  const RecordDecl *RD = RT->getDecl();
1292 
1293  // If this is a C++ record, check the bases first.
1294  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1295  for (const auto &I : CXXRD->bases())
1296  if (!isRecordWithSSEVectorType(Context, I.getType()))
1297  return false;
1298 
1299  for (const auto *i : RD->fields()) {
1300  QualType FT = i->getType();
1301 
1302  if (isSSEVectorType(Context, FT))
1303  return true;
1304 
1305  if (isRecordWithSSEVectorType(Context, FT))
1306  return true;
1307  }
1308 
1309  return false;
1310 }
1311 
1312 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1313  unsigned Align) const {
1314  // Otherwise, if the alignment is less than or equal to the minimum ABI
1315  // alignment, just use the default; the backend will handle this.
1316  if (Align <= MinABIStackAlignInBytes)
1317  return 0; // Use default alignment.
1318 
1319  // On non-Darwin, the stack type alignment is always 4.
1320  if (!IsDarwinVectorABI) {
1321  // Set explicit alignment, since we may need to realign the top.
1322  return MinABIStackAlignInBytes;
1323  }
1324 
1325  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1326  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1327  isRecordWithSSEVectorType(getContext(), Ty)))
1328  return 16;
1329 
1330  return MinABIStackAlignInBytes;
1331 }
1332 
1333 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1334  CCState &State) const {
1335  if (!ByVal) {
1336  if (State.FreeRegs) {
1337  --State.FreeRegs; // Non-byval indirects just use one pointer.
1338  if (!IsMCUABI)
1339  return getNaturalAlignIndirectInReg(Ty);
1340  }
1341  return getNaturalAlignIndirect(Ty, false);
1342  }
1343 
1344  // Compute the byval alignment.
1345  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1346  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1347  if (StackAlign == 0)
1348  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1349 
1350  // If the stack alignment is less than the type alignment, realign the
1351  // argument.
1352  bool Realign = TypeAlign > StackAlign;
1354  /*ByVal=*/true, Realign);
1355 }
1356 
1357 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1358  const Type *T = isSingleElementStruct(Ty, getContext());
1359  if (!T)
1360  T = Ty.getTypePtr();
1361 
1362  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1363  BuiltinType::Kind K = BT->getKind();
1364  if (K == BuiltinType::Float || K == BuiltinType::Double)
1365  return Float;
1366  }
1367  return Integer;
1368 }
1369 
1370 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1371  if (!IsSoftFloatABI) {
1372  Class C = classify(Ty);
1373  if (C == Float)
1374  return false;
1375  }
1376 
1377  unsigned Size = getContext().getTypeSize(Ty);
1378  unsigned SizeInRegs = (Size + 31) / 32;
1379 
1380  if (SizeInRegs == 0)
1381  return false;
1382 
1383  if (!IsMCUABI) {
1384  if (SizeInRegs > State.FreeRegs) {
1385  State.FreeRegs = 0;
1386  return false;
1387  }
1388  } else {
1389  // The MCU psABI allows passing parameters in-reg even if there are
1390  // earlier parameters that are passed on the stack. Also,
1391  // it does not allow passing >8-byte structs in-register,
1392  // even if there are 3 free registers available.
1393  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1394  return false;
1395  }
1396 
1397  State.FreeRegs -= SizeInRegs;
1398  return true;
1399 }
1400 
1401 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1402  bool &InReg,
1403  bool &NeedsPadding) const {
1404  // On Windows, aggregates other than HFAs are never passed in registers, and
1405  // they do not consume register slots. Homogenous floating-point aggregates
1406  // (HFAs) have already been dealt with at this point.
1407  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1408  return false;
1409 
1410  NeedsPadding = false;
1411  InReg = !IsMCUABI;
1412 
1413  if (!updateFreeRegs(Ty, State))
1414  return false;
1415 
1416  if (IsMCUABI)
1417  return true;
1418 
1419  if (State.CC == llvm::CallingConv::X86_FastCall ||
1420  State.CC == llvm::CallingConv::X86_VectorCall) {
1421  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1422  NeedsPadding = true;
1423 
1424  return false;
1425  }
1426 
1427  return true;
1428 }
1429 
1430 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1431  if (!updateFreeRegs(Ty, State))
1432  return false;
1433 
1434  if (IsMCUABI)
1435  return false;
1436 
1437  if (State.CC == llvm::CallingConv::X86_FastCall ||
1438  State.CC == llvm::CallingConv::X86_VectorCall) {
1439  if (getContext().getTypeSize(Ty) > 32)
1440  return false;
1441 
1442  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1443  Ty->isReferenceType());
1444  }
1445 
1446  return true;
1447 }
1448 
1450  CCState &State) const {
1451  // FIXME: Set alignment on indirect arguments.
1452 
1454 
1455  // Check with the C++ ABI first.
1456  const RecordType *RT = Ty->getAs<RecordType>();
1457  if (RT) {
1458  CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
1459  if (RAA == CGCXXABI::RAA_Indirect) {
1460  return getIndirectResult(Ty, false, State);
1461  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1462  // The field index doesn't matter, we'll fix it up later.
1463  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1464  }
1465  }
1466 
1467  // vectorcall adds the concept of a homogenous vector aggregate, similar
1468  // to other targets.
1469  const Type *Base = nullptr;
1470  uint64_t NumElts = 0;
1471  if (State.CC == llvm::CallingConv::X86_VectorCall &&
1472  isHomogeneousAggregate(Ty, Base, NumElts)) {
1473  if (State.FreeSSERegs >= NumElts) {
1474  State.FreeSSERegs -= NumElts;
1475  if (Ty->isBuiltinType() || Ty->isVectorType())
1476  return ABIArgInfo::getDirect();
1477  return ABIArgInfo::getExpand();
1478  }
1479  return getIndirectResult(Ty, /*ByVal=*/false, State);
1480  }
1481 
1482  if (isAggregateTypeForABI(Ty)) {
1483  // Structures with flexible arrays are always indirect.
1484  // FIXME: This should not be byval!
1485  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1486  return getIndirectResult(Ty, true, State);
1487 
1488  // Ignore empty structs/unions on non-Windows.
1489  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1490  return ABIArgInfo::getIgnore();
1491 
1492  llvm::LLVMContext &LLVMContext = getVMContext();
1493  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1494  bool NeedsPadding = false;
1495  bool InReg;
1496  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1497  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1498  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1499  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1500  if (InReg)
1501  return ABIArgInfo::getDirectInReg(Result);
1502  else
1503  return ABIArgInfo::getDirect(Result);
1504  }
1505  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1506 
1507  // Expand small (<= 128-bit) record types when we know that the stack layout
1508  // of those arguments will match the struct. This is important because the
1509  // LLVM backend isn't smart enough to remove byval, which inhibits many
1510  // optimizations.
1511  // Don't do this for the MCU if there are still free integer registers
1512  // (see X86_64 ABI for full explanation).
1513  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1514  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1516  State.CC == llvm::CallingConv::X86_FastCall ||
1517  State.CC == llvm::CallingConv::X86_VectorCall,
1518  PaddingType);
1519 
1520  return getIndirectResult(Ty, true, State);
1521  }
1522 
1523  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1524  // On Darwin, some vectors are passed in memory, we handle this by passing
1525  // it as an i8/i16/i32/i64.
1526  if (IsDarwinVectorABI) {
1527  uint64_t Size = getContext().getTypeSize(Ty);
1528  if ((Size == 8 || Size == 16 || Size == 32) ||
1529  (Size == 64 && VT->getNumElements() == 1))
1530  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1531  Size));
1532  }
1533 
1534  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1535  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1536 
1537  return ABIArgInfo::getDirect();
1538  }
1539 
1540 
1541  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1542  Ty = EnumTy->getDecl()->getIntegerType();
1543 
1544  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1545 
1546  if (Ty->isPromotableIntegerType()) {
1547  if (InReg)
1548  return ABIArgInfo::getExtendInReg();
1549  return ABIArgInfo::getExtend();
1550  }
1551 
1552  if (InReg)
1553  return ABIArgInfo::getDirectInReg();
1554  return ABIArgInfo::getDirect();
1555 }
1556 
1557 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1558  CCState State(FI.getCallingConvention());
1559  if (IsMCUABI)
1560  State.FreeRegs = 3;
1561  else if (State.CC == llvm::CallingConv::X86_FastCall)
1562  State.FreeRegs = 2;
1563  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1564  State.FreeRegs = 2;
1565  State.FreeSSERegs = 6;
1566  } else if (FI.getHasRegParm())
1567  State.FreeRegs = FI.getRegParm();
1568  else
1569  State.FreeRegs = DefaultNumRegisterParameters;
1570 
1571  if (!getCXXABI().classifyReturnType(FI)) {
1573  } else if (FI.getReturnInfo().isIndirect()) {
1574  // The C++ ABI is not aware of register usage, so we have to check if the
1575  // return value was sret and put it in a register ourselves if appropriate.
1576  if (State.FreeRegs) {
1577  --State.FreeRegs; // The sret parameter consumes a register.
1578  if (!IsMCUABI)
1579  FI.getReturnInfo().setInReg(true);
1580  }
1581  }
1582 
1583  // The chain argument effectively gives us another free register.
1584  if (FI.isChainCall())
1585  ++State.FreeRegs;
1586 
1587  bool UsedInAlloca = false;
1588  for (auto &I : FI.arguments()) {
1589  I.info = classifyArgumentType(I.type, State);
1590  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1591  }
1592 
1593  // If we needed to use inalloca for any argument, do a second pass and rewrite
1594  // all the memory arguments to use inalloca.
1595  if (UsedInAlloca)
1596  rewriteWithInAlloca(FI);
1597 }
1598 
1599 void
1600 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1601  CharUnits &StackOffset, ABIArgInfo &Info,
1602  QualType Type) const {
1603  // Arguments are always 4-byte-aligned.
1604  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1605 
1606  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1607  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1608  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1609  StackOffset += getContext().getTypeSizeInChars(Type);
1610 
1611  // Insert padding bytes to respect alignment.
1612  CharUnits FieldEnd = StackOffset;
1613  StackOffset = FieldEnd.alignTo(FieldAlign);
1614  if (StackOffset != FieldEnd) {
1615  CharUnits NumBytes = StackOffset - FieldEnd;
1616  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1617  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1618  FrameFields.push_back(Ty);
1619  }
1620 }
1621 
1622 static bool isArgInAlloca(const ABIArgInfo &Info) {
1623  // Leave ignored and inreg arguments alone.
1624  switch (Info.getKind()) {
1625  case ABIArgInfo::InAlloca:
1626  return true;
1627  case ABIArgInfo::Indirect:
1628  assert(Info.getIndirectByVal());
1629  return true;
1630  case ABIArgInfo::Ignore:
1631  return false;
1632  case ABIArgInfo::Direct:
1633  case ABIArgInfo::Extend:
1634  if (Info.getInReg())
1635  return false;
1636  return true;
1637  case ABIArgInfo::Expand:
1639  // These are aggregate types which are never passed in registers when
1640  // inalloca is involved.
1641  return true;
1642  }
1643  llvm_unreachable("invalid enum");
1644 }
1645 
1646 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1647  assert(IsWin32StructABI && "inalloca only supported on win32");
1648 
1649  // Build a packed struct type for all of the arguments in memory.
1650  SmallVector<llvm::Type *, 6> FrameFields;
1651 
1652  // The stack alignment is always 4.
1653  CharUnits StackAlign = CharUnits::fromQuantity(4);
1654 
1655  CharUnits StackOffset;
1657 
1658  // Put 'this' into the struct before 'sret', if necessary.
1659  bool IsThisCall =
1660  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1661  ABIArgInfo &Ret = FI.getReturnInfo();
1662  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1663  isArgInAlloca(I->info)) {
1664  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1665  ++I;
1666  }
1667 
1668  // Put the sret parameter into the inalloca struct if it's in memory.
1669  if (Ret.isIndirect() && !Ret.getInReg()) {
1670  CanQualType PtrTy = getContext().getPointerType(FI.getReturnType());
1671  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1672  // On Windows, the hidden sret parameter is always returned in eax.
1673  Ret.setInAllocaSRet(IsWin32StructABI);
1674  }
1675 
1676  // Skip the 'this' parameter in ecx.
1677  if (IsThisCall)
1678  ++I;
1679 
1680  // Put arguments passed in memory into the struct.
1681  for (; I != E; ++I) {
1682  if (isArgInAlloca(I->info))
1683  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1684  }
1685 
1686  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1687  /*isPacked=*/true),
1688  StackAlign);
1689 }
1690 
1691 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1692  Address VAListAddr, QualType Ty) const {
1693 
1694  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1695 
1696  // x86-32 changes the alignment of certain arguments on the stack.
1697  //
1698  // Just messing with TypeInfo like this works because we never pass
1699  // anything indirectly.
1701  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1702 
1703  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1705  /*AllowHigherAlign*/ true);
1706 }
1707 
1708 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1709  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1710  assert(Triple.getArch() == llvm::Triple::x86);
1711 
1712  switch (Opts.getStructReturnConvention()) {
1714  break;
1715  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1716  return false;
1717  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1718  return true;
1719  }
1720 
1721  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1722  return true;
1723 
1724  switch (Triple.getOS()) {
1725  case llvm::Triple::DragonFly:
1726  case llvm::Triple::FreeBSD:
1727  case llvm::Triple::OpenBSD:
1728  case llvm::Triple::Bitrig:
1729  case llvm::Triple::Win32:
1730  return true;
1731  default:
1732  return false;
1733  }
1734 }
1735 
1736 void X86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
1737  llvm::GlobalValue *GV,
1738  CodeGen::CodeGenModule &CGM) const {
1739  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1740  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1741  // Get the LLVM function.
1742  llvm::Function *Fn = cast<llvm::Function>(GV);
1743 
1744  // Now add the 'alignstack' attribute with a value of 16.
1745  llvm::AttrBuilder B;
1746  B.addStackAlignmentAttr(16);
1747  Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
1748  llvm::AttributeSet::get(CGM.getLLVMContext(),
1749  llvm::AttributeSet::FunctionIndex,
1750  B));
1751  }
1752  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1753  llvm::Function *Fn = cast<llvm::Function>(GV);
1754  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1755  }
1756  }
1757 }
1758 
1759 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1761  llvm::Value *Address) const {
1763 
1764  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1765 
1766  // 0-7 are the eight integer registers; the order is different
1767  // on Darwin (for EH), but the range is the same.
1768  // 8 is %eip.
1769  AssignToArrayRange(Builder, Address, Four8, 0, 8);
1770 
1771  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1772  // 12-16 are st(0..4). Not sure why we stop at 4.
1773  // These have size 16, which is sizeof(long double) on
1774  // platforms with 8-byte alignment for that type.
1775  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1776  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1777 
1778  } else {
1779  // 9 is %eflags, which doesn't get a size on Darwin for some
1780  // reason.
1781  Builder.CreateAlignedStore(
1782  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1783  CharUnits::One());
1784 
1785  // 11-16 are st(0..5). Not sure why we stop at 5.
1786  // These have size 12, which is sizeof(long double) on
1787  // platforms with 4-byte alignment for that type.
1788  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1789  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1790  }
1791 
1792  return false;
1793 }
1794 
1795 //===----------------------------------------------------------------------===//
1796 // X86-64 ABI Implementation
1797 //===----------------------------------------------------------------------===//
1798 
1799 
1800 namespace {
1801 /// The AVX ABI level for X86 targets.
1802 enum class X86AVXABILevel {
1803  None,
1804  AVX,
1805  AVX512
1806 };
1807 
1808 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
1809 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
1810  switch (AVXLevel) {
1811  case X86AVXABILevel::AVX512:
1812  return 512;
1813  case X86AVXABILevel::AVX:
1814  return 256;
1815  case X86AVXABILevel::None:
1816  return 128;
1817  }
1818  llvm_unreachable("Unknown AVXLevel");
1819 }
1820 
1821 /// X86_64ABIInfo - The X86_64 ABI information.
1822 class X86_64ABIInfo : public SwiftABIInfo {
1823  enum Class {
1824  Integer = 0,
1825  SSE,
1826  SSEUp,
1827  X87,
1828  X87Up,
1829  ComplexX87,
1830  NoClass,
1831  Memory
1832  };
1833 
1834  /// merge - Implement the X86_64 ABI merging algorithm.
1835  ///
1836  /// Merge an accumulating classification \arg Accum with a field
1837  /// classification \arg Field.
1838  ///
1839  /// \param Accum - The accumulating classification. This should
1840  /// always be either NoClass or the result of a previous merge
1841  /// call. In addition, this should never be Memory (the caller
1842  /// should just return Memory for the aggregate).
1843  static Class merge(Class Accum, Class Field);
1844 
1845  /// postMerge - Implement the X86_64 ABI post merging algorithm.
1846  ///
1847  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1848  /// final MEMORY or SSE classes when necessary.
1849  ///
1850  /// \param AggregateSize - The size of the current aggregate in
1851  /// the classification process.
1852  ///
1853  /// \param Lo - The classification for the parts of the type
1854  /// residing in the low word of the containing object.
1855  ///
1856  /// \param Hi - The classification for the parts of the type
1857  /// residing in the higher words of the containing object.
1858  ///
1859  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1860 
1861  /// classify - Determine the x86_64 register classes in which the
1862  /// given type T should be passed.
1863  ///
1864  /// \param Lo - The classification for the parts of the type
1865  /// residing in the low word of the containing object.
1866  ///
1867  /// \param Hi - The classification for the parts of the type
1868  /// residing in the high word of the containing object.
1869  ///
1870  /// \param OffsetBase - The bit offset of this type in the
1871  /// containing object. Some parameters are classified different
1872  /// depending on whether they straddle an eightbyte boundary.
1873  ///
1874  /// \param isNamedArg - Whether the argument in question is a "named"
1875  /// argument, as used in AMD64-ABI 3.5.7.
1876  ///
1877  /// If a word is unused its result will be NoClass; if a type should
1878  /// be passed in Memory then at least the classification of \arg Lo
1879  /// will be Memory.
1880  ///
1881  /// The \arg Lo class will be NoClass iff the argument is ignored.
1882  ///
1883  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1884  /// also be ComplexX87.
1885  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1886  bool isNamedArg) const;
1887 
1888  llvm::Type *GetByteVectorType(QualType Ty) const;
1889  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
1890  unsigned IROffset, QualType SourceTy,
1891  unsigned SourceOffset) const;
1892  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
1893  unsigned IROffset, QualType SourceTy,
1894  unsigned SourceOffset) const;
1895 
1896  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1897  /// such that the argument will be returned in memory.
1898  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
1899 
1900  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1901  /// such that the argument will be passed in memory.
1902  ///
1903  /// \param freeIntRegs - The number of free integer registers remaining
1904  /// available.
1905  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
1906 
1907  ABIArgInfo classifyReturnType(QualType RetTy) const;
1908 
1910  unsigned freeIntRegs,
1911  unsigned &neededInt,
1912  unsigned &neededSSE,
1913  bool isNamedArg) const;
1914 
1915  bool IsIllegalVectorType(QualType Ty) const;
1916 
1917  /// The 0.98 ABI revision clarified a lot of ambiguities,
1918  /// unfortunately in ways that were not always consistent with
1919  /// certain previous compilers. In particular, platforms which
1920  /// required strict binary compatibility with older versions of GCC
1921  /// may need to exempt themselves.
1922  bool honorsRevision0_98() const {
1923  return !getTarget().getTriple().isOSDarwin();
1924  }
1925 
1926  /// GCC classifies <1 x long long> as SSE but compatibility with older clang
1927  // compilers require us to classify it as INTEGER.
1928  bool classifyIntegerMMXAsSSE() const {
1929  const llvm::Triple &Triple = getTarget().getTriple();
1930  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
1931  return false;
1932  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
1933  return false;
1934  return true;
1935  }
1936 
1937  X86AVXABILevel AVXLevel;
1938  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
1939  // 64-bit hardware.
1940  bool Has64BitPointers;
1941 
1942 public:
1943  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
1944  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
1945  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
1946  }
1947 
1948  bool isPassedUsingAVXType(QualType type) const {
1949  unsigned neededInt, neededSSE;
1950  // The freeIntRegs argument doesn't matter here.
1951  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
1952  /*isNamedArg*/true);
1953  if (info.isDirect()) {
1954  llvm::Type *ty = info.getCoerceToType();
1955  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
1956  return (vectorTy->getBitWidth() > 128);
1957  }
1958  return false;
1959  }
1960 
1961  void computeInfo(CGFunctionInfo &FI) const override;
1962 
1963  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1964  QualType Ty) const override;
1965  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
1966  QualType Ty) const override;
1967 
1968  bool has64BitPointers() const {
1969  return Has64BitPointers;
1970  }
1971 
1972  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
1973  ArrayRef<llvm::Type*> scalars,
1974  bool asReturnValue) const override {
1975  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
1976  }
1977 };
1978 
1979 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1980 class WinX86_64ABIInfo : public ABIInfo {
1981 public:
1982  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
1983  : ABIInfo(CGT),
1984  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
1985 
1986  void computeInfo(CGFunctionInfo &FI) const override;
1987 
1988  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1989  QualType Ty) const override;
1990 
1991  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1992  // FIXME: Assumes vectorcall is in use.
1993  return isX86VectorTypeForVectorCall(getContext(), Ty);
1994  }
1995 
1996  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1997  uint64_t NumMembers) const override {
1998  // FIXME: Assumes vectorcall is in use.
1999  return isX86VectorCallAggregateSmallEnough(NumMembers);
2000  }
2001 
2002 private:
2003  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
2004  bool IsReturnType) const;
2005 
2006  bool IsMingw64;
2007 };
2008 
2009 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2010 public:
2011  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2012  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2013 
2014  const X86_64ABIInfo &getABIInfo() const {
2015  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2016  }
2017 
2018  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2019  return 7;
2020  }
2021 
2022  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2023  llvm::Value *Address) const override {
2024  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2025 
2026  // 0-15 are the 16 integer registers.
2027  // 16 is %rip.
2028  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2029  return false;
2030  }
2031 
2032  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2033  StringRef Constraint,
2034  llvm::Type* Ty) const override {
2035  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2036  }
2037 
2038  bool isNoProtoCallVariadic(const CallArgList &args,
2039  const FunctionNoProtoType *fnType) const override {
2040  // The default CC on x86-64 sets %al to the number of SSA
2041  // registers used, and GCC sets this when calling an unprototyped
2042  // function, so we override the default behavior. However, don't do
2043  // that when AVX types are involved: the ABI explicitly states it is
2044  // undefined, and it doesn't work in practice because of how the ABI
2045  // defines varargs anyway.
2046  if (fnType->getCallConv() == CC_C) {
2047  bool HasAVXType = false;
2048  for (CallArgList::const_iterator
2049  it = args.begin(), ie = args.end(); it != ie; ++it) {
2050  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2051  HasAVXType = true;
2052  break;
2053  }
2054  }
2055 
2056  if (!HasAVXType)
2057  return true;
2058  }
2059 
2060  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2061  }
2062 
2063  llvm::Constant *
2064  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2065  unsigned Sig;
2066  if (getABIInfo().has64BitPointers())
2067  Sig = (0xeb << 0) | // jmp rel8
2068  (0x0a << 8) | // .+0x0c
2069  ('F' << 16) |
2070  ('T' << 24);
2071  else
2072  Sig = (0xeb << 0) | // jmp rel8
2073  (0x06 << 8) | // .+0x08
2074  ('F' << 16) |
2075  ('T' << 24);
2076  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2077  }
2078 
2079  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2080  CodeGen::CodeGenModule &CGM) const override {
2081  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2082  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2083  llvm::Function *Fn = cast<llvm::Function>(GV);
2084  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2085  }
2086  }
2087  }
2088 };
2089 
2090 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2091 public:
2092  PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2093  : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2094 
2095  void getDependentLibraryOption(llvm::StringRef Lib,
2096  llvm::SmallString<24> &Opt) const override {
2097  Opt = "\01";
2098  // If the argument contains a space, enclose it in quotes.
2099  if (Lib.find(" ") != StringRef::npos)
2100  Opt += "\"" + Lib.str() + "\"";
2101  else
2102  Opt += Lib;
2103  }
2104 };
2105 
2106 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2107  // If the argument does not end in .lib, automatically add the suffix.
2108  // If the argument contains a space, enclose it in quotes.
2109  // This matches the behavior of MSVC.
2110  bool Quote = (Lib.find(" ") != StringRef::npos);
2111  std::string ArgStr = Quote ? "\"" : "";
2112  ArgStr += Lib;
2113  if (!Lib.endswith_lower(".lib"))
2114  ArgStr += ".lib";
2115  ArgStr += Quote ? "\"" : "";
2116  return ArgStr;
2117 }
2118 
2119 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2120 public:
2121  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2122  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2123  unsigned NumRegisterParameters)
2124  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2125  Win32StructABI, NumRegisterParameters, false) {}
2126 
2127  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2128  CodeGen::CodeGenModule &CGM) const override;
2129 
2130  void getDependentLibraryOption(llvm::StringRef Lib,
2131  llvm::SmallString<24> &Opt) const override {
2132  Opt = "/DEFAULTLIB:";
2133  Opt += qualifyWindowsLibrary(Lib);
2134  }
2135 
2136  void getDetectMismatchOption(llvm::StringRef Name,
2137  llvm::StringRef Value,
2138  llvm::SmallString<32> &Opt) const override {
2139  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2140  }
2141 };
2142 
2143 static void addStackProbeSizeTargetAttribute(const Decl *D,
2144  llvm::GlobalValue *GV,
2145  CodeGen::CodeGenModule &CGM) {
2146  if (D && isa<FunctionDecl>(D)) {
2147  if (CGM.getCodeGenOpts().StackProbeSize != 4096) {
2148  llvm::Function *Fn = cast<llvm::Function>(GV);
2149 
2150  Fn->addFnAttr("stack-probe-size",
2151  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2152  }
2153  }
2154 }
2155 
2156 void WinX86_32TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2157  llvm::GlobalValue *GV,
2158  CodeGen::CodeGenModule &CGM) const {
2159  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2160 
2161  addStackProbeSizeTargetAttribute(D, GV, CGM);
2162 }
2163 
2164 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2165 public:
2166  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2167  X86AVXABILevel AVXLevel)
2168  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2169 
2170  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2171  CodeGen::CodeGenModule &CGM) const override;
2172 
2173  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2174  return 7;
2175  }
2176 
2177  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2178  llvm::Value *Address) const override {
2179  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2180 
2181  // 0-15 are the 16 integer registers.
2182  // 16 is %rip.
2183  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2184  return false;
2185  }
2186 
2187  void getDependentLibraryOption(llvm::StringRef Lib,
2188  llvm::SmallString<24> &Opt) const override {
2189  Opt = "/DEFAULTLIB:";
2190  Opt += qualifyWindowsLibrary(Lib);
2191  }
2192 
2193  void getDetectMismatchOption(llvm::StringRef Name,
2194  llvm::StringRef Value,
2195  llvm::SmallString<32> &Opt) const override {
2196  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2197  }
2198 };
2199 
2200 void WinX86_64TargetCodeGenInfo::setTargetAttributes(const Decl *D,
2201  llvm::GlobalValue *GV,
2202  CodeGen::CodeGenModule &CGM) const {
2204 
2205  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2206  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2207  llvm::Function *Fn = cast<llvm::Function>(GV);
2208  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2209  }
2210  }
2211 
2212  addStackProbeSizeTargetAttribute(D, GV, CGM);
2213 }
2214 }
2215 
2216 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2217  Class &Hi) const {
2218  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2219  //
2220  // (a) If one of the classes is Memory, the whole argument is passed in
2221  // memory.
2222  //
2223  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2224  // memory.
2225  //
2226  // (c) If the size of the aggregate exceeds two eightbytes and the first
2227  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2228  // argument is passed in memory. NOTE: This is necessary to keep the
2229  // ABI working for processors that don't support the __m256 type.
2230  //
2231  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2232  //
2233  // Some of these are enforced by the merging logic. Others can arise
2234  // only with unions; for example:
2235  // union { _Complex double; unsigned; }
2236  //
2237  // Note that clauses (b) and (c) were added in 0.98.
2238  //
2239  if (Hi == Memory)
2240  Lo = Memory;
2241  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2242  Lo = Memory;
2243  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2244  Lo = Memory;
2245  if (Hi == SSEUp && Lo != SSE)
2246  Hi = SSE;
2247 }
2248 
2249 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2250  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2251  // classified recursively so that always two fields are
2252  // considered. The resulting class is calculated according to
2253  // the classes of the fields in the eightbyte:
2254  //
2255  // (a) If both classes are equal, this is the resulting class.
2256  //
2257  // (b) If one of the classes is NO_CLASS, the resulting class is
2258  // the other class.
2259  //
2260  // (c) If one of the classes is MEMORY, the result is the MEMORY
2261  // class.
2262  //
2263  // (d) If one of the classes is INTEGER, the result is the
2264  // INTEGER.
2265  //
2266  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2267  // MEMORY is used as class.
2268  //
2269  // (f) Otherwise class SSE is used.
2270 
2271  // Accum should never be memory (we should have returned) or
2272  // ComplexX87 (because this cannot be passed in a structure).
2273  assert((Accum != Memory && Accum != ComplexX87) &&
2274  "Invalid accumulated classification during merge.");
2275  if (Accum == Field || Field == NoClass)
2276  return Accum;
2277  if (Field == Memory)
2278  return Memory;
2279  if (Accum == NoClass)
2280  return Field;
2281  if (Accum == Integer || Field == Integer)
2282  return Integer;
2283  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2284  Accum == X87 || Accum == X87Up)
2285  return Memory;
2286  return SSE;
2287 }
2288 
2289 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2290  Class &Lo, Class &Hi, bool isNamedArg) const {
2291  // FIXME: This code can be simplified by introducing a simple value class for
2292  // Class pairs with appropriate constructor methods for the various
2293  // situations.
2294 
2295  // FIXME: Some of the split computations are wrong; unaligned vectors
2296  // shouldn't be passed in registers for example, so there is no chance they
2297  // can straddle an eightbyte. Verify & simplify.
2298 
2299  Lo = Hi = NoClass;
2300 
2301  Class &Current = OffsetBase < 64 ? Lo : Hi;
2302  Current = Memory;
2303 
2304  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2305  BuiltinType::Kind k = BT->getKind();
2306 
2307  if (k == BuiltinType::Void) {
2308  Current = NoClass;
2309  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2310  Lo = Integer;
2311  Hi = Integer;
2312  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2313  Current = Integer;
2314  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2315  Current = SSE;
2316  } else if (k == BuiltinType::LongDouble) {
2317  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2318  if (LDF == &llvm::APFloat::IEEEquad) {
2319  Lo = SSE;
2320  Hi = SSEUp;
2321  } else if (LDF == &llvm::APFloat::x87DoubleExtended) {
2322  Lo = X87;
2323  Hi = X87Up;
2324  } else if (LDF == &llvm::APFloat::IEEEdouble) {
2325  Current = SSE;
2326  } else
2327  llvm_unreachable("unexpected long double representation!");
2328  }
2329  // FIXME: _Decimal32 and _Decimal64 are SSE.
2330  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2331  return;
2332  }
2333 
2334  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2335  // Classify the underlying integer type.
2336  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2337  return;
2338  }
2339 
2340  if (Ty->hasPointerRepresentation()) {
2341  Current = Integer;
2342  return;
2343  }
2344 
2345  if (Ty->isMemberPointerType()) {
2346  if (Ty->isMemberFunctionPointerType()) {
2347  if (Has64BitPointers) {
2348  // If Has64BitPointers, this is an {i64, i64}, so classify both
2349  // Lo and Hi now.
2350  Lo = Hi = Integer;
2351  } else {
2352  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2353  // straddles an eightbyte boundary, Hi should be classified as well.
2354  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2355  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2356  if (EB_FuncPtr != EB_ThisAdj) {
2357  Lo = Hi = Integer;
2358  } else {
2359  Current = Integer;
2360  }
2361  }
2362  } else {
2363  Current = Integer;
2364  }
2365  return;
2366  }
2367 
2368  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2369  uint64_t Size = getContext().getTypeSize(VT);
2370  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2371  // gcc passes the following as integer:
2372  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2373  // 2 bytes - <2 x char>, <1 x short>
2374  // 1 byte - <1 x char>
2375  Current = Integer;
2376 
2377  // If this type crosses an eightbyte boundary, it should be
2378  // split.
2379  uint64_t EB_Lo = (OffsetBase) / 64;
2380  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2381  if (EB_Lo != EB_Hi)
2382  Hi = Lo;
2383  } else if (Size == 64) {
2384  QualType ElementType = VT->getElementType();
2385 
2386  // gcc passes <1 x double> in memory. :(
2387  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2388  return;
2389 
2390  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2391  // pass them as integer. For platforms where clang is the de facto
2392  // platform compiler, we must continue to use integer.
2393  if (!classifyIntegerMMXAsSSE() &&
2394  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2395  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2396  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2397  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2398  Current = Integer;
2399  else
2400  Current = SSE;
2401 
2402  // If this type crosses an eightbyte boundary, it should be
2403  // split.
2404  if (OffsetBase && OffsetBase != 64)
2405  Hi = Lo;
2406  } else if (Size == 128 ||
2407  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2408  // Arguments of 256-bits are split into four eightbyte chunks. The
2409  // least significant one belongs to class SSE and all the others to class
2410  // SSEUP. The original Lo and Hi design considers that types can't be
2411  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2412  // This design isn't correct for 256-bits, but since there're no cases
2413  // where the upper parts would need to be inspected, avoid adding
2414  // complexity and just consider Hi to match the 64-256 part.
2415  //
2416  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2417  // registers if they are "named", i.e. not part of the "..." of a
2418  // variadic function.
2419  //
2420  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2421  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2422  Lo = SSE;
2423  Hi = SSEUp;
2424  }
2425  return;
2426  }
2427 
2428  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2429  QualType ET = getContext().getCanonicalType(CT->getElementType());
2430 
2431  uint64_t Size = getContext().getTypeSize(Ty);
2432  if (ET->isIntegralOrEnumerationType()) {
2433  if (Size <= 64)
2434  Current = Integer;
2435  else if (Size <= 128)
2436  Lo = Hi = Integer;
2437  } else if (ET == getContext().FloatTy) {
2438  Current = SSE;
2439  } else if (ET == getContext().DoubleTy) {
2440  Lo = Hi = SSE;
2441  } else if (ET == getContext().LongDoubleTy) {
2442  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2443  if (LDF == &llvm::APFloat::IEEEquad)
2444  Current = Memory;
2445  else if (LDF == &llvm::APFloat::x87DoubleExtended)
2446  Current = ComplexX87;
2447  else if (LDF == &llvm::APFloat::IEEEdouble)
2448  Lo = Hi = SSE;
2449  else
2450  llvm_unreachable("unexpected long double representation!");
2451  }
2452 
2453  // If this complex type crosses an eightbyte boundary then it
2454  // should be split.
2455  uint64_t EB_Real = (OffsetBase) / 64;
2456  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2457  if (Hi == NoClass && EB_Real != EB_Imag)
2458  Hi = Lo;
2459 
2460  return;
2461  }
2462 
2463  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2464  // Arrays are treated like structures.
2465 
2466  uint64_t Size = getContext().getTypeSize(Ty);
2467 
2468  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2469  // than four eightbytes, ..., it has class MEMORY.
2470  if (Size > 256)
2471  return;
2472 
2473  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2474  // fields, it has class MEMORY.
2475  //
2476  // Only need to check alignment of array base.
2477  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2478  return;
2479 
2480  // Otherwise implement simplified merge. We could be smarter about
2481  // this, but it isn't worth it and would be harder to verify.
2482  Current = NoClass;
2483  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2484  uint64_t ArraySize = AT->getSize().getZExtValue();
2485 
2486  // The only case a 256-bit wide vector could be used is when the array
2487  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2488  // to work for sizes wider than 128, early check and fallback to memory.
2489  if (Size > 128 && EltSize != 256)
2490  return;
2491 
2492  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2493  Class FieldLo, FieldHi;
2494  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2495  Lo = merge(Lo, FieldLo);
2496  Hi = merge(Hi, FieldHi);
2497  if (Lo == Memory || Hi == Memory)
2498  break;
2499  }
2500 
2501  postMerge(Size, Lo, Hi);
2502  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2503  return;
2504  }
2505 
2506  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2507  uint64_t Size = getContext().getTypeSize(Ty);
2508 
2509  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2510  // than four eightbytes, ..., it has class MEMORY.
2511  if (Size > 256)
2512  return;
2513 
2514  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2515  // copy constructor or a non-trivial destructor, it is passed by invisible
2516  // reference.
2517  if (getRecordArgABI(RT, getCXXABI()))
2518  return;
2519 
2520  const RecordDecl *RD = RT->getDecl();
2521 
2522  // Assume variable sized types are passed in memory.
2523  if (RD->hasFlexibleArrayMember())
2524  return;
2525 
2526  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2527 
2528  // Reset Lo class, this will be recomputed.
2529  Current = NoClass;
2530 
2531  // If this is a C++ record, classify the bases first.
2532  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2533  for (const auto &I : CXXRD->bases()) {
2534  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2535  "Unexpected base class!");
2536  const CXXRecordDecl *Base =
2537  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2538 
2539  // Classify this field.
2540  //
2541  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2542  // single eightbyte, each is classified separately. Each eightbyte gets
2543  // initialized to class NO_CLASS.
2544  Class FieldLo, FieldHi;
2545  uint64_t Offset =
2546  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2547  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2548  Lo = merge(Lo, FieldLo);
2549  Hi = merge(Hi, FieldHi);
2550  if (Lo == Memory || Hi == Memory) {
2551  postMerge(Size, Lo, Hi);
2552  return;
2553  }
2554  }
2555  }
2556 
2557  // Classify the fields one at a time, merging the results.
2558  unsigned idx = 0;
2559  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2560  i != e; ++i, ++idx) {
2561  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2562  bool BitField = i->isBitField();
2563 
2564  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2565  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2566  //
2567  // The only case a 256-bit wide vector could be used is when the struct
2568  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2569  // to work for sizes wider than 128, early check and fallback to memory.
2570  //
2571  if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
2572  Lo = Memory;
2573  postMerge(Size, Lo, Hi);
2574  return;
2575  }
2576  // Note, skip this test for bit-fields, see below.
2577  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2578  Lo = Memory;
2579  postMerge(Size, Lo, Hi);
2580  return;
2581  }
2582 
2583  // Classify this field.
2584  //
2585  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2586  // exceeds a single eightbyte, each is classified
2587  // separately. Each eightbyte gets initialized to class
2588  // NO_CLASS.
2589  Class FieldLo, FieldHi;
2590 
2591  // Bit-fields require special handling, they do not force the
2592  // structure to be passed in memory even if unaligned, and
2593  // therefore they can straddle an eightbyte.
2594  if (BitField) {
2595  // Ignore padding bit-fields.
2596  if (i->isUnnamedBitfield())
2597  continue;
2598 
2599  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2600  uint64_t Size = i->getBitWidthValue(getContext());
2601 
2602  uint64_t EB_Lo = Offset / 64;
2603  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2604 
2605  if (EB_Lo) {
2606  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2607  FieldLo = NoClass;
2608  FieldHi = Integer;
2609  } else {
2610  FieldLo = Integer;
2611  FieldHi = EB_Hi ? Integer : NoClass;
2612  }
2613  } else
2614  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2615  Lo = merge(Lo, FieldLo);
2616  Hi = merge(Hi, FieldHi);
2617  if (Lo == Memory || Hi == Memory)
2618  break;
2619  }
2620 
2621  postMerge(Size, Lo, Hi);
2622  }
2623 }
2624 
2625 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2626  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2627  // place naturally.
2628  if (!isAggregateTypeForABI(Ty)) {
2629  // Treat an enum type as its underlying type.
2630  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2631  Ty = EnumTy->getDecl()->getIntegerType();
2632 
2633  return (Ty->isPromotableIntegerType() ?
2634  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2635  }
2636 
2637  return getNaturalAlignIndirect(Ty);
2638 }
2639 
2640 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2641  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2642  uint64_t Size = getContext().getTypeSize(VecTy);
2643  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2644  if (Size <= 64 || Size > LargestVector)
2645  return true;
2646  }
2647 
2648  return false;
2649 }
2650 
2651 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2652  unsigned freeIntRegs) const {
2653  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2654  // place naturally.
2655  //
2656  // This assumption is optimistic, as there could be free registers available
2657  // when we need to pass this argument in memory, and LLVM could try to pass
2658  // the argument in the free register. This does not seem to happen currently,
2659  // but this code would be much safer if we could mark the argument with
2660  // 'onstack'. See PR12193.
2661  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2662  // Treat an enum type as its underlying type.
2663  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2664  Ty = EnumTy->getDecl()->getIntegerType();
2665 
2666  return (Ty->isPromotableIntegerType() ?
2667  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
2668  }
2669 
2670  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
2671  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
2672 
2673  // Compute the byval alignment. We specify the alignment of the byval in all
2674  // cases so that the mid-level optimizer knows the alignment of the byval.
2675  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2676 
2677  // Attempt to avoid passing indirect results using byval when possible. This
2678  // is important for good codegen.
2679  //
2680  // We do this by coercing the value into a scalar type which the backend can
2681  // handle naturally (i.e., without using byval).
2682  //
2683  // For simplicity, we currently only do this when we have exhausted all of the
2684  // free integer registers. Doing this when there are free integer registers
2685  // would require more care, as we would have to ensure that the coerced value
2686  // did not claim the unused register. That would require either reording the
2687  // arguments to the function (so that any subsequent inreg values came first),
2688  // or only doing this optimization when there were no following arguments that
2689  // might be inreg.
2690  //
2691  // We currently expect it to be rare (particularly in well written code) for
2692  // arguments to be passed on the stack when there are still free integer
2693  // registers available (this would typically imply large structs being passed
2694  // by value), so this seems like a fair tradeoff for now.
2695  //
2696  // We can revisit this if the backend grows support for 'onstack' parameter
2697  // attributes. See PR12193.
2698  if (freeIntRegs == 0) {
2699  uint64_t Size = getContext().getTypeSize(Ty);
2700 
2701  // If this type fits in an eightbyte, coerce it into the matching integral
2702  // type, which will end up on the stack (with alignment 8).
2703  if (Align == 8 && Size <= 64)
2704  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2705  Size));
2706  }
2707 
2709 }
2710 
2711 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2712 /// register. Pick an LLVM IR type that will be passed as a vector register.
2713 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2714  // Wrapper structs/arrays that only contain vectors are passed just like
2715  // vectors; strip them off if present.
2716  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2717  Ty = QualType(InnerTy, 0);
2718 
2719  llvm::Type *IRType = CGT.ConvertType(Ty);
2720  if (isa<llvm::VectorType>(IRType) ||
2721  IRType->getTypeID() == llvm::Type::FP128TyID)
2722  return IRType;
2723 
2724  // We couldn't find the preferred IR vector type for 'Ty'.
2725  uint64_t Size = getContext().getTypeSize(Ty);
2726  assert((Size == 128 || Size == 256) && "Invalid type found!");
2727 
2728  // Return a LLVM IR vector type based on the size of 'Ty'.
2729  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2730  Size / 64);
2731 }
2732 
2733 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2734 /// is known to either be off the end of the specified type or being in
2735 /// alignment padding. The user type specified is known to be at most 128 bits
2736 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2737 /// classification that put one of the two halves in the INTEGER class.
2738 ///
2739 /// It is conservatively correct to return false.
2740 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2741  unsigned EndBit, ASTContext &Context) {
2742  // If the bytes being queried are off the end of the type, there is no user
2743  // data hiding here. This handles analysis of builtins, vectors and other
2744  // types that don't contain interesting padding.
2745  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2746  if (TySize <= StartBit)
2747  return true;
2748 
2749  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2750  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2751  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2752 
2753  // Check each element to see if the element overlaps with the queried range.
2754  for (unsigned i = 0; i != NumElts; ++i) {
2755  // If the element is after the span we care about, then we're done..
2756  unsigned EltOffset = i*EltSize;
2757  if (EltOffset >= EndBit) break;
2758 
2759  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2760  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2761  EndBit-EltOffset, Context))
2762  return false;
2763  }
2764  // If it overlaps no elements, then it is safe to process as padding.
2765  return true;
2766  }
2767 
2768  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2769  const RecordDecl *RD = RT->getDecl();
2770  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
2771 
2772  // If this is a C++ record, check the bases first.
2773  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2774  for (const auto &I : CXXRD->bases()) {
2775  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2776  "Unexpected base class!");
2777  const CXXRecordDecl *Base =
2778  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2779 
2780  // If the base is after the span we care about, ignore it.
2781  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
2782  if (BaseOffset >= EndBit) continue;
2783 
2784  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2785  if (!BitsContainNoUserData(I.getType(), BaseStart,
2786  EndBit-BaseOffset, Context))
2787  return false;
2788  }
2789  }
2790 
2791  // Verify that no field has data that overlaps the region of interest. Yes
2792  // this could be sped up a lot by being smarter about queried fields,
2793  // however we're only looking at structs up to 16 bytes, so we don't care
2794  // much.
2795  unsigned idx = 0;
2796  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2797  i != e; ++i, ++idx) {
2798  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
2799 
2800  // If we found a field after the region we care about, then we're done.
2801  if (FieldOffset >= EndBit) break;
2802 
2803  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2804  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2805  Context))
2806  return false;
2807  }
2808 
2809  // If nothing in this record overlapped the area of interest, then we're
2810  // clean.
2811  return true;
2812  }
2813 
2814  return false;
2815 }
2816 
2817 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
2818 /// float member at the specified offset. For example, {int,{float}} has a
2819 /// float at offset 4. It is conservatively correct for this routine to return
2820 /// false.
2821 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
2822  const llvm::DataLayout &TD) {
2823  // Base case if we find a float.
2824  if (IROffset == 0 && IRType->isFloatTy())
2825  return true;
2826 
2827  // If this is a struct, recurse into the field at the specified offset.
2828  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2829  const llvm::StructLayout *SL = TD.getStructLayout(STy);
2830  unsigned Elt = SL->getElementContainingOffset(IROffset);
2831  IROffset -= SL->getElementOffset(Elt);
2832  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
2833  }
2834 
2835  // If this is an array, recurse into the field at the specified offset.
2836  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2837  llvm::Type *EltTy = ATy->getElementType();
2838  unsigned EltSize = TD.getTypeAllocSize(EltTy);
2839  IROffset -= IROffset/EltSize*EltSize;
2840  return ContainsFloatAtOffset(EltTy, IROffset, TD);
2841  }
2842 
2843  return false;
2844 }
2845 
2846 
2847 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2848 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2849 llvm::Type *X86_64ABIInfo::
2850 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2851  QualType SourceTy, unsigned SourceOffset) const {
2852  // The only three choices we have are either double, <2 x float>, or float. We
2853  // pass as float if the last 4 bytes is just padding. This happens for
2854  // structs that contain 3 floats.
2855  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
2856  SourceOffset*8+64, getContext()))
2857  return llvm::Type::getFloatTy(getVMContext());
2858 
2859  // We want to pass as <2 x float> if the LLVM IR type contains a float at
2860  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
2861  // case.
2862  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
2863  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
2864  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
2865 
2866  return llvm::Type::getDoubleTy(getVMContext());
2867 }
2868 
2869 
2870 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2871 /// an 8-byte GPR. This means that we either have a scalar or we are talking
2872 /// about the high or low part of an up-to-16-byte struct. This routine picks
2873 /// the best LLVM IR type to represent this, which may be i64 or may be anything
2874 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
2875 /// etc).
2876 ///
2877 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
2878 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
2879 /// the 8-byte value references. PrefType may be null.
2880 ///
2881 /// SourceTy is the source-level type for the entire argument. SourceOffset is
2882 /// an offset into this that we're processing (which is always either 0 or 8).
2883 ///
2884 llvm::Type *X86_64ABIInfo::
2885 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
2886  QualType SourceTy, unsigned SourceOffset) const {
2887  // If we're dealing with an un-offset LLVM IR type, then it means that we're
2888  // returning an 8-byte unit starting with it. See if we can safely use it.
2889  if (IROffset == 0) {
2890  // Pointers and int64's always fill the 8-byte unit.
2891  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
2892  IRType->isIntegerTy(64))
2893  return IRType;
2894 
2895  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2896  // goodness in the source type is just tail padding. This is allowed to
2897  // kick in for struct {double,int} on the int, but not on
2898  // struct{double,int,int} because we wouldn't return the second int. We
2899  // have to do this analysis on the source type because we can't depend on
2900  // unions being lowered a specific way etc.
2901  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2902  IRType->isIntegerTy(32) ||
2903  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
2904  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
2905  cast<llvm::IntegerType>(IRType)->getBitWidth();
2906 
2907  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
2908  SourceOffset*8+64, getContext()))
2909  return IRType;
2910  }
2911  }
2912 
2913  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
2914  // If this is a struct, recurse into the field at the specified offset.
2915  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
2916  if (IROffset < SL->getSizeInBytes()) {
2917  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2918  IROffset -= SL->getElementOffset(FieldIdx);
2919 
2920  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2921  SourceTy, SourceOffset);
2922  }
2923  }
2924 
2925  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
2926  llvm::Type *EltTy = ATy->getElementType();
2927  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
2928  unsigned EltOffset = IROffset/EltSize*EltSize;
2929  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2930  SourceOffset);
2931  }
2932 
2933  // Okay, we don't have any better idea of what to pass, so we pass this in an
2934  // integer register that isn't too big to fit the rest of the struct.
2935  unsigned TySizeInBytes =
2936  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
2937 
2938  assert(TySizeInBytes != SourceOffset && "Empty field?");
2939 
2940  // It is always safe to classify this as an integer type up to i64 that
2941  // isn't larger than the structure.
2942  return llvm::IntegerType::get(getVMContext(),
2943  std::min(TySizeInBytes-SourceOffset, 8U)*8);
2944 }
2945 
2946 
2947 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2948 /// be used as elements of a two register pair to pass or return, return a
2949 /// first class aggregate to represent them. For example, if the low part of
2950 /// a by-value argument should be passed as i32* and the high part as float,
2951 /// return {i32*, float}.
2952 static llvm::Type *
2954  const llvm::DataLayout &TD) {
2955  // In order to correctly satisfy the ABI, we need to the high part to start
2956  // at offset 8. If the high and low parts we inferred are both 4-byte types
2957  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
2958  // the second element at offset 8. Check for this:
2959  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
2960  unsigned HiAlign = TD.getABITypeAlignment(Hi);
2961  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
2962  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2963 
2964  // To handle this, we have to increase the size of the low part so that the
2965  // second element will start at an 8 byte offset. We can't increase the size
2966  // of the second element because it might make us access off the end of the
2967  // struct.
2968  if (HiStart != 8) {
2969  // There are usually two sorts of types the ABI generation code can produce
2970  // for the low part of a pair that aren't 8 bytes in size: float or
2971  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
2972  // NaCl).
2973  // Promote these to a larger type.
2974  if (Lo->isFloatTy())
2975  Lo = llvm::Type::getDoubleTy(Lo->getContext());
2976  else {
2977  assert((Lo->isIntegerTy() || Lo->isPointerTy())
2978  && "Invalid/unknown lo type");
2979  Lo = llvm::Type::getInt64Ty(Lo->getContext());
2980  }
2981  }
2982 
2983  llvm::StructType *Result = llvm::StructType::get(Lo, Hi, nullptr);
2984 
2985 
2986  // Verify that the second element is at an 8-byte offset.
2987  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2988  "Invalid x86-64 argument pair!");
2989  return Result;
2990 }
2991 
2993 classifyReturnType(QualType RetTy) const {
2994  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2995  // classification algorithm.
2996  X86_64ABIInfo::Class Lo, Hi;
2997  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2998 
2999  // Check some invariants.
3000  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3001  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3002 
3003  llvm::Type *ResType = nullptr;
3004  switch (Lo) {
3005  case NoClass:
3006  if (Hi == NoClass)
3007  return ABIArgInfo::getIgnore();
3008  // If the low part is just padding, it takes no register, leave ResType
3009  // null.
3010  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3011  "Unknown missing lo part");
3012  break;
3013 
3014  case SSEUp:
3015  case X87Up:
3016  llvm_unreachable("Invalid classification for lo word.");
3017 
3018  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3019  // hidden argument.
3020  case Memory:
3021  return getIndirectReturnResult(RetTy);
3022 
3023  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3024  // available register of the sequence %rax, %rdx is used.
3025  case Integer:
3026  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3027 
3028  // If we have a sign or zero extended integer, make sure to return Extend
3029  // so that the parameter gets the right LLVM IR attributes.
3030  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3031  // Treat an enum type as its underlying type.
3032  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3033  RetTy = EnumTy->getDecl()->getIntegerType();
3034 
3035  if (RetTy->isIntegralOrEnumerationType() &&
3036  RetTy->isPromotableIntegerType())
3037  return ABIArgInfo::getExtend();
3038  }
3039  break;
3040 
3041  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3042  // available SSE register of the sequence %xmm0, %xmm1 is used.
3043  case SSE:
3044  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3045  break;
3046 
3047  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3048  // returned on the X87 stack in %st0 as 80-bit x87 number.
3049  case X87:
3050  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3051  break;
3052 
3053  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3054  // part of the value is returned in %st0 and the imaginary part in
3055  // %st1.
3056  case ComplexX87:
3057  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3058  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3059  llvm::Type::getX86_FP80Ty(getVMContext()),
3060  nullptr);
3061  break;
3062  }
3063 
3064  llvm::Type *HighPart = nullptr;
3065  switch (Hi) {
3066  // Memory was handled previously and X87 should
3067  // never occur as a hi class.
3068  case Memory:
3069  case X87:
3070  llvm_unreachable("Invalid classification for hi word.");
3071 
3072  case ComplexX87: // Previously handled.
3073  case NoClass:
3074  break;
3075 
3076  case Integer:
3077  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3078  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3079  return ABIArgInfo::getDirect(HighPart, 8);
3080  break;
3081  case SSE:
3082  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3083  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3084  return ABIArgInfo::getDirect(HighPart, 8);
3085  break;
3086 
3087  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3088  // is passed in the next available eightbyte chunk if the last used
3089  // vector register.
3090  //
3091  // SSEUP should always be preceded by SSE, just widen.
3092  case SSEUp:
3093  assert(Lo == SSE && "Unexpected SSEUp classification.");
3094  ResType = GetByteVectorType(RetTy);
3095  break;
3096 
3097  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3098  // returned together with the previous X87 value in %st0.
3099  case X87Up:
3100  // If X87Up is preceded by X87, we don't need to do
3101  // anything. However, in some cases with unions it may not be
3102  // preceded by X87. In such situations we follow gcc and pass the
3103  // extra bits in an SSE reg.
3104  if (Lo != X87) {
3105  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3106  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3107  return ABIArgInfo::getDirect(HighPart, 8);
3108  }
3109  break;
3110  }
3111 
3112  // If a high part was specified, merge it together with the low part. It is
3113  // known to pass in the high eightbyte of the result. We do this by forming a
3114  // first class struct aggregate with the high and low part: {low, high}
3115  if (HighPart)
3116  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3117 
3118  return ABIArgInfo::getDirect(ResType);
3119 }
3120 
3122  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3123  bool isNamedArg)
3124  const
3125 {
3127 
3128  X86_64ABIInfo::Class Lo, Hi;
3129  classify(Ty, 0, Lo, Hi, isNamedArg);
3130 
3131  // Check some invariants.
3132  // FIXME: Enforce these by construction.
3133  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3134  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3135 
3136  neededInt = 0;
3137  neededSSE = 0;
3138  llvm::Type *ResType = nullptr;
3139  switch (Lo) {
3140  case NoClass:
3141  if (Hi == NoClass)
3142  return ABIArgInfo::getIgnore();
3143  // If the low part is just padding, it takes no register, leave ResType
3144  // null.
3145  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3146  "Unknown missing lo part");
3147  break;
3148 
3149  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3150  // on the stack.
3151  case Memory:
3152 
3153  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3154  // COMPLEX_X87, it is passed in memory.
3155  case X87:
3156  case ComplexX87:
3157  if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
3158  ++neededInt;
3159  return getIndirectResult(Ty, freeIntRegs);
3160 
3161  case SSEUp:
3162  case X87Up:
3163  llvm_unreachable("Invalid classification for lo word.");
3164 
3165  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3166  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3167  // and %r9 is used.
3168  case Integer:
3169  ++neededInt;
3170 
3171  // Pick an 8-byte type based on the preferred type.
3172  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3173 
3174  // If we have a sign or zero extended integer, make sure to return Extend
3175  // so that the parameter gets the right LLVM IR attributes.
3176  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3177  // Treat an enum type as its underlying type.
3178  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3179  Ty = EnumTy->getDecl()->getIntegerType();
3180 
3181  if (Ty->isIntegralOrEnumerationType() &&
3183  return ABIArgInfo::getExtend();
3184  }
3185 
3186  break;
3187 
3188  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3189  // available SSE register is used, the registers are taken in the
3190  // order from %xmm0 to %xmm7.
3191  case SSE: {
3192  llvm::Type *IRType = CGT.ConvertType(Ty);
3193  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3194  ++neededSSE;
3195  break;
3196  }
3197  }
3198 
3199  llvm::Type *HighPart = nullptr;
3200  switch (Hi) {
3201  // Memory was handled previously, ComplexX87 and X87 should
3202  // never occur as hi classes, and X87Up must be preceded by X87,
3203  // which is passed in memory.
3204  case Memory:
3205  case X87:
3206  case ComplexX87:
3207  llvm_unreachable("Invalid classification for hi word.");
3208 
3209  case NoClass: break;
3210 
3211  case Integer:
3212  ++neededInt;
3213  // Pick an 8-byte type based on the preferred type.
3214  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3215 
3216  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3217  return ABIArgInfo::getDirect(HighPart, 8);
3218  break;
3219 
3220  // X87Up generally doesn't occur here (long double is passed in
3221  // memory), except in situations involving unions.
3222  case X87Up:
3223  case SSE:
3224  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3225 
3226  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3227  return ABIArgInfo::getDirect(HighPart, 8);
3228 
3229  ++neededSSE;
3230  break;
3231 
3232  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3233  // eightbyte is passed in the upper half of the last used SSE
3234  // register. This only happens when 128-bit vectors are passed.
3235  case SSEUp:
3236  assert(Lo == SSE && "Unexpected SSEUp classification");
3237  ResType = GetByteVectorType(Ty);
3238  break;
3239  }
3240 
3241  // If a high part was specified, merge it together with the low part. It is
3242  // known to pass in the high eightbyte of the result. We do this by forming a
3243  // first class struct aggregate with the high and low part: {low, high}
3244  if (HighPart)
3245  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3246 
3247  return ABIArgInfo::getDirect(ResType);
3248 }
3249 
3250 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3251 
3252  if (!getCXXABI().classifyReturnType(FI))
3254 
3255  // Keep track of the number of assigned registers.
3256  unsigned freeIntRegs = 6, freeSSERegs = 8;
3257 
3258  // If the return value is indirect, then the hidden argument is consuming one
3259  // integer register.
3260  if (FI.getReturnInfo().isIndirect())
3261  --freeIntRegs;
3262 
3263  // The chain argument effectively gives us another free register.
3264  if (FI.isChainCall())
3265  ++freeIntRegs;
3266 
3267  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3268  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3269  // get assigned (in left-to-right order) for passing as follows...
3270  unsigned ArgNo = 0;
3271  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3272  it != ie; ++it, ++ArgNo) {
3273  bool IsNamedArg = ArgNo < NumRequiredArgs;
3274 
3275  unsigned neededInt, neededSSE;
3276  it->info = classifyArgumentType(it->type, freeIntRegs, neededInt,
3277  neededSSE, IsNamedArg);
3278 
3279  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3280  // eightbyte of an argument, the whole argument is passed on the
3281  // stack. If registers have already been assigned for some
3282  // eightbytes of such an argument, the assignments get reverted.
3283  if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) {
3284  freeIntRegs -= neededInt;
3285  freeSSERegs -= neededSSE;
3286  } else {
3287  it->info = getIndirectResult(it->type, freeIntRegs);
3288  }
3289  }
3290 }
3291 
3293  Address VAListAddr, QualType Ty) {
3294  Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3295  VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3296  llvm::Value *overflow_arg_area =
3297  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3298 
3299  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3300  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3301  // It isn't stated explicitly in the standard, but in practice we use
3302  // alignment greater than 16 where necessary.
3303  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3304  if (Align > CharUnits::fromQuantity(8)) {
3305  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3306  Align);
3307  }
3308 
3309  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3310  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3311  llvm::Value *Res =
3312  CGF.Builder.CreateBitCast(overflow_arg_area,
3313  llvm::PointerType::getUnqual(LTy));
3314 
3315  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3316  // l->overflow_arg_area + sizeof(type).
3317  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3318  // an 8 byte boundary.
3319 
3320  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3321  llvm::Value *Offset =
3322  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3323  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3324  "overflow_arg_area.next");
3325  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3326 
3327  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3328  return Address(Res, Align);
3329 }
3330 
3331 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3332  QualType Ty) const {
3333  // Assume that va_list type is correct; should be pointer to LLVM type:
3334  // struct {
3335  // i32 gp_offset;
3336  // i32 fp_offset;
3337  // i8* overflow_arg_area;
3338  // i8* reg_save_area;
3339  // };
3340  unsigned neededInt, neededSSE;
3341 
3342  Ty = getContext().getCanonicalType(Ty);
3343  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3344  /*isNamedArg*/false);
3345 
3346  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3347  // in the registers. If not go to step 7.
3348  if (!neededInt && !neededSSE)
3349  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3350 
3351  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3352  // general purpose registers needed to pass type and num_fp to hold
3353  // the number of floating point registers needed.
3354 
3355  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3356  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3357  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3358  //
3359  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3360  // register save space).
3361 
3362  llvm::Value *InRegs = nullptr;
3363  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3364  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3365  if (neededInt) {
3366  gp_offset_p =
3367  CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3368  "gp_offset_p");
3369  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3370  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3371  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3372  }
3373 
3374  if (neededSSE) {
3375  fp_offset_p =
3376  CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3377  "fp_offset_p");
3378  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3379  llvm::Value *FitsInFP =
3380  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3381  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3382  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3383  }
3384 
3385  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3386  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3387  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3388  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3389 
3390  // Emit code to load the value if it was passed in registers.
3391 
3392  CGF.EmitBlock(InRegBlock);
3393 
3394  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3395  // an offset of l->gp_offset and/or l->fp_offset. This may require
3396  // copying to a temporary location in case the parameter is passed
3397  // in different register classes or requires an alignment greater
3398  // than 8 for general purpose registers and 16 for XMM registers.
3399  //
3400  // FIXME: This really results in shameful code when we end up needing to
3401  // collect arguments from different places; often what should result in a
3402  // simple assembling of a structure from scattered addresses has many more
3403  // loads than necessary. Can we clean this up?
3404  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3405  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3406  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3407  "reg_save_area");
3408 
3409  Address RegAddr = Address::invalid();
3410  if (neededInt && neededSSE) {
3411  // FIXME: Cleanup.
3412  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3413  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3414  Address Tmp = CGF.CreateMemTemp(Ty);
3415  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3416  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3417  llvm::Type *TyLo = ST->getElementType(0);
3418  llvm::Type *TyHi = ST->getElementType(1);
3419  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3420  "Unexpected ABI info for mixed regs");
3421  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3422  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3423  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3424  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3425  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3426  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3427 
3428  // Copy the first element.
3429  llvm::Value *V =
3431  CGF.Builder.CreateBitCast(RegLoAddr, PTyLo));
3432  CGF.Builder.CreateStore(V,
3433  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3434 
3435  // Copy the second element.
3437  CGF.Builder.CreateBitCast(RegHiAddr, PTyHi));
3439  getDataLayout().getStructLayout(ST)->getElementOffset(1));
3440  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3441 
3442  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3443  } else if (neededInt) {
3444  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3446  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3447 
3448  // Copy to a temporary if necessary to ensure the appropriate alignment.
3449  std::pair<CharUnits, CharUnits> SizeAlign =
3450  getContext().getTypeInfoInChars(Ty);
3451  uint64_t TySize = SizeAlign.first.getQuantity();
3452  CharUnits TyAlign = SizeAlign.second;
3453 
3454  // Copy into a temporary if the type is more aligned than the
3455  // register save area.
3456  if (TyAlign.getQuantity() > 8) {
3457  Address Tmp = CGF.CreateMemTemp(Ty);
3458  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3459  RegAddr = Tmp;
3460  }
3461 
3462  } else if (neededSSE == 1) {
3463  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3465  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3466  } else {
3467  assert(neededSSE == 2 && "Invalid number of needed registers!");
3468  // SSE registers are spaced 16 bytes apart in the register save
3469  // area, we need to collect the two eightbytes together.
3470  // The ABI isn't explicit about this, but it seems reasonable
3471  // to assume that the slots are 16-byte aligned, since the stack is
3472  // naturally 16-byte aligned and the prologue is expected to store
3473  // all the SSE registers to the RSA.
3474  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3476  Address RegAddrHi =
3477  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3479  llvm::Type *DoubleTy = CGF.DoubleTy;
3480  llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy, nullptr);
3481  llvm::Value *V;
3482  Address Tmp = CGF.CreateMemTemp(Ty);
3483  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3484  V = CGF.Builder.CreateLoad(
3485  CGF.Builder.CreateElementBitCast(RegAddrLo, DoubleTy));
3486  CGF.Builder.CreateStore(V,
3487  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3488  V = CGF.Builder.CreateLoad(
3489  CGF.Builder.CreateElementBitCast(RegAddrHi, DoubleTy));
3490  CGF.Builder.CreateStore(V,
3492 
3493  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3494  }
3495 
3496  // AMD64-ABI 3.5.7p5: Step 5. Set:
3497  // l->gp_offset = l->gp_offset + num_gp * 8
3498  // l->fp_offset = l->fp_offset + num_fp * 16.
3499  if (neededInt) {
3500  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3501  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3502  gp_offset_p);
3503  }
3504  if (neededSSE) {
3505  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3506  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3507  fp_offset_p);
3508  }
3509  CGF.EmitBranch(ContBlock);
3510 
3511  // Emit code to load the value if it was passed in memory.
3512 
3513  CGF.EmitBlock(InMemBlock);
3514  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3515 
3516  // Return the appropriate result.
3517 
3518  CGF.EmitBlock(ContBlock);
3519  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3520  "vaarg.addr");
3521  return ResAddr;
3522 }
3523 
3524 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3525  QualType Ty) const {
3526  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3527  CGF.getContext().getTypeInfoInChars(Ty),
3529  /*allowHigherAlign*/ false);
3530 }
3531 
3532 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3533  bool IsReturnType) const {
3534 
3535  if (Ty->isVoidType())
3536  return ABIArgInfo::getIgnore();
3537 
3538  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3539  Ty = EnumTy->getDecl()->getIntegerType();
3540 
3541  TypeInfo Info = getContext().getTypeInfo(Ty);
3542  uint64_t Width = Info.Width;
3543  CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
3544 
3545  const RecordType *RT = Ty->getAs<RecordType>();
3546  if (RT) {
3547  if (!IsReturnType) {
3548  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
3549  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
3550  }
3551 
3552  if (RT->getDecl()->hasFlexibleArrayMember())
3553  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3554 
3555  }
3556 
3557  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3558  // other targets.
3559  const Type *Base = nullptr;
3560  uint64_t NumElts = 0;
3561  if (FreeSSERegs && isHomogeneousAggregate(Ty, Base, NumElts)) {
3562  if (FreeSSERegs >= NumElts) {
3563  FreeSSERegs -= NumElts;
3564  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3565  return ABIArgInfo::getDirect();
3566  return ABIArgInfo::getExpand();
3567  }
3568  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3569  }
3570 
3571 
3572  if (Ty->isMemberPointerType()) {
3573  // If the member pointer is represented by an LLVM int or ptr, pass it
3574  // directly.
3575  llvm::Type *LLTy = CGT.ConvertType(Ty);
3576  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3577  return ABIArgInfo::getDirect();
3578  }
3579 
3580  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3581  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3582  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3583  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3584  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3585 
3586  // Otherwise, coerce it to a small integer.
3587  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3588  }
3589 
3590  // Bool type is always extended to the ABI, other builtin types are not
3591  // extended.
3592  const BuiltinType *BT = Ty->getAs<BuiltinType>();
3593  if (BT && BT->getKind() == BuiltinType::Bool)
3594  return ABIArgInfo::getExtend();
3595 
3596  // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3597  // passes them indirectly through memory.
3598  if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3599  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3600  if (LDF == &llvm::APFloat::x87DoubleExtended)
3601  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3602  }
3603 
3604  return ABIArgInfo::getDirect();
3605 }
3606 
3607 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3608  bool IsVectorCall =
3609  FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3610 
3611  // We can use up to 4 SSE return registers with vectorcall.
3612  unsigned FreeSSERegs = IsVectorCall ? 4 : 0;
3613  if (!getCXXABI().classifyReturnType(FI))
3614  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true);
3615 
3616  // We can use up to 6 SSE register parameters with vectorcall.
3617  FreeSSERegs = IsVectorCall ? 6 : 0;
3618  for (auto &I : FI.arguments())
3619  I.info = classify(I.type, FreeSSERegs, false);
3620 }
3621 
3622 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3623  QualType Ty) const {
3624  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3625  CGF.getContext().getTypeInfoInChars(Ty),
3627  /*allowHigherAlign*/ false);
3628 }
3629 
3630 // PowerPC-32
3631 namespace {
3632 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
3633 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
3634 bool IsSoftFloatABI;
3635 public:
3636  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
3637  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
3638 
3639  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3640  QualType Ty) const override;
3641 };
3642 
3643 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
3644 public:
3645  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
3646  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
3647 
3648  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3649  // This is recovered from gcc output.
3650  return 1; // r1 is the dedicated stack pointer
3651  }
3652 
3653  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3654  llvm::Value *Address) const override;
3655 };
3656 
3657 }
3658 
3659 // TODO: this implementation is now likely redundant with
3660 // DefaultABIInfo::EmitVAArg.
3661 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
3662  QualType Ty) const {
3663  const unsigned OverflowLimit = 8;
3664  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
3665  // TODO: Implement this. For now ignore.
3666  (void)CTy;
3667  return Address::invalid(); // FIXME?
3668  }
3669 
3670  // struct __va_list_tag {
3671  // unsigned char gpr;
3672  // unsigned char fpr;
3673  // unsigned short reserved;
3674  // void *overflow_arg_area;
3675  // void *reg_save_area;
3676  // };
3677 
3678  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
3679  bool isInt =
3680  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
3681  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
3682 
3683  // All aggregates are passed indirectly? That doesn't seem consistent
3684  // with the argument-lowering code.
3685  bool isIndirect = Ty->isAggregateType();
3686 
3687  CGBuilderTy &Builder = CGF.Builder;
3688 
3689  // The calling convention either uses 1-2 GPRs or 1 FPR.
3690  Address NumRegsAddr = Address::invalid();
3691  if (isInt || IsSoftFloatABI) {
3692  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
3693  } else {
3694  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
3695  }
3696 
3697  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
3698 
3699  // "Align" the register count when TY is i64.
3700  if (isI64 || (isF64 && IsSoftFloatABI)) {
3701  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
3702  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
3703  }
3704 
3705  llvm::Value *CC =
3706  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
3707 
3708  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
3709  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
3710  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
3711 
3712  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
3713 
3714  llvm::Type *DirectTy = CGF.ConvertType(Ty);
3715  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
3716 
3717  // Case 1: consume registers.
3718  Address RegAddr = Address::invalid();
3719  {
3720  CGF.EmitBlock(UsingRegs);
3721 
3722  Address RegSaveAreaPtr =
3723  Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
3724  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
3726  assert(RegAddr.getElementType() == CGF.Int8Ty);
3727 
3728  // Floating-point registers start after the general-purpose registers.
3729  if (!(isInt || IsSoftFloatABI)) {
3730  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
3732  }
3733 
3734  // Get the address of the saved value by scaling the number of
3735  // registers we've used by the number of
3736  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
3737  llvm::Value *RegOffset =
3738  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
3739  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
3740  RegAddr.getPointer(), RegOffset),
3741  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
3742  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
3743 
3744  // Increase the used-register count.
3745  NumRegs =
3746  Builder.CreateAdd(NumRegs,
3747  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
3748  Builder.CreateStore(NumRegs, NumRegsAddr);
3749 
3750  CGF.EmitBranch(Cont);
3751  }
3752 
3753  // Case 2: consume space in the overflow area.
3754  Address MemAddr = Address::invalid();
3755  {
3756  CGF.EmitBlock(UsingOverflow);
3757 
3758  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
3759 
3760  // Everything in the overflow area is rounded up to a size of at least 4.
3761  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
3762 
3763  CharUnits Size;
3764  if (!isIndirect) {
3765  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
3766  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
3767  } else {
3768  Size = CGF.getPointerSize();
3769  }
3770 
3771  Address OverflowAreaAddr =
3772  Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
3773  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
3774  OverflowAreaAlign);
3775  // Round up address of argument to alignment
3776  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3777  if (Align > OverflowAreaAlign) {
3778  llvm::Value *Ptr = OverflowArea.getPointer();
3779  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
3780  Align);
3781  }
3782 
3783  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
3784 
3785  // Increase the overflow area.
3786  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
3787  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
3788  CGF.EmitBranch(Cont);
3789  }
3790 
3791  CGF.EmitBlock(Cont);
3792 
3793  // Merge the cases with a phi.
3794  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
3795  "vaarg.addr");
3796 
3797  // Load the pointer if the argument was passed indirectly.
3798  if (isIndirect) {
3799  Result = Address(Builder.CreateLoad(Result, "aggr"),
3800  getContext().getTypeAlignInChars(Ty));
3801  }
3802 
3803  return Result;
3804 }
3805 
3806 bool
3807 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3808  llvm::Value *Address) const {
3809  // This is calculated from the LLVM and GCC tables and verified
3810  // against gcc output. AFAIK all ABIs use the same encoding.
3811 
3812  CodeGen::CGBuilderTy &Builder = CGF.Builder;
3813 
3814  llvm::IntegerType *i8 = CGF.Int8Ty;
3815  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
3816  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
3817  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
3818 
3819  // 0-31: r0-31, the 4-byte general-purpose registers
3820  AssignToArrayRange(Builder, Address, Four8, 0, 31);
3821 
3822  // 32-63: fp0-31, the 8-byte floating-point registers
3823  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
3824 
3825  // 64-76 are various 4-byte special-purpose registers:
3826  // 64: mq
3827  // 65: lr
3828  // 66: ctr
3829  // 67: ap
3830  // 68-75 cr0-7
3831  // 76: xer
3832  AssignToArrayRange(Builder, Address, Four8, 64, 76);
3833 
3834  // 77-108: v0-31, the 16-byte vector registers
3835  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
3836 
3837  // 109: vrsave
3838  // 110: vscr
3839  // 111: spe_acc
3840  // 112: spefscr
3841  // 113: sfp
3842  AssignToArrayRange(Builder, Address, Four8, 109, 113);
3843 
3844  return false;
3845 }
3846 
3847 // PowerPC-64
3848 
3849 namespace {
3850 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
3851 class PPC64_SVR4_ABIInfo : public ABIInfo {
3852 public:
3853  enum ABIKind {
3854  ELFv1 = 0,
3855  ELFv2
3856  };
3857 
3858 private:
3859  static const unsigned GPRBits = 64;
3860  ABIKind Kind;
3861  bool HasQPX;
3862 
3863  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
3864  // will be passed in a QPX register.
3865  bool IsQPXVectorTy(const Type *Ty) const {
3866  if (!HasQPX)
3867  return false;
3868 
3869  if (const VectorType *VT = Ty->getAs<VectorType>()) {
3870  unsigned NumElements = VT->getNumElements();
3871  if (NumElements == 1)
3872  return false;
3873 
3874  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
3875  if (getContext().getTypeSize(Ty) <= 256)
3876  return true;
3877  } else if (VT->getElementType()->
3878  isSpecificBuiltinType(BuiltinType::Float)) {
3879  if (getContext().getTypeSize(Ty) <= 128)
3880  return true;
3881  }
3882  }
3883 
3884  return false;
3885  }
3886 
3887  bool IsQPXVectorTy(QualType Ty) const {
3888  return IsQPXVectorTy(Ty.getTypePtr());
3889  }
3890 
3891 public:
3892  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX)
3893  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX) {}
3894 
3895  bool isPromotableTypeForABI(QualType Ty) const;
3896  CharUnits getParamTypeAlignment(QualType Ty) const;
3897 
3898  ABIArgInfo classifyReturnType(QualType RetTy) const;
3900 
3901  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
3902  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
3903  uint64_t Members) const override;
3904 
3905  // TODO: We can add more logic to computeInfo to improve performance.
3906  // Example: For aggregate arguments that fit in a register, we could
3907  // use getDirectInReg (as is done below for structs containing a single
3908  // floating-point value) to avoid pushing them to memory on function
3909  // entry. This would require changing the logic in PPCISelLowering
3910  // when lowering the parameters in the caller and args in the callee.
3911  void computeInfo(CGFunctionInfo &FI) const override {
3912  if (!getCXXABI().classifyReturnType(FI))
3914  for (auto &I : FI.arguments()) {
3915  // We rely on the default argument classification for the most part.
3916  // One exception: An aggregate containing a single floating-point
3917  // or vector item must be passed in a register if one is available.
3918  const Type *T = isSingleElementStruct(I.type, getContext());
3919  if (T) {
3920  const BuiltinType *BT = T->getAs<BuiltinType>();
3921  if (IsQPXVectorTy(T) ||
3922  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
3923  (BT && BT->isFloatingPoint())) {
3924  QualType QT(T, 0);
3925  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
3926  continue;
3927  }
3928  }
3930  }
3931  }
3932 
3933  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3934  QualType Ty) const override;
3935 };
3936 
3937 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
3938 
3939 public:
3940  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
3941  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX)
3942  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX)) {}
3943 
3944  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3945  // This is recovered from gcc output.
3946  return 1; // r1 is the dedicated stack pointer
3947  }
3948 
3949  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3950  llvm::Value *Address) const override;
3951 };
3952 
3953 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
3954 public:
3955  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
3956 
3957  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
3958  // This is recovered from gcc output.
3959  return 1; // r1 is the dedicated stack pointer
3960  }
3961 
3962  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
3963  llvm::Value *Address) const override;
3964 };
3965 
3966 }
3967 
3968 // Return true if the ABI requires Ty to be passed sign- or zero-
3969 // extended to 64 bits.
3970 bool
3971 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
3972  // Treat an enum type as its underlying type.
3973  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3974  Ty = EnumTy->getDecl()->getIntegerType();
3975 
3976  // Promotable integer types are required to be promoted by the ABI.
3977  if (Ty->isPromotableIntegerType())
3978  return true;
3979 
3980  // In addition to the usual promotable integer types, we also need to
3981  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
3982  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
3983  switch (BT->getKind()) {
3984  case BuiltinType::Int:
3985  case BuiltinType::UInt:
3986  return true;
3987  default:
3988  break;
3989  }
3990 
3991  return false;
3992 }
3993 
3994 /// isAlignedParamType - Determine whether a type requires 16-byte or
3995 /// higher alignment in the parameter area. Always returns at least 8.
3996 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
3997  // Complex types are passed just like their elements.
3998  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
3999  Ty = CTy->getElementType();
4000 
4001  // Only vector types of size 16 bytes need alignment (larger types are
4002  // passed via reference, smaller types are not aligned).
4003  if (IsQPXVectorTy(Ty)) {
4004  if (getContext().getTypeSize(Ty) > 128)
4005  return CharUnits::fromQuantity(32);
4006 
4007  return CharUnits::fromQuantity(16);
4008  } else if (Ty->isVectorType()) {
4009  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4010  }
4011 
4012  // For single-element float/vector structs, we consider the whole type
4013  // to have the same alignment requirements as its single element.
4014  const Type *AlignAsType = nullptr;
4015  const Type *EltType = isSingleElementStruct(Ty, getContext());
4016  if (EltType) {
4017  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4018  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4019  getContext().getTypeSize(EltType) == 128) ||
4020  (BT && BT->isFloatingPoint()))
4021  AlignAsType = EltType;
4022  }
4023 
4024  // Likewise for ELFv2 homogeneous aggregates.
4025  const Type *Base = nullptr;
4026  uint64_t Members = 0;
4027  if (!AlignAsType && Kind == ELFv2 &&
4028  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4029  AlignAsType = Base;
4030 
4031  // With special case aggregates, only vector base types need alignment.
4032  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4033  if (getContext().getTypeSize(AlignAsType) > 128)
4034  return CharUnits::fromQuantity(32);
4035 
4036  return CharUnits::fromQuantity(16);
4037  } else if (AlignAsType) {
4038  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4039  }
4040 
4041  // Otherwise, we only need alignment for any aggregate type that
4042  // has an alignment requirement of >= 16 bytes.
4043  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4044  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4045  return CharUnits::fromQuantity(32);
4046  return CharUnits::fromQuantity(16);
4047  }
4048 
4049  return CharUnits::fromQuantity(8);
4050 }
4051 
4052 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4053 /// aggregate. Base is set to the base element type, and Members is set
4054 /// to the number of base elements.
4055 bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
4056  uint64_t &Members) const {
4057  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4058  uint64_t NElements = AT->getSize().getZExtValue();
4059  if (NElements == 0)
4060  return false;
4061  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4062  return false;
4063  Members *= NElements;
4064  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4065  const RecordDecl *RD = RT->getDecl();
4066  if (RD->hasFlexibleArrayMember())
4067  return false;
4068 
4069  Members = 0;
4070 
4071  // If this is a C++ record, check the bases first.
4072  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4073  for (const auto &I : CXXRD->bases()) {
4074  // Ignore empty records.
4075  if (isEmptyRecord(getContext(), I.getType(), true))
4076  continue;
4077 
4078  uint64_t FldMembers;
4079  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4080  return false;
4081 
4082  Members += FldMembers;
4083  }
4084  }
4085 
4086  for (const auto *FD : RD->fields()) {
4087  // Ignore (non-zero arrays of) empty records.
4088  QualType FT = FD->getType();
4089  while (const ConstantArrayType *AT =
4090  getContext().getAsConstantArrayType(FT)) {
4091  if (AT->getSize().getZExtValue() == 0)
4092  return false;
4093  FT = AT->getElementType();
4094  }
4095  if (isEmptyRecord(getContext(), FT, true))
4096  continue;
4097 
4098  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4099  if (getContext().getLangOpts().CPlusPlus &&
4100  FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
4101  continue;
4102 
4103  uint64_t FldMembers;
4104  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4105  return false;
4106 
4107  Members = (RD->isUnion() ?
4108  std::max(Members, FldMembers) : Members + FldMembers);
4109  }
4110 
4111  if (!Base)
4112  return false;
4113 
4114  // Ensure there is no padding.
4115  if (getContext().getTypeSize(Base) * Members !=
4116  getContext().getTypeSize(Ty))
4117  return false;
4118  } else {
4119  Members = 1;
4120  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4121  Members = 2;
4122  Ty = CT->getElementType();
4123  }
4124 
4125  // Most ABIs only support float, double, and some vector type widths.
4127  return false;
4128 
4129  // The base type must be the same for all members. Types that
4130  // agree in both total size and mode (float vs. vector) are
4131  // treated as being equivalent here.
4132  const Type *TyPtr = Ty.getTypePtr();
4133  if (!Base) {
4134  Base = TyPtr;
4135  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4136  // so make sure to widen it explicitly.
4137  if (const VectorType *VT = Base->getAs<VectorType>()) {
4138  QualType EltTy = VT->getElementType();
4139  unsigned NumElements =
4140  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4141  Base = getContext()
4142  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4143  .getTypePtr();
4144  }
4145  }
4146 
4147  if (Base->isVectorType() != TyPtr->isVectorType() ||
4148  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4149  return false;
4150  }
4151  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4152 }
4153 
4154 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4155  // Homogeneous aggregates for ELFv2 must have base types of float,
4156  // double, long double, or 128-bit vectors.
4157  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4158  if (BT->getKind() == BuiltinType::Float ||
4159  BT->getKind() == BuiltinType::Double ||
4160  BT->getKind() == BuiltinType::LongDouble)
4161  return true;
4162  }
4163  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4164  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4165  return true;
4166  }
4167  return false;
4168 }
4169 
4170 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4171  const Type *Base, uint64_t Members) const {
4172  // Vector types require one register, floating point types require one
4173  // or two registers depending on their size.
4174  uint32_t NumRegs =
4175  Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
4176 
4177  // Homogeneous Aggregates may occupy at most 8 registers.
4178  return Members * NumRegs <= 8;
4179 }
4180 
4181 ABIArgInfo
4184 
4185  if (Ty->isAnyComplexType())
4186  return ABIArgInfo::getDirect();
4187 
4188  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4189  // or via reference (larger than 16 bytes).
4190  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4191  uint64_t Size = getContext().getTypeSize(Ty);
4192  if (Size > 128)
4193  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4194  else if (Size < 128) {
4195  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4196  return ABIArgInfo::getDirect(CoerceTy);
4197  }
4198  }
4199 
4200  if (isAggregateTypeForABI(Ty)) {
4201  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
4202  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
4203 
4204  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4205  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4206 
4207  // ELFv2 homogeneous aggregates are passed as array types.
4208  const Type *Base = nullptr;
4209  uint64_t Members = 0;
4210  if (Kind == ELFv2 &&
4211  isHomogeneousAggregate(Ty, Base, Members)) {
4212  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4213  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4214  return ABIArgInfo::getDirect(CoerceTy);
4215  }
4216 
4217  // If an aggregate may end up fully in registers, we do not
4218  // use the ByVal method, but pass the aggregate as array.
4219  // This is usually beneficial since we avoid forcing the
4220  // back-end to store the argument to memory.
4221  uint64_t Bits = getContext().getTypeSize(Ty);
4222  if (Bits > 0 && Bits <= 8 * GPRBits) {
4223  llvm::Type *CoerceTy;
4224 
4225  // Types up to 8 bytes are passed as integer type (which will be
4226  // properly aligned in the argument save area doubleword).
4227  if (Bits <= GPRBits)
4228  CoerceTy =
4229  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4230  // Larger types are passed as arrays, with the base type selected
4231  // according to the required alignment in the save area.
4232  else {
4233  uint64_t RegBits = ABIAlign * 8;
4234  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4235  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4236  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4237  }
4238 
4239  return ABIArgInfo::getDirect(CoerceTy);
4240  }
4241 
4242  // All other aggregates are passed ByVal.
4244  /*ByVal=*/true,
4245  /*Realign=*/TyAlign > ABIAlign);
4246  }
4247 
4248  return (isPromotableTypeForABI(Ty) ?
4250 }
4251 
4252 ABIArgInfo
4254  if (RetTy->isVoidType())
4255  return ABIArgInfo::getIgnore();
4256 
4257  if (RetTy->isAnyComplexType())
4258  return ABIArgInfo::getDirect();
4259 
4260  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4261  // or via reference (larger than 16 bytes).
4262  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4263  uint64_t Size = getContext().getTypeSize(RetTy);
4264  if (Size > 128)
4265  return getNaturalAlignIndirect(RetTy);
4266  else if (Size < 128) {
4267  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4268  return ABIArgInfo::getDirect(CoerceTy);
4269  }
4270  }
4271 
4272  if (isAggregateTypeForABI(RetTy)) {
4273  // ELFv2 homogeneous aggregates are returned as array types.
4274  const Type *Base = nullptr;
4275  uint64_t Members = 0;
4276  if (Kind == ELFv2 &&
4277  isHomogeneousAggregate(RetTy, Base, Members)) {
4278  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4279  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4280  return ABIArgInfo::getDirect(CoerceTy);
4281  }
4282 
4283  // ELFv2 small aggregates are returned in up to two registers.
4284  uint64_t Bits = getContext().getTypeSize(RetTy);
4285  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4286  if (Bits == 0)
4287  return ABIArgInfo::getIgnore();
4288 
4289  llvm::Type *CoerceTy;
4290  if (Bits > GPRBits) {
4291  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4292  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy, nullptr);
4293  } else
4294  CoerceTy =
4295  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4296  return ABIArgInfo::getDirect(CoerceTy);
4297  }
4298 
4299  // All other aggregates are returned indirectly.
4300  return getNaturalAlignIndirect(RetTy);
4301  }
4302 
4303  return (isPromotableTypeForABI(RetTy) ?
4305 }
4306 
4307 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4308 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4309  QualType Ty) const {
4310  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4311  TypeInfo.second = getParamTypeAlignment(Ty);
4312 
4313  CharUnits SlotSize = CharUnits::fromQuantity(8);
4314 
4315  // If we have a complex type and the base type is smaller than 8 bytes,
4316  // the ABI calls for the real and imaginary parts to be right-adjusted
4317  // in separate doublewords. However, Clang expects us to produce a
4318  // pointer to a structure with the two parts packed tightly. So generate
4319  // loads of the real and imaginary parts relative to the va_list pointer,
4320  // and store them to a temporary structure.
4321  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4322  CharUnits EltSize = TypeInfo.first / 2;
4323  if (EltSize < SlotSize) {
4324  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4325  SlotSize * 2, SlotSize,
4326  SlotSize, /*AllowHigher*/ true);
4327 
4328  Address RealAddr = Addr;
4329  Address ImagAddr = RealAddr;
4330  if (CGF.CGM.getDataLayout().isBigEndian()) {
4331  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4332  SlotSize - EltSize);
4333  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4334  2 * SlotSize - EltSize);
4335  } else {
4336  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4337  }
4338 
4339  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4340  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4341  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4342  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4343  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4344 
4345  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4346  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4347  /*init*/ true);
4348  return Temp;
4349  }
4350  }
4351 
4352  // Otherwise, just use the general rule.
4353  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4354  TypeInfo, SlotSize, /*AllowHigher*/ true);
4355 }
4356 
4357 static bool
4359  llvm::Value *Address) {
4360  // This is calculated from the LLVM and GCC tables and verified
4361  // against gcc output. AFAIK all ABIs use the same encoding.
4362 
4363  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4364 
4365  llvm::IntegerType *i8 = CGF.Int8Ty;
4366  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4367  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4368  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4369 
4370  // 0-31: r0-31, the 8-byte general-purpose registers
4371  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4372 
4373  // 32-63: fp0-31, the 8-byte floating-point registers
4374  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4375 
4376  // 64-76 are various 4-byte special-purpose registers:
4377  // 64: mq
4378  // 65: lr
4379  // 66: ctr
4380  // 67: ap
4381  // 68-75 cr0-7
4382  // 76: xer
4383  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4384 
4385  // 77-108: v0-31, the 16-byte vector registers
4386  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4387 
4388  // 109: vrsave
4389  // 110: vscr
4390  // 111: spe_acc
4391  // 112: spefscr
4392  // 113: sfp
4393  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4394 
4395  return false;
4396 }
4397 
4398 bool
4399 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4401  llvm::Value *Address) const {
4402 
4403  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4404 }
4405 
4406 bool
4407 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4408  llvm::Value *Address) const {
4409 
4410  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4411 }
4412 
4413 //===----------------------------------------------------------------------===//
4414 // AArch64 ABI Implementation
4415 //===----------------------------------------------------------------------===//
4416 
4417 namespace {
4418 
4419 class AArch64ABIInfo : public SwiftABIInfo {
4420 public:
4421  enum ABIKind {
4422  AAPCS = 0,
4423  DarwinPCS
4424  };
4425 
4426 private:
4427  ABIKind Kind;
4428 
4429 public:
4430  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4431  : SwiftABIInfo(CGT), Kind(Kind) {}
4432 
4433 private:
4434  ABIKind getABIKind() const { return Kind; }
4435  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4436 
4437  ABIArgInfo classifyReturnType(QualType RetTy) const;
4439  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4440  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4441  uint64_t Members) const override;
4442 
4443  bool isIllegalVectorType(QualType Ty) const;
4444 
4445  void computeInfo(CGFunctionInfo &FI) const override {
4446  if (!getCXXABI().classifyReturnType(FI))
4448 
4449  for (auto &it : FI.arguments())
4450  it.info = classifyArgumentType(it.type);
4451  }
4452 
4453  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4454  CodeGenFunction &CGF) const;
4455 
4456  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4457  CodeGenFunction &CGF) const;
4458 
4459  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4460  QualType Ty) const override {
4461  return isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4462  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4463  }
4464 
4465  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
4466  ArrayRef<llvm::Type*> scalars,
4467  bool asReturnValue) const override {
4468  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4469  }
4470 };
4471 
4472 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4473 public:
4474  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4475  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4476 
4477  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4478  return "mov\tfp, fp\t\t; marker for objc_retainAutoreleaseReturnValue";
4479  }
4480 
4481  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4482  return 31;
4483  }
4484 
4485  bool doesReturnSlotInterfereWithArgs() const override { return false; }
4486 };
4487 }
4488 
4491 
4492  // Handle illegal vector types here.
4493  if (isIllegalVectorType(Ty)) {
4494  uint64_t Size = getContext().getTypeSize(Ty);
4495  // Android promotes <2 x i8> to i16, not i32
4496  if (isAndroid() && (Size <= 16)) {
4497  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
4498  return ABIArgInfo::getDirect(ResType);
4499  }
4500  if (Size <= 32) {
4501  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
4502  return ABIArgInfo::getDirect(ResType);
4503  }
4504  if (Size == 64) {
4505  llvm::Type *ResType =
4506  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
4507  return ABIArgInfo::getDirect(ResType);
4508  }
4509  if (Size == 128) {
4510  llvm::Type *ResType =
4511  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
4512  return ABIArgInfo::getDirect(ResType);
4513  }
4514  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4515  }
4516 
4517  if (!isAggregateTypeForABI(Ty)) {
4518  // Treat an enum type as its underlying type.
4519  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4520  Ty = EnumTy->getDecl()->getIntegerType();
4521 
4522  return (Ty->isPromotableIntegerType() && isDarwinPCS()
4524  : ABIArgInfo::getDirect());
4525  }
4526 
4527  // Structures with either a non-trivial destructor or a non-trivial
4528  // copy constructor are always indirect.
4529  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
4530  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
4532  }
4533 
4534  // Empty records are always ignored on Darwin, but actually passed in C++ mode
4535  // elsewhere for GNU compatibility.
4536  if (isEmptyRecord(getContext(), Ty, true)) {
4537  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
4538  return ABIArgInfo::getIgnore();
4539 
4540  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
4541  }
4542 
4543  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
4544  const Type *Base = nullptr;
4545  uint64_t Members = 0;
4546  if (isHomogeneousAggregate(Ty, Base, Members)) {
4547  return ABIArgInfo::getDirect(
4548  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
4549  }
4550 
4551  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
4552  uint64_t Size = getContext().getTypeSize(Ty);
4553  if (Size <= 128) {
4554  unsigned Alignment = getContext().getTypeAlign(Ty);
4555  Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4556 
4557  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4558  // For aggregates with 16-byte alignment, we use i128.
4559  if (Alignment < 128 && Size == 128) {
4560  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4561  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4562  }
4563  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4564  }
4565 
4566  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4567 }
4568 
4570  if (RetTy->isVoidType())
4571  return ABIArgInfo::getIgnore();
4572 
4573  // Large vector types should be returned via memory.
4574  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
4575  return getNaturalAlignIndirect(RetTy);
4576 
4577  if (!isAggregateTypeForABI(RetTy)) {
4578  // Treat an enum type as its underlying type.
4579  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
4580  RetTy = EnumTy->getDecl()->getIntegerType();
4581 
4582  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
4584  : ABIArgInfo::getDirect());
4585  }
4586 
4587  if (isEmptyRecord(getContext(), RetTy, true))
4588  return ABIArgInfo::getIgnore();
4589 
4590  const Type *Base = nullptr;
4591  uint64_t Members = 0;
4592  if (isHomogeneousAggregate(RetTy, Base, Members))
4593  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
4594  return ABIArgInfo::getDirect();
4595 
4596  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
4597  uint64_t Size = getContext().getTypeSize(RetTy);
4598  if (Size <= 128) {
4599  unsigned Alignment = getContext().getTypeAlign(RetTy);
4600  Size = 64 * ((Size + 63) / 64); // round up to multiple of 8 bytes
4601 
4602  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
4603  // For aggregates with 16-byte alignment, we use i128.
4604  if (Alignment < 128 && Size == 128) {
4605  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
4606  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
4607  }
4608  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
4609  }
4610 
4611  return getNaturalAlignIndirect(RetTy);
4612 }
4613 
4614 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
4615 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
4616  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4617  // Check whether VT is legal.
4618  unsigned NumElements = VT->getNumElements();
4619  uint64_t Size = getContext().getTypeSize(VT);
4620  // NumElements should be power of 2.
4621  if (!llvm::isPowerOf2_32(NumElements))
4622  return true;
4623  return Size != 64 && (Size != 128 || NumElements == 1);
4624  }
4625  return false;
4626 }
4627 
4628 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4629  // Homogeneous aggregates for AAPCS64 must have base types of a floating
4630  // point type or a short-vector type. This is the same as the 32-bit ABI,
4631  // but with the difference that any floating-point type is allowed,
4632  // including __fp16.
4633  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4634  if (BT->isFloatingPoint())
4635  return true;
4636  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
4637  unsigned VecSize = getContext().getTypeSize(VT);
4638  if (VecSize == 64 || VecSize == 128)
4639  return true;
4640  }
4641  return false;
4642 }
4643 
4644 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
4645  uint64_t Members) const {
4646  return Members <= 4;
4647 }
4648 
4649 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
4650  QualType Ty,
4651  CodeGenFunction &CGF) const {
4653  bool IsIndirect = AI.isIndirect();
4654 
4655  llvm::Type *BaseTy = CGF.ConvertType(Ty);
4656  if (IsIndirect)
4657  BaseTy = llvm::PointerType::getUnqual(BaseTy);
4658  else if (AI.getCoerceToType())
4659  BaseTy = AI.getCoerceToType();
4660 
4661  unsigned NumRegs = 1;
4662  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
4663  BaseTy = ArrTy->getElementType();
4664  NumRegs = ArrTy->getNumElements();
4665  }
4666  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
4667 
4668  // The AArch64 va_list type and handling is specified in the Procedure Call
4669  // Standard, section B.4:
4670  //
4671  // struct {
4672  // void *__stack;
4673  // void *__gr_top;
4674  // void *__vr_top;
4675  // int __gr_offs;
4676  // int __vr_offs;
4677  // };
4678 
4679  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
4680  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
4681  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
4682  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
4683 
4684  auto TyInfo = getContext().getTypeInfoInChars(Ty);
4685  CharUnits TyAlign = TyInfo.second;
4686 
4687  Address reg_offs_p = Address::invalid();
4688  llvm::Value *reg_offs = nullptr;
4689  int reg_top_index;
4690  CharUnits reg_top_offset;
4691  int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
4692  if (!IsFPR) {
4693  // 3 is the field number of __gr_offs
4694  reg_offs_p =
4695  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
4696  "gr_offs_p");
4697  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
4698  reg_top_index = 1; // field number for __gr_top
4699  reg_top_offset = CharUnits::fromQuantity(8);
4700  RegSize = llvm::alignTo(RegSize, 8);
4701  } else {
4702  // 4 is the field number of __vr_offs.
4703  reg_offs_p =
4704  CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
4705  "vr_offs_p");
4706  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
4707  reg_top_index = 2; // field number for __vr_top
4708  reg_top_offset = CharUnits::fromQuantity(16);
4709  RegSize = 16 * NumRegs;
4710  }
4711 
4712  //=======================================
4713  // Find out where argument was passed
4714  //=======================================
4715 
4716  // If reg_offs >= 0 we're already using the stack for this type of
4717  // argument. We don't want to keep updating reg_offs (in case it overflows,
4718  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
4719  // whatever they get).
4720  llvm::Value *UsingStack = nullptr;
4721  UsingStack = CGF.Builder.CreateICmpSGE(
4722  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
4723 
4724  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
4725 
4726  // Otherwise, at least some kind of argument could go in these registers, the
4727  // question is whether this particular type is too big.
4728  CGF.EmitBlock(MaybeRegBlock);
4729 
4730  // Integer arguments may need to correct register alignment (for example a
4731  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
4732  // align __gr_offs to calculate the potential address.
4733  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
4734  int Align = TyAlign.getQuantity();
4735 
4736  reg_offs = CGF.Builder.CreateAdd(
4737  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
4738  "align_regoffs");
4739  reg_offs = CGF.Builder.CreateAnd(
4740  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
4741  "aligned_regoffs");
4742  }
4743 
4744  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
4745  // The fact that this is done unconditionally reflects the fact that
4746  // allocating an argument to the stack also uses up all the remaining
4747  // registers of the appropriate kind.
4748  llvm::Value *NewOffset = nullptr;
4749  NewOffset = CGF.Builder.CreateAdd(
4750  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
4751  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
4752 
4753  // Now we're in a position to decide whether this argument really was in
4754  // registers or not.
4755  llvm::Value *InRegs = nullptr;
4756  InRegs = CGF.Builder.CreateICmpSLE(
4757  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
4758 
4759  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
4760 
4761  //=======================================
4762  // Argument was in registers
4763  //=======================================
4764 
4765  // Now we emit the code for if the argument was originally passed in
4766  // registers. First start the appropriate block:
4767  CGF.EmitBlock(InRegBlock);
4768 
4769  llvm::Value *reg_top = nullptr;
4770  Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
4771  reg_top_offset, "reg_top_p");
4772  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
4773  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
4774  CharUnits::fromQuantity(IsFPR ? 16 : 8));
4775  Address RegAddr = Address::invalid();
4776  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
4777 
4778  if (IsIndirect) {
4779  // If it's been passed indirectly (actually a struct), whatever we find from
4780  // stored registers or on the stack will actually be a struct **.
4781  MemTy = llvm::PointerType::getUnqual(MemTy);
4782  }
4783 
4784  const Type *Base = nullptr;
4785  uint64_t NumMembers = 0;
4786  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
4787  if (IsHFA && NumMembers > 1) {
4788  // Homogeneous aggregates passed in registers will have their elements split
4789  // and stored 16-bytes apart regardless of size (they're notionally in qN,
4790  // qN+1, ...). We reload and store into a temporary local variable
4791  // contiguously.
4792  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
4793  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
4794  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
4795  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
4796  Address Tmp = CGF.CreateTempAlloca(HFATy,
4797  std::max(TyAlign, BaseTyInfo.second));
4798 
4799  // On big-endian platforms, the value will be right-aligned in its slot.
4800  int Offset = 0;
4801  if (CGF.CGM.getDataLayout().isBigEndian() &&
4802  BaseTyInfo.first.getQuantity() < 16)
4803  Offset = 16 - BaseTyInfo.first.getQuantity();
4804 
4805  for (unsigned i = 0; i < NumMembers; ++i) {
4806  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
4807  Address LoadAddr =
4808  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
4809  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
4810 
4811  Address StoreAddr =
4812  CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
4813 
4814  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
4815  CGF.Builder.CreateStore(Elem, StoreAddr);
4816  }
4817 
4818  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
4819  } else {
4820  // Otherwise the object is contiguous in memory.
4821 
4822  // It might be right-aligned in its slot.
4823  CharUnits SlotSize = BaseAddr.getAlignment();
4824  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
4825  (IsHFA || !isAggregateTypeForABI(Ty)) &&
4826  TyInfo.first < SlotSize) {
4827  CharUnits Offset = SlotSize - TyInfo.first;
4828  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
4829  }
4830 
4831  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
4832  }
4833 
4834  CGF.EmitBranch(ContBlock);
4835 
4836  //=======================================
4837  // Argument was on the stack
4838  //=======================================
4839  CGF.EmitBlock(OnStackBlock);
4840 
4841  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
4842  CharUnits::Zero(), "stack_p");
4843  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
4844 
4845  // Again, stack arguments may need realignment. In this case both integer and
4846  // floating-point ones might be affected.
4847  if (!IsIndirect && TyAlign.getQuantity() > 8) {
4848  int Align = TyAlign.getQuantity();
4849 
4850  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
4851 
4852  OnStackPtr = CGF.Builder.CreateAdd(
4853  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
4854  "align_stack");
4855  OnStackPtr = CGF.Builder.CreateAnd(
4856  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
4857  "align_stack");
4858 
4859  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
4860  }
4861  Address OnStackAddr(OnStackPtr,
4862  std::max(CharUnits::fromQuantity(8), TyAlign));
4863 
4864  // All stack slots are multiples of 8 bytes.
4865  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
4866  CharUnits StackSize;
4867  if (IsIndirect)
4868  StackSize = StackSlotSize;
4869  else
4870  StackSize = TyInfo.first.alignTo(StackSlotSize);
4871 
4872  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
4873  llvm::Value *NewStack =
4874  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
4875 
4876  // Write the new value of __stack for the next call to va_arg
4877  CGF.Builder.CreateStore(NewStack, stack_p);
4878 
4879  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
4880  TyInfo.first < StackSlotSize) {
4881  CharUnits Offset = StackSlotSize - TyInfo.first;
4882  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
4883  }
4884 
4885  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
4886 
4887  CGF.EmitBranch(ContBlock);
4888 
4889  //=======================================
4890  // Tidy up
4891  //=======================================
4892  CGF.EmitBlock(ContBlock);
4893 
4894  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
4895  OnStackAddr, OnStackBlock, "vaargs.addr");
4896 
4897  if (IsIndirect)
4898  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
4899  TyInfo.second);
4900 
4901  return ResAddr;
4902 }
4903 
4904 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4905  CodeGenFunction &CGF) const {
4906  // The backend's lowering doesn't support va_arg for aggregates or
4907  // illegal vector types. Lower VAArg here for these cases and use
4908  // the LLVM va_arg instruction for everything else.
4909  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
4910  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
4911 
4912  CharUnits SlotSize = CharUnits::fromQuantity(8);
4913 
4914  // Empty records are ignored for parameter passing purposes.
4915  if (isEmptyRecord(getContext(), Ty, true)) {
4916  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
4917  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
4918  return Addr;
4919  }
4920 
4921  // The size of the actual thing passed, which might end up just
4922  // being a pointer for indirect types.
4923  auto TyInfo = getContext().getTypeInfoInChars(Ty);
4924 
4925  // Arguments bigger than 16 bytes which aren't homogeneous
4926  // aggregates should be passed indirectly.
4927  bool IsIndirect = false;
4928  if (TyInfo.first.getQuantity() > 16) {
4929  const Type *Base = nullptr;
4930  uint64_t Members = 0;
4931  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
4932  }
4933 
4934  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4935  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
4936 }
4937 
4938 //===----------------------------------------------------------------------===//
4939 // ARM ABI Implementation
4940 //===----------------------------------------------------------------------===//
4941 
4942 namespace {
4943 
4944 class ARMABIInfo : public SwiftABIInfo {
4945 public:
4946  enum ABIKind {
4947  APCS = 0,
4948  AAPCS = 1,
4949  AAPCS_VFP = 2,
4950  AAPCS16_VFP = 3,
4951  };
4952 
4953 private:
4954  ABIKind Kind;
4955 
4956 public:
4957  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
4958  : SwiftABIInfo(CGT), Kind(_Kind) {
4959  setCCs();
4960  }
4961 
4962  bool isEABI() const {
4963  switch (getTarget().getTriple().getEnvironment()) {
4964  case llvm::Triple::Android:
4965  case llvm::Triple::EABI:
4966  case llvm::Triple::EABIHF:
4967  case llvm::Triple::GNUEABI:
4968  case llvm::Triple::GNUEABIHF:
4969  case llvm::Triple::MuslEABI:
4970  case llvm::Triple::MuslEABIHF:
4971  return true;
4972  default:
4973  return false;
4974  }
4975  }
4976 
4977  bool isEABIHF() const {
4978  switch (getTarget().getTriple().getEnvironment()) {
4979  case llvm::Triple::EABIHF:
4980  case llvm::Triple::GNUEABIHF:
4981  case llvm::Triple::MuslEABIHF:
4982  return true;
4983  default:
4984  return false;
4985  }
4986  }
4987 
4988  ABIKind getABIKind() const { return Kind; }
4989 
4990 private:
4991  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
4992  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
4993  bool isIllegalVectorType(QualType Ty) const;
4994 
4995  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4996  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4997  uint64_t Members) const override;
4998 
4999  void computeInfo(CGFunctionInfo &FI) const override;
5000 
5001  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5002  QualType Ty) const override;
5003 
5004  llvm::CallingConv::ID getLLVMDefaultCC() const;
5005  llvm::CallingConv::ID getABIDefaultCC() const;
5006  void setCCs();
5007 
5008  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5009  ArrayRef<llvm::Type*> scalars,
5010  bool asReturnValue) const override {
5011  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5012  }
5013 };
5014 
5015 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5016 public:
5017  ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5018  :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5019 
5020  const ARMABIInfo &getABIInfo() const {
5021  return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5022  }
5023 
5024  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5025  return 13;
5026  }
5027 
5028  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5029  return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue";
5030  }
5031 
5032  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5033  llvm::Value *Address) const override {
5034  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5035 
5036  // 0-15 are the 16 integer registers.
5037  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5038  return false;
5039  }
5040 
5041  unsigned getSizeOfUnwindException() const override {
5042  if (getABIInfo().isEABI()) return 88;
5044  }
5045 
5046  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5047  CodeGen::CodeGenModule &CGM) const override {
5048  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5049  if (!FD)
5050  return;
5051 
5052  const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5053  if (!Attr)
5054  return;
5055 
5056  const char *Kind;
5057  switch (Attr->getInterrupt()) {
5058  case ARMInterruptAttr::Generic: Kind = ""; break;
5059  case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5060  case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5061  case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5062  case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5063  case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5064  }
5065 
5066  llvm::Function *Fn = cast<llvm::Function>(GV);
5067 
5068  Fn->addFnAttr("interrupt", Kind);
5069 
5070  ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5071  if (ABI == ARMABIInfo::APCS)
5072  return;
5073 
5074  // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5075  // however this is not necessarily true on taking any interrupt. Instruct
5076  // the backend to perform a realignment as part of the function prologue.
5077  llvm::AttrBuilder B;
5078  B.addStackAlignmentAttr(8);
5079  Fn->addAttributes(llvm::AttributeSet::FunctionIndex,
5080  llvm::AttributeSet::get(CGM.getLLVMContext(),
5081  llvm::AttributeSet::FunctionIndex,
5082  B));
5083  }
5084 };
5085 
5086 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5087 public:
5088  WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5089  : ARMTargetCodeGenInfo(CGT, K) {}
5090 
5091  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5092  CodeGen::CodeGenModule &CGM) const override;
5093 
5094  void getDependentLibraryOption(llvm::StringRef Lib,
5095  llvm::SmallString<24> &Opt) const override {
5096  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5097  }
5098 
5099  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5100  llvm::SmallString<32> &Opt) const override {
5101  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5102  }
5103 };
5104 
5105 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5106  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5107  ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5108  addStackProbeSizeTargetAttribute(D, GV, CGM);
5109 }
5110 }
5111 
5112 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5113  if (!getCXXABI().classifyReturnType(FI))
5114  FI.getReturnInfo() =
5116 
5117  for (auto &I : FI.arguments())
5119 
5120  // Always honor user-specified calling convention.
5122  return;
5123 
5124  llvm::CallingConv::ID cc = getRuntimeCC();
5125  if (cc != llvm::CallingConv::C)
5127 }
5128 
5129 /// Return the default calling convention that LLVM will use.
5130 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5131  // The default calling convention that LLVM will infer.
5132  if (isEABIHF() || getTarget().getTriple().isWatchABI())
5133  return llvm::CallingConv::ARM_AAPCS_VFP;
5134  else if (isEABI())
5135  return llvm::CallingConv::ARM_AAPCS;
5136  else
5137  return llvm::CallingConv::ARM_APCS;
5138 }
5139 
5140 /// Return the calling convention that our ABI would like us to use
5141 /// as the C calling convention.
5142 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5143  switch (getABIKind()) {
5144  case APCS: return llvm::CallingConv::ARM_APCS;
5145  case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5146  case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5147  case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5148  }
5149  llvm_unreachable("bad ABI kind");
5150 }
5151 
5152 void ARMABIInfo::setCCs() {
5153  assert(getRuntimeCC() == llvm::CallingConv::C);
5154 
5155  // Don't muddy up the IR with a ton of explicit annotations if
5156  // they'd just match what LLVM will infer from the triple.
5157  llvm::CallingConv::ID abiCC = getABIDefaultCC();
5158  if (abiCC != getLLVMDefaultCC())
5159  RuntimeCC = abiCC;
5160 
5161  // AAPCS apparently requires runtime support functions to be soft-float, but
5162  // that's almost certainly for historic reasons (Thumb1 not supporting VFP
5163  // most likely). It's more convenient for AAPCS16_VFP to be hard-float.
5164  switch (getABIKind()) {
5165  case APCS:
5166  case AAPCS16_VFP:
5167  if (abiCC != getLLVMDefaultCC())
5168  BuiltinCC = abiCC;
5169  break;
5170  case AAPCS:
5171  case AAPCS_VFP:
5172  BuiltinCC = llvm::CallingConv::ARM_AAPCS;
5173  break;
5174  }
5175 }
5176 
5178  bool isVariadic) const {
5179  // 6.1.2.1 The following argument types are VFP CPRCs:
5180  // A single-precision floating-point type (including promoted
5181  // half-precision types); A double-precision floating-point type;
5182  // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5183  // with a Base Type of a single- or double-precision floating-point type,
5184  // 64-bit containerized vectors or 128-bit containerized vectors with one
5185  // to four Elements.
5186  bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5187 
5189 
5190  // Handle illegal vector types here.
5191  if (isIllegalVectorType(Ty)) {
5192  uint64_t Size = getContext().getTypeSize(Ty);
5193  if (Size <= 32) {
5194  llvm::Type *ResType =
5195  llvm::Type::getInt32Ty(getVMContext());
5196  return ABIArgInfo::getDirect(ResType);
5197  }
5198  if (Size == 64) {
5199  llvm::Type *ResType = llvm::VectorType::get(
5200  llvm::Type::getInt32Ty(getVMContext()), 2);
5201  return ABIArgInfo::getDirect(ResType);
5202  }
5203  if (Size == 128) {
5204  llvm::Type *ResType = llvm::VectorType::get(
5205  llvm::Type::getInt32Ty(getVMContext()), 4);
5206  return ABIArgInfo::getDirect(ResType);
5207  }
5208  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5209  }
5210 
5211  // __fp16 gets passed as if it were an int or float, but with the top 16 bits
5212  // unspecified. This is not done for OpenCL as it handles the half type
5213  // natively, and does not need to interwork with AAPCS code.
5214  if (Ty->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5215  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5216  llvm::Type::getFloatTy(getVMContext()) :
5217  llvm::Type::getInt32Ty(getVMContext());
5218  return ABIArgInfo::getDirect(ResType);
5219  }
5220 
5221  if (!isAggregateTypeForABI(Ty)) {
5222  // Treat an enum type as its underlying type.
5223  if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5224  Ty = EnumTy->getDecl()->getIntegerType();
5225  }
5226 
5228  : ABIArgInfo::getDirect());
5229  }
5230 
5231  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
5232  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
5233  }
5234 
5235  // Ignore empty records.
5236  if (isEmptyRecord(getContext(), Ty, true))
5237  return ABIArgInfo::getIgnore();
5238 
5239  if (IsEffectivelyAAPCS_VFP) {
5240  // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5241  // into VFP registers.
5242  const Type *Base = nullptr;
5243  uint64_t Members = 0;
5244  if (isHomogeneousAggregate(Ty, Base, Members)) {
5245  assert(Base && "Base class should be set for homogeneous aggregate");
5246  // Base can be a floating-point or a vector.
5247  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5248  }
5249  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5250  // WatchOS does have homogeneous aggregates. Note that we intentionally use
5251  // this convention even for a variadic function: the backend will use GPRs
5252  // if needed.
5253  const Type *Base = nullptr;
5254  uint64_t Members = 0;
5255  if (isHomogeneousAggregate(Ty, Base, Members)) {
5256  assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5257  llvm::Type *Ty =
5258  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5259  return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5260  }
5261  }
5262 
5263  if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5264  getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5265  // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5266  // bigger than 128-bits, they get placed in space allocated by the caller,
5267  // and a pointer is passed.
5268  return ABIArgInfo::getIndirect(
5269  CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5270  }
5271 
5272  // Support byval for ARM.
5273  // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5274  // most 8-byte. We realign the indirect argument if type alignment is bigger
5275  // than ABI alignment.
5276  uint64_t ABIAlign = 4;
5277  uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8;
5278  if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5279  getABIKind() == ARMABIInfo::AAPCS)
5280  ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5281 
5282  if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5283  assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5285  /*ByVal=*/true,
5286  /*Realign=*/TyAlign > ABIAlign);
5287  }
5288 
5289  // Otherwise, pass by coercing to a structure of the appropriate size.
5290  llvm::Type* ElemTy;
5291  unsigned SizeRegs;
5292  // FIXME: Try to match the types of the arguments more accurately where
5293  // we can.
5294  if (getContext().getTypeAlign(Ty) <= 32) {
5295  ElemTy = llvm::Type::getInt32Ty(getVMContext());
5296  SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5297  } else {
5298  ElemTy = llvm::Type::getInt64Ty(getVMContext());
5299  SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5300  }
5301 
5302  return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5303 }
5304 
5305 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5306  llvm::LLVMContext &VMContext) {
5307  // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5308  // is called integer-like if its size is less than or equal to one word, and
5309  // the offset of each of its addressable sub-fields is zero.
5310 
5311  uint64_t Size = Context.getTypeSize(Ty);
5312 
5313  // Check that the type fits in a word.
5314  if (Size > 32)
5315  return false;
5316 
5317  // FIXME: Handle vector types!
5318  if (Ty->isVectorType())
5319  return false;
5320 
5321  // Float types are never treated as "integer like".
5322  if (Ty->isRealFloatingType())
5323  return false;
5324 
5325  // If this is a builtin or pointer type then it is ok.
5326  if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5327  return true;
5328 
5329  // Small complex integer types are "integer like".
5330  if (const ComplexType *CT = Ty->getAs<ComplexType>())
5331  return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5332 
5333  // Single element and zero sized arrays should be allowed, by the definition
5334  // above, but they are not.
5335 
5336  // Otherwise, it must be a record type.
5337  const RecordType *RT = Ty->getAs<RecordType>();
5338  if (!RT) return false;
5339 
5340  // Ignore records with flexible arrays.
5341  const RecordDecl *RD = RT->getDecl();
5342  if (RD->hasFlexibleArrayMember())
5343  return false;
5344 
5345  // Check that all sub-fields are at offset 0, and are themselves "integer
5346  // like".
5347  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5348 
5349  bool HadField = false;
5350  unsigned idx = 0;
5351  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5352  i != e; ++i, ++idx) {
5353  const FieldDecl *FD = *i;
5354 
5355  // Bit-fields are not addressable, we only need to verify they are "integer
5356  // like". We still have to disallow a subsequent non-bitfield, for example:
5357  // struct { int : 0; int x }
5358  // is non-integer like according to gcc.
5359  if (FD->isBitField()) {
5360  if (!RD->isUnion())
5361  HadField = true;
5362 
5363  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5364  return false;
5365 
5366  continue;
5367  }
5368 
5369  // Check if this field is at offset 0.
5370  if (Layout.getFieldOffset(idx) != 0)
5371  return false;
5372 
5373  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5374  return false;
5375 
5376  // Only allow at most one field in a structure. This doesn't match the
5377  // wording above, but follows gcc in situations with a field following an
5378  // empty structure.
5379  if (!RD->isUnion()) {
5380  if (HadField)
5381  return false;
5382 
5383  HadField = true;
5384  }
5385  }
5386 
5387  return true;
5388 }
5389 
5391  bool isVariadic) const {
5392  bool IsEffectivelyAAPCS_VFP =
5393  (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5394 
5395  if (RetTy->isVoidType())
5396  return ABIArgInfo::getIgnore();
5397 
5398  // Large vector types should be returned via memory.
5399  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5400  return getNaturalAlignIndirect(RetTy);
5401  }
5402 
5403  // __fp16 gets returned as if it were an int or float, but with the top 16
5404  // bits unspecified. This is not done for OpenCL as it handles the half type
5405  // natively, and does not need to interwork with AAPCS code.
5406  if (RetTy->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5407  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5408  llvm::Type::getFloatTy(getVMContext()) :
5409  llvm::Type::getInt32Ty(getVMContext());
5410  return ABIArgInfo::getDirect(ResType);
5411  }
5412 
5413  if (!isAggregateTypeForABI(RetTy)) {
5414  // Treat an enum type as its underlying type.
5415  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5416  RetTy = EnumTy->getDecl()->getIntegerType();
5417 
5419  : ABIArgInfo::getDirect();
5420  }
5421 
5422  // Are we following APCS?
5423  if (getABIKind() == APCS) {
5424  if (isEmptyRecord(getContext(), RetTy, false))
5425  return ABIArgInfo::getIgnore();
5426 
5427  // Complex types are all returned as packed integers.
5428  //
5429  // FIXME: Consider using 2 x vector types if the back end handles them
5430  // correctly.
5431  if (RetTy->isAnyComplexType())
5432  return ABIArgInfo::getDirect(llvm::IntegerType::get(
5433  getVMContext(), getContext().getTypeSize(RetTy)));
5434 
5435  // Integer like structures are returned in r0.
5436  if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5437  // Return in the smallest viable integer type.
5438  uint64_t Size = getContext().getTypeSize(RetTy);
5439  if (Size <= 8)
5440  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5441  if (Size <= 16)
5442  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5443  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5444  }
5445 
5446  // Otherwise return in memory.
5447  return getNaturalAlignIndirect(RetTy);
5448  }
5449 
5450  // Otherwise this is an AAPCS variant.
5451 
5452  if (isEmptyRecord(getContext(), RetTy, true))
5453  return ABIArgInfo::getIgnore();
5454 
5455  // Check for homogeneous aggregates with AAPCS-VFP.
5456  if (IsEffectivelyAAPCS_VFP) {
5457  const Type *Base = nullptr;
5458  uint64_t Members = 0;
5459  if (isHomogeneousAggregate(RetTy, Base, Members)) {
5460  assert(Base && "Base class should be set for homogeneous aggregate");
5461  // Homogeneous Aggregates are returned directly.
5462  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5463  }
5464  }
5465 
5466  // Aggregates <= 4 bytes are returned in r0; other aggregates
5467  // are returned indirectly.
5468  uint64_t Size = getContext().getTypeSize(RetTy);
5469  if (Size <= 32) {
5470  if (getDataLayout().isBigEndian())
5471  // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
5472  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5473 
5474  // Return in the smallest viable integer type.
5475  if (Size <= 8)
5476  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5477  if (Size <= 16)
5478  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5479  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5480  } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
5481  llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
5482  llvm::Type *CoerceTy =
5483  llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
5484  return ABIArgInfo::getDirect(CoerceTy);
5485  }
5486 
5487  return getNaturalAlignIndirect(RetTy);
5488 }
5489 
5490 /// isIllegalVector - check whether Ty is an illegal vector type.
5491 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
5492  if (const VectorType *VT = Ty->getAs<VectorType> ()) {
5493  if (isAndroid()) {
5494  // Android shipped using Clang 3.1, which supported a slightly different
5495  // vector ABI. The primary differences were that 3-element vector types
5496  // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
5497  // accepts that legacy behavior for Android only.
5498  // Check whether VT is legal.
5499  unsigned NumElements = VT->getNumElements();
5500  // NumElements should be power of 2 or equal to 3.
5501  if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
5502  return true;
5503  } else {
5504  // Check whether VT is legal.
5505  unsigned NumElements = VT->getNumElements();
5506  uint64_t Size = getContext().getTypeSize(VT);
5507  // NumElements should be power of 2.
5508  if (!llvm::isPowerOf2_32(NumElements))
5509  return true;
5510  // Size should be greater than 32 bits.
5511  return Size <= 32;
5512  }
5513  }
5514  return false;
5515 }
5516 
5517 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5518  // Homogeneous aggregates for AAPCS-VFP must have base types of float,
5519  // double, or 64-bit or 128-bit vectors.
5520  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5521  if (BT->getKind() == BuiltinType::Float ||
5522  BT->getKind() == BuiltinType::Double ||
5523  BT->getKind() == BuiltinType::LongDouble)
5524  return true;
5525  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5526  unsigned VecSize = getContext().getTypeSize(VT);
5527  if (VecSize == 64 || VecSize == 128)
5528  return true;
5529  }
5530  return false;
5531 }
5532 
5533 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5534  uint64_t Members) const {
5535  return Members <= 4;
5536 }
5537 
5538 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5539  QualType Ty) const {
5540  CharUnits SlotSize = CharUnits::fromQuantity(4);
5541 
5542  // Empty records are ignored for parameter passing purposes.
5543  if (isEmptyRecord(getContext(), Ty, true)) {
5544  Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
5545  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5546  return Addr;
5547  }
5548 
5549  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5550  CharUnits TyAlignForABI = TyInfo.second;
5551 
5552  // Use indirect if size of the illegal vector is bigger than 16 bytes.
5553  bool IsIndirect = false;
5554  const Type *Base = nullptr;
5555  uint64_t Members = 0;
5556  if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
5557  IsIndirect = true;
5558 
5559  // ARMv7k passes structs bigger than 16 bytes indirectly, in space
5560  // allocated by the caller.
5561  } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
5562  getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5563  !isHomogeneousAggregate(Ty, Base, Members)) {
5564  IsIndirect = true;
5565 
5566  // Otherwise, bound the type's ABI alignment.
5567  // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
5568  // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
5569  // Our callers should be prepared to handle an under-aligned address.
5570  } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5571  getABIKind() == ARMABIInfo::AAPCS) {
5572  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
5573  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
5574  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5575  // ARMv7k allows type alignment up to 16 bytes.
5576  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
5577  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
5578  } else {
5579  TyAlignForABI = CharUnits::fromQuantity(4);
5580  }
5581  TyInfo.second = TyAlignForABI;
5582 
5583  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
5584  SlotSize, /*AllowHigherAlign*/ true);
5585 }
5586 
5587 //===----------------------------------------------------------------------===//
5588 // NVPTX ABI Implementation
5589 //===----------------------------------------------------------------------===//
5590 
5591 namespace {
5592 
5593 class NVPTXABIInfo : public ABIInfo {
5594 public:
5595  NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
5596 
5597  ABIArgInfo classifyReturnType(QualType RetTy) const;
5599 
5600  void computeInfo(CGFunctionInfo &FI) const override;
5601  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5602  QualType Ty) const override;
5603 };
5604 
5605 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
5606 public:
5607  NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
5608  : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
5609 
5610  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5611  CodeGen::CodeGenModule &M) const override;
5612 private:
5613  // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
5614  // resulting MDNode to the nvvm.annotations MDNode.
5615  static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
5616 };
5617 
5619  if (RetTy->isVoidType())
5620  return ABIArgInfo::getIgnore();
5621 
5622  // note: this is different from default ABI
5623  if (!RetTy->isScalarType())
5624  return ABIArgInfo::getDirect();
5625 
5626  // Treat an enum type as its underlying type.
5627  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5628  RetTy = EnumTy->getDecl()->getIntegerType();
5629 
5630  return (RetTy->isPromotableIntegerType() ?
5631  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5632 }
5633 
5635  // Treat an enum type as its underlying type.
5636  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5637  Ty = EnumTy->getDecl()->getIntegerType();
5638 
5639  // Return aggregates type as indirect by value
5640  if (isAggregateTypeForABI(Ty))
5641  return getNaturalAlignIndirect(Ty, /* byval */ true);
5642 
5643  return (Ty->isPromotableIntegerType() ?
5644  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
5645 }
5646 
5647 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
5648  if (!getCXXABI().classifyReturnType(FI))
5650  for (auto &I : FI.arguments())
5652 
5653  // Always honor user-specified calling convention.
5655  return;
5656 
5657  FI.setEffectiveCallingConvention(getRuntimeCC());
5658 }
5659 
5660 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5661  QualType Ty) const {
5662  llvm_unreachable("NVPTX does not support varargs");
5663 }
5664 
5665 void NVPTXTargetCodeGenInfo::
5666 setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5667  CodeGen::CodeGenModule &M) const{
5668  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5669  if (!FD) return;
5670 
5671  llvm::Function *F = cast<llvm::Function>(GV);
5672 
5673  // Perform special handling in OpenCL mode
5674  if (M.getLangOpts().OpenCL) {
5675  // Use OpenCL function attributes to check for kernel functions
5676  // By default, all functions are device functions
5677  if (FD->hasAttr<OpenCLKernelAttr>()) {
5678  // OpenCL __kernel functions get kernel metadata
5679  // Create !{<func-ref>, metadata !"kernel", i32 1} node
5680  addNVVMMetadata(F, "kernel", 1);
5681  // And kernel functions are not subject to inlining
5682  F->addFnAttr(llvm::Attribute::NoInline);
5683  }
5684  }
5685 
5686  // Perform special handling in CUDA mode.
5687  if (M.getLangOpts().CUDA) {
5688  // CUDA __global__ functions get a kernel metadata entry. Since
5689  // __global__ functions cannot be called from the device, we do not
5690  // need to set the noinline attribute.
5691  if (FD->hasAttr<CUDAGlobalAttr>()) {
5692  // Create !{<func-ref>, metadata !"kernel", i32 1} node
5693  addNVVMMetadata(F, "kernel", 1);
5694  }
5695  if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
5696  // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
5697  llvm::APSInt MaxThreads(32);
5698  MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
5699  if (MaxThreads > 0)
5700  addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
5701 
5702  // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
5703  // not specified in __launch_bounds__ or if the user specified a 0 value,
5704  // we don't have to add a PTX directive.
5705  if (Attr->getMinBlocks()) {
5706  llvm::APSInt MinBlocks(32);
5707  MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
5708  if (MinBlocks > 0)
5709  // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
5710  addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
5711  }
5712  }
5713  }
5714 }
5715 
5716 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
5717  int Operand) {
5718  llvm::Module *M = F->getParent();
5719  llvm::LLVMContext &Ctx = M->getContext();
5720 
5721  // Get "nvvm.annotations" metadata node
5722  llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
5723 
5724  llvm::Metadata *MDVals[] = {
5725  llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
5726  llvm::ConstantAsMetadata::get(
5727  llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
5728  // Append metadata to nvvm.annotations
5729  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
5730 }
5731 }
5732 
5733 //===----------------------------------------------------------------------===//
5734 // SystemZ ABI Implementation
5735 //===----------------------------------------------------------------------===//
5736 
5737 namespace {
5738 
5739 class SystemZABIInfo : public SwiftABIInfo {
5740  bool HasVector;
5741 
5742 public:
5743  SystemZABIInfo(CodeGenTypes &CGT, bool HV)
5744  : SwiftABIInfo(CGT), HasVector(HV) {}
5745 
5746  bool isPromotableIntegerType(QualType Ty) const;
5747  bool isCompoundType(QualType Ty) const;
5748  bool isVectorArgumentType(QualType Ty) const;
5749  bool isFPArgumentType(QualType Ty) const;
5750  QualType GetSingleElementType(QualType Ty) const;
5751 
5752  ABIArgInfo classifyReturnType(QualType RetTy) const;
5754 
5755  void computeInfo(CGFunctionInfo &FI) const override {
5756  if (!getCXXABI().classifyReturnType(FI))
5758  for (auto &I : FI.arguments())
5760  }
5761 
5762  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5763  QualType Ty) const override;
5764 
5765  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
5766  ArrayRef<llvm::Type*> scalars,
5767  bool asReturnValue) const override {
5768  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5769  }
5770 };
5771 
5772 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
5773 public:
5774  SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
5775  : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
5776 };
5777 
5778 }
5779 
5780 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
5781  // Treat an enum type as its underlying type.
5782  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5783  Ty = EnumTy->getDecl()->getIntegerType();
5784 
5785  // Promotable integer types are required to be promoted by the ABI.
5786  if (Ty->isPromotableIntegerType())
5787  return true;
5788 
5789  // 32-bit values must also be promoted.
5790  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5791  switch (BT->getKind()) {
5792  case BuiltinType::Int:
5793  case BuiltinType::UInt:
5794  return true;
5795  default:
5796  return false;
5797  }
5798  return false;
5799 }
5800 
5801 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
5802  return (Ty->isAnyComplexType() ||
5803  Ty->isVectorType() ||
5804  isAggregateTypeForABI(Ty));
5805 }
5806 
5807 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
5808  return (HasVector &&
5809  Ty->isVectorType() &&
5810  getContext().getTypeSize(Ty) <= 128);
5811 }
5812 
5813 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
5814  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
5815  switch (BT->getKind()) {
5816  case BuiltinType::Float:
5817  case BuiltinType::Double:
5818  return true;
5819  default:
5820  return false;
5821  }
5822 
5823  return false;
5824 }
5825 
5826 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
5827  if (const RecordType *RT = Ty->getAsStructureType()) {
5828  const RecordDecl *RD = RT->getDecl();
5829  QualType Found;
5830 
5831  // If this is a C++ record, check the bases first.
5832  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
5833  for (const auto &I : CXXRD->bases()) {
5834  QualType Base = I.getType();
5835 
5836  // Empty bases don't affect things either way.
5837  if (isEmptyRecord(getContext(), Base, true))
5838  continue;
5839 
5840  if (!Found.isNull())
5841  return Ty;
5842  Found = GetSingleElementType(Base);
5843  }
5844 
5845  // Check the fields.
5846  for (const auto *FD : RD->fields()) {
5847  // For compatibility with GCC, ignore empty bitfields in C++ mode.
5848  // Unlike isSingleElementStruct(), empty structure and array fields
5849  // do count. So do anonymous bitfields that aren't zero-sized.
5850  if (getContext().getLangOpts().CPlusPlus &&
5851  FD->isBitField() && FD->getBitWidthValue(getContext()) == 0)
5852  continue;
5853 
5854  // Unlike isSingleElementStruct(), arrays do not count.
5855  // Nested structures still do though.
5856  if (!Found.isNull())
5857  return Ty;
5858  Found = GetSingleElementType(FD->getType());
5859  }
5860 
5861  // Unlike isSingleElementStruct(), trailing padding is allowed.
5862  // An 8-byte aligned struct s { float f; } is passed as a double.
5863  if (!Found.isNull())
5864  return Found;
5865  }
5866 
5867  return Ty;
5868 }
5869 
5870 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5871  QualType Ty) const {
5872  // Assume that va_list type is correct; should be pointer to LLVM type:
5873  // struct {
5874  // i64 __gpr;
5875  // i64 __fpr;
5876  // i8 *__overflow_arg_area;
5877  // i8 *__reg_save_area;
5878  // };
5879 
5880  // Every non-vector argument occupies 8 bytes and is passed by preference
5881  // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
5882  // always passed on the stack.
5883  Ty = getContext().getCanonicalType(Ty);
5884  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5885  llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
5886  llvm::Type *DirectTy = ArgTy;
5888  bool IsIndirect = AI.isIndirect();
5889  bool InFPRs = false;
5890  bool IsVector = false;
5891  CharUnits UnpaddedSize;
5892  CharUnits DirectAlign;
5893  if (IsIndirect) {
5894  DirectTy = llvm::PointerType::getUnqual(DirectTy);
5895  UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
5896  } else {
5897  if (AI.getCoerceToType())
5898  ArgTy = AI.getCoerceToType();
5899  InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
5900  IsVector = ArgTy->isVectorTy();
5901  UnpaddedSize = TyInfo.first;
5902  DirectAlign = TyInfo.second;
5903  }
5904  CharUnits PaddedSize = CharUnits::fromQuantity(8);
5905  if (IsVector && UnpaddedSize > PaddedSize)
5906  PaddedSize = CharUnits::fromQuantity(16);
5907  assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
5908 
5909  CharUnits Padding = (PaddedSize - UnpaddedSize);
5910 
5911  llvm::Type *IndexTy = CGF.Int64Ty;
5912  llvm::Value *PaddedSizeV =
5913  llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
5914 
5915  if (IsVector) {
5916  // Work out the address of a vector argument on the stack.
5917  // Vector arguments are always passed in the high bits of a
5918  // single (8 byte) or double (16 byte) stack slot.
5919  Address OverflowArgAreaPtr =
5920  CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
5921  "overflow_arg_area_ptr");
5922  Address OverflowArgArea =
5923  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
5924  TyInfo.second);
5925  Address MemAddr =
5926  CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
5927 
5928  // Update overflow_arg_area_ptr pointer
5929  llvm::Value *NewOverflowArgArea =
5930  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
5931  "overflow_arg_area");
5932  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
5933 
5934  return MemAddr;
5935  }
5936 
5937  assert(PaddedSize.getQuantity() == 8);
5938 
5939  unsigned MaxRegs, RegCountField, RegSaveIndex;
5940  CharUnits RegPadding;
5941  if (InFPRs) {
5942  MaxRegs = 4; // Maximum of 4 FPR arguments
5943  RegCountField = 1; // __fpr
5944  RegSaveIndex = 16; // save offset for f0
5945  RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
5946  } else {
5947  MaxRegs = 5; // Maximum of 5 GPR arguments
5948  RegCountField = 0; // __gpr
5949  RegSaveIndex = 2; // save offset for r2
5950  RegPadding = Padding; // values are passed in the low bits of a GPR
5951  }
5952 
5953  Address RegCountPtr = CGF.Builder.CreateStructGEP(
5954  VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
5955  "reg_count_ptr");
5956  llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
5957  llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
5958  llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
5959  "fits_in_regs");
5960 
5961  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5962  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
5963  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5964  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
5965 
5966  // Emit code to load the value if it was passed in registers.
5967  CGF.EmitBlock(InRegBlock);
5968 
5969  // Work out the address of an argument register.
5970  llvm::Value *ScaledRegCount =
5971  CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
5972  llvm::Value *RegBase =
5973  llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
5974  + RegPadding.getQuantity());
5975  llvm::Value *RegOffset =
5976  CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
5977  Address RegSaveAreaPtr =
5978  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5979  "reg_save_area_ptr");
5980  llvm::Value *RegSaveArea =
5981  CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
5982  Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
5983  "raw_reg_addr"),
5984  PaddedSize);
5985  Address RegAddr =
5986  CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
5987 
5988  // Update the register count
5989  llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
5990  llvm::Value *NewRegCount =
5991  CGF.Builder.CreateAdd(RegCount, One, "reg_count");
5992  CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
5993  CGF.EmitBranch(ContBlock);
5994 
5995  // Emit code to load the value if it was passed in memory.
5996  CGF.EmitBlock(InMemBlock);
5997 
5998  // Work out the address of a stack argument.
5999  Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6000  VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6001  Address OverflowArgArea =
6002  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6003  PaddedSize);
6004  Address RawMemAddr =
6005  CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6006  Address MemAddr =
6007  CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6008 
6009  // Update overflow_arg_area_ptr pointer
6010  llvm::Value *NewOverflowArgArea =
6011  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6012  "overflow_arg_area");
6013  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6014  CGF.EmitBranch(ContBlock);
6015 
6016  // Return the appropriate result.
6017  CGF.EmitBlock(ContBlock);
6018  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6019  MemAddr, InMemBlock, "va_arg.addr");
6020 
6021  if (IsIndirect)
6022  ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6023  TyInfo.second);
6024 
6025  return ResAddr;
6026 }
6027 
6029  if (RetTy->isVoidType())
6030  return ABIArgInfo::getIgnore();
6031  if (isVectorArgumentType(RetTy))
6032  return ABIArgInfo::getDirect();
6033  if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6034  return getNaturalAlignIndirect(RetTy);
6035  return (isPromotableIntegerType(RetTy) ?
6036  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6037 }
6038 
6040  // Handle the generic C++ ABI.
6041  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6042  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6043 
6044  // Integers and enums are extended to full register width.
6045  if (isPromotableIntegerType(Ty))
6046  return ABIArgInfo::getExtend();
6047 
6048  // Handle vector types and vector-like structure types. Note that
6049  // as opposed to float-like structure types, we do not allow any
6050  // padding for vector-like structures, so verify the sizes match.
6051  uint64_t Size = getContext().getTypeSize(Ty);
6052  QualType SingleElementTy = GetSingleElementType(Ty);
6053  if (isVectorArgumentType(SingleElementTy) &&
6054  getContext().getTypeSize(SingleElementTy) == Size)
6055  return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6056 
6057  // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6058  if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6059  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6060 
6061  // Handle small structures.
6062  if (const RecordType *RT = Ty->getAs<RecordType>()) {
6063  // Structures with flexible arrays have variable length, so really
6064  // fail the size test above.
6065  const RecordDecl *RD = RT->getDecl();
6066  if (RD->hasFlexibleArrayMember())
6067  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6068 
6069  // The structure is passed as an unextended integer, a float, or a double.
6070  llvm::Type *PassTy;
6071  if (isFPArgumentType(SingleElementTy)) {
6072  assert(Size == 32 || Size == 64);
6073  if (Size == 32)
6074  PassTy = llvm::Type::getFloatTy(getVMContext());
6075  else
6076  PassTy = llvm::Type::getDoubleTy(getVMContext());
6077  } else
6078  PassTy = llvm::IntegerType::get(getVMContext(), Size);
6079  return ABIArgInfo::getDirect(PassTy);
6080  }
6081 
6082  // Non-structure compounds are passed indirectly.
6083  if (isCompoundType(Ty))
6084  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6085 
6086  return ABIArgInfo::getDirect(nullptr);
6087 }
6088 
6089 //===----------------------------------------------------------------------===//
6090 // MSP430 ABI Implementation
6091 //===----------------------------------------------------------------------===//
6092 
6093 namespace {
6094 
6095 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6096 public:
6097  MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6098  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6099  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6100  CodeGen::CodeGenModule &M) const override;
6101 };
6102 
6103 }
6104 
6105 void MSP430TargetCodeGenInfo::setTargetAttributes(const Decl *D,
6106  llvm::GlobalValue *GV,
6107  CodeGen::CodeGenModule &M) const {
6108  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6109  if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6110  // Handle 'interrupt' attribute:
6111  llvm::Function *F = cast<llvm::Function>(GV);
6112 
6113  // Step 1: Set ISR calling convention.
6114  F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6115 
6116  // Step 2: Add attributes goodness.
6117  F->addFnAttr(llvm::Attribute::NoInline);
6118 
6119  // Step 3: Emit ISR vector alias.
6120  unsigned Num = attr->getNumber() / 2;
6122  "__isr_" + Twine(Num), F);
6123  }
6124  }
6125 }
6126 
6127 //===----------------------------------------------------------------------===//
6128 // MIPS ABI Implementation. This works for both little-endian and
6129 // big-endian variants.
6130 //===----------------------------------------------------------------------===//
6131 
6132 namespace {
6133 class MipsABIInfo : public ABIInfo {
6134  bool IsO32;
6135  unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6136  void CoerceToIntArgs(uint64_t TySize,
6137  SmallVectorImpl<llvm::Type *> &ArgList) const;
6138  llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6139  llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6140  llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6141 public:
6142  MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6143  ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6144  StackAlignInBytes(IsO32 ? 8 : 16) {}
6145 
6146  ABIArgInfo classifyReturnType(QualType RetTy) const;
6147  ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6148  void computeInfo(CGFunctionInfo &FI) const override;
6149  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6150  QualType Ty) const override;
6151  bool shouldSignExtUnsignedType(QualType Ty) const override;
6152 };
6153 
6154 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6155  unsigned SizeOfUnwindException;
6156 public:
6157  MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6158  : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6159  SizeOfUnwindException(IsO32 ? 24 : 32) {}
6160 
6161  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6162  return 29;
6163  }
6164 
6165  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6166  CodeGen::CodeGenModule &CGM) const override {
6167  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6168  if (!FD) return;
6169  llvm::Function *Fn = cast<llvm::Function>(GV);
6170  if (FD->hasAttr<Mips16Attr>()) {
6171  Fn->addFnAttr("mips16");
6172  }
6173  else if (FD->hasAttr<NoMips16Attr>()) {
6174  Fn->addFnAttr("nomips16");
6175  }
6176 
6177  const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6178  if (!Attr)
6179  return;
6180 
6181  const char *Kind;
6182  switch (Attr->getInterrupt()) {
6183  case MipsInterruptAttr::eic: Kind = "eic"; break;
6184  case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6185  case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6186  case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6187  case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6188  case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6189  case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6190  case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6191  case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6192  }
6193 
6194  Fn->addFnAttr("interrupt", Kind);
6195 
6196  }
6197 
6198  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6199  llvm::Value *Address) const override;
6200 
6201  unsigned getSizeOfUnwindException() const override {
6202  return SizeOfUnwindException;
6203  }
6204 };
6205 }
6206 
6207 void MipsABIInfo::CoerceToIntArgs(
6208  uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6209  llvm::IntegerType *IntTy =
6210  llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6211 
6212  // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6213  for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6214  ArgList.push_back(IntTy);
6215 
6216  // If necessary, add one more integer type to ArgList.
6217  unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6218 
6219  if (R)
6220  ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6221 }
6222 
6223 // In N32/64, an aligned double precision floating point field is passed in
6224 // a register.
6225 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6226  SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6227 
6228  if (IsO32) {
6229  CoerceToIntArgs(TySize, ArgList);
6230  return llvm::StructType::get(getVMContext(), ArgList);
6231  }
6232 
6233  if (Ty->isComplexType())
6234  return CGT.ConvertType(Ty);
6235 
6236  const RecordType *RT = Ty->getAs<RecordType>();
6237 
6238  // Unions/vectors are passed in integer registers.
6239  if (!RT || !RT->isStructureOrClassType()) {
6240  CoerceToIntArgs(TySize, ArgList);
6241  return llvm::StructType::get(getVMContext(), ArgList);
6242  }
6243 
6244  const RecordDecl *RD = RT->getDecl();
6245  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6246  assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6247 
6248  uint64_t LastOffset = 0;
6249  unsigned idx = 0;
6250  llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6251 
6252  // Iterate over fields in the struct/class and check if there are any aligned
6253  // double fields.
6254  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6255  i != e; ++i, ++idx) {
6256  const QualType Ty = i->getType();
6257  const BuiltinType *BT = Ty->getAs<BuiltinType>();
6258 
6259  if (!BT || BT->getKind() != BuiltinType::Double)
6260  continue;
6261 
6262  uint64_t Offset = Layout.getFieldOffset(idx);
6263  if (Offset % 64) // Ignore doubles that are not aligned.
6264  continue;
6265 
6266  // Add ((Offset - LastOffset) / 64) args of type i64.
6267  for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6268  ArgList.push_back(I64);
6269 
6270  // Add double type.
6271  ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6272  LastOffset = Offset + 64;
6273  }
6274 
6275  CoerceToIntArgs(TySize - LastOffset, IntArgList);
6276  ArgList.append(IntArgList.begin(), IntArgList.end());
6277 
6278  return llvm::StructType::get(getVMContext(), ArgList);
6279 }
6280 
6281 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6282  uint64_t Offset) const {
6283  if (OrigOffset + MinABIStackAlignInBytes > Offset)
6284  return nullptr;
6285 
6286  return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6287 }
6288 
6289 ABIArgInfo
6290 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6292 
6293  uint64_t OrigOffset = Offset;
6294  uint64_t TySize = getContext().getTypeSize(Ty);
6295  uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6296 
6297  Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6298  (uint64_t)StackAlignInBytes);
6299  unsigned CurrOffset = llvm::alignTo(Offset, Align);
6300  Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6301 
6302  if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6303  // Ignore empty aggregates.
6304  if (TySize == 0)
6305  return ABIArgInfo::getIgnore();
6306 
6307  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
6308  Offset = OrigOffset + MinABIStackAlignInBytes;
6309  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6310  }
6311 
6312  // If we have reached here, aggregates are passed directly by coercing to
6313  // another structure type. Padding is inserted if the offset of the
6314  // aggregate is unaligned.
6315  ABIArgInfo ArgInfo =
6316  ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6317  getPaddingType(OrigOffset, CurrOffset));
6318  ArgInfo.setInReg(true);
6319  return ArgInfo;
6320  }
6321 
6322  // Treat an enum type as its underlying type.
6323  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6324  Ty = EnumTy->getDecl()->getIntegerType();
6325 
6326  // All integral types are promoted to the GPR width.
6327  if (Ty->isIntegralOrEnumerationType())
6328  return ABIArgInfo::getExtend();
6329 
6330  return ABIArgInfo::getDirect(
6331  nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6332 }
6333 
6334 llvm::Type*
6335 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6336  const RecordType *RT = RetTy->getAs<RecordType>();
6338 
6339  if (RT && RT->isStructureOrClassType()) {
6340  const RecordDecl *RD = RT->getDecl();
6341  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6342  unsigned FieldCnt = Layout.getFieldCount();
6343 
6344  // N32/64 returns struct/classes in floating point registers if the
6345  // following conditions are met:
6346  // 1. The size of the struct/class is no larger than 128-bit.
6347  // 2. The struct/class has one or two fields all of which are floating
6348  // point types.
6349  // 3. The offset of the first field is zero (this follows what gcc does).
6350  //
6351  // Any other composite results are returned in integer registers.
6352  //
6353  if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6354  RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6355  for (; b != e; ++b) {
6356  const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6357 
6358  if (!BT || !BT->isFloatingPoint())
6359  break;
6360 
6361  RTList.push_back(CGT.ConvertType(b->getType()));
6362  }
6363 
6364  if (b == e)
6365  return llvm::StructType::get(getVMContext(), RTList,
6366  RD->hasAttr<PackedAttr>());
6367 
6368  RTList.clear();
6369  }
6370  }
6371 
6372  CoerceToIntArgs(Size, RTList);
6373  return llvm::StructType::get(getVMContext(), RTList);
6374 }
6375 
6377  uint64_t Size = getContext().getTypeSize(RetTy);
6378 
6379  if (RetTy->isVoidType())
6380  return ABIArgInfo::getIgnore();
6381 
6382  // O32 doesn't treat zero-sized structs differently from other structs.
6383  // However, N32/N64 ignores zero sized return values.
6384  if (!IsO32 && Size == 0)
6385  return ABIArgInfo::getIgnore();
6386 
6387  if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6388  if (Size <= 128) {
6389  if (RetTy->isAnyComplexType())
6390  return ABIArgInfo::getDirect();
6391 
6392  // O32 returns integer vectors in registers and N32/N64 returns all small
6393  // aggregates in registers.
6394  if (!IsO32 ||
6395  (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6396  ABIArgInfo ArgInfo =
6397  ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6398  ArgInfo.setInReg(true);
6399  return ArgInfo;
6400  }
6401  }
6402 
6403  return getNaturalAlignIndirect(RetTy);
6404  }
6405 
6406  // Treat an enum type as its underlying type.
6407  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6408  RetTy = EnumTy->getDecl()->getIntegerType();
6409 
6410  return (RetTy->isPromotableIntegerType() ?
6411  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6412 }
6413 
6414 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
6415  ABIArgInfo &RetInfo = FI.getReturnInfo();
6416  if (!getCXXABI().classifyReturnType(FI))
6417  RetInfo = classifyReturnType(FI.getReturnType());
6418 
6419  // Check if a pointer to an aggregate is passed as a hidden argument.
6420  uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
6421 
6422  for (auto &I : FI.arguments())
6423  I.info = classifyArgumentType(I.type, Offset);
6424 }
6425 
6426 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6427  QualType OrigTy) const {
6428  QualType Ty = OrigTy;
6429 
6430  // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
6431  // Pointers are also promoted in the same way but this only matters for N32.
6432  unsigned SlotSizeInBits = IsO32 ? 32 : 64;
6433  unsigned PtrWidth = getTarget().getPointerWidth(0);
6434  bool DidPromote = false;
6435  if ((Ty->isIntegerType() &&
6436  getContext().getIntWidth(Ty) < SlotSizeInBits) ||
6437  (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
6438  DidPromote = true;
6439  Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
6440  Ty->isSignedIntegerType());
6441  }
6442 
6443  auto TyInfo = getContext().getTypeInfoInChars(Ty);
6444 
6445  // The alignment of things in the argument area is never larger than
6446  // StackAlignInBytes.
6447  TyInfo.second =
6448  std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
6449 
6450  // MinABIStackAlignInBytes is the size of argument slots on the stack.
6451  CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
6452 
6453  Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
6454  TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
6455 
6456 
6457  // If there was a promotion, "unpromote" into a temporary.
6458  // TODO: can we just use a pointer into a subset of the original slot?
6459  if (DidPromote) {
6460  Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
6461  llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
6462 
6463  // Truncate down to the right width.
6464  llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
6465  : CGF.IntPtrTy);
6466  llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
6467  if (OrigTy->isPointerType())
6468  V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
6469 
6470  CGF.Builder.CreateStore(V, Temp);
6471  Addr = Temp;
6472  }
6473 
6474  return Addr;
6475 }
6476 
6477 bool MipsABIInfo::shouldSignExtUnsignedType(QualType Ty) const {
6478  int TySize = getContext().getTypeSize(Ty);
6479 
6480  // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
6481  if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
6482  return true;
6483 
6484  return false;
6485 }
6486 
6487 bool
6488 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6489  llvm::Value *Address) const {
6490  // This information comes from gcc's implementation, which seems to
6491  // as canonical as it gets.
6492 
6493  // Everything on MIPS is 4 bytes. Double-precision FP registers
6494  // are aliased to pairs of single-precision FP registers.
6495  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
6496 
6497  // 0-31 are the general purpose registers, $0 - $31.
6498  // 32-63 are the floating-point registers, $f0 - $f31.
6499  // 64 and 65 are the multiply/divide registers, $hi and $lo.
6500  // 66 is the (notional, I think) register for signal-handler return.
6501  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
6502 
6503  // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
6504  // They are one bit wide and ignored here.
6505 
6506  // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
6507  // (coprocessor 1 is the FP unit)
6508  // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
6509  // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
6510  // 176-181 are the DSP accumulator registers.
6511  AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
6512  return false;
6513 }
6514 
6515 //===----------------------------------------------------------------------===//
6516 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
6517 // Currently subclassed only to implement custom OpenCL C function attribute
6518 // handling.
6519 //===----------------------------------------------------------------------===//
6520 
6521 namespace {
6522 
6523 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
6524 public:
6525  TCETargetCodeGenInfo(CodeGenTypes &CGT)
6526  : DefaultTargetCodeGenInfo(CGT) {}
6527 
6528  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6529  CodeGen::CodeGenModule &M) const override;
6530 };
6531 
6532 void TCETargetCodeGenInfo::setTargetAttributes(
6533  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6534  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6535  if (!FD) return;
6536 
6537  llvm::Function *F = cast<llvm::Function>(GV);
6538 
6539  if (M.getLangOpts().OpenCL) {
6540  if (FD->hasAttr<OpenCLKernelAttr>()) {
6541  // OpenCL C Kernel functions are not subject to inlining
6542  F->addFnAttr(llvm::Attribute::NoInline);
6543  const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
6544  if (Attr) {
6545  // Convert the reqd_work_group_size() attributes to metadata.
6546  llvm::LLVMContext &Context = F->getContext();
6547  llvm::NamedMDNode *OpenCLMetadata =
6548  M.getModule().getOrInsertNamedMetadata(
6549  "opencl.kernel_wg_size_info");
6550 
6552  Operands.push_back(llvm::ConstantAsMetadata::get(F));
6553 
6554  Operands.push_back(
6555  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6556  M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
6557  Operands.push_back(
6558  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6559  M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
6560  Operands.push_back(
6561  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
6562  M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
6563 
6564  // Add a boolean constant operand for "required" (true) or "hint"
6565  // (false) for implementing the work_group_size_hint attr later.
6566  // Currently always true as the hint is not yet implemented.
6567  Operands.push_back(
6568  llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
6569  OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
6570  }
6571  }
6572  }
6573 }
6574 
6575 }
6576 
6577 //===----------------------------------------------------------------------===//
6578 // Hexagon ABI Implementation
6579 //===----------------------------------------------------------------------===//
6580 
6581 namespace {
6582 
6583 class HexagonABIInfo : public ABIInfo {
6584 
6585 
6586 public:
6587  HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6588 
6589 private:
6590 
6591  ABIArgInfo classifyReturnType(QualType RetTy) const;
6593 
6594  void computeInfo(CGFunctionInfo &FI) const override;
6595 
6596  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6597  QualType Ty) const override;
6598 };
6599 
6600 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
6601 public:
6602  HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
6603  :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
6604 
6605  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
6606  return 29;
6607  }
6608 };
6609 
6610 }
6611 
6612 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
6613  if (!getCXXABI().classifyReturnType(FI))
6615  for (auto &I : FI.arguments())
6617 }
6618 
6620  if (!isAggregateTypeForABI(Ty)) {
6621  // Treat an enum type as its underlying type.
6622  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6623  Ty = EnumTy->getDecl()->getIntegerType();
6624 
6625  return (Ty->isPromotableIntegerType() ?
6626  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6627  }
6628 
6629  // Ignore empty records.
6630  if (isEmptyRecord(getContext(), Ty, true))
6631  return ABIArgInfo::getIgnore();
6632 
6633  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
6634  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
6635 
6636  uint64_t Size = getContext().getTypeSize(Ty);
6637  if (Size > 64)
6638  return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
6639  // Pass in the smallest viable integer type.
6640  else if (Size > 32)
6641  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6642  else if (Size > 16)
6643  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6644  else if (Size > 8)
6645  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6646  else
6647  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6648 }
6649 
6651  if (RetTy->isVoidType())
6652  return ABIArgInfo::getIgnore();
6653 
6654  // Large vector types should be returned via memory.
6655  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
6656  return getNaturalAlignIndirect(RetTy);
6657 
6658  if (!isAggregateTypeForABI(RetTy)) {
6659  // Treat an enum type as its underlying type.
6660  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6661  RetTy = EnumTy->getDecl()->getIntegerType();
6662 
6663  return (RetTy->isPromotableIntegerType() ?
6664  ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
6665  }
6666 
6667  if (isEmptyRecord(getContext(), RetTy, true))
6668  return ABIArgInfo::getIgnore();
6669 
6670  // Aggregates <= 8 bytes are returned in r0; other aggregates
6671  // are returned indirectly.
6672  uint64_t Size = getContext().getTypeSize(RetTy);
6673  if (Size <= 64) {
6674  // Return in the smallest viable integer type.
6675  if (Size <= 8)
6676  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6677  if (Size <= 16)
6678  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6679  if (Size <= 32)
6680  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6681  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
6682  }
6683 
6684  return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
6685 }
6686 
6687 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6688  QualType Ty) const {
6689  // FIXME: Someone needs to audit that this handle alignment correctly.
6690  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
6691  getContext().getTypeInfoInChars(Ty),
6693  /*AllowHigherAlign*/ true);
6694 }
6695 
6696 //===----------------------------------------------------------------------===//
6697 // Lanai ABI Implementation
6698 //===----------------------------------------------------------------------===//
6699 
6700 namespace {
6701 class LanaiABIInfo : public DefaultABIInfo {
6702 public:
6703  LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6704 
6705  bool shouldUseInReg(QualType Ty, CCState &State) const;
6706 
6707  void computeInfo(CGFunctionInfo &FI) const override {
6708  CCState State(FI.getCallingConvention());
6709  // Lanai uses 4 registers to pass arguments unless the function has the
6710  // regparm attribute set.
6711  if (FI.getHasRegParm()) {
6712  State.FreeRegs = FI.getRegParm();
6713  } else {
6714  State.FreeRegs = 4;
6715  }
6716 
6717  if (!getCXXABI().classifyReturnType(FI))
6719  for (auto &I : FI.arguments())
6720  I.info = classifyArgumentType(I.type, State);
6721  }
6722 
6723  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
6724  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
6725 };
6726 } // end anonymous namespace
6727 
6728 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
6729  unsigned Size = getContext().getTypeSize(Ty);
6730  unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
6731 
6732  if (SizeInRegs == 0)
6733  return false;
6734 
6735  if (SizeInRegs > State.FreeRegs) {
6736  State.FreeRegs = 0;
6737  return false;
6738  }
6739 
6740  State.FreeRegs -= SizeInRegs;
6741 
6742  return true;
6743 }
6744 
6745 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
6746  CCState &State) const {
6747  if (!ByVal) {
6748  if (State.FreeRegs) {
6749  --State.FreeRegs; // Non-byval indirects just use one pointer.
6750  return getNaturalAlignIndirectInReg(Ty);
6751  }
6752  return getNaturalAlignIndirect(Ty, false);
6753  }
6754 
6755  // Compute the byval alignment.
6756  const unsigned MinABIStackAlignInBytes = 4;
6757  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
6758  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
6759  /*Realign=*/TypeAlign >
6760  MinABIStackAlignInBytes);
6761 }
6762 
6764  CCState &State) const {
6765  // Check with the C++ ABI first.
6766  const RecordType *RT = Ty->getAs<RecordType>();
6767  if (RT) {
6768  CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
6769  if (RAA == CGCXXABI::RAA_Indirect) {
6770  return getIndirectResult(Ty, /*ByVal=*/false, State);
6771  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
6772  return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
6773  }
6774  }
6775 
6776  if (isAggregateTypeForABI(Ty)) {
6777  // Structures with flexible arrays are always indirect.
6778  if (RT && RT->getDecl()->hasFlexibleArrayMember())
6779  return getIndirectResult(Ty, /*ByVal=*/true, State);
6780 
6781  // Ignore empty structs/unions.
6782  if (isEmptyRecord(getContext(), Ty, true))
6783  return ABIArgInfo::getIgnore();
6784 
6785  llvm::LLVMContext &LLVMContext = getVMContext();
6786  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
6787  if (SizeInRegs <= State.FreeRegs) {
6788  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
6789  SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
6790  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
6791  State.FreeRegs -= SizeInRegs;
6792  return ABIArgInfo::getDirectInReg(Result);
6793  } else {
6794  State.FreeRegs = 0;
6795  }
6796  return getIndirectResult(Ty, true, State);
6797  }
6798 
6799  // Treat an enum type as its underlying type.
6800  if (const auto *EnumTy = Ty->getAs<EnumType>())
6801  Ty = EnumTy->getDecl()->getIntegerType();
6802 
6803  bool InReg = shouldUseInReg(Ty, State);
6804  if (Ty->isPromotableIntegerType()) {
6805  if (InReg)
6806  return ABIArgInfo::getDirectInReg();
6807  return ABIArgInfo::getExtend();
6808  }
6809  if (InReg)
6810  return ABIArgInfo::getDirectInReg();
6811  return ABIArgInfo::getDirect();
6812 }
6813 
6814 namespace {
6815 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
6816 public:
6817  LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
6818  : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
6819 };
6820 }
6821 
6822 //===----------------------------------------------------------------------===//
6823 // AMDGPU ABI Implementation
6824 //===----------------------------------------------------------------------===//
6825 
6826 namespace {
6827 
6828 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
6829 public:
6830  AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
6831  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6832  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6833  CodeGen::CodeGenModule &M) const override;
6834  unsigned getOpenCLKernelCallingConv() const override;
6835 };
6836 
6837 }
6838 
6839 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
6840  const Decl *D,
6841  llvm::GlobalValue *GV,
6842  CodeGen::CodeGenModule &M) const {
6843  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6844  if (!FD)
6845  return;
6846 
6847  if (const auto Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
6848  llvm::Function *F = cast<llvm::Function>(GV);
6849  uint32_t NumVGPR = Attr->getNumVGPR();
6850  if (NumVGPR != 0)
6851  F->addFnAttr("amdgpu_num_vgpr", llvm::utostr(NumVGPR));
6852  }
6853 
6854  if (const auto Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
6855  llvm::Function *F = cast<llvm::Function>(GV);
6856  unsigned NumSGPR = Attr->getNumSGPR();
6857  if (NumSGPR != 0)
6858  F->addFnAttr("amdgpu_num_sgpr", llvm::utostr(NumSGPR));
6859  }
6860 }
6861 
6862 
6863 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
6864  return llvm::CallingConv::AMDGPU_KERNEL;
6865 }
6866 
6867 //===----------------------------------------------------------------------===//
6868 // SPARC v8 ABI Implementation.
6869 // Based on the SPARC Compliance Definition version 2.4.1.
6870 //
6871 // Ensures that complex values are passed in registers.
6872 //
6873 namespace {
6874 class SparcV8ABIInfo : public DefaultABIInfo {
6875 public:
6876  SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
6877 
6878 private:
6879  ABIArgInfo classifyReturnType(QualType RetTy) const;
6880  void computeInfo(CGFunctionInfo &FI) const override;
6881 };
6882 } // end anonymous namespace
6883 
6884 
6885 ABIArgInfo
6887  if (Ty->isAnyComplexType()) {
6888  return ABIArgInfo::getDirect();
6889  }
6890  else {
6892  }
6893 }
6894 
6895 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
6896 
6898  for (auto &Arg : FI.arguments())
6899  Arg.info = classifyArgumentType(Arg.type);
6900 }
6901 
6902 namespace {
6903 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
6904 public:
6905  SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
6906  : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
6907 };
6908 } // end anonymous namespace
6909 
6910 //===----------------------------------------------------------------------===//
6911 // SPARC v9 ABI Implementation.
6912 // Based on the SPARC Compliance Definition version 2.4.1.
6913 //
6914 // Function arguments a mapped to a nominal "parameter array" and promoted to
6915 // registers depending on their type. Each argument occupies 8 or 16 bytes in
6916 // the array, structs larger than 16 bytes are passed indirectly.
6917 //
6918 // One case requires special care:
6919 //
6920 // struct mixed {
6921 // int i;
6922 // float f;
6923 // };
6924 //
6925 // When a struct mixed is passed by value, it only occupies 8 bytes in the
6926 // parameter array, but the int is passed in an integer register, and the float
6927 // is passed in a floating point register. This is represented as two arguments
6928 // with the LLVM IR inreg attribute:
6929 //
6930 // declare void f(i32 inreg %i, float inreg %f)
6931 //
6932 // The code generator will only allocate 4 bytes from the parameter array for
6933 // the inreg arguments. All other arguments are allocated a multiple of 8
6934 // bytes.
6935 //
6936 namespace {
6937 class SparcV9ABIInfo : public ABIInfo {
6938 public:
6939  SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6940 
6941 private:
6942  ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
6943  void computeInfo(CGFunctionInfo &FI) const override;
6944  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6945  QualType Ty) const override;
6946 
6947  // Coercion type builder for structs passed in registers. The coercion type
6948  // serves two purposes:
6949  //
6950  // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
6951  // in registers.
6952  // 2. Expose aligned floating point elements as first-level elements, so the
6953  // code generator knows to pass them in floating point registers.
6954  //
6955  // We also compute the InReg flag which indicates that the struct contains
6956  // aligned 32-bit floats.
6957  //
6958  struct CoerceBuilder {
6959  llvm::LLVMContext &Context;
6960  const llvm::DataLayout &DL;
6962  uint64_t Size;
6963  bool InReg;
6964 
6965  CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
6966  : Context(c), DL(dl), Size(0), InReg(false) {}
6967 
6968  // Pad Elems with integers until Size is ToSize.
6969  void pad(uint64_t ToSize) {
6970  assert(ToSize >= Size && "Cannot remove elements");
6971  if (ToSize == Size)
6972  return;
6973 
6974  // Finish the current 64-bit word.
6975  uint64_t Aligned = llvm::alignTo(Size, 64);
6976  if (Aligned > Size && Aligned <= ToSize) {
6977  Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
6978  Size = Aligned;
6979  }
6980 
6981  // Add whole 64-bit words.
6982  while (Size + 64 <= ToSize) {
6983  Elems.push_back(llvm::Type::getInt64Ty(Context));
6984  Size += 64;
6985  }
6986 
6987  // Final in-word padding.
6988  if (Size < ToSize) {
6989  Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
6990  Size = ToSize;
6991  }
6992  }
6993 
6994  // Add a floating point element at Offset.
6995  void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
6996  // Unaligned floats are treated as integers.
6997  if (Offset % Bits)
6998  return;
6999  // The InReg flag is only required if there are any floats < 64 bits.
7000  if (Bits < 64)
7001  InReg = true;
7002  pad(Offset);
7003  Elems.push_back(Ty);
7004  Size = Offset + Bits;
7005  }
7006 
7007  // Add a struct type to the coercion type, starting at Offset (in bits).
7008  void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7009  const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7010  for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7011  llvm::Type *ElemTy = StrTy->getElementType(i);
7012  uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7013  switch (ElemTy->getTypeID()) {
7014  case llvm::Type::StructTyID:
7015  addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7016  break;
7017  case llvm::Type::FloatTyID:
7018  addFloat(ElemOffset, ElemTy, 32);
7019  break;
7020  case llvm::Type::DoubleTyID:
7021  addFloat(ElemOffset, ElemTy, 64);
7022  break;
7023  case llvm::Type::FP128TyID:
7024  addFloat(ElemOffset, ElemTy, 128);
7025  break;
7026  case llvm::Type::PointerTyID:
7027  if (ElemOffset % 64 == 0) {
7028  pad(ElemOffset);
7029  Elems.push_back(ElemTy);
7030  Size += 64;
7031  }
7032  break;
7033  default:
7034  break;
7035  }
7036  }
7037  }
7038 
7039  // Check if Ty is a usable substitute for the coercion type.
7040  bool isUsableType(llvm::StructType *Ty) const {
7041  return llvm::makeArrayRef(Elems) == Ty->elements();
7042  }
7043 
7044  // Get the coercion type as a literal struct type.
7045  llvm::Type *getType() const {
7046  if (Elems.size() == 1)
7047  return Elems.front();
7048  else
7049  return llvm::StructType::get(Context, Elems);
7050  }
7051  };
7052 };
7053 } // end anonymous namespace
7054 
7055 ABIArgInfo
7056 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
7057  if (Ty->isVoidType())
7058  return ABIArgInfo::getIgnore();
7059 
7060  uint64_t Size = getContext().getTypeSize(Ty);
7061 
7062  // Anything too big to fit in registers is passed with an explicit indirect
7063  // pointer / sret pointer.
7064  if (Size > SizeLimit)
7065  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
7066 
7067  // Treat an enum type as its underlying type.
7068  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7069  Ty = EnumTy->getDecl()->getIntegerType();
7070 
7071  // Integer types smaller than a register are extended.
7072  if (Size < 64 && Ty->isIntegerType())
7073  return ABIArgInfo::getExtend();
7074 
7075  // Other non-aggregates go in registers.
7076  if (!isAggregateTypeForABI(Ty))
7077  return ABIArgInfo::getDirect();
7078 
7079  // If a C++ object has either a non-trivial copy constructor or a non-trivial
7080  // destructor, it is passed with an explicit indirect pointer / sret pointer.
7081  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
7082  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
7083 
7084  // This is a small aggregate type that should be passed in registers.
7085  // Build a coercion type from the LLVM struct type.
7086  llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
7087  if (!StrTy)
7088  return ABIArgInfo::getDirect();
7089 
7090  CoerceBuilder CB(getVMContext(), getDataLayout());
7091  CB.addStruct(0, StrTy);
7092  CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
7093 
7094  // Try to use the original type for coercion.
7095  llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
7096 
7097  if (CB.InReg)
7098  return ABIArgInfo::getDirectInReg(CoerceTy);
7099  else
7100  return ABIArgInfo::getDirect(CoerceTy);
7101 }
7102 
7103 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7104  QualType Ty) const {
7105  ABIArgInfo AI = classifyType(Ty, 16 * 8);
7106  llvm::Type *ArgTy = CGT.ConvertType(Ty);
7107  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7108  AI.setCoerceToType(ArgTy);
7109 
7110  CharUnits SlotSize = CharUnits::fromQuantity(8);
7111 
7112  CGBuilderTy &Builder = CGF.Builder;
7113  Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
7114  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7115 
7116  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
7117 
7118  Address ArgAddr = Address::invalid();
7119  CharUnits Stride;
7120  switch (AI.getKind()) {
7121  case ABIArgInfo::Expand:
7123  case ABIArgInfo::InAlloca:
7124  llvm_unreachable("Unsupported ABI kind for va_arg");
7125 
7126  case ABIArgInfo::Extend: {
7127  Stride = SlotSize;
7128  CharUnits Offset = SlotSize - TypeInfo.first;
7129  ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
7130  break;
7131  }
7132 
7133  case ABIArgInfo::Direct: {
7134  auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
7135  Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
7136  ArgAddr = Addr;
7137  break;
7138  }
7139 
7140  case ABIArgInfo::Indirect:
7141  Stride = SlotSize;
7142  ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
7143  ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
7144  TypeInfo.second);
7145  break;
7146 
7147  case ABIArgInfo::Ignore:
7148  return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
7149  }
7150 
7151  // Update VAList.
7152  llvm::Value *NextPtr =
7153  Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
7154  Builder.CreateStore(NextPtr, VAListAddr);
7155 
7156  return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
7157 }
7158 
7159 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7160  FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
7161  for (auto &I : FI.arguments())
7162  I.info = classifyType(I.type, 16 * 8);
7163 }
7164 
7165 namespace {
7166 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
7167 public:
7168  SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
7169  : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
7170 
7171  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7172  return 14;
7173  }
7174 
7175  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7176  llvm::Value *Address) const override;
7177 };
7178 } // end anonymous namespace
7179 
7180 bool
7181 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7182  llvm::Value *Address) const {
7183  // This is calculated from the LLVM and GCC tables and verified
7184  // against gcc output. AFAIK all ABIs use the same encoding.
7185 
7186  CodeGen::CGBuilderTy &Builder = CGF.Builder;
7187 
7188  llvm::IntegerType *i8 = CGF.Int8Ty;
7189  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
7190  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
7191 
7192  // 0-31: the 8-byte general-purpose registers
7193  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
7194 
7195  // 32-63: f0-31, the 4-byte floating-point registers
7196  AssignToArrayRange(Builder, Address, Four8, 32, 63);
7197 
7198  // Y = 64
7199  // PSR = 65
7200  // WIM = 66
7201  // TBR = 67
7202  // PC = 68
7203  // NPC = 69
7204  // FSR = 70
7205  // CSR = 71
7206  AssignToArrayRange(Builder, Address, Eight8, 64, 71);
7207 
7208  // 72-87: d0-15, the 8-byte floating-point registers
7209  AssignToArrayRange(Builder, Address, Eight8, 72, 87);
7210 
7211  return false;
7212 }
7213 
7214 
7215 //===----------------------------------------------------------------------===//
7216 // XCore ABI Implementation
7217 //===----------------------------------------------------------------------===//
7218 
7219 namespace {
7220 
7221 /// A SmallStringEnc instance is used to build up the TypeString by passing
7222 /// it by reference between functions that append to it.
7223 typedef llvm::SmallString<128> SmallStringEnc;
7224 
7225 /// TypeStringCache caches the meta encodings of Types.
7226 ///
7227 /// The reason for caching TypeStrings is two fold:
7228 /// 1. To cache a type's encoding for later uses;
7229 /// 2. As a means to break recursive member type inclusion.
7230 ///
7231 /// A cache Entry can have a Status of:
7232 /// NonRecursive: The type encoding is not recursive;
7233 /// Recursive: The type encoding is recursive;
7234 /// Incomplete: An incomplete TypeString;
7235 /// IncompleteUsed: An incomplete TypeString that has been used in a
7236 /// Recursive type encoding.
7237 ///
7238 /// A NonRecursive entry will have all of its sub-members expanded as fully
7239 /// as possible. Whilst it may contain types which are recursive, the type
7240 /// itself is not recursive and thus its encoding may be safely used whenever
7241 /// the type is encountered.
7242 ///
7243 /// A Recursive entry will have all of its sub-members expanded as fully as
7244 /// possible. The type itself is recursive and it may contain other types which
7245 /// are recursive. The Recursive encoding must not be used during the expansion
7246 /// of a recursive type's recursive branch. For simplicity the code uses
7247 /// IncompleteCount to reject all usage of Recursive encodings for member types.
7248 ///
7249 /// An Incomplete entry is always a RecordType and only encodes its
7250 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
7251 /// are placed into the cache during type expansion as a means to identify and
7252 /// handle recursive inclusion of types as sub-members. If there is recursion
7253 /// the entry becomes IncompleteUsed.
7254 ///
7255 /// During the expansion of a RecordType's members:
7256 ///
7257 /// If the cache contains a NonRecursive encoding for the member type, the
7258 /// cached encoding is used;
7259 ///
7260 /// If the cache contains a Recursive encoding for the member type, the
7261 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
7262 ///
7263 /// If the member is a RecordType, an Incomplete encoding is placed into the
7264 /// cache to break potential recursive inclusion of itself as a sub-member;
7265 ///
7266 /// Once a member RecordType has been expanded, its temporary incomplete
7267 /// entry is removed from the cache. If a Recursive encoding was swapped out
7268 /// it is swapped back in;
7269 ///
7270 /// If an incomplete entry is used to expand a sub-member, the incomplete
7271 /// entry is marked as IncompleteUsed. The cache keeps count of how many
7272 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
7273 ///
7274 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
7275 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
7276 /// Else the member is part of a recursive type and thus the recursion has
7277 /// been exited too soon for the encoding to be correct for the member.
7278 ///
7279 class TypeStringCache {
7280  enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
7281  struct Entry {
7282  std::string Str; // The encoded TypeString for the type.
7283  enum Status State; // Information about the encoding in 'Str'.
7284  std::string Swapped; // A temporary place holder for a Recursive encoding
7285  // during the expansion of RecordType's members.
7286  };
7287  std::map<const IdentifierInfo *, struct Entry> Map;
7288  unsigned IncompleteCount; // Number of Incomplete entries in the Map.
7289  unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
7290 public:
7291  TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
7292  void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
7293  bool removeIncomplete(const IdentifierInfo *ID);
7294  void addIfComplete(const IdentifierInfo *ID, StringRef Str,
7295  bool IsRecursive);
7296  StringRef lookupStr(const IdentifierInfo *ID);
7297 };
7298 
7299 /// TypeString encodings for enum & union fields must be order.
7300 /// FieldEncoding is a helper for this ordering process.
7301 class FieldEncoding {
7302  bool HasName;
7303  std::string Enc;
7304 public:
7305  FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
7306  StringRef str() {return Enc.c_str();}
7307  bool operator<(const FieldEncoding &rhs) const {
7308  if (HasName != rhs.HasName) return HasName;
7309  return Enc < rhs.Enc;
7310  }
7311 };
7312 
7313 class XCoreABIInfo : public DefaultABIInfo {
7314 public:
7315  XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7316  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7317  QualType Ty) const override;
7318 };
7319 
7320 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
7321  mutable TypeStringCache TSC;
7322 public:
7323  XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
7324  :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
7325  void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7326  CodeGen::CodeGenModule &M) const override;
7327 };
7328 
7329 } // End anonymous namespace.
7330 
7331 // TODO: this implementation is likely now redundant with the default
7332 // EmitVAArg.
7333 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7334  QualType Ty) const {
7335  CGBuilderTy &Builder = CGF.Builder;
7336 
7337  // Get the VAList.
7338  CharUnits SlotSize = CharUnits::fromQuantity(4);
7339  Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
7340 
7341  // Handle the argument.
7343  CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
7344  llvm::Type *ArgTy = CGT.ConvertType(Ty);
7345  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
7346  AI.setCoerceToType(ArgTy);
7347  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
7348 
7349  Address Val = Address::invalid();
7350  CharUnits ArgSize = CharUnits::Zero();
7351  switch (AI.getKind()) {
7352  case ABIArgInfo::Expand:
7354  case ABIArgInfo::InAlloca:
7355  llvm_unreachable("Unsupported ABI kind for va_arg");
7356  case ABIArgInfo::Ignore:
7357  Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
7358  ArgSize = CharUnits::Zero();
7359  break;
7360  case ABIArgInfo::Extend:
7361  case ABIArgInfo::Direct:
7362  Val = Builder.CreateBitCast(AP, ArgPtrTy);
7363  ArgSize = CharUnits::fromQuantity(
7364  getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
7365  ArgSize = ArgSize.alignTo(SlotSize);
7366  break;
7367  case ABIArgInfo::Indirect:
7368  Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
7369  Val = Address(Builder.CreateLoad(Val), TypeAlign);
7370  ArgSize = SlotSize;
7371  break;
7372  }
7373 
7374  // Increment the VAList.
7375  if (!ArgSize.isZero()) {
7376  llvm::Value *APN =
7377  Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
7378  Builder.CreateStore(APN, VAListAddr);
7379  }
7380 
7381  return Val;
7382 }
7383 
7384 /// During the expansion of a RecordType, an incomplete TypeString is placed
7385 /// into the cache as a means to identify and break recursion.
7386 /// If there is a Recursive encoding in the cache, it is swapped out and will
7387 /// be reinserted by removeIncomplete().
7388 /// All other types of encoding should have been used rather than arriving here.
7389 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
7390  std::string StubEnc) {
7391  if (!ID)
7392  return;
7393  Entry &E = Map[ID];
7394  assert( (E.Str.empty() || E.State == Recursive) &&
7395  "Incorrectly use of addIncomplete");
7396  assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
7397  E.Swapped.swap(E.Str); // swap out the Recursive
7398  E.Str.swap(StubEnc);
7399  E.State = Incomplete;
7400  ++IncompleteCount;
7401 }
7402 
7403 /// Once the RecordType has been expanded, the temporary incomplete TypeString
7404 /// must be removed from the cache.
7405 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
7406 /// Returns true if the RecordType was defined recursively.
7407 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
7408  if (!ID)
7409  return false;
7410  auto I = Map.find(ID);
7411  assert(I != Map.end() && "Entry not present");
7412  Entry &E = I->second;
7413  assert( (E.State == Incomplete ||
7414  E.State == IncompleteUsed) &&
7415  "Entry must be an incomplete type");
7416  bool IsRecursive = false;
7417  if (E.State == IncompleteUsed) {
7418  // We made use of our Incomplete encoding, thus we are recursive.
7419  IsRecursive = true;
7420  --IncompleteUsedCount;
7421  }
7422  if (E.Swapped.empty())
7423  Map.erase(I);
7424  else {
7425  // Swap the Recursive back.
7426  E.Swapped.swap(E.Str);
7427  E.Swapped.clear();
7428  E.State = Recursive;
7429  }
7430  --IncompleteCount;
7431  return IsRecursive;
7432 }
7433 
7434 /// Add the encoded TypeString to the cache only if it is NonRecursive or
7435 /// Recursive (viz: all sub-members were expanded as fully as possible).
7436 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
7437  bool IsRecursive) {
7438  if (!ID || IncompleteUsedCount)
7439  return; // No key or it is is an incomplete sub-type so don't add.
7440  Entry &E = Map[ID];
7441  if (IsRecursive && !E.Str.empty()) {
7442  assert(E.State==Recursive && E.Str.size() == Str.size() &&
7443  "This is not the same Recursive entry");
7444  // The parent container was not recursive after all, so we could have used
7445  // this Recursive sub-member entry after all, but we assumed the worse when
7446  // we started viz: IncompleteCount!=0.
7447  return;
7448  }
7449  assert(E.Str.empty() && "Entry already present");
7450  E.Str = Str.str();
7451  E.State = IsRecursive? Recursive : NonRecursive;
7452 }
7453 
7454 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
7455 /// are recursively expanding a type (IncompleteCount != 0) and the cached
7456 /// encoding is Recursive, return an empty StringRef.
7457 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
7458  if (!ID)
7459  return StringRef(); // We have no key.
7460  auto I = Map.find(ID);
7461  if (I == Map.end())
7462  return StringRef(); // We have no encoding.
7463  Entry &E = I->second;
7464  if (E.State == Recursive && IncompleteCount)
7465  return StringRef(); // We don't use Recursive encodings for member types.
7466 
7467  if (E.State == Incomplete) {
7468  // The incomplete type is being used to break out of recursion.
7469  E.State = IncompleteUsed;
7470  ++IncompleteUsedCount;
7471  }
7472  return E.Str.c_str();
7473 }
7474 
7475 /// The XCore ABI includes a type information section that communicates symbol
7476 /// type information to the linker. The linker uses this information to verify
7477 /// safety/correctness of things such as array bound and pointers et al.
7478 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
7479 /// This type information (TypeString) is emitted into meta data for all global
7480 /// symbols: definitions, declarations, functions & variables.
7481 ///
7482 /// The TypeString carries type, qualifier, name, size & value details.
7483 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
7484 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
7485 /// The output is tested by test/CodeGen/xcore-stringtype.c.
7486 ///
7487 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7488  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
7489 
7490 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
7491 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7492  CodeGen::CodeGenModule &CGM) const {
7493  SmallStringEnc Enc;
7494  if (getTypeString(Enc, D, CGM, TSC)) {
7495  llvm::LLVMContext &Ctx = CGM.getModule().getContext();
7496  llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
7497  llvm::MDString::get(Ctx, Enc.str())};
7498  llvm::NamedMDNode *MD =
7499  CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
7500  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
7501  }
7502 }
7503 
7504 //===----------------------------------------------------------------------===//
7505 // SPIR ABI Implementation
7506 //===----------------------------------------------------------------------===//
7507 
7508 namespace {
7509 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
7510 public:
7511  SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7512  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
7513  void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7514  CodeGen::CodeGenModule &M) const override;
7515  unsigned getOpenCLKernelCallingConv() const override;
7516 };
7517 } // End anonymous namespace.
7518 
7519 /// Emit SPIR specific metadata: OpenCL and SPIR version.
7520 void SPIRTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
7521  CodeGen::CodeGenModule &CGM) const {
7522  llvm::LLVMContext &Ctx = CGM.getModule().getContext();
7523  llvm::Type *Int32Ty = llvm::Type::getInt32Ty(Ctx);
7524  llvm::Module &M = CGM.getModule();
7525  // SPIR v2.0 s2.12 - The SPIR version used by the module is stored in the
7526  // opencl.spir.version named metadata.
7527  llvm::Metadata *SPIRVerElts[] = {
7528  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, 2)),
7529  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, 0))};
7530  llvm::NamedMDNode *SPIRVerMD =
7531  M.getOrInsertNamedMetadata("opencl.spir.version");
7532  SPIRVerMD->addOperand(llvm::MDNode::get(Ctx, SPIRVerElts));
7533  // SPIR v2.0 s2.13 - The OpenCL version used by the module is stored in the
7534  // opencl.ocl.version named metadata node.
7535  llvm::Metadata *OCLVerElts[] = {
7536  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
7537  Int32Ty, CGM.getLangOpts().OpenCLVersion / 100)),
7538  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(
7539  Int32Ty, (CGM.getLangOpts().OpenCLVersion % 100) / 10))};
7540  llvm::NamedMDNode *OCLVerMD =
7541  M.getOrInsertNamedMetadata("opencl.ocl.version");
7542  OCLVerMD->addOperand(llvm::MDNode::get(Ctx, OCLVerElts));
7543 }
7544 
7545 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7546  return llvm::CallingConv::SPIR_KERNEL;
7547 }
7548 
7549 static bool appendType(SmallStringEnc &Enc, QualType QType,
7550  const CodeGen::CodeGenModule &CGM,
7551  TypeStringCache &TSC);
7552 
7553 /// Helper function for appendRecordType().
7554 /// Builds a SmallVector containing the encoded field types in declaration
7555 /// order.
7557  const RecordDecl *RD,
7558  const CodeGen::CodeGenModule &CGM,
7559  TypeStringCache &TSC) {
7560  for (const auto *Field : RD->fields()) {
7561  SmallStringEnc Enc;
7562  Enc += "m(";
7563  Enc += Field->getName();
7564  Enc += "){";
7565  if (Field->isBitField()) {
7566  Enc += "b(";
7567  llvm::raw_svector_ostream OS(Enc);
7568  OS << Field->getBitWidthValue(CGM.getContext());
7569  Enc += ':';
7570  }
7571  if (!appendType(Enc, Field->getType(), CGM, TSC))
7572  return false;
7573  if (Field->isBitField())
7574  Enc += ')';
7575  Enc += '}';
7576  FE.emplace_back(!Field->getName().empty(), Enc);
7577  }
7578  return true;
7579 }
7580 
7581 /// Appends structure and union types to Enc and adds encoding to cache.
7582 /// Recursively calls appendType (via extractFieldType) for each field.
7583 /// Union types have their fields ordered according to the ABI.
7584 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
7585  const CodeGen::CodeGenModule &CGM,
7586  TypeStringCache &TSC, const IdentifierInfo *ID) {
7587  // Append the cached TypeString if we have one.
7588  StringRef TypeString = TSC.lookupStr(ID);
7589  if (!TypeString.empty()) {
7590  Enc += TypeString;
7591  return true;
7592  }
7593 
7594  // Start to emit an incomplete TypeString.
7595  size_t Start = Enc.size();
7596  Enc += (RT->isUnionType()? 'u' : 's');
7597  Enc += '(';
7598  if (ID)
7599  Enc += ID->getName();
7600  Enc += "){";
7601 
7602  // We collect all encoded fields and order as necessary.
7603  bool IsRecursive = false;
7604  const RecordDecl *RD = RT->getDecl()->getDefinition();
7605  if (RD && !RD->field_empty()) {
7606  // An incomplete TypeString stub is placed in the cache for this RecordType
7607  // so that recursive calls to this RecordType will use it whilst building a
7608  // complete TypeString for this RecordType.
7610  std::string StubEnc(Enc.substr(Start).str());
7611  StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
7612  TSC.addIncomplete(ID, std::move(StubEnc));
7613  if (!extractFieldType(FE, RD, CGM, TSC)) {
7614  (void) TSC.removeIncomplete(ID);
7615  return false;
7616  }
7617  IsRecursive = TSC.removeIncomplete(ID);
7618  // The ABI requires unions to be sorted but not structures.
7619  // See FieldEncoding::operator< for sort algorithm.
7620  if (RT->isUnionType())
7621  std::sort(FE.begin(), FE.end());
7622  // We can now complete the TypeString.
7623  unsigned E = FE.size();
7624  for (unsigned I = 0; I != E; ++I) {
7625  if (I)
7626  Enc += ',';
7627  Enc += FE[I].str();
7628  }
7629  }
7630  Enc += '}';
7631  TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
7632  return true;
7633 }
7634 
7635 /// Appends enum types to Enc and adds the encoding to the cache.
7636 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
7637  TypeStringCache &TSC,
7638  const IdentifierInfo *ID) {
7639  // Append the cached TypeString if we have one.
7640  StringRef TypeString = TSC.lookupStr(ID);
7641  if (!TypeString.empty()) {
7642  Enc += TypeString;
7643  return true;
7644  }
7645 
7646  size_t Start = Enc.size();
7647  Enc += "e(";
7648  if (ID)
7649  Enc += ID->getName();
7650  Enc += "){";
7651 
7652  // We collect all encoded enumerations and order them alphanumerically.
7653  if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
7655  for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
7656  ++I) {
7657  SmallStringEnc EnumEnc;
7658  EnumEnc += "m(";
7659  EnumEnc += I->getName();
7660  EnumEnc += "){";
7661  I->getInitVal().toString(EnumEnc);
7662  EnumEnc += '}';
7663  FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
7664  }
7665  std::sort(FE.begin(), FE.end());
7666  unsigned E = FE.size();
7667  for (unsigned I = 0; I != E; ++I) {
7668  if (I)
7669  Enc += ',';
7670  Enc += FE[I].str();
7671  }
7672  }
7673  Enc += '}';
7674  TSC.addIfComplete(ID, Enc.substr(Start), false);
7675  return true;
7676 }
7677 
7678 /// Appends type's qualifier to Enc.
7679 /// This is done prior to appending the type's encoding.
7680 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
7681  // Qualifiers are emitted in alphabetical order.
7682  static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
7683  int Lookup = 0;
7684  if (QT.isConstQualified())
7685  Lookup += 1<<0;
7686  if (QT.isRestrictQualified())
7687  Lookup += 1<<1;
7688  if (QT.isVolatileQualified())
7689  Lookup += 1<<2;
7690  Enc += Table[Lookup];
7691 }
7692 
7693 /// Appends built-in types to Enc.
7694 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
7695  const char *EncType;
7696  switch (BT->getKind()) {
7697  case BuiltinType::Void:
7698  EncType = "0";
7699  break;
7700  case BuiltinType::Bool:
7701  EncType = "b";
7702  break;
7703  case BuiltinType::Char_U:
7704  EncType = "uc";
7705  break;
7706  case BuiltinType::UChar:
7707  EncType = "uc";
7708  break;
7709  case BuiltinType::SChar:
7710  EncType = "sc";
7711  break;
7712  case BuiltinType::UShort:
7713  EncType = "us";
7714  break;
7715  case BuiltinType::Short:
7716  EncType = "ss";
7717  break;
7718  case BuiltinType::UInt:
7719  EncType = "ui";
7720  break;
7721  case BuiltinType::Int:
7722  EncType = "si";
7723  break;
7724  case BuiltinType::ULong:
7725  EncType = "ul";
7726  break;
7727  case BuiltinType::Long:
7728  EncType = "sl";
7729  break;
7730  case BuiltinType::ULongLong:
7731  EncType = "ull";
7732  break;
7733  case BuiltinType::LongLong:
7734  EncType = "sll";
7735  break;
7736  case BuiltinType::Float:
7737  EncType = "ft";
7738  break;
7739  case BuiltinType::Double:
7740  EncType = "d";
7741  break;
7742  case BuiltinType::LongDouble:
7743  EncType = "ld";
7744  break;
7745  default:
7746  return false;
7747  }
7748  Enc += EncType;
7749  return true;
7750 }
7751 
7752 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
7753 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
7754  const CodeGen::CodeGenModule &CGM,
7755  TypeStringCache &TSC) {
7756  Enc += "p(";
7757  if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
7758  return false;
7759  Enc += ')';
7760  return true;
7761 }
7762 
7763 /// Appends array encoding to Enc before calling appendType for the element.
7764 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
7765  const ArrayType *AT,
7766  const CodeGen::CodeGenModule &CGM,
7767  TypeStringCache &TSC, StringRef NoSizeEnc) {
7768  if (AT->getSizeModifier() != ArrayType::Normal)
7769  return false;
7770  Enc += "a(";
7771  if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
7772  CAT->getSize().toStringUnsigned(Enc);
7773  else
7774  Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
7775  Enc += ':';
7776  // The Qualifiers should be attached to the type rather than the array.
7777  appendQualifier(Enc, QT);
7778  if (!appendType(Enc, AT->getElementType(), CGM, TSC))
7779  return false;
7780  Enc += ')';
7781  return true;
7782 }
7783 
7784 /// Appends a function encoding to Enc, calling appendType for the return type
7785 /// and the arguments.
7786 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
7787  const CodeGen::CodeGenModule &CGM,
7788  TypeStringCache &TSC) {
7789  Enc += "f{";
7790  if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
7791  return false;
7792  Enc += "}(";
7793  if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
7794  // N.B. we are only interested in the adjusted param types.
7795  auto I = FPT->param_type_begin();
7796  auto E = FPT->param_type_end();
7797  if (I != E) {
7798  do {
7799  if (!appendType(Enc, *I, CGM, TSC))
7800  return false;
7801  ++I;
7802  if (I != E)
7803  Enc += ',';
7804  } while (I != E);
7805  if (FPT->isVariadic())
7806  Enc += ",va";
7807  } else {
7808  if (FPT->isVariadic())
7809  Enc += "va";
7810  else
7811  Enc += '0';
7812  }
7813  }
7814  Enc += ')';
7815  return true;
7816 }
7817 
7818 /// Handles the type's qualifier before dispatching a call to handle specific
7819 /// type encodings.
7820 static bool appendType(SmallStringEnc &Enc, QualType QType,
7821  const CodeGen::CodeGenModule &CGM,
7822  TypeStringCache &TSC) {
7823 
7824  QualType QT = QType.getCanonicalType();
7825 
7826  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
7827  // The Qualifiers should be attached to the type rather than the array.
7828  // Thus we don't call appendQualifier() here.
7829  return appendArrayType(Enc, QT, AT, CGM, TSC, "");
7830 
7831  appendQualifier(Enc, QT);
7832 
7833  if (const BuiltinType *BT = QT->getAs<BuiltinType>())
7834  return appendBuiltinType(Enc, BT);
7835 
7836  if (const PointerType *PT = QT->getAs<PointerType>())
7837  return appendPointerType(Enc, PT, CGM, TSC);
7838 
7839  if (const EnumType *ET = QT->getAs<EnumType>())
7840  return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
7841 
7842  if (const RecordType *RT = QT->getAsStructureType())
7843  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7844 
7845  if (const RecordType *RT = QT->getAsUnionType())
7846  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
7847 
7848  if (const FunctionType *FT = QT->getAs<FunctionType>())
7849  return appendFunctionType(Enc, FT, CGM, TSC);
7850 
7851  return false;
7852 }
7853 
7854 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
7855  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
7856  if (!D)
7857  return false;
7858 
7859  if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
7860  if (FD->getLanguageLinkage() != CLanguageLinkage)
7861  return false;
7862  return appendType(Enc, FD->getType(), CGM, TSC);
7863  }
7864 
7865  if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
7866  if (VD->getLanguageLinkage() != CLanguageLinkage)
7867  return false;
7868  QualType QT = VD->getType().getCanonicalType();
7869  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
7870  // Global ArrayTypes are given a size of '*' if the size is unknown.
7871  // The Qualifiers should be attached to the type rather than the array.
7872  // Thus we don't call appendQualifier() here.
7873  return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
7874  }
7875  return appendType(Enc, QT, CGM, TSC);
7876  }
7877  return false;
7878 }
7879 
7880 
7881 //===----------------------------------------------------------------------===//
7882 // Driver code
7883 //===----------------------------------------------------------------------===//
7884 
7885 const llvm::Triple &CodeGenModule::getTriple() const {
7886  return getTarget().getTriple();
7887 }
7888 
7890  return getTriple().supportsCOMDAT();
7891 }
7892 
7894  if (TheTargetCodeGenInfo)
7895  return *TheTargetCodeGenInfo;
7896 
7897  // Helper to set the unique_ptr while still keeping the return value.
7898  auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
7899  this->TheTargetCodeGenInfo.reset(P);
7900  return *P;
7901  };
7902 
7903  const llvm::Triple &Triple = getTarget().getTriple();
7904  switch (Triple.getArch()) {
7905  default:
7906  return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
7907 
7908  case llvm::Triple::le32:
7909  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
7910  case llvm::Triple::mips:
7911  case llvm::Triple::mipsel:
7912  if (Triple.getOS() == llvm::Triple::NaCl)
7913  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
7914  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
7915 
7916  case llvm::Triple::mips64:
7917  case llvm::Triple::mips64el:
7918  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
7919 
7920  case llvm::Triple::aarch64:
7921  case llvm::Triple::aarch64_be: {
7922  AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
7923  if (getTarget().getABI() == "darwinpcs")
7924  Kind = AArch64ABIInfo::DarwinPCS;
7925 
7926  return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
7927  }
7928 
7929  case llvm::Triple::wasm32:
7930  case llvm::Triple::wasm64:
7931  return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
7932 
7933  case llvm::Triple::arm:
7934  case llvm::Triple::armeb:
7935  case llvm::Triple::thumb:
7936  case llvm::Triple::thumbeb: {
7937  if (Triple.getOS() == llvm::Triple::Win32) {
7938  return SetCGInfo(
7939  new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
7940  }
7941 
7942  ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
7943  StringRef ABIStr = getTarget().getABI();
7944  if (ABIStr == "apcs-gnu")
7945  Kind = ARMABIInfo::APCS;
7946  else if (ABIStr == "aapcs16")
7947  Kind = ARMABIInfo::AAPCS16_VFP;
7948  else if (CodeGenOpts.FloatABI == "hard" ||
7949  (CodeGenOpts.FloatABI != "soft" &&
7950  (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
7951  Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
7952  Triple.getEnvironment() == llvm::Triple::EABIHF)))
7953  Kind = ARMABIInfo::AAPCS_VFP;
7954 
7955  return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
7956  }
7957 
7958  case llvm::Triple::ppc:
7959  return SetCGInfo(
7960  new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
7961  case llvm::Triple::ppc64:
7962  if (Triple.isOSBinFormatELF()) {
7963  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
7964  if (getTarget().getABI() == "elfv2")
7965  Kind = PPC64_SVR4_ABIInfo::ELFv2;
7966  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7967 
7968  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7969  } else
7970  return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
7971  case llvm::Triple::ppc64le: {
7972  assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
7973  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
7974  if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
7975  Kind = PPC64_SVR4_ABIInfo::ELFv1;
7976  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
7977 
7978  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX));
7979  }
7980 
7981  case llvm::Triple::nvptx:
7982  case llvm::Triple::nvptx64:
7983  return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
7984 
7985  case llvm::Triple::msp430:
7986  return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
7987 
7988  case llvm::Triple::systemz: {
7989  bool HasVector = getTarget().getABI() == "vector";
7990  return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
7991  }
7992 
7993  case llvm::Triple::tce:
7994  return SetCGInfo(new TCETargetCodeGenInfo(Types));
7995 
7996  case llvm::Triple::x86: {
7997  bool IsDarwinVectorABI = Triple.isOSDarwin();
7998  bool RetSmallStructInRegABI =
7999  X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
8000  bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
8001 
8002  if (Triple.getOS() == llvm::Triple::Win32) {
8003  return SetCGInfo(new WinX86_32TargetCodeGenInfo(
8004  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8005  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
8006  } else {
8007  return SetCGInfo(new X86_32TargetCodeGenInfo(
8008  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
8009  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
8010  CodeGenOpts.FloatABI == "soft"));
8011  }
8012  }
8013 
8014  case llvm::Triple::x86_64: {
8015  StringRef ABI = getTarget().getABI();
8016  X86AVXABILevel AVXLevel =
8017  (ABI == "avx512"
8018  ? X86AVXABILevel::AVX512
8019  : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
8020 
8021  switch (Triple.getOS()) {
8022  case llvm::Triple::Win32:
8023  return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
8024  case llvm::Triple::PS4:
8025  return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
8026  default:
8027  return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
8028  }
8029  }
8030  case llvm::Triple::hexagon:
8031  return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
8032  case llvm::Triple::lanai:
8033  return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
8034  case llvm::Triple::r600:
8035  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8036  case llvm::Triple::amdgcn:
8037  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
8038  case llvm::Triple::sparc:
8039  return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
8040  case llvm::Triple::sparcv9:
8041  return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
8042  case llvm::Triple::xcore:
8043  return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
8044  case llvm::Triple::spir:
8045  case llvm::Triple::spir64:
8046  return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
8047  }
8048 }
Kind getKind() const
Definition: Type.h:2060
Ignore - Ignore the argument (treat as void).
FunctionDecl - An instance of this class is created to represent a function declaration or definition...
Definition: Decl.h:1561
void setEffectiveCallingConvention(unsigned Value)
External linkage, which indicates that the entity can be referred to from other translation units...
Definition: Linkage.h:50
static ABIArgInfo getExtend(llvm::Type *T=nullptr)
static bool occupiesMoreThan(CodeGenTypes &cgt, ArrayRef< llvm::Type * > scalarTypes, unsigned maxAllRegisters)
Does the given lowering require more than the given number of registers when expanded?
PointerType - C99 6.7.5.1 - Pointer Declarators.
Definition: Type.h:2179
A (possibly-)qualified type.
Definition: Type.h:598
const ABIInfo & getABIInfo() const
getABIInfo() - Returns ABI info helper for the target.
llvm::Type * ConvertTypeForMem(QualType T)
unsigned getFieldCount() const
getFieldCount - Get the number of fields in the layout.
Definition: RecordLayout.h:173
bool isSpecificBuiltinType(unsigned K) const
Test for a particular builtin type.
Definition: Type.h:5647
CanQualType getReturnType() const
bool hasFloatingRepresentation() const
Determine whether this type has a floating-point representation of some sort, e.g., it is a floating-point type or a vector thereof.
Definition: Type.cpp:1792
bool isBitField() const
Determines whether this field is a bitfield.
Definition: Decl.h:2361
bool isMemberPointerType() const
Definition: Type.h:5506
unsigned getInAllocaFieldIndex() const
llvm::Module & getModule() const
llvm::LLVMContext & getLLVMContext()
static ABIArgInfo classifyType(CodeGenModule &CGM, CanQualType type, bool forReturn)
FunctionType - C99 6.7.5.3 - Function Declarators.
Definition: Type.h:2879
llvm::ConstantInt * getSize(CharUnits N)
Definition: CGBuilder.h:61
llvm::AllocaInst * CreateTempAlloca(llvm::Type *Ty, const Twine &Name="tmp")
CreateTempAlloca - This creates a alloca and inserts it into the entry block.
Definition: CGExpr.cpp:69
Extend - Valid only for integer argument types.
QuantityType getQuantity() const
getQuantity - Get the raw integer representation of this quantity.
Definition: CharUnits.h:179
CodeGen::ABIArgInfo getNaturalAlignIndirect(QualType Ty, bool ByRef=true, bool Realign=false, llvm::Type *Padding=nullptr) const
A convenience method to return an indirect ABIArgInfo with an expected alignment equal to the ABI ali...
llvm::LoadInst * CreateDefaultAlignedLoad(llvm::Value *Addr, const llvm::Twine &Name="")
Definition: CGBuilder.h:127
Address getAddress() const
Definition: CGValue.h:331
static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends enum types to Enc and adds the encoding to the cache.
CodeGen::CGCXXABI & getCXXABI() const
Direct - Pass the argument directly using the normal converted LLVM type, or by coercing to another s...
CGCXXABI & getCXXABI() const
Definition: CodeGenTypes.h:179
StringRef P
static const Type * isSingleElementStruct(QualType T, ASTContext &Context)
isSingleElementStruct - Determine if a structure is a "single element struct", i.e.
bool hasFlexibleArrayMember() const
Definition: Decl.h:3305
bool isEnumeralType() const
Definition: Type.h:5542
ASTContext & getContext() const
Definition: CodeGenTypes.h:176
const llvm::DataLayout & getDataLayout() const
The base class of the type hierarchy.
Definition: Type.h:1281
Represents an array type, per C99 6.7.5.2 - Array Declarators.
Definition: Type.h:2456
static bool appendType(SmallStringEnc &Enc, QualType QType, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Handles the type's qualifier before dispatching a call to handle specific type encodings.
CharUnits alignTo(const CharUnits &Align) const
alignTo - Returns the next integer (mod 2**64) that is greater than or equal to this quantity and is ...
Definition: CharUnits.h:184
bool isBlockPointerType() const
Definition: Type.h:5488
llvm::IntegerType * Int8Ty
i8, i16, i32, and i64
virtual bool isNoProtoCallVariadic(const CodeGen::CallArgList &args, const FunctionNoProtoType *fnType) const
Determine whether a call to an unprototyped functions under the given calling convention should use t...
VarDecl - An instance of this class is created to represent a variable declaration or definition...
Definition: Decl.h:768
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition: Address.h:52
CallingConv getCallConv() const
Definition: Type.h:3017
field_iterator field_begin() const
Definition: Decl.cpp:3767
void setCoerceToType(llvm::Type *T)
uint64_t getTypeSize(QualType T) const
Return the size of the specified (complete) type T, in bits.
Definition: ASTContext.h:1813
virtual bool shouldSignExtUnsignedType(QualType Ty) const
Address CreateConstInBoundsByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Given a pointer to i8, adjust it by a given constant offset.
Definition: CGBuilder.h:245
virtual void getDependentLibraryOption(llvm::StringRef Lib, llvm::SmallString< 24 > &Opt) const
Gets the linker options necessary to link a dependent library on this platform.
static ABIArgInfo getIgnore()
static bool isAggregateTypeForABI(QualType T)
llvm::LLVMContext & getVMContext() const
bool isUnionType() const
Definition: Type.cpp:391
bool isVoidType() const
Definition: Type.h:5680
RecordDecl - Represents a struct/union/class.
Definition: Decl.h:3253
const_arg_iterator arg_end() const
CodeGen::CodeGenTypes & CGT
Definition: ABIInfo.h:51
One of these records is kept for each identifier that is lexed.
bool isScalarType() const
Definition: Type.h:5715
class LLVM_ALIGNAS(8) DependentTemplateSpecializationType const IdentifierInfo * Name
Represents a template specialization type whose template cannot be resolved, e.g. ...
Definition: Type.h:4549
Indirect - Pass the argument indirectly via a hidden pointer with the specified alignment (0 indicate...
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...
Definition: ASTContext.h:92
LineState State
ABIArgInfo classifyArgumentType(CodeGenModule &CGM, CanQualType type)
Classify the rules for how to pass a particular type.
static llvm::Type * GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, const llvm::DataLayout &TD)
GetX86_64ByValArgumentPair - Given a high and low type that can ideally be used as elements of a two ...
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, Address VAListAddr, QualType Ty)
bool isReferenceType() const
Definition: Type.h:5491
bool isStructureOrClassType() const
Definition: Type.cpp:378
FieldDecl - An instance of this class is created by Sema::ActOnField to represent a member of a struc...
Definition: Decl.h:2293
static ABIArgInfo getExtendInReg(llvm::Type *T=nullptr)
virtual unsigned getOpenCLKernelCallingConv() const
Get LLVM calling convention for OpenCL kernel.
ABIArgInfo classifyReturnType(CodeGenModule &CGM, CanQualType type)
Classify the rules for how to return a particular type.
virtual CodeGen::Address EmitMSVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const
Emit the target dependent code to load a value of.
const RecordType * getAsUnionType() const
NOTE: getAs*ArrayType are methods on ASTContext.
Definition: Type.cpp:450
static CharUnits Zero()
Zero - Construct a CharUnits quantity of zero.
Definition: CharUnits.h:53
llvm::Type * getCoerceToType() const
static ABIArgInfo getIndirectInReg(CharUnits Alignment, bool ByVal=true, bool Realign=false)
static ABIArgInfo getDirect(llvm::Type *T=nullptr, unsigned Offset=0, llvm::Type *Padding=nullptr, bool CanBeFlattened=true)
static bool hasScalarEvaluationKind(QualType T)
static ABIArgInfo getExpandWithPadding(bool PaddingInReg, llvm::Type *Padding)
static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends structure and union types to Enc and adds encoding to cache.
Address CreateElementBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Cast the element type of the given address to a different type, preserving information like the align...
Definition: CGBuilder.h:168
CharUnits - This is an opaque type for sizes expressed in character units.
Definition: CharUnits.h:38
uint32_t Offset
Definition: CacheTokens.cpp:44
QualType getReturnType() const
Definition: Type.h:3009
field_range fields() const
Definition: Decl.h:3382
static void rewriteInputConstraintReferences(unsigned FirstIn, unsigned NumNewOuts, std::string &AsmString)
Rewrite input constraint references after adding some output constraints.
static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty)
RecordDecl * getDecl() const
Definition: Type.h:3716
CodeGen::ABIArgInfo getNaturalAlignIndirectInReg(QualType Ty, bool Realign=false) const
llvm::CallInst * CreateMemCpy(Address Dest, Address Src, llvm::Value *Size, bool IsVolatile=false)
Definition: CGBuilder.h:270
ABIArgInfo - Helper class to encapsulate information about how a specific C type should be passed to ...
unsigned getCallingConvention() const
getCallingConvention - Return the user specified calling convention, which has been translated into a...
unsigned Align
Definition: ASTContext.h:83
const ASTRecordLayout & getASTRecordLayout(const RecordDecl *D) const
Get or compute information about the layout of the specified record (struct/union/class) D...
llvm::BasicBlock * createBasicBlock(const Twine &name="", llvm::Function *parent=nullptr, llvm::BasicBlock *before=nullptr)
createBasicBlock - Create an LLVM basic block.
uint64_t getFieldOffset(unsigned FieldNo) const
getFieldOffset - Get the offset of the given field index, in bits.
Definition: RecordLayout.h:177
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, unsigned EndBit, ASTContext &Context)
BitsContainNoUserData - Return true if the specified [start,end) bit range is known to either be off ...
static ABIArgInfo getExpand()
virtual StringRef getABI() const
Get the ABI currently in use.
detail::InMemoryDirectory::const_iterator I
llvm::StructType * getCoerceAndExpandType() const
static QualType useFirstFieldIfTransparentUnion(QualType Ty)
Pass transparent unions as if they were the type of the first element.
std::pair< CharUnits, CharUnits > getTypeInfoInChars(const Type *T) const
QualType getType() const
Definition: Decl.h:599
bool isUnnamedBitfield() const
Determines whether this is an unnamed bitfield.
Definition: Decl.h:2367
std::string FloatABI
The ABI to use for passing floating point arguments.
field_iterator field_end() const
Definition: Decl.h:3385
const ArrayType * getAsArrayTypeUnsafe() const
A variant of getAs<> for array types which silently discards qualifiers from the outermost type...
Definition: Type.h:5835
EnumDecl * getDecl() const
Definition: Type.h:3739
Represents a K&R-style 'int foo()' function, which has no information available about its arguments...
Definition: Type.h:3039
unsigned getNumRequiredArgs() const
static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, const llvm::DataLayout &TD)
ContainsFloatAtOffset - Return true if the specified LLVM IR type has a float member at the specified...
LValue MakeAddrLValue(Address Addr, QualType T, AlignmentSource AlignSource=AlignmentSource::Type)
bool isUnion() const
Definition: Decl.h:2939
static CharUnits One()
One - Construct a CharUnits quantity of one.
Definition: CharUnits.h:58
const llvm::DataLayout & getDataLayout() const
Represents a prototype with parameter type info, e.g.
Definition: Type.h:3073
bool isFloatingPoint() const
Definition: Type.h:2084
const TargetCodeGenInfo & getTargetCodeGenInfo()
static bool extractFieldType(SmallVectorImpl< FieldEncoding > &FE, const RecordDecl *RD, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Helper function for appendRecordType().
const TargetInfo & getTarget() const
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, llvm::Value *Array, llvm::Value *Value, unsigned FirstIndex, unsigned LastIndex)
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context)
void setAddress(Address address)
Definition: CGValue.h:332
ASTContext * Context
bool isRealFloatingType() const
Floating point categories.
Definition: Type.cpp:1799
ASTRecordLayout - This class contains layout information for one RecordDecl, which is a struct/union/...
Definition: RecordLayout.h:34
Exposes information about the current target.
llvm::Value * getPointer() const
Definition: Address.h:38
StringRef getName() const
Return the actual identifier string.
virtual bool isHomogeneousAggregateBaseType(QualType Ty) const
static Address invalid()
Definition: Address.h:35
bool isAnyComplexType() const
Definition: Type.h:5545
static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT)
Appends built-in types to Enc.
CharUnits getIndirectAlign() const
virtual bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy, unsigned elts) const
ASTContext & getContext() const
CharUnits getBaseClassOffset(const CXXRecordDecl *Base) const
getBaseClassOffset - Get the offset, in chars, for the given base class.
Definition: RecordLayout.h:219
bool isFloatingType() const
Definition: Type.cpp:1783
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition: CharUnits.h:63
static bool getTypeString(SmallStringEnc &Enc, const Decl *D, CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
The XCore ABI includes a type information section that communicates symbol type information to the li...
char __ovld __cnfn min(char x, char y)
Returns y if y < x, otherwise it returns x.
llvm::LLVMContext & getLLVMContext()
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, Address VAListAddr, llvm::Type *DirectTy, CharUnits DirectSize, CharUnits DirectAlign, CharUnits SlotSize, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
const IdentifierInfo * getBaseTypeIdentifier() const
Retrieves a pointer to the name of the base type.
Definition: Type.cpp:47
Represents a GCC generic vector type.
Definition: Type.h:2756
Implements C++ ABI-specific semantic analysis functions.
Definition: CXXABI.h:30
The result type of a method or function.
llvm::Type * getPaddingType() const
RecordDecl * getDefinition() const
getDefinition - Returns the RecordDecl that actually defines this struct/union/class.
Definition: Decl.h:3372
bool isUnsignedIntegerOrEnumerationType() const
Determines whether this is an integer type that is unsigned or an enumeration types whose underlying ...
Definition: Type.cpp:1762
The l-value was considered opaque, so the alignment was determined from a type.
Pass it as a pointer to temporary memory.
Definition: CGCXXABI.h:135
static void appendQualifier(SmallStringEnc &Enc, QualType QT)
Appends type's qualifier to Enc.
static Address emitMergePHI(CodeGenFunction &CGF, Address Addr1, llvm::BasicBlock *Block1, Address Addr2, llvm::BasicBlock *Block2, const llvm::Twine &Name="")
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, bool AllowArrays)
isEmptyField - Return true iff a the field is "empty", that is it is an unnamed bit-field or an (arra...
Address CreateBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Definition: CGBuilder.h:160
#define false
Definition: stdbool.h:33
CharUnits getTypeAlignInChars(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in characters.
Kind
bool isIntegralOrEnumerationType() const
Determine whether this type is an integral or enumeration type.
Definition: Type.h:5730
ASTContext & getContext() const
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of enums...
Definition: Type.h:3733
const Type * getTypePtr() const
Retrieves a pointer to the underlying (unqualified) type.
Definition: Type.h:5259
bool isComplexType() const
isComplexType() does not include complex integers (a GCC extension).
Definition: Type.cpp:397
bool isBuiltinType() const
Helper methods to distinguish type categories.
Definition: Type.h:5536
const llvm::DataLayout & getDataLayout() const
Definition: CodeGenTypes.h:173
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays)
isEmptyRecord - Return true iff a structure contains only empty fields.
static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a function encoding to Enc, calling appendType for the return type and the arguments...
const std::string ID
void setArgStruct(llvm::StructType *Ty, CharUnits Align)
bool isHomogeneousAggregate(QualType Ty, const Type *&Base, uint64_t &Members) const
isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous aggregate. ...
CoerceAndExpand - Only valid for aggregate argument types.
const ConstantArrayType * getAsConstantArrayType(QualType T) const
Definition: ASTContext.h:2114
bool isMultipleOf(CharUnits N) const
Test whether this is a multiple of the other value.
Definition: CharUnits.h:137
CharUnits alignmentOfArrayElement(CharUnits elementSize) const
Given that this is the alignment of the first element of an array, return the minimum alignment of an...
Definition: CharUnits.h:197
const CodeGenOptions & getCodeGenOpts() const
An aligned address.
Definition: Address.h:25
const LangOptions & getLangOpts() const
llvm::LLVMContext & getLLVMContext()
Definition: CodeGenTypes.h:180
bool operator<(DeclarationName LHS, DeclarationName RHS)
Ordering on two declaration names.
bool isVectorType() const
Definition: Type.h:5548
bool isPromotableIntegerType() const
More type predicates useful for type checking/promotion.
Definition: Type.cpp:2320
bool isMemberFunctionPointerType() const
Definition: Type.h:5509
TargetCodeGenInfo - This class organizes various target-specific codegeneration issues, like target-specific attributes, builtins and so on.
InAlloca - Pass the argument directly using the LLVM inalloca attribute.
X86AVXABILevel
The AVX ABI level for X86 targets.
bool isVolatileQualified() const
Determine whether this type is volatile-qualified.
Definition: Type.h:5329
static llvm::Value * emitRoundPointerUpToAlignment(CodeGenFunction &CGF, llvm::Value *Ptr, CharUnits Align)
QualType getPointeeType() const
Definition: Type.h:2193
CGFunctionInfo - Class to encapsulate the information about a function definition.
CharUnits getAlignment() const
Return the alignment of this pointer.
Definition: Address.h:67
This class organizes the cross-function state that is used while generating LLVM code.
bool canHaveCoerceToType() const
virtual void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const
setTargetAttributes - Provides a convenient hook to handle extra target-specific attributes for the g...
virtual bool isHomogeneousAggregateSmallEnough(const Type *Base, uint64_t Members) const
bool isAggregateType() const
Determines whether the type is a C++ aggregate type or C aggregate or union type. ...
Definition: Type.cpp:1868
A refining implementation of ABIInfo for targets that support swiftcall.
Definition: ABIInfo.h:131
bool isZero() const
isZero - Test whether the quantity equals zero.
Definition: CharUnits.h:116
unsigned getDirectOffset() const
static ABIArgInfo getDirectInReg(llvm::Type *T=nullptr)
Address CreateMemTemp(QualType T, const Twine &Name="tmp")
CreateMemTemp - Create a temporary memory object of the given type, with appropriate alignment...
Definition: CGExpr.cpp:98
const internal::VariadicAllOfMatcher< Type > type
Matches Types in the clang AST.
Definition: ASTMatchers.h:1983
Address CreateStructGEP(Address Addr, unsigned Index, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:183
static bool appendArrayType(SmallStringEnc &Enc, QualType QT, const ArrayType *AT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, StringRef NoSizeEnc)
Appends array encoding to Enc before calling appendType for the element.
std::unique_ptr< DiagnosticConsumer > create(StringRef OutputFile, DiagnosticOptions *Diags, bool MergeChildRecords=false)
Returns a DiagnosticConsumer that serializes diagnostics to a bitcode file.
llvm::LoadInst * CreateLoad(Address Addr, const llvm::Twine &Name="")
Definition: CGBuilder.h:70
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
EnumDecl - Represents an enum.
Definition: Decl.h:3013
detail::InMemoryDirectory::const_iterator E
for(auto typeArg:T->getTypeArgsAsWritten())
bool isHalfType() const
Definition: Type.h:5686
llvm::StoreInst * CreateStore(llvm::Value *Val, Address Addr, bool IsVolatile=false)
Definition: CGBuilder.h:113
const llvm::Triple & getTriple() const
bool field_empty() const
Definition: Decl.h:3391
specific_decl_iterator - Iterates over a subrange of declarations stored in a DeclContext, providing only those that are of type SpecificDecl (or a class derived from it).
Definition: DeclBase.h:1473
unsigned Map[Count]
The type of a lookup table which maps from language-specific address spaces to target-specific ones...
Definition: AddressSpaces.h:45
const RecordType * getAsStructureType() const
Definition: Type.cpp:431
llvm::PointerType * getType() const
Return the type of the pointer value.
Definition: Address.h:44
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of structs/unions/cl...
Definition: Type.h:3707
Complex values, per C99 6.2.5p11.
Definition: Type.h:2119
const T * getAs() const
Member-template getAs<specific type>'.
Definition: Type.h:5818
QualType getCanonicalType() const
Definition: Type.h:5298
Pass it using the normal C aggregate rules for the ABI, potentially introducing extra copies and pass...
Definition: CGCXXABI.h:127
Address CreateConstArrayGEP(Address Addr, uint64_t Index, CharUnits EltSize, const llvm::Twine &Name="")
Given addr = [n x T]* ...
Definition: CGBuilder.h:206
void EmitStoreOfComplex(ComplexPairTy V, LValue dest, bool isInit)
EmitStoreOfComplex - Store a complex number into the specified l-value.
LanguageLinkage getLanguageLinkage() const
Compute the language linkage.
Definition: Decl.cpp:2619
Implements C++ ABI-specific code generation functions.
Definition: CGCXXABI.h:43
This class organizes the cross-module state that is used while lowering AST types to LLVM types...
Definition: CodeGenTypes.h:120
CodeGenOptions - Track various options which control how the code is optimized and passed to the back...
const TargetInfo & getTarget() const
Expand - Only valid for aggregate argument types.
bool isRestrictQualified() const
Determine whether this type is restrict-qualified.
Definition: Type.h:5323
void EmitBlock(llvm::BasicBlock *BB, bool IsFinished=false)
EmitBlock - Emit the given block.
Definition: CGStmt.cpp:397
static bool isArgInAlloca(const ABIArgInfo &Info)
static ABIArgInfo getInAlloca(unsigned FieldIndex)
Represents a base class of a C++ class.
Definition: DeclCXX.h:159
char __ovld __cnfn max(char x, char y)
Returns y if x < y, otherwise it returns x.
Pass it on the stack using its defined layout.
Definition: CGCXXABI.h:132
uint64_t getPointerWidth(unsigned AddrSpace) const
Return the width of pointers on this target, for the specified address space.
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, CGCXXABI &CXXABI)
FormatToken * Current
Address CreateConstByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:251
Represents a C++ struct/union/class.
Definition: DeclCXX.h:263
BoundNodesTreeBuilder *const Builder
void EmitBranch(llvm::BasicBlock *Block)
EmitBranch - Emit a branch to the specified basic block from the current insert block, taking care to avoid creation of branches from dummy blocks.
Definition: CGStmt.cpp:417
llvm::Type * ConvertType(QualType T)
ArraySizeModifier getSizeModifier() const
Definition: Type.h:2491
virtual RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const =0
Returns how an argument of the given record type should be passed.
QualType getVectorType(QualType VectorType, unsigned NumElts, VectorType::VectorKind VecKind) const
Return the unique reference to a vector type of the specified element type and size.
This class is used for builtin types like 'int'.
Definition: Type.h:2039
const TargetInfo & getTarget() const
Definition: CodeGenTypes.h:178
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType ValueTy, bool IsIndirect, std::pair< CharUnits, CharUnits > ValueInfo, CharUnits SlotSizeAndAlign, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
const_arg_iterator arg_begin() const
QualType getType() const
Definition: CGValue.h:258
ABIInfo - Target specific hooks for defining how a type should be passed or returned from functions...
Definition: ABIInfo.h:49
uint64_t Width
Definition: ASTContext.h:82
static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a pointer encoding to Enc before calling appendType for the pointee.
virtual unsigned getSizeOfUnwindException() const
Determines the size of struct _Unwind_Exception on this platform, in 8-bit units. ...
QualType getElementType() const
Definition: Type.h:2490
llvm::StoreInst * CreateAlignedStore(llvm::Value *Val, llvm::Value *Addr, CharUnits Align, bool IsVolatile=false)
Definition: CGBuilder.h:120
bool getIndirectRealign() const
int64_t toBits(CharUnits CharSize) const
Convert a size in characters to a size in bits.
LValue - This represents an lvalue references.
Definition: CGValue.h:152
ASTContext & getContext() const
void setInAllocaSRet(bool SRet)
EnumDecl * getDefinition() const
Definition: Decl.h:3082
bool isSignedIntegerType() const
Return true if this is an integer type that is signed, according to C99 6.2.5p4 [char, signed char, short, int, long..], or an enum decl which has a signed representation.
Definition: Type.cpp:1706
bool isConstQualified() const
Determine whether this type is const-qualified.
Definition: Type.h:5318
RecordArgABI
Specify how one should pass an argument of a record type.
Definition: CGCXXABI.h:124
bool isNull() const
Return true if this QualType doesn't point to a type yet.
Definition: Type.h:665
static bool isIntegerLikeType(QualType Ty, ASTContext &Context, llvm::LLVMContext &VMContext)
static bool isSSEVectorType(ASTContext &Context, QualType Ty)
CallArgList - Type for representing both the value and type of arguments in a call.
Definition: CGCall.h:56
static bool PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address)
Represents the canonical version of C arrays with a specified constant size.
Definition: Type.h:2512
static ABIArgInfo getIndirect(CharUnits Alignment, bool ByVal=true, bool Realign=false, llvm::Type *Padding=nullptr)
Attr - This represents one attribute.
Definition: Attr.h:45
bool hasPointerRepresentation() const
Whether this type is represented natively as a pointer.
Definition: Type.h:5765
bool isIntegerType() const
isIntegerType() does not include complex integers (a GCC extension).
Definition: Type.h:5702
bool isPointerType() const
Definition: Type.h:5482