Bug Summary

File:lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Warning:line 1070, column 5
Value stored to 'CurOp' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86MCCodeEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86/MCTargetDesc -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/X86/MCTargetDesc -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp -faddrsig
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86MCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/X86BaseInfo.h"
15#include "MCTargetDesc/X86FixupKinds.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/MC/MCCodeEmitter.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCFixup.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrDesc.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/raw_ostream.h"
30#include <cassert>
31#include <cstdint>
32#include <cstdlib>
33
34using namespace llvm;
35
36#define DEBUG_TYPE"mccodeemitter" "mccodeemitter"
37
38namespace {
39
40class X86MCCodeEmitter : public MCCodeEmitter {
41 const MCInstrInfo &MCII;
42 MCContext &Ctx;
43
44public:
45 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
46 : MCII(mcii), Ctx(ctx) {
47 }
48 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
49 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
50 ~X86MCCodeEmitter() override = default;
51
52 bool is64BitMode(const MCSubtargetInfo &STI) const {
53 return STI.getFeatureBits()[X86::Mode64Bit];
54 }
55
56 bool is32BitMode(const MCSubtargetInfo &STI) const {
57 return STI.getFeatureBits()[X86::Mode32Bit];
58 }
59
60 bool is16BitMode(const MCSubtargetInfo &STI) const {
61 return STI.getFeatureBits()[X86::Mode16Bit];
62 }
63
64 /// Is16BitMemOperand - Return true if the specified instruction has
65 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
66 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
67 const MCSubtargetInfo &STI) const {
68 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
69 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
70 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
71
72 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
73 Disp.isImm() && Disp.getImm() < 0x10000)
74 return true;
75 if ((BaseReg.getReg() != 0 &&
76 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
77 (IndexReg.getReg() != 0 &&
78 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
79 return true;
80 return false;
81 }
82
83 unsigned GetX86RegNum(const MCOperand &MO) const {
84 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
85 }
86
87 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const {
88 return Ctx.getRegisterInfo()->getEncodingValue(
89 MI.getOperand(OpNum).getReg());
90 }
91
92 // Does this register require a bit to be set in REX prefix.
93 bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const {
94 return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
95 }
96
97 void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
98 OS << (char)C;
99 ++CurByte;
100 }
101
102 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
103 raw_ostream &OS) const {
104 // Output the constant in little endian byte order.
105 for (unsigned i = 0; i != Size; ++i) {
106 EmitByte(Val & 255, CurByte, OS);
107 Val >>= 8;
108 }
109 }
110
111 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
112 unsigned ImmSize, MCFixupKind FixupKind,
113 unsigned &CurByte, raw_ostream &OS,
114 SmallVectorImpl<MCFixup> &Fixups,
115 int ImmOffset = 0) const;
116
117 static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
118 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!")((Mod < 4 && RegOpcode < 8 && RM < 8
&& "ModRM Fields out of range!") ? static_cast<void
> (0) : __assert_fail ("Mod < 4 && RegOpcode < 8 && RM < 8 && \"ModRM Fields out of range!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 118, __PRETTY_FUNCTION__));
119 return RM | (RegOpcode << 3) | (Mod << 6);
120 }
121
122 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
123 unsigned &CurByte, raw_ostream &OS) const {
124 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
125 }
126
127 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
128 unsigned &CurByte, raw_ostream &OS) const {
129 // SIB byte is in the same format as the ModRMByte.
130 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
131 }
132
133 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
134 uint64_t TSFlags, bool Rex, unsigned &CurByte,
135 raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
137
138 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
139 SmallVectorImpl<MCFixup> &Fixups,
140 const MCSubtargetInfo &STI) const override;
141
142 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
143 const MCInst &MI, const MCInstrDesc &Desc,
144 raw_ostream &OS) const;
145
146 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
147 const MCInst &MI, raw_ostream &OS) const;
148
149 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
150 const MCInst &MI, const MCInstrDesc &Desc,
151 const MCSubtargetInfo &STI, raw_ostream &OS) const;
152
153 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
154 int MemOperand, const MCInstrDesc &Desc) const;
155
156 bool isPCRel32Branch(const MCInst &MI) const;
157};
158
159} // end anonymous namespace
160
161/// isDisp8 - Return true if this signed displacement fits in a 8-bit
162/// sign-extended field.
163static bool isDisp8(int Value) {
164 return Value == (int8_t)Value;
165}
166
167/// isCDisp8 - Return true if this signed displacement fits in a 8-bit
168/// compressed dispacement field.
169static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
170 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&((((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
"Compressed 8-bit displacement is only valid for EVEX inst."
) ? static_cast<void> (0) : __assert_fail ("((TSFlags & X86II::EncodingMask) == X86II::EVEX) && \"Compressed 8-bit displacement is only valid for EVEX inst.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 171, __PRETTY_FUNCTION__))
171 "Compressed 8-bit displacement is only valid for EVEX inst.")((((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
"Compressed 8-bit displacement is only valid for EVEX inst."
) ? static_cast<void> (0) : __assert_fail ("((TSFlags & X86II::EncodingMask) == X86II::EVEX) && \"Compressed 8-bit displacement is only valid for EVEX inst.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 171, __PRETTY_FUNCTION__));
172
173 unsigned CD8_Scale =
174 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
175 if (CD8_Scale == 0) {
176 CValue = Value;
177 return isDisp8(Value);
178 }
179
180 unsigned Mask = CD8_Scale - 1;
181 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.")(((CD8_Scale & Mask) == 0 && "Invalid memory object size."
) ? static_cast<void> (0) : __assert_fail ("(CD8_Scale & Mask) == 0 && \"Invalid memory object size.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 181, __PRETTY_FUNCTION__));
182 if (Value & Mask) // Unaligned offset
183 return false;
184 Value /= (int)CD8_Scale;
185 bool Ret = (Value == (int8_t)Value);
186
187 if (Ret)
188 CValue = Value;
189 return Ret;
190}
191
192/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
193/// in an instruction with the specified TSFlags.
194static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
195 unsigned Size = X86II::getSizeOfImm(TSFlags);
196 bool isPCRel = X86II::isImmPCRel(TSFlags);
197
198 if (X86II::isImmSigned(TSFlags)) {
199 switch (Size) {
200 default: llvm_unreachable("Unsupported signed fixup size!")::llvm::llvm_unreachable_internal("Unsupported signed fixup size!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 200);
201 case 4: return MCFixupKind(X86::reloc_signed_4byte);
202 }
203 }
204 return MCFixup::getKindForSize(Size, isPCRel);
205}
206
207/// Is32BitMemOperand - Return true if the specified instruction has
208/// a 32-bit memory operand. Op specifies the operand # of the memoperand.
209static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
210 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
211 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
212
213 if ((BaseReg.getReg() != 0 &&
214 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
215 (IndexReg.getReg() != 0 &&
216 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
217 return true;
218 if (BaseReg.getReg() == X86::EIP) {
219 assert(IndexReg.getReg() == 0 && "Invalid eip-based address.")((IndexReg.getReg() == 0 && "Invalid eip-based address."
) ? static_cast<void> (0) : __assert_fail ("IndexReg.getReg() == 0 && \"Invalid eip-based address.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 219, __PRETTY_FUNCTION__));
220 return true;
221 }
222 if (IndexReg.getReg() == X86::EIZ)
223 return true;
224 return false;
225}
226
227/// Is64BitMemOperand - Return true if the specified instruction has
228/// a 64-bit memory operand. Op specifies the operand # of the memoperand.
229#ifndef NDEBUG
230static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
231 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
232 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
233
234 if ((BaseReg.getReg() != 0 &&
235 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
236 (IndexReg.getReg() != 0 &&
237 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
238 return true;
239 return false;
240}
241#endif
242
243/// StartsWithGlobalOffsetTable - Check if this expression starts with
244/// _GLOBAL_OFFSET_TABLE_ and if it is of the form
245/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
246/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
247/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
248/// of a binary expression.
249enum GlobalOffsetTableExprKind {
250 GOT_None,
251 GOT_Normal,
252 GOT_SymDiff
253};
254static GlobalOffsetTableExprKind
255StartsWithGlobalOffsetTable(const MCExpr *Expr) {
256 const MCExpr *RHS = nullptr;
257 if (Expr->getKind() == MCExpr::Binary) {
258 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
259 Expr = BE->getLHS();
260 RHS = BE->getRHS();
261 }
262
263 if (Expr->getKind() != MCExpr::SymbolRef)
264 return GOT_None;
265
266 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
267 const MCSymbol &S = Ref->getSymbol();
268 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
269 return GOT_None;
270 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
271 return GOT_SymDiff;
272 return GOT_Normal;
273}
274
275static bool HasSecRelSymbolRef(const MCExpr *Expr) {
276 if (Expr->getKind() == MCExpr::SymbolRef) {
277 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
278 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
279 }
280 return false;
281}
282
283bool X86MCCodeEmitter::isPCRel32Branch(const MCInst &MI) const {
284 unsigned Opcode = MI.getOpcode();
285 const MCInstrDesc &Desc = MCII.get(Opcode);
286 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4) ||
287 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
288 return false;
289
290 unsigned CurOp = X86II::getOperandBias(Desc);
291 const MCOperand &Op = MI.getOperand(CurOp);
292 if (!Op.isExpr())
293 return false;
294
295 const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
296 return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None;
297}
298
299void X86MCCodeEmitter::
300EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
301 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
302 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
303 const MCExpr *Expr = nullptr;
304 if (DispOp.isImm()) {
305 // If this is a simple integer displacement that doesn't require a
306 // relocation, emit it now.
307 if (FixupKind != FK_PCRel_1 &&
308 FixupKind != FK_PCRel_2 &&
309 FixupKind != FK_PCRel_4) {
310 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
311 return;
312 }
313 Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
314 } else {
315 Expr = DispOp.getExpr();
316 }
317
318 // If we have an immoffset, add it to the expression.
319 if ((FixupKind == FK_Data_4 ||
320 FixupKind == FK_Data_8 ||
321 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
322 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
323 if (Kind != GOT_None) {
324 assert(ImmOffset == 0)((ImmOffset == 0) ? static_cast<void> (0) : __assert_fail
("ImmOffset == 0", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 324, __PRETTY_FUNCTION__));
325
326 if (Size == 8) {
327 FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
328 } else {
329 assert(Size == 4)((Size == 4) ? static_cast<void> (0) : __assert_fail ("Size == 4"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 329, __PRETTY_FUNCTION__));
330 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
331 }
332
333 if (Kind == GOT_Normal)
334 ImmOffset = CurByte;
335 } else if (Expr->getKind() == MCExpr::SymbolRef) {
336 if (HasSecRelSymbolRef(Expr)) {
337 FixupKind = MCFixupKind(FK_SecRel_4);
338 }
339 } else if (Expr->getKind() == MCExpr::Binary) {
340 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
341 if (HasSecRelSymbolRef(Bin->getLHS())
342 || HasSecRelSymbolRef(Bin->getRHS())) {
343 FixupKind = MCFixupKind(FK_SecRel_4);
344 }
345 }
346 }
347
348 // If the fixup is pc-relative, we need to bias the value to be relative to
349 // the start of the field, not the end of the field.
350 if (FixupKind == FK_PCRel_4 ||
351 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
352 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) ||
353 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
354 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) ||
355 FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) {
356 ImmOffset -= 4;
357 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
358 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
359 // this needs to be a GOTPC32 relocation.
360 if (StartsWithGlobalOffsetTable(Expr) != GOT_None)
361 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
362 }
363 if (FixupKind == FK_PCRel_2)
364 ImmOffset -= 2;
365 if (FixupKind == FK_PCRel_1)
366 ImmOffset -= 1;
367
368 if (ImmOffset)
369 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
370 Ctx);
371
372 // Emit a symbolic constant as a fixup and 4 zeros.
373 Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
374 EmitConstant(0, Size, CurByte, OS);
375}
376
377void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
378 unsigned RegOpcodeField,
379 uint64_t TSFlags, bool Rex,
380 unsigned &CurByte, raw_ostream &OS,
381 SmallVectorImpl<MCFixup> &Fixups,
382 const MCSubtargetInfo &STI) const {
383 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
384 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
385 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
386 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
387 unsigned BaseReg = Base.getReg();
388 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
389
390 // Handle %rip relative addressing.
391 if (BaseReg == X86::RIP ||
392 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
393 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode")((is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode"
) ? static_cast<void> (0) : __assert_fail ("is64BitMode(STI) && \"Rip-relative addressing requires 64-bit mode\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 393, __PRETTY_FUNCTION__));
394 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address")((IndexReg.getReg() == 0 && "Invalid rip-relative address"
) ? static_cast<void> (0) : __assert_fail ("IndexReg.getReg() == 0 && \"Invalid rip-relative address\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 394, __PRETTY_FUNCTION__));
395 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
396
397 unsigned Opcode = MI.getOpcode();
398 // movq loads are handled with a special relocation form which allows the
399 // linker to eliminate some loads for GOT references which end up in the
400 // same linkage unit.
401 unsigned FixupKind = [=]() {
402 switch (Opcode) {
403 default:
404 return X86::reloc_riprel_4byte;
405 case X86::MOV64rm:
406 assert(Rex)((Rex) ? static_cast<void> (0) : __assert_fail ("Rex", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 406, __PRETTY_FUNCTION__));
407 return X86::reloc_riprel_4byte_movq_load;
408 case X86::CALL64m:
409 case X86::JMP64m:
410 case X86::TAILJMPm64:
411 case X86::TEST64mr:
412 case X86::ADC64rm:
413 case X86::ADD64rm:
414 case X86::AND64rm:
415 case X86::CMP64rm:
416 case X86::OR64rm:
417 case X86::SBB64rm:
418 case X86::SUB64rm:
419 case X86::XOR64rm:
420 return Rex ? X86::reloc_riprel_4byte_relax_rex
421 : X86::reloc_riprel_4byte_relax;
422 }
423 }();
424
425 // rip-relative addressing is actually relative to the *next* instruction.
426 // Since an immediate can follow the mod/rm byte for an instruction, this
427 // means that we need to bias the displacement field of the instruction with
428 // the size of the immediate field. If we have this case, add it into the
429 // expression to emit.
430 // Note: rip-relative addressing using immediate displacement values should
431 // not be adjusted, assuming it was the user's intent.
432 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
433 ? X86II::getSizeOfImm(TSFlags)
434 : 0;
435
436 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
437 CurByte, OS, Fixups, -ImmSize);
438 return;
439 }
440
441 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
442
443 // 16-bit addressing forms of the ModR/M byte have a different encoding for
444 // the R/M field and are far more limited in which registers can be used.
445 if (Is16BitMemOperand(MI, Op, STI)) {
446 if (BaseReg) {
447 // For 32-bit addressing, the row and column values in Table 2-2 are
448 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
449 // some special cases. And GetX86RegNum reflects that numbering.
450 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
451 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
452 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
453 // while values 0-3 indicate the allowed combinations (base+index) of
454 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
455 //
456 // R16Table[] is a lookup from the normal RegNo, to the row values from
457 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
458 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
459 unsigned RMfield = R16Table[BaseRegNo];
460
461 assert(RMfield && "invalid 16-bit base register")((RMfield && "invalid 16-bit base register") ? static_cast
<void> (0) : __assert_fail ("RMfield && \"invalid 16-bit base register\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 461, __PRETTY_FUNCTION__));
462
463 if (IndexReg.getReg()) {
464 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
465
466 assert(IndexReg16 && "invalid 16-bit index register")((IndexReg16 && "invalid 16-bit index register") ? static_cast
<void> (0) : __assert_fail ("IndexReg16 && \"invalid 16-bit index register\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 466, __PRETTY_FUNCTION__));
467 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
468 assert(((IndexReg16 ^ RMfield) & 2) &&((((IndexReg16 ^ RMfield) & 2) && "invalid 16-bit base/index register combination"
) ? static_cast<void> (0) : __assert_fail ("((IndexReg16 ^ RMfield) & 2) && \"invalid 16-bit base/index register combination\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 469, __PRETTY_FUNCTION__))
469 "invalid 16-bit base/index register combination")((((IndexReg16 ^ RMfield) & 2) && "invalid 16-bit base/index register combination"
) ? static_cast<void> (0) : __assert_fail ("((IndexReg16 ^ RMfield) & 2) && \"invalid 16-bit base/index register combination\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 469, __PRETTY_FUNCTION__));
470 assert(Scale.getImm() == 1 &&((Scale.getImm() == 1 && "invalid scale for 16-bit memory reference"
) ? static_cast<void> (0) : __assert_fail ("Scale.getImm() == 1 && \"invalid scale for 16-bit memory reference\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 471, __PRETTY_FUNCTION__))
471 "invalid scale for 16-bit memory reference")((Scale.getImm() == 1 && "invalid scale for 16-bit memory reference"
) ? static_cast<void> (0) : __assert_fail ("Scale.getImm() == 1 && \"invalid scale for 16-bit memory reference\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 471, __PRETTY_FUNCTION__));
472
473 // Allow base/index to appear in either order (although GAS doesn't).
474 if (IndexReg16 & 2)
475 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
476 else
477 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
478 }
479
480 if (Disp.isImm() && isDisp8(Disp.getImm())) {
481 if (Disp.getImm() == 0 && RMfield != 6) {
482 // There is no displacement; just the register.
483 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
484 return;
485 }
486 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
487 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
488 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
489 return;
490 }
491 // This is the [REG]+disp16 case.
492 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
493 } else {
494 // There is no BaseReg; this is the plain [disp16] case.
495 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
496 }
497
498 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
499 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
500 return;
501 }
502
503 // Determine whether a SIB byte is needed.
504 // If no BaseReg, issue a RIP relative instruction only if the MCE can
505 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
506 // 2-7) and absolute references.
507
508 if (// The SIB byte must be used if there is an index register.
509 IndexReg.getReg() == 0 &&
510 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
511 // encode to an R/M value of 4, which indicates that a SIB byte is
512 // present.
513 BaseRegNo != N86::ESP &&
514 // If there is no base register and we're in 64-bit mode, we need a SIB
515 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
516 (!is64BitMode(STI) || BaseReg != 0)) {
517
518 if (BaseReg == 0) { // [disp32] in X86-32 mode
519 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
520 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
521 return;
522 }
523
524 // If the base is not EBP/ESP and there is no displacement, use simple
525 // indirect register encoding, this handles addresses like [EAX]. The
526 // encoding for [EBP] with no displacement means [disp32] so we handle it
527 // by emitting a displacement of 0 below.
528 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
529 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
530 return;
531 }
532
533 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
534 if (Disp.isImm()) {
535 if (!HasEVEX && isDisp8(Disp.getImm())) {
536 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
537 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
538 return;
539 }
540 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
541 // 32-bit displacement.
542 int CDisp8 = 0;
543 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
544 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
545 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
546 CDisp8 - Disp.getImm());
547 return;
548 }
549 }
550
551 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
552 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
553 unsigned Opcode = MI.getOpcode();
554 unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
555 : X86::reloc_signed_4byte;
556 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS,
557 Fixups);
558 return;
559 }
560
561 // We need a SIB byte, so start by outputting the ModR/M byte first
562 assert(IndexReg.getReg() != X86::ESP &&((IndexReg.getReg() != X86::ESP && IndexReg.getReg() !=
X86::RSP && "Cannot use ESP as index reg!") ? static_cast
<void> (0) : __assert_fail ("IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && \"Cannot use ESP as index reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 563, __PRETTY_FUNCTION__))
563 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!")((IndexReg.getReg() != X86::ESP && IndexReg.getReg() !=
X86::RSP && "Cannot use ESP as index reg!") ? static_cast
<void> (0) : __assert_fail ("IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && \"Cannot use ESP as index reg!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 563, __PRETTY_FUNCTION__));
564
565 bool ForceDisp32 = false;
566 bool ForceDisp8 = false;
567 int CDisp8 = 0;
568 int ImmOffset = 0;
569 if (BaseReg == 0) {
570 // If there is no base register, we emit the special case SIB byte with
571 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
572 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
573 ForceDisp32 = true;
574 } else if (!Disp.isImm()) {
575 // Emit the normal disp32 encoding.
576 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
577 ForceDisp32 = true;
578 } else if (Disp.getImm() == 0 &&
579 // Base reg can't be anything that ends up with '5' as the base
580 // reg, it is the magic [*] nomenclature that indicates no base.
581 BaseRegNo != N86::EBP) {
582 // Emit no displacement ModR/M byte
583 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
584 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
585 // Emit the disp8 encoding.
586 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
587 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
588 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
589 // Emit the disp8 encoding.
590 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
591 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
592 ImmOffset = CDisp8 - Disp.getImm();
593 } else {
594 // Emit the normal disp32 encoding.
595 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
596 }
597
598 // Calculate what the SS field value should be...
599 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
600 unsigned SS = SSTable[Scale.getImm()];
601
602 if (BaseReg == 0) {
603 // Handle the SIB byte for the case where there is no base, see Intel
604 // Manual 2A, table 2-7. The displacement has already been output.
605 unsigned IndexRegNo;
606 if (IndexReg.getReg())
607 IndexRegNo = GetX86RegNum(IndexReg);
608 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
609 IndexRegNo = 4;
610 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
611 } else {
612 unsigned IndexRegNo;
613 if (IndexReg.getReg())
614 IndexRegNo = GetX86RegNum(IndexReg);
615 else
616 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
617 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
618 }
619
620 // Do we need to output a displacement?
621 if (ForceDisp8)
622 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
623 else if (ForceDisp32 || Disp.getImm() != 0)
624 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
625 CurByte, OS, Fixups);
626}
627
628/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
629/// called VEX.
630void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
631 int MemOperand, const MCInst &MI,
632 const MCInstrDesc &Desc,
633 raw_ostream &OS) const {
634 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.")((!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX."
) ? static_cast<void> (0) : __assert_fail ("!(TSFlags & X86II::LOCK) && \"Can't have LOCK VEX.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 634, __PRETTY_FUNCTION__));
635
636 uint64_t Encoding = TSFlags & X86II::EncodingMask;
637 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
638 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
639 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
640
641 // VEX_R: opcode externsion equivalent to REX.R in
642 // 1's complement (inverted) form
643 //
644 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
645 // 0: Same as REX_R=1 (64 bit mode only)
646 //
647 uint8_t VEX_R = 0x1;
648 uint8_t EVEX_R2 = 0x1;
649
650 // VEX_X: equivalent to REX.X, only used when a
651 // register is used for index in SIB Byte.
652 //
653 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
654 // 0: Same as REX.X=1 (64-bit mode only)
655 uint8_t VEX_X = 0x1;
656
657 // VEX_B:
658 //
659 // 1: Same as REX_B=0 (ignored in 32-bit mode)
660 // 0: Same as REX_B=1 (64 bit mode only)
661 //
662 uint8_t VEX_B = 0x1;
663
664 // VEX_W: opcode specific (use like REX.W, or used for
665 // opcode extension, or ignored, depending on the opcode byte)
666 uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
667
668 // VEX_5M (VEX m-mmmmm field):
669 //
670 // 0b00000: Reserved for future use
671 // 0b00001: implied 0F leading opcode
672 // 0b00010: implied 0F 38 leading opcode bytes
673 // 0b00011: implied 0F 3A leading opcode bytes
674 // 0b00100-0b11111: Reserved for future use
675 // 0b01000: XOP map select - 08h instructions with imm byte
676 // 0b01001: XOP map select - 09h instructions with no imm byte
677 // 0b01010: XOP map select - 0Ah instructions with imm dword
678 uint8_t VEX_5M;
679 switch (TSFlags & X86II::OpMapMask) {
680 default: llvm_unreachable("Invalid prefix!")::llvm::llvm_unreachable_internal("Invalid prefix!", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 680);
681 case X86II::TB: VEX_5M = 0x1; break; // 0F
682 case X86II::T8: VEX_5M = 0x2; break; // 0F 38
683 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
684 case X86II::XOP8: VEX_5M = 0x8; break;
685 case X86II::XOP9: VEX_5M = 0x9; break;
686 case X86II::XOPA: VEX_5M = 0xA; break;
687 }
688
689 // VEX_4V (VEX vvvv field): a register specifier
690 // (in 1's complement form) or 1111 if unused.
691 uint8_t VEX_4V = 0xf;
692 uint8_t EVEX_V2 = 0x1;
693
694 // EVEX_L2/VEX_L (Vector Length):
695 //
696 // L2 L
697 // 0 0: scalar or 128-bit vector
698 // 0 1: 256-bit vector
699 // 1 0: 512-bit vector
700 //
701 uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
702 uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
703
704 // VEX_PP: opcode extension providing equivalent
705 // functionality of a SIMD prefix
706 //
707 // 0b00: None
708 // 0b01: 66
709 // 0b10: F3
710 // 0b11: F2
711 //
712 uint8_t VEX_PP = 0;
713 switch (TSFlags & X86II::OpPrefixMask) {
714 case X86II::PD: VEX_PP = 0x1; break; // 66
715 case X86II::XS: VEX_PP = 0x2; break; // F3
716 case X86II::XD: VEX_PP = 0x3; break; // F2
717 }
718
719 // EVEX_U
720 uint8_t EVEX_U = 1; // Always '1' so far
721
722 // EVEX_z
723 uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
724
725 // EVEX_b
726 uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
727
728 // EVEX_rc
729 uint8_t EVEX_rc = 0;
730
731 // EVEX_aaa
732 uint8_t EVEX_aaa = 0;
733
734 bool EncodeRC = false;
735
736 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
737 unsigned NumOps = Desc.getNumOperands();
738 unsigned CurOp = X86II::getOperandBias(Desc);
739
740 switch (TSFlags & X86II::FormMask) {
741 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!")::llvm::llvm_unreachable_internal("Unexpected form in EmitVEXOpcodePrefix!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 741);
742 case X86II::RawFrm:
743 break;
744 case X86II::MRMDestMem: {
745 // MRMDestMem instructions forms:
746 // MemAddr, src1(ModR/M)
747 // MemAddr, src1(VEX_4V), src2(ModR/M)
748 // MemAddr, src1(ModR/M), imm8
749 //
750 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
751 VEX_B = ~(BaseRegEnc >> 3) & 1;
752 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
753 VEX_X = ~(IndexRegEnc >> 3) & 1;
754 if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
755 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
756
757 CurOp += X86::AddrNumOperands;
758
759 if (HasEVEX_K)
760 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
761
762 if (HasVEX_4V) {
763 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
764 VEX_4V = ~VRegEnc & 0xf;
765 EVEX_V2 = ~(VRegEnc >> 4) & 1;
766 }
767
768 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
769 VEX_R = ~(RegEnc >> 3) & 1;
770 EVEX_R2 = ~(RegEnc >> 4) & 1;
771 break;
772 }
773 case X86II::MRMSrcMem: {
774 // MRMSrcMem instructions forms:
775 // src1(ModR/M), MemAddr
776 // src1(ModR/M), src2(VEX_4V), MemAddr
777 // src1(ModR/M), MemAddr, imm8
778 // src1(ModR/M), MemAddr, src2(Imm[7:4])
779 //
780 // FMA4:
781 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
782 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
783 VEX_R = ~(RegEnc >> 3) & 1;
784 EVEX_R2 = ~(RegEnc >> 4) & 1;
785
786 if (HasEVEX_K)
787 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
788
789 if (HasVEX_4V) {
790 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
791 VEX_4V = ~VRegEnc & 0xf;
792 EVEX_V2 = ~(VRegEnc >> 4) & 1;
793 }
794
795 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
796 VEX_B = ~(BaseRegEnc >> 3) & 1;
797 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
798 VEX_X = ~(IndexRegEnc >> 3) & 1;
799 if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
800 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
801
802 break;
803 }
804 case X86II::MRMSrcMem4VOp3: {
805 // Instruction format for 4VOp3:
806 // src1(ModR/M), MemAddr, src3(VEX_4V)
807 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
808 VEX_R = ~(RegEnc >> 3) & 1;
809
810 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
811 VEX_B = ~(BaseRegEnc >> 3) & 1;
812 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
813 VEX_X = ~(IndexRegEnc >> 3) & 1;
814
815 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf;
816 break;
817 }
818 case X86II::MRMSrcMemOp4: {
819 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
820 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
821 VEX_R = ~(RegEnc >> 3) & 1;
822
823 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
824 VEX_4V = ~VRegEnc & 0xf;
825
826 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
827 VEX_B = ~(BaseRegEnc >> 3) & 1;
828 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
829 VEX_X = ~(IndexRegEnc >> 3) & 1;
830 break;
831 }
832 case X86II::MRM0m: case X86II::MRM1m:
833 case X86II::MRM2m: case X86II::MRM3m:
834 case X86II::MRM4m: case X86II::MRM5m:
835 case X86II::MRM6m: case X86II::MRM7m: {
836 // MRM[0-9]m instructions forms:
837 // MemAddr
838 // src1(VEX_4V), MemAddr
839 if (HasVEX_4V) {
840 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
841 VEX_4V = ~VRegEnc & 0xf;
842 EVEX_V2 = ~(VRegEnc >> 4) & 1;
843 }
844
845 if (HasEVEX_K)
846 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
847
848 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
849 VEX_B = ~(BaseRegEnc >> 3) & 1;
850 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
851 VEX_X = ~(IndexRegEnc >> 3) & 1;
852 break;
853 }
854 case X86II::MRMSrcReg: {
855 // MRMSrcReg instructions forms:
856 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
857 // dst(ModR/M), src1(ModR/M)
858 // dst(ModR/M), src1(ModR/M), imm8
859 //
860 // FMA4:
861 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
862 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
863 VEX_R = ~(RegEnc >> 3) & 1;
864 EVEX_R2 = ~(RegEnc >> 4) & 1;
865
866 if (HasEVEX_K)
867 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
868
869 if (HasVEX_4V) {
870 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
871 VEX_4V = ~VRegEnc & 0xf;
872 EVEX_V2 = ~(VRegEnc >> 4) & 1;
873 }
874
875 RegEnc = getX86RegEncoding(MI, CurOp++);
876 VEX_B = ~(RegEnc >> 3) & 1;
877 VEX_X = ~(RegEnc >> 4) & 1;
878
879 if (EVEX_b) {
880 if (HasEVEX_RC) {
881 unsigned RcOperand = NumOps-1;
882 assert(RcOperand >= CurOp)((RcOperand >= CurOp) ? static_cast<void> (0) : __assert_fail
("RcOperand >= CurOp", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 882, __PRETTY_FUNCTION__));
883 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
884 }
885 EncodeRC = true;
886 }
887 break;
888 }
889 case X86II::MRMSrcReg4VOp3: {
890 // Instruction format for 4VOp3:
891 // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
892 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
893 VEX_R = ~(RegEnc >> 3) & 1;
894
895 RegEnc = getX86RegEncoding(MI, CurOp++);
896 VEX_B = ~(RegEnc >> 3) & 1;
897
898 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
899 break;
900 }
901 case X86II::MRMSrcRegOp4: {
902 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
903 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
904 VEX_R = ~(RegEnc >> 3) & 1;
905
906 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
907 VEX_4V = ~VRegEnc & 0xf;
908
909 // Skip second register source (encoded in Imm[7:4])
910 ++CurOp;
911
912 RegEnc = getX86RegEncoding(MI, CurOp++);
913 VEX_B = ~(RegEnc >> 3) & 1;
914 VEX_X = ~(RegEnc >> 4) & 1;
915 break;
916 }
917 case X86II::MRMDestReg: {
918 // MRMDestReg instructions forms:
919 // dst(ModR/M), src(ModR/M)
920 // dst(ModR/M), src(ModR/M), imm8
921 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
922 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
923 VEX_B = ~(RegEnc >> 3) & 1;
924 VEX_X = ~(RegEnc >> 4) & 1;
925
926 if (HasEVEX_K)
927 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
928
929 if (HasVEX_4V) {
930 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
931 VEX_4V = ~VRegEnc & 0xf;
932 EVEX_V2 = ~(VRegEnc >> 4) & 1;
933 }
934
935 RegEnc = getX86RegEncoding(MI, CurOp++);
936 VEX_R = ~(RegEnc >> 3) & 1;
937 EVEX_R2 = ~(RegEnc >> 4) & 1;
938 if (EVEX_b)
939 EncodeRC = true;
940 break;
941 }
942 case X86II::MRM0r: case X86II::MRM1r:
943 case X86II::MRM2r: case X86II::MRM3r:
944 case X86II::MRM4r: case X86II::MRM5r:
945 case X86II::MRM6r: case X86II::MRM7r: {
946 // MRM0r-MRM7r instructions forms:
947 // dst(VEX_4V), src(ModR/M), imm8
948 if (HasVEX_4V) {
949 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
950 VEX_4V = ~VRegEnc & 0xf;
951 EVEX_V2 = ~(VRegEnc >> 4) & 1;
952 }
953 if (HasEVEX_K)
954 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
955
956 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
957 VEX_B = ~(RegEnc >> 3) & 1;
958 VEX_X = ~(RegEnc >> 4) & 1;
959 break;
960 }
961 }
962
963 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
964 // VEX opcode prefix can have 2 or 3 bytes
965 //
966 // 3 bytes:
967 // +-----+ +--------------+ +-------------------+
968 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
969 // +-----+ +--------------+ +-------------------+
970 // 2 bytes:
971 // +-----+ +-------------------+
972 // | C5h | | R | vvvv | L | pp |
973 // +-----+ +-------------------+
974 //
975 // XOP uses a similar prefix:
976 // +-----+ +--------------+ +-------------------+
977 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
978 // +-----+ +--------------+ +-------------------+
979 uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
980
981 // Can we use the 2 byte VEX prefix?
982 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
983 EmitByte(0xC5, CurByte, OS);
984 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
985 return;
986 }
987
988 // 3 byte VEX prefix
989 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
990 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
991 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
992 } else {
993 assert(Encoding == X86II::EVEX && "unknown encoding!")((Encoding == X86II::EVEX && "unknown encoding!") ? static_cast
<void> (0) : __assert_fail ("Encoding == X86II::EVEX && \"unknown encoding!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 993, __PRETTY_FUNCTION__));
994 // EVEX opcode prefix can have 4 bytes
995 //
996 // +-----+ +--------------+ +-------------------+ +------------------------+
997 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
998 // +-----+ +--------------+ +-------------------+ +------------------------+
999 assert((VEX_5M & 0x3) == VEX_5M(((VEX_5M & 0x3) == VEX_5M && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"
) ? static_cast<void> (0) : __assert_fail ("(VEX_5M & 0x3) == VEX_5M && \"More than 2 significant bits in VEX.m-mmmm fields for EVEX!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1000, __PRETTY_FUNCTION__))
1000 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!")(((VEX_5M & 0x3) == VEX_5M && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"
) ? static_cast<void> (0) : __assert_fail ("(VEX_5M & 0x3) == VEX_5M && \"More than 2 significant bits in VEX.m-mmmm fields for EVEX!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1000, __PRETTY_FUNCTION__));
1001
1002 EmitByte(0x62, CurByte, OS);
1003 EmitByte((VEX_R << 7) |
1004 (VEX_X << 6) |
1005 (VEX_B << 5) |
1006 (EVEX_R2 << 4) |
1007 VEX_5M, CurByte, OS);
1008 EmitByte((VEX_W << 7) |
1009 (VEX_4V << 3) |
1010 (EVEX_U << 2) |
1011 VEX_PP, CurByte, OS);
1012 if (EncodeRC)
1013 EmitByte((EVEX_z << 7) |
1014 (EVEX_rc << 5) |
1015 (EVEX_b << 4) |
1016 (EVEX_V2 << 3) |
1017 EVEX_aaa, CurByte, OS);
1018 else
1019 EmitByte((EVEX_z << 7) |
1020 (EVEX_L2 << 6) |
1021 (VEX_L << 5) |
1022 (EVEX_b << 4) |
1023 (EVEX_V2 << 3) |
1024 EVEX_aaa, CurByte, OS);
1025 }
1026}
1027
1028/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1029/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1030/// size, and 3) use of X86-64 extended registers.
1031uint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1032 int MemOperand,
1033 const MCInstrDesc &Desc) const {
1034 uint8_t REX = 0;
1035 bool UsesHighByteReg = false;
1036
1037 if (TSFlags & X86II::REX_W)
1038 REX |= 1 << 3; // set REX.W
1039
1040 if (MI.getNumOperands() == 0) return REX;
1041
1042 unsigned NumOps = MI.getNumOperands();
1043 unsigned CurOp = X86II::getOperandBias(Desc);
1044
1045 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1046 for (unsigned i = CurOp; i != NumOps; ++i) {
1047 const MCOperand &MO = MI.getOperand(i);
1048 if (!MO.isReg()) continue;
1049 unsigned Reg = MO.getReg();
1050 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1051 UsesHighByteReg = true;
1052 if (X86II::isX86_64NonExtLowByteReg(Reg))
1053 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1054 // that returns non-zero.
1055 REX |= 0x40; // REX fixed encoding prefix
1056 }
1057
1058 switch (TSFlags & X86II::FormMask) {
1059 case X86II::AddRegFrm:
1060 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1061 break;
1062 case X86II::MRMSrcReg:
1063 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1064 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1065 break;
1066 case X86II::MRMSrcMem: {
1067 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1068 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1069 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1070 CurOp += X86::AddrNumOperands;
Value stored to 'CurOp' is never read
1071 break;
1072 }
1073 case X86II::MRMDestReg:
1074 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1075 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1076 break;
1077 case X86II::MRMDestMem:
1078 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1079 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1080 CurOp += X86::AddrNumOperands;
1081 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
1082 break;
1083 case X86II::MRMXm:
1084 case X86II::MRM0m: case X86II::MRM1m:
1085 case X86II::MRM2m: case X86II::MRM3m:
1086 case X86II::MRM4m: case X86II::MRM5m:
1087 case X86II::MRM6m: case X86II::MRM7m:
1088 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
1089 REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
1090 break;
1091 case X86II::MRMXr:
1092 case X86II::MRM0r: case X86II::MRM1r:
1093 case X86II::MRM2r: case X86II::MRM3r:
1094 case X86II::MRM4r: case X86II::MRM5r:
1095 case X86II::MRM6r: case X86II::MRM7r:
1096 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
1097 break;
1098 }
1099 if (REX && UsesHighByteReg)
1100 report_fatal_error("Cannot encode high byte register in REX-prefixed instruction");
1101
1102 return REX;
1103}
1104
1105/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1106void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1107 unsigned SegOperand,
1108 const MCInst &MI,
1109 raw_ostream &OS) const {
1110 // Check for explicit segment override on memory operand.
1111 switch (MI.getOperand(SegOperand).getReg()) {
1112 default: llvm_unreachable("Unknown segment register!")::llvm::llvm_unreachable_internal("Unknown segment register!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1112);
1113 case 0: break;
1114 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1115 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1116 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1117 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1118 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1119 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1120 }
1121}
1122
1123/// Emit all instruction prefixes prior to the opcode.
1124///
1125/// MemOperand is the operand # of the start of a memory operand if present. If
1126/// Not present, it is -1.
1127///
1128/// Returns true if a REX prefix was used.
1129bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1130 int MemOperand, const MCInst &MI,
1131 const MCInstrDesc &Desc,
1132 const MCSubtargetInfo &STI,
1133 raw_ostream &OS) const {
1134 bool Ret = false;
1135 // Emit the operand size opcode prefix as needed.
1136 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
1137 : X86II::OpSize16))
1138 EmitByte(0x66, CurByte, OS);
1139
1140 // Emit the LOCK opcode prefix.
1141 if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1142 EmitByte(0xF0, CurByte, OS);
1143
1144 // Emit the NOTRACK opcode prefix.
1145 if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1146 EmitByte(0x3E, CurByte, OS);
1147
1148 switch (TSFlags & X86II::OpPrefixMask) {
1149 case X86II::PD: // 66
1150 EmitByte(0x66, CurByte, OS);
1151 break;
1152 case X86II::XS: // F3
1153 EmitByte(0xF3, CurByte, OS);
1154 break;
1155 case X86II::XD: // F2
1156 EmitByte(0xF2, CurByte, OS);
1157 break;
1158 }
1159
1160 // Handle REX prefix.
1161 // FIXME: Can this come before F2 etc to simplify emission?
1162 if (is64BitMode(STI)) {
1163 if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
1164 EmitByte(0x40 | REX, CurByte, OS);
1165 Ret = true;
1166 }
1167 } else {
1168 assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode.")((!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode."
) ? static_cast<void> (0) : __assert_fail ("!(TSFlags & X86II::REX_W) && \"REX.W requires 64bit mode.\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1168, __PRETTY_FUNCTION__));
1169 }
1170
1171 // 0x0F escape code must be emitted just before the opcode.
1172 switch (TSFlags & X86II::OpMapMask) {
1173 case X86II::TB: // Two-byte opcode map
1174 case X86II::T8: // 0F 38
1175 case X86II::TA: // 0F 3A
1176 case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1177 EmitByte(0x0F, CurByte, OS);
1178 break;
1179 }
1180
1181 switch (TSFlags & X86II::OpMapMask) {
1182 case X86II::T8: // 0F 38
1183 EmitByte(0x38, CurByte, OS);
1184 break;
1185 case X86II::TA: // 0F 3A
1186 EmitByte(0x3A, CurByte, OS);
1187 break;
1188 }
1189 return Ret;
1190}
1191
1192void X86MCCodeEmitter::
1193encodeInstruction(const MCInst &MI, raw_ostream &OS,
1194 SmallVectorImpl<MCFixup> &Fixups,
1195 const MCSubtargetInfo &STI) const {
1196 unsigned Opcode = MI.getOpcode();
1197 const MCInstrDesc &Desc = MCII.get(Opcode);
1198 uint64_t TSFlags = Desc.TSFlags;
1199 unsigned Flags = MI.getFlags();
1200
1201 // Pseudo instructions don't get encoded.
1202 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1203 return;
1204
1205 unsigned NumOps = Desc.getNumOperands();
1206 unsigned CurOp = X86II::getOperandBias(Desc);
1207
1208 // Keep track of the current byte being emitted.
1209 unsigned CurByte = 0;
1210
1211 // Encoding type for this instruction.
1212 uint64_t Encoding = TSFlags & X86II::EncodingMask;
1213
1214 // It uses the VEX.VVVV field?
1215 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1216 bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1217
1218 // It uses the EVEX.aaa field?
1219 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1220 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1221
1222 // Used if a register is encoded in 7:4 of immediate.
1223 unsigned I8RegNum = 0;
1224
1225 // Determine where the memory operand starts, if present.
1226 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
1227 if (MemoryOperand != -1) MemoryOperand += CurOp;
1228
1229 // Emit segment override opcode prefix as needed.
1230 if (MemoryOperand >= 0)
1231 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1232 MI, OS);
1233
1234 // Emit the repeat opcode prefix as needed.
1235 if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
1236 EmitByte(0xF3, CurByte, OS);
1237 if (Flags & X86::IP_HAS_REPEAT_NE)
1238 EmitByte(0xF2, CurByte, OS);
1239
1240 // Emit the address size opcode prefix as needed.
1241 bool need_address_override;
1242 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
1243 if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
1244 (is32BitMode(STI) && AdSize == X86II::AdSize16) ||
1245 (is64BitMode(STI) && AdSize == X86II::AdSize32)) {
1246 need_address_override = true;
1247 } else if (MemoryOperand < 0) {
1248 need_address_override = false;
1249 } else if (is64BitMode(STI)) {
1250 assert(!Is16BitMemOperand(MI, MemoryOperand, STI))((!Is16BitMemOperand(MI, MemoryOperand, STI)) ? static_cast<
void> (0) : __assert_fail ("!Is16BitMemOperand(MI, MemoryOperand, STI)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1250, __PRETTY_FUNCTION__));
1251 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1252 } else if (is32BitMode(STI)) {
1253 assert(!Is64BitMemOperand(MI, MemoryOperand))((!Is64BitMemOperand(MI, MemoryOperand)) ? static_cast<void
> (0) : __assert_fail ("!Is64BitMemOperand(MI, MemoryOperand)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1253, __PRETTY_FUNCTION__));
1254 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1255 } else {
1256 assert(is16BitMode(STI))((is16BitMode(STI)) ? static_cast<void> (0) : __assert_fail
("is16BitMode(STI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1256, __PRETTY_FUNCTION__));
1257 assert(!Is64BitMemOperand(MI, MemoryOperand))((!Is64BitMemOperand(MI, MemoryOperand)) ? static_cast<void
> (0) : __assert_fail ("!Is64BitMemOperand(MI, MemoryOperand)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1257, __PRETTY_FUNCTION__));
1258 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1259 }
1260
1261 if (need_address_override)
1262 EmitByte(0x67, CurByte, OS);
1263
1264 bool Rex = false;
1265 if (Encoding == 0)
1266 Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1267 else
1268 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1269
1270 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1271
1272 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1273 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1274
1275 uint64_t Form = TSFlags & X86II::FormMask;
1276 switch (Form) {
1277 default: errs() << "FORM: " << Form << "\n";
1278 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!")::llvm::llvm_unreachable_internal("Unknown FormMask value in X86MCCodeEmitter!"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1278);
1279 case X86II::Pseudo:
1280 llvm_unreachable("Pseudo instruction shouldn't be emitted")::llvm::llvm_unreachable_internal("Pseudo instruction shouldn't be emitted"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1280);
1281 case X86II::RawFrmDstSrc: {
1282 unsigned siReg = MI.getOperand(1).getReg();
1283 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||((((siReg == X86::SI && MI.getOperand(0).getReg() == X86
::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg
() == X86::EDI) || (siReg == X86::RSI && MI.getOperand
(0).getReg() == X86::RDI)) && "SI and DI register sizes do not match"
) ? static_cast<void> (0) : __assert_fail ("((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && \"SI and DI register sizes do not match\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1286, __PRETTY_FUNCTION__))
1284 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||((((siReg == X86::SI && MI.getOperand(0).getReg() == X86
::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg
() == X86::EDI) || (siReg == X86::RSI && MI.getOperand
(0).getReg() == X86::RDI)) && "SI and DI register sizes do not match"
) ? static_cast<void> (0) : __assert_fail ("((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && \"SI and DI register sizes do not match\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1286, __PRETTY_FUNCTION__))
1285 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&((((siReg == X86::SI && MI.getOperand(0).getReg() == X86
::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg
() == X86::EDI) || (siReg == X86::RSI && MI.getOperand
(0).getReg() == X86::RDI)) && "SI and DI register sizes do not match"
) ? static_cast<void> (0) : __assert_fail ("((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && \"SI and DI register sizes do not match\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1286, __PRETTY_FUNCTION__))
1286 "SI and DI register sizes do not match")((((siReg == X86::SI && MI.getOperand(0).getReg() == X86
::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg
() == X86::EDI) || (siReg == X86::RSI && MI.getOperand
(0).getReg() == X86::RDI)) && "SI and DI register sizes do not match"
) ? static_cast<void> (0) : __assert_fail ("((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && \"SI and DI register sizes do not match\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1286, __PRETTY_FUNCTION__));
1287 // Emit segment override opcode prefix as needed (not for %ds).
1288 if (MI.getOperand(2).getReg() != X86::DS)
1289 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1290 // Emit AdSize prefix as needed.
1291 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1292 (is32BitMode(STI) && siReg == X86::SI))
1293 EmitByte(0x67, CurByte, OS);
1294 CurOp += 3; // Consume operands.
1295 EmitByte(BaseOpcode, CurByte, OS);
1296 break;
1297 }
1298 case X86II::RawFrmSrc: {
1299 unsigned siReg = MI.getOperand(0).getReg();
1300 // Emit segment override opcode prefix as needed (not for %ds).
1301 if (MI.getOperand(1).getReg() != X86::DS)
1302 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1303 // Emit AdSize prefix as needed.
1304 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1305 (is32BitMode(STI) && siReg == X86::SI))
1306 EmitByte(0x67, CurByte, OS);
1307 CurOp += 2; // Consume operands.
1308 EmitByte(BaseOpcode, CurByte, OS);
1309 break;
1310 }
1311 case X86II::RawFrmDst: {
1312 unsigned siReg = MI.getOperand(0).getReg();
1313 // Emit AdSize prefix as needed.
1314 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1315 (is32BitMode(STI) && siReg == X86::DI))
1316 EmitByte(0x67, CurByte, OS);
1317 ++CurOp; // Consume operand.
1318 EmitByte(BaseOpcode, CurByte, OS);
1319 break;
1320 }
1321 case X86II::RawFrm: {
1322 EmitByte(BaseOpcode, CurByte, OS);
1323
1324 if (!is64BitMode(STI) || !isPCRel32Branch(MI))
1325 break;
1326
1327 const MCOperand &Op = MI.getOperand(CurOp++);
1328 EmitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
1329 MCFixupKind(X86::reloc_branch_4byte_pcrel), CurByte, OS,
1330 Fixups);
1331 break;
1332 }
1333 case X86II::RawFrmMemOffs:
1334 // Emit segment override opcode prefix as needed.
1335 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1336 EmitByte(BaseOpcode, CurByte, OS);
1337 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1338 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1339 CurByte, OS, Fixups);
1340 ++CurOp; // skip segment operand
1341 break;
1342 case X86II::RawFrmImm8:
1343 EmitByte(BaseOpcode, CurByte, OS);
1344 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1345 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1346 CurByte, OS, Fixups);
1347 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1348 OS, Fixups);
1349 break;
1350 case X86II::RawFrmImm16:
1351 EmitByte(BaseOpcode, CurByte, OS);
1352 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1353 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1354 CurByte, OS, Fixups);
1355 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1356 OS, Fixups);
1357 break;
1358
1359 case X86II::AddRegFrm:
1360 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1361 break;
1362
1363 case X86II::MRMDestReg: {
1364 EmitByte(BaseOpcode, CurByte, OS);
1365 unsigned SrcRegNum = CurOp + 1;
1366
1367 if (HasEVEX_K) // Skip writemask
1368 ++SrcRegNum;
1369
1370 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1371 ++SrcRegNum;
1372
1373 EmitRegModRMByte(MI.getOperand(CurOp),
1374 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1375 CurOp = SrcRegNum + 1;
1376 break;
1377 }
1378 case X86II::MRMDestMem: {
1379 EmitByte(BaseOpcode, CurByte, OS);
1380 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1381
1382 if (HasEVEX_K) // Skip writemask
1383 ++SrcRegNum;
1384
1385 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1386 ++SrcRegNum;
1387
1388 emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
1389 Rex, CurByte, OS, Fixups, STI);
1390 CurOp = SrcRegNum + 1;
1391 break;
1392 }
1393 case X86II::MRMSrcReg: {
1394 EmitByte(BaseOpcode, CurByte, OS);
1395 unsigned SrcRegNum = CurOp + 1;
1396
1397 if (HasEVEX_K) // Skip writemask
1398 ++SrcRegNum;
1399
1400 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1401 ++SrcRegNum;
1402
1403 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1404 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1405 CurOp = SrcRegNum + 1;
1406 if (HasVEX_I8Reg)
1407 I8RegNum = getX86RegEncoding(MI, CurOp++);
1408 // do not count the rounding control operand
1409 if (HasEVEX_RC)
1410 --NumOps;
1411 break;
1412 }
1413 case X86II::MRMSrcReg4VOp3: {
1414 EmitByte(BaseOpcode, CurByte, OS);
1415 unsigned SrcRegNum = CurOp + 1;
1416
1417 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1418 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1419 CurOp = SrcRegNum + 1;
1420 ++CurOp; // Encoded in VEX.VVVV
1421 break;
1422 }
1423 case X86II::MRMSrcRegOp4: {
1424 EmitByte(BaseOpcode, CurByte, OS);
1425 unsigned SrcRegNum = CurOp + 1;
1426
1427 // Skip 1st src (which is encoded in VEX_VVVV)
1428 ++SrcRegNum;
1429
1430 // Capture 2nd src (which is encoded in Imm[7:4])
1431 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg")((HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"
) ? static_cast<void> (0) : __assert_fail ("HasVEX_I8Reg && \"MRMSrcRegOp4 should imply VEX_I8Reg\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1431, __PRETTY_FUNCTION__));
1432 I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1433
1434 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1435 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1436 CurOp = SrcRegNum + 1;
1437 break;
1438 }
1439 case X86II::MRMSrcMem: {
1440 unsigned FirstMemOp = CurOp+1;
1441
1442 if (HasEVEX_K) // Skip writemask
1443 ++FirstMemOp;
1444
1445 if (HasVEX_4V)
1446 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1447
1448 EmitByte(BaseOpcode, CurByte, OS);
1449
1450 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1451 TSFlags, Rex, CurByte, OS, Fixups, STI);
1452 CurOp = FirstMemOp + X86::AddrNumOperands;
1453 if (HasVEX_I8Reg)
1454 I8RegNum = getX86RegEncoding(MI, CurOp++);
1455 break;
1456 }
1457 case X86II::MRMSrcMem4VOp3: {
1458 unsigned FirstMemOp = CurOp+1;
1459
1460 EmitByte(BaseOpcode, CurByte, OS);
1461
1462 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1463 TSFlags, Rex, CurByte, OS, Fixups, STI);
1464 CurOp = FirstMemOp + X86::AddrNumOperands;
1465 ++CurOp; // Encoded in VEX.VVVV.
1466 break;
1467 }
1468 case X86II::MRMSrcMemOp4: {
1469 unsigned FirstMemOp = CurOp+1;
1470
1471 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1472
1473 // Capture second register source (encoded in Imm[7:4])
1474 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg")((HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"
) ? static_cast<void> (0) : __assert_fail ("HasVEX_I8Reg && \"MRMSrcRegOp4 should imply VEX_I8Reg\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1474, __PRETTY_FUNCTION__));
1475 I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1476
1477 EmitByte(BaseOpcode, CurByte, OS);
1478
1479 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1480 TSFlags, Rex, CurByte, OS, Fixups, STI);
1481 CurOp = FirstMemOp + X86::AddrNumOperands;
1482 break;
1483 }
1484
1485 case X86II::MRMXr:
1486 case X86II::MRM0r: case X86II::MRM1r:
1487 case X86II::MRM2r: case X86II::MRM3r:
1488 case X86II::MRM4r: case X86II::MRM5r:
1489 case X86II::MRM6r: case X86II::MRM7r:
1490 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1491 ++CurOp;
1492 if (HasEVEX_K) // Skip writemask
1493 ++CurOp;
1494 EmitByte(BaseOpcode, CurByte, OS);
1495 EmitRegModRMByte(MI.getOperand(CurOp++),
1496 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1497 CurByte, OS);
1498 break;
1499
1500 case X86II::MRMXm:
1501 case X86II::MRM0m: case X86II::MRM1m:
1502 case X86II::MRM2m: case X86II::MRM3m:
1503 case X86II::MRM4m: case X86II::MRM5m:
1504 case X86II::MRM6m: case X86II::MRM7m:
1505 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1506 ++CurOp;
1507 if (HasEVEX_K) // Skip writemask
1508 ++CurOp;
1509 EmitByte(BaseOpcode, CurByte, OS);
1510 emitMemModRMByte(MI, CurOp,
1511 (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1512 Rex, CurByte, OS, Fixups, STI);
1513 CurOp += X86::AddrNumOperands;
1514 break;
1515
1516 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1517 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1518 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1519 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1520 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1521 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1522 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1523 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1524 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1525 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1526 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1527 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1528 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1529 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1530 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1531 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1532 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1533 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1534 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1535 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1536 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1537 case X86II::MRM_FF:
1538 EmitByte(BaseOpcode, CurByte, OS);
1539 EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
1540 break;
1541 }
1542
1543 if (HasVEX_I8Reg) {
1544 // The last source register of a 4 operand instruction in AVX is encoded
1545 // in bits[7:4] of a immediate byte.
1546 assert(I8RegNum < 16 && "Register encoding out of range")((I8RegNum < 16 && "Register encoding out of range"
) ? static_cast<void> (0) : __assert_fail ("I8RegNum < 16 && \"Register encoding out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1546, __PRETTY_FUNCTION__));
1547 I8RegNum <<= 4;
1548 if (CurOp != NumOps) {
1549 unsigned Val = MI.getOperand(CurOp++).getImm();
1550 assert(Val < 16 && "Immediate operand value out of range")((Val < 16 && "Immediate operand value out of range"
) ? static_cast<void> (0) : __assert_fail ("Val < 16 && \"Immediate operand value out of range\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp"
, 1550, __PRETTY_FUNCTION__));
1551 I8RegNum |= Val;
1552 }
1553 EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
1554 CurByte, OS, Fixups);
1555 } else {
1556 // If there is a remaining operand, it must be a trailing immediate. Emit it
1557 // according to the right size for the instruction. Some instructions
1558 // (SSE4a extrq and insertq) have two trailing immediates.
1559 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1560 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1561 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1562 CurByte, OS, Fixups);
1563 }
1564 }
1565
1566 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1567 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1568
1569#ifndef NDEBUG
1570 // FIXME: Verify.
1571 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1572 errs() << "Cannot encode all operands of: ";
1573 MI.dump();
1574 errs() << '\n';
1575 abort();
1576 }
1577#endif
1578}
1579
1580MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
1581 const MCRegisterInfo &MRI,
1582 MCContext &Ctx) {
1583 return new X86MCCodeEmitter(MCII, Ctx);
1584}