18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc05",
"cortex-a5")
200 .
Case(
"0xc07",
"cortex-a7")
201 .
Case(
"0xc08",
"cortex-a8")
202 .
Case(
"0xc09",
"cortex-a9")
203 .
Case(
"0xc0f",
"cortex-a15")
204 .
Case(
"0xc0e",
"cortex-a17")
205 .
Case(
"0xc20",
"cortex-m0")
206 .
Case(
"0xc23",
"cortex-m3")
207 .
Case(
"0xc24",
"cortex-m4")
208 .
Case(
"0xc27",
"cortex-m7")
209 .
Case(
"0xd20",
"cortex-m23")
210 .
Case(
"0xd21",
"cortex-m33")
211 .
Case(
"0xd24",
"cortex-m52")
212 .
Case(
"0xd22",
"cortex-m55")
213 .
Case(
"0xd23",
"cortex-m85")
214 .
Case(
"0xc18",
"cortex-r8")
215 .
Case(
"0xd13",
"cortex-r52")
216 .
Case(
"0xd15",
"cortex-r82")
217 .
Case(
"0xd02",
"cortex-a34")
218 .
Case(
"0xd04",
"cortex-a35")
219 .
Case(
"0xd03",
"cortex-a53")
220 .
Case(
"0xd05",
"cortex-a55")
221 .
Case(
"0xd46",
"cortex-a510")
222 .
Case(
"0xd80",
"cortex-a520")
223 .
Case(
"0xd88",
"cortex-a520ae")
224 .
Case(
"0xd07",
"cortex-a57")
225 .
Case(
"0xd06",
"cortex-a65")
226 .
Case(
"0xd43",
"cortex-a65ae")
227 .
Case(
"0xd08",
"cortex-a72")
228 .
Case(
"0xd09",
"cortex-a73")
229 .
Case(
"0xd0a",
"cortex-a75")
230 .
Case(
"0xd0b",
"cortex-a76")
231 .
Case(
"0xd0e",
"cortex-a76ae")
232 .
Case(
"0xd0d",
"cortex-a77")
233 .
Case(
"0xd41",
"cortex-a78")
234 .
Case(
"0xd42",
"cortex-a78ae")
235 .
Case(
"0xd4b",
"cortex-a78c")
236 .
Case(
"0xd47",
"cortex-a710")
237 .
Case(
"0xd4d",
"cortex-a715")
238 .
Case(
"0xd81",
"cortex-a720")
239 .
Case(
"0xd89",
"cortex-a720ae")
240 .
Case(
"0xd44",
"cortex-x1")
241 .
Case(
"0xd4c",
"cortex-x1c")
242 .
Case(
"0xd48",
"cortex-x2")
243 .
Case(
"0xd4e",
"cortex-x3")
244 .
Case(
"0xd82",
"cortex-x4")
245 .
Case(
"0xd4a",
"neoverse-e1")
246 .
Case(
"0xd0c",
"neoverse-n1")
247 .
Case(
"0xd49",
"neoverse-n2")
248 .
Case(
"0xd8e",
"neoverse-n3")
249 .
Case(
"0xd40",
"neoverse-v1")
250 .
Case(
"0xd4f",
"neoverse-v2")
251 .
Case(
"0xd84",
"neoverse-v3")
252 .
Case(
"0xd83",
"neoverse-v3ae")
256 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
258 .
Case(
"0x516",
"thunderx2t99")
259 .
Case(
"0x0516",
"thunderx2t99")
260 .
Case(
"0xaf",
"thunderx2t99")
261 .
Case(
"0x0af",
"thunderx2t99")
262 .
Case(
"0xa1",
"thunderxt88")
263 .
Case(
"0x0a1",
"thunderxt88")
267 if (Implementer ==
"0x46") {
269 .
Case(
"0x001",
"a64fx")
273 if (Implementer ==
"0x4e") {
275 .
Case(
"0x004",
"carmel")
279 if (Implementer ==
"0x48")
284 .
Case(
"0xd01",
"tsv110")
287 if (Implementer ==
"0x51")
292 .
Case(
"0x06f",
"krait")
293 .
Case(
"0x201",
"kryo")
294 .
Case(
"0x205",
"kryo")
295 .
Case(
"0x211",
"kryo")
296 .
Case(
"0x800",
"cortex-a73")
297 .
Case(
"0x801",
"cortex-a73")
298 .
Case(
"0x802",
"cortex-a75")
299 .
Case(
"0x803",
"cortex-a75")
300 .
Case(
"0x804",
"cortex-a76")
301 .
Case(
"0x805",
"cortex-a76")
302 .
Case(
"0xc00",
"falkor")
303 .
Case(
"0xc01",
"saphira")
305 if (Implementer ==
"0x53") {
308 unsigned Variant = 0, Part = 0;
313 if (
I.consume_front(
"CPU variant"))
314 I.ltrim(
"\t :").getAsInteger(0, Variant);
319 if (
I.consume_front(
"CPU part"))
320 I.ltrim(
"\t :").getAsInteger(0, Part);
322 unsigned Exynos = (Variant << 12) | Part;
334 if (Implementer ==
"0x6d") {
337 .
Case(
"0xd49",
"neoverse-n2")
341 if (Implementer ==
"0xc0") {
343 .
Case(
"0xac3",
"ampere1")
344 .
Case(
"0xac4",
"ampere1a")
345 .
Case(
"0xac5",
"ampere1b")
353StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
373 return HaveVectorSupport?
"z13" :
"zEC12";
376 return HaveVectorSupport?
"z14" :
"zEC12";
379 return HaveVectorSupport?
"z15" :
"zEC12";
383 return HaveVectorSupport?
"z16" :
"zEC12";
394 ProcCpuinfoContent.
split(Lines,
"\n");
398 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I)
400 size_t Pos = Lines[
I].find(
':');
402 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
410 bool HaveVectorSupport =
false;
411 for (
unsigned I = 0, E = CPUFeatures.size();
I != E; ++
I) {
412 if (CPUFeatures[
I] ==
"vx")
413 HaveVectorSupport =
true;
417 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
419 size_t Pos = Lines[
I].find(
"machine = ");
421 Pos +=
sizeof(
"machine = ") - 1;
423 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
424 return getCPUNameFromS390Model(Id, HaveVectorSupport);
436 ProcCpuinfoContent.
split(Lines,
"\n");
440 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
442 UArch = Lines[
I].substr(5).ltrim(
"\t :");
448 .
Case(
"sifive,u74-mc",
"sifive-u74")
449 .
Case(
"sifive,bullet0",
"sifive-u74")
454#if !defined(__linux__) || !defined(__x86_64__)
457 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
459 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
461 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
463 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
465 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
467 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
469 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
471 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
473 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
475 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
477 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
479 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
481 struct bpf_prog_load_attr {
497 int fd = syscall(321 , 5 , &attr,
505 memset(&attr, 0,
sizeof(attr));
510 fd = syscall(321 , 5 , &attr,
sizeof(attr));
519#if defined(__i386__) || defined(_M_IX86) || \
520 defined(__x86_64__) || defined(_M_X64)
529static bool isCpuIdSupported() {
530#if defined(__GNUC__) || defined(__clang__)
532 int __cpuid_supported;
535 " movl %%eax,%%ecx\n"
536 " xorl $0x00200000,%%eax\n"
542 " cmpl %%eax,%%ecx\n"
546 :
"=r"(__cpuid_supported)
549 if (!__cpuid_supported)
559static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
560 unsigned *rECX,
unsigned *rEDX) {
561#if defined(__GNUC__) || defined(__clang__)
562#if defined(__x86_64__)
565 __asm__(
"movq\t%%rbx, %%rsi\n\t"
567 "xchgq\t%%rbx, %%rsi\n\t"
568 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
571#elif defined(__i386__)
572 __asm__(
"movl\t%%ebx, %%esi\n\t"
574 "xchgl\t%%ebx, %%esi\n\t"
575 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
581#elif defined(_MSC_VER)
584 __cpuid(registers,
value);
585 *rEAX = registers[0];
586 *rEBX = registers[1];
587 *rECX = registers[2];
588 *rEDX = registers[3];
600VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
601 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
602 if (MaxLeaf ==
nullptr)
607 if (!isCpuIdSupported())
608 return VendorSignatures::UNKNOWN;
610 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
611 return VendorSignatures::UNKNOWN;
614 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
615 return VendorSignatures::GENUINE_INTEL;
618 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
619 return VendorSignatures::AUTHENTIC_AMD;
621 return VendorSignatures::UNKNOWN;
634static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
635 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
637#if defined(__GNUC__) || defined(__clang__)
638#if defined(__x86_64__)
641 __asm__(
"movq\t%%rbx, %%rsi\n\t"
643 "xchgq\t%%rbx, %%rsi\n\t"
644 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
645 :
"a"(
value),
"c"(subleaf));
647#elif defined(__i386__)
648 __asm__(
"movl\t%%ebx, %%esi\n\t"
650 "xchgl\t%%ebx, %%esi\n\t"
651 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
652 :
"a"(
value),
"c"(subleaf));
657#elif defined(_MSC_VER)
659 __cpuidex(registers,
value, subleaf);
660 *rEAX = registers[0];
661 *rEBX = registers[1];
662 *rECX = registers[2];
663 *rEDX = registers[3];
671static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
672#if defined(__GNUC__) || defined(__clang__)
676 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
678#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
679 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
688static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
690 *Family = (
EAX >> 8) & 0xf;
692 if (*Family == 6 || *Family == 0xf) {
695 *Family += (
EAX >> 20) & 0xff;
702getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
703 const unsigned *Features,
704 unsigned *
Type,
unsigned *Subtype) {
705 auto testFeature = [&](
unsigned F) {
706 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
719 if (testFeature(X86::FEATURE_MMX)) {
735 *
Type = X86::INTEL_CORE2;
744 *
Type = X86::INTEL_CORE2;
753 *
Type = X86::INTEL_COREI7;
754 *Subtype = X86::INTEL_COREI7_NEHALEM;
761 *
Type = X86::INTEL_COREI7;
762 *Subtype = X86::INTEL_COREI7_WESTMERE;
768 *
Type = X86::INTEL_COREI7;
769 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
774 *
Type = X86::INTEL_COREI7;
775 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
784 *
Type = X86::INTEL_COREI7;
785 *Subtype = X86::INTEL_COREI7_HASWELL;
794 *
Type = X86::INTEL_COREI7;
795 *Subtype = X86::INTEL_COREI7_BROADWELL;
806 *
Type = X86::INTEL_COREI7;
807 *Subtype = X86::INTEL_COREI7_SKYLAKE;
813 *
Type = X86::INTEL_COREI7;
814 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
819 *
Type = X86::INTEL_COREI7;
820 if (testFeature(X86::FEATURE_AVX512BF16)) {
822 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
823 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
825 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
827 CPU =
"skylake-avx512";
828 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
835 *
Type = X86::INTEL_COREI7;
836 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
842 CPU =
"icelake-client";
843 *
Type = X86::INTEL_COREI7;
844 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
851 *
Type = X86::INTEL_COREI7;
852 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
868 *
Type = X86::INTEL_COREI7;
869 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
875 *
Type = X86::INTEL_COREI7;
876 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
884 *
Type = X86::INTEL_COREI7;
885 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
891 *
Type = X86::INTEL_COREI7;
892 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
897 CPU =
"graniterapids";
898 *
Type = X86::INTEL_COREI7;
899 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
904 CPU =
"graniterapids-d";
905 *
Type = X86::INTEL_COREI7;
906 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
912 CPU =
"icelake-server";
913 *
Type = X86::INTEL_COREI7;
914 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
921 CPU =
"sapphirerapids";
922 *
Type = X86::INTEL_COREI7;
923 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
932 *
Type = X86::INTEL_BONNELL;
943 *
Type = X86::INTEL_SILVERMONT;
949 *
Type = X86::INTEL_GOLDMONT;
952 CPU =
"goldmont-plus";
953 *
Type = X86::INTEL_GOLDMONT_PLUS;
960 *
Type = X86::INTEL_TREMONT;
965 CPU =
"sierraforest";
966 *
Type = X86::INTEL_SIERRAFOREST;
972 *
Type = X86::INTEL_GRANDRIDGE;
977 CPU =
"clearwaterforest";
978 *
Type = X86::INTEL_CLEARWATERFOREST;
984 *
Type = X86::INTEL_KNL;
988 *
Type = X86::INTEL_KNM;
995 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
997 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
998 CPU =
"icelake-client";
999 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1001 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
1003 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1004 CPU =
"cascadelake";
1005 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
1006 CPU =
"skylake-avx512";
1007 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
1009 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1010 if (testFeature(X86::FEATURE_SHA))
1014 }
else if (testFeature(X86::FEATURE_ADX)) {
1016 }
else if (testFeature(X86::FEATURE_AVX2)) {
1018 }
else if (testFeature(X86::FEATURE_AVX)) {
1019 CPU =
"sandybridge";
1020 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
1021 if (testFeature(X86::FEATURE_MOVBE))
1025 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
1027 }
else if (testFeature(X86::FEATURE_SSSE3)) {
1028 if (testFeature(X86::FEATURE_MOVBE))
1032 }
else if (testFeature(X86::FEATURE_64BIT)) {
1034 }
else if (testFeature(X86::FEATURE_SSE3)) {
1036 }
else if (testFeature(X86::FEATURE_SSE2)) {
1038 }
else if (testFeature(X86::FEATURE_SSE)) {
1040 }
else if (testFeature(X86::FEATURE_MMX)) {
1049 if (testFeature(X86::FEATURE_64BIT)) {
1053 if (testFeature(X86::FEATURE_SSE3)) {
1068getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
1069 const unsigned *Features,
1070 unsigned *
Type,
unsigned *Subtype) {
1071 auto testFeature = [&](
unsigned F) {
1072 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
1101 if (testFeature(X86::FEATURE_SSE)) {
1108 if (testFeature(X86::FEATURE_SSE3)) {
1116 *
Type = X86::AMDFAM10H;
1119 *Subtype = X86::AMDFAM10H_BARCELONA;
1122 *Subtype = X86::AMDFAM10H_SHANGHAI;
1125 *Subtype = X86::AMDFAM10H_ISTANBUL;
1131 *
Type = X86::AMD_BTVER1;
1135 *
Type = X86::AMDFAM15H;
1136 if (Model >= 0x60 && Model <= 0x7f) {
1138 *Subtype = X86::AMDFAM15H_BDVER4;
1141 if (Model >= 0x30 && Model <= 0x3f) {
1143 *Subtype = X86::AMDFAM15H_BDVER3;
1146 if ((Model >= 0x10 && Model <= 0x1f) ||
Model == 0x02) {
1148 *Subtype = X86::AMDFAM15H_BDVER2;
1151 if (Model <= 0x0f) {
1152 *Subtype = X86::AMDFAM15H_BDVER1;
1158 *
Type = X86::AMD_BTVER2;
1162 *
Type = X86::AMDFAM17H;
1163 if ((Model >= 0x30 && Model <= 0x3f) || (
Model == 0x47) ||
1164 (Model >= 0x60 && Model <= 0x67) || (
Model >= 0x68 &&
Model <= 0x6f) ||
1165 (Model >= 0x70 && Model <= 0x7f) || (
Model >= 0x84 &&
Model <= 0x87) ||
1166 (Model >= 0x90 && Model <= 0x97) || (
Model >= 0x98 &&
Model <= 0x9f) ||
1167 (Model >= 0xa0 && Model <= 0xaf)) {
1178 *Subtype = X86::AMDFAM17H_ZNVER2;
1181 if ((Model >= 0x10 && Model <= 0x1f) || (
Model >= 0x20 &&
Model <= 0x2f)) {
1185 *Subtype = X86::AMDFAM17H_ZNVER1;
1191 *
Type = X86::AMDFAM19H;
1192 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1193 (
Model >= 0x30 &&
Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1200 *Subtype = X86::AMDFAM19H_ZNVER3;
1203 if ((Model >= 0x10 && Model <= 0x1f) || (
Model >= 0x60 &&
Model <= 0x6f) ||
1204 (Model >= 0x70 && Model <= 0x77) || (
Model >= 0x78 &&
Model <= 0x7f) ||
1205 (Model >= 0xa0 && Model <= 0xaf)) {
1212 *Subtype = X86::AMDFAM19H_ZNVER4;
1223static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1224 unsigned *Features) {
1227 auto setFeature = [&](
unsigned F) {
1228 Features[
F / 32] |= 1U << (
F % 32);
1231 if ((EDX >> 15) & 1)
1232 setFeature(X86::FEATURE_CMOV);
1233 if ((EDX >> 23) & 1)
1234 setFeature(X86::FEATURE_MMX);
1235 if ((EDX >> 25) & 1)
1236 setFeature(X86::FEATURE_SSE);
1237 if ((EDX >> 26) & 1)
1238 setFeature(X86::FEATURE_SSE2);
1241 setFeature(X86::FEATURE_SSE3);
1243 setFeature(X86::FEATURE_PCLMUL);
1245 setFeature(X86::FEATURE_SSSE3);
1246 if ((ECX >> 12) & 1)
1247 setFeature(X86::FEATURE_FMA);
1248 if ((ECX >> 19) & 1)
1249 setFeature(X86::FEATURE_SSE4_1);
1250 if ((ECX >> 20) & 1) {
1251 setFeature(X86::FEATURE_SSE4_2);
1252 setFeature(X86::FEATURE_CRC32);
1254 if ((ECX >> 23) & 1)
1255 setFeature(X86::FEATURE_POPCNT);
1256 if ((ECX >> 25) & 1)
1257 setFeature(X86::FEATURE_AES);
1259 if ((ECX >> 22) & 1)
1260 setFeature(X86::FEATURE_MOVBE);
1265 const unsigned AVXBits = (1 << 27) | (1 << 28);
1266 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1267 ((
EAX & 0x6) == 0x6);
1268#if defined(__APPLE__)
1272 bool HasAVX512Save =
true;
1275 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1279 setFeature(X86::FEATURE_AVX);
1282 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1284 if (HasLeaf7 && ((EBX >> 3) & 1))
1285 setFeature(X86::FEATURE_BMI);
1286 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1287 setFeature(X86::FEATURE_AVX2);
1288 if (HasLeaf7 && ((EBX >> 8) & 1))
1289 setFeature(X86::FEATURE_BMI2);
1290 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1291 setFeature(X86::FEATURE_AVX512F);
1292 setFeature(X86::FEATURE_EVEX512);
1294 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1295 setFeature(X86::FEATURE_AVX512DQ);
1296 if (HasLeaf7 && ((EBX >> 19) & 1))
1297 setFeature(X86::FEATURE_ADX);
1298 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1299 setFeature(X86::FEATURE_AVX512IFMA);
1300 if (HasLeaf7 && ((EBX >> 23) & 1))
1301 setFeature(X86::FEATURE_CLFLUSHOPT);
1302 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1303 setFeature(X86::FEATURE_AVX512PF);
1304 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1305 setFeature(X86::FEATURE_AVX512ER);
1306 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1307 setFeature(X86::FEATURE_AVX512CD);
1308 if (HasLeaf7 && ((EBX >> 29) & 1))
1309 setFeature(X86::FEATURE_SHA);
1310 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1311 setFeature(X86::FEATURE_AVX512BW);
1312 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1313 setFeature(X86::FEATURE_AVX512VL);
1315 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1316 setFeature(X86::FEATURE_AVX512VBMI);
1317 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1318 setFeature(X86::FEATURE_AVX512VBMI2);
1319 if (HasLeaf7 && ((ECX >> 8) & 1))
1320 setFeature(X86::FEATURE_GFNI);
1321 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1322 setFeature(X86::FEATURE_VPCLMULQDQ);
1323 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1324 setFeature(X86::FEATURE_AVX512VNNI);
1325 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1326 setFeature(X86::FEATURE_AVX512BITALG);
1327 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1328 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1330 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1331 setFeature(X86::FEATURE_AVX5124VNNIW);
1332 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1333 setFeature(X86::FEATURE_AVX5124FMAPS);
1334 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1335 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1339 bool HasLeaf7Subleaf1 =
1340 HasLeaf7 &&
EAX >= 1 &&
1341 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1342 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1343 setFeature(X86::FEATURE_AVX512BF16);
1345 unsigned MaxExtLevel;
1346 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1348 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1349 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1350 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1351 setFeature(X86::FEATURE_SSE4_A);
1352 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1353 setFeature(X86::FEATURE_XOP);
1354 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1355 setFeature(X86::FEATURE_FMA4);
1357 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1358 setFeature(X86::FEATURE_64BIT);
1362 unsigned MaxLeaf = 0;
1364 if (Vendor == VendorSignatures::UNKNOWN)
1368 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1370 unsigned Family = 0,
Model = 0;
1372 detectX86FamilyModel(EAX, &Family, &Model);
1373 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1378 unsigned Subtype = 0;
1382 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1383 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1385 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1386 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1396#elif defined(__APPLE__) && defined(__powerpc__)
1398 host_basic_info_data_t hostInfo;
1399 mach_msg_type_number_t infoCount;
1401 infoCount = HOST_BASIC_INFO_COUNT;
1402 mach_port_t hostPort = mach_host_self();
1403 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1405 mach_port_deallocate(mach_task_self(), hostPort);
1407 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1410 switch (hostInfo.cpu_subtype) {
1440#elif defined(__linux__) && defined(__powerpc__)
1444 return detail::getHostCPUNameForPowerPC(
Content);
1446#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1450 return detail::getHostCPUNameForARM(
Content);
1452#elif defined(__linux__) && defined(__s390x__)
1456 return detail::getHostCPUNameForS390x(
Content);
1458#elif defined(__MVS__)
1463 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1466 int ReadValue = *StartToCVTOffset;
1468 ReadValue = (ReadValue & 0x7FFFFFFF);
1469 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1474 Id = decodePackedBCD<uint16_t>(Id,
false);
1478 bool HaveVectorSupport = CVT[244] & 0x80;
1479 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1481#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1482#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1483#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1484#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1485#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1486#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1487#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1488#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1489#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1490#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1491#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1492#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1496 size_t Length =
sizeof(Family);
1497 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1500 case CPUFAMILY_ARM_SWIFT:
1502 case CPUFAMILY_ARM_CYCLONE:
1504 case CPUFAMILY_ARM_TYPHOON:
1506 case CPUFAMILY_ARM_TWISTER:
1508 case CPUFAMILY_ARM_HURRICANE:
1510 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1512 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1514 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1516 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1518 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1520 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1529 switch (_system_configuration.implementation) {
1531 if (_system_configuration.version == PV_4_3)
1535 if (_system_configuration.version == PV_5)
1539 if (_system_configuration.version == PV_6_Compat)
1559#elif defined(__loongarch__)
1563 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1565 switch (processor_id & 0xf000) {
1574#elif defined(__riscv)
1576#if defined(__linux__)
1579 return detail::getHostCPUNameForRISCV(
Content);
1581#if __riscv_xlen == 64
1582 return "generic-rv64";
1583#elif __riscv_xlen == 32
1584 return "generic-rv32";
1586#error "Unhandled value of __riscv_xlen"
1590#elif defined(__sparc__)
1591#if defined(__linux__)
1594 ProcCpuinfoContent.
split(Lines,
"\n");
1598 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I) {
1600 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1632#if defined(__linux__)
1635 return detail::getHostCPUNameForSPARC(
Content);
1636#elif defined(__sun__) && defined(__svr4__)
1640 kstat_named_t *brand = NULL;
1644 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1645 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1646 ksp->ks_type == KSTAT_TYPE_NAMED)
1648 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1649 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1650 buf = KSTAT_NAMED_STR_PTR(brand);
1655 .
Case(
"TMS390S10",
"supersparc")
1656 .
Case(
"TMS390Z50",
"supersparc")
1659 .
Case(
"MB86904",
"supersparc")
1660 .
Case(
"MB86907",
"supersparc")
1661 .
Case(
"RT623",
"hypersparc")
1662 .
Case(
"RT625",
"hypersparc")
1663 .
Case(
"RT626",
"hypersparc")
1664 .
Case(
"UltraSPARC-I",
"ultrasparc")
1665 .
Case(
"UltraSPARC-II",
"ultrasparc")
1666 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1667 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1668 .
Case(
"SPARC64-III",
"ultrasparc")
1669 .
Case(
"SPARC64-IV",
"ultrasparc")
1670 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1671 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1672 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1673 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1674 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1675 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1676 .
Case(
"SPARC64-V",
"ultrasparc3")
1677 .
Case(
"SPARC64-VI",
"ultrasparc3")
1678 .
Case(
"SPARC64-VII",
"ultrasparc3")
1679 .
Case(
"UltraSPARC-T1",
"niagara")
1680 .
Case(
"UltraSPARC-T2",
"niagara2")
1681 .
Case(
"UltraSPARC-T2",
"niagara2")
1682 .
Case(
"UltraSPARC-T2+",
"niagara2")
1683 .
Case(
"SPARC-T3",
"niagara3")
1684 .
Case(
"SPARC-T4",
"niagara4")
1685 .
Case(
"SPARC-T5",
"niagara4")
1687 .
Case(
"SPARC-M7",
"niagara4" )
1688 .
Case(
"SPARC-S7",
"niagara4" )
1689 .
Case(
"SPARC-M8",
"niagara4" )
1712#if defined(__i386__) || defined(_M_IX86) || \
1713 defined(__x86_64__) || defined(_M_X64)
1718 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1721 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1723 Features[
"cx8"] = (
EDX >> 8) & 1;
1724 Features[
"cmov"] = (
EDX >> 15) & 1;
1725 Features[
"mmx"] = (
EDX >> 23) & 1;
1726 Features[
"fxsr"] = (
EDX >> 24) & 1;
1727 Features[
"sse"] = (
EDX >> 25) & 1;
1728 Features[
"sse2"] = (
EDX >> 26) & 1;
1730 Features[
"sse3"] = (
ECX >> 0) & 1;
1731 Features[
"pclmul"] = (
ECX >> 1) & 1;
1732 Features[
"ssse3"] = (
ECX >> 9) & 1;
1733 Features[
"cx16"] = (
ECX >> 13) & 1;
1734 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1735 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1736 Features[
"crc32"] = Features[
"sse4.2"];
1737 Features[
"movbe"] = (
ECX >> 22) & 1;
1738 Features[
"popcnt"] = (
ECX >> 23) & 1;
1739 Features[
"aes"] = (
ECX >> 25) & 1;
1740 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1745 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1746 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1747#if defined(__APPLE__)
1751 bool HasAVX512Save =
true;
1754 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1757 const unsigned AMXBits = (1 << 17) | (1 << 18);
1758 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1760 Features[
"avx"] = HasAVXSave;
1761 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1763 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1764 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1766 unsigned MaxExtLevel;
1767 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1769 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1770 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1771 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1772 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1773 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1774 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1775 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1776 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1777 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1778 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1779 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1781 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1785 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1786 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1787 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1788 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1789 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1792 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1794 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1795 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1796 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1798 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1799 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1800 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1801 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1803 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1804 Features[
"evex512"] = Features[
"avx512f"];
1805 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1806 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1807 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1808 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1809 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1810 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1811 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1812 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1813 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1814 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1815 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1816 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1818 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1819 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1820 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1821 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1822 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1823 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1824 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1825 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1826 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1827 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1828 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1829 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1830 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1831 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1832 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1833 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1834 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1835 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1837 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1838 Features[
"avx512vp2intersect"] =
1839 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1840 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1841 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1852 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1853 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1854 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1855 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1856 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1859 bool HasLeaf7Subleaf1 =
1860 HasLeaf7 &&
EAX >= 1 &&
1861 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1862 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1863 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1864 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1865 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1866 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1867 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1868 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1869 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1870 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1871 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1872 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1873 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1874 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1875 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1876 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1877 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1878 Features[
"avx10.1-256"] = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1879 bool HasAPXF = HasLeaf7Subleaf1 && ((
EDX >> 21) & 1);
1880 Features[
"egpr"] = HasAPXF;
1881 Features[
"push2pop2"] = HasAPXF;
1882 Features[
"ppx"] = HasAPXF;
1883 Features[
"ndd"] = HasAPXF;
1884 Features[
"ccmp"] = HasAPXF;
1885 Features[
"cf"] = HasAPXF;
1887 bool HasLeafD = MaxLevel >= 0xd &&
1888 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1891 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1892 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1893 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1895 bool HasLeaf14 = MaxLevel >= 0x14 &&
1896 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1898 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1901 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1902 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1905 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1906 Features[
"avx10.1-512"] =
1907 Features[
"avx10.1-256"] && HasLeaf24 && ((
EBX >> 18) & 1);
1911#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1918 P->getBuffer().split(Lines,
"\n");
1923 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I)
1925 Lines[
I].split(CPUFeatures,
' ');
1929#if defined(__aarch64__)
1931 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1937#if defined(__aarch64__)
1938 .
Case(
"asimd",
"neon")
1939 .
Case(
"fp",
"fp-armv8")
1940 .
Case(
"crc32",
"crc")
1941 .
Case(
"atomics",
"lse")
1943 .
Case(
"sve2",
"sve2")
1945 .
Case(
"half",
"fp16")
1946 .
Case(
"neon",
"neon")
1947 .
Case(
"vfpv3",
"vfp3")
1948 .
Case(
"vfpv3d16",
"vfp3d16")
1949 .
Case(
"vfpv4",
"vfp4")
1950 .
Case(
"idiva",
"hwdiv-arm")
1951 .
Case(
"idivt",
"hwdiv")
1955#if defined(__aarch64__)
1958 if (CPUFeatures[
I] ==
"aes")
1960 else if (CPUFeatures[
I] ==
"pmull")
1961 crypto |= CAP_PMULL;
1962 else if (CPUFeatures[
I] ==
"sha1")
1964 else if (CPUFeatures[
I] ==
"sha2")
1968 if (LLVMFeatureStr !=
"")
1969 Features[LLVMFeatureStr] =
true;
1972#if defined(__aarch64__)
1974 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1975 Features[
"crypto"] =
true;
1980#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1982 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1983 Features[
"neon"] =
true;
1984 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1985 Features[
"crc"] =
true;
1986 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1987 Features[
"crypto"] =
true;
1991#elif defined(__linux__) && defined(__loongarch__)
1992#include <sys/auxv.h>
1994 unsigned long hwcap = getauxval(AT_HWCAP);
1995 bool HasFPU = hwcap & (1UL << 3);
1997 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
1999 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
2000 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
2002 Features[
"lsx"] = hwcap & (1UL << 4);
2003 Features[
"lasx"] = hwcap & (1UL << 5);
2004 Features[
"lvz"] = hwcap & (1UL << 9);
2017 T.setArchName(
"arm");
2018#elif defined(__arm64e__)
2020 T.setArchName(
"arm64e");
2021#elif defined(__aarch64__)
2023 T.setArchName(
"arm64");
2024#elif defined(__x86_64h__)
2026 T.setArchName(
"x86_64h");
2027#elif defined(__x86_64__)
2029 T.setArchName(
"x86_64");
2030#elif defined(__i386__)
2032 T.setArchName(
"i386");
2033#elif defined(__powerpc__)
2035 T.setArchName(
"powerpc");
2037# error "Unimplemented host arch fixup"
2044 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2050 PT = withHostArch(PT);
2062#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2064 if (CPU ==
"generic")
2067 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.