30#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \
31 "LoongArch Pre-RA pseudo instruction expansion pass"
32#define LOONGARCH_EXPAND_PSEUDO_NAME \
33 "LoongArch pseudo instruction expansion pass"
63 unsigned FlagsHi,
unsigned SecondOpcode,
88char LoongArchPreRAExpandPseudo::ID = 0;
90bool LoongArchPreRAExpandPseudo::runOnMachineFunction(
MachineFunction &MF) {
112bool LoongArchPreRAExpandPseudo::expandMI(
115 switch (
MBBI->getOpcode()) {
116 case LoongArch::PseudoLA_PCREL:
117 return expandLoadAddressPcrel(
MBB,
MBBI, NextMBBI);
118 case LoongArch::PseudoLA_GOT:
119 return expandLoadAddressGot(
MBB,
MBBI, NextMBBI);
120 case LoongArch::PseudoLA_TLS_LE:
121 return expandLoadAddressTLSLE(
MBB,
MBBI, NextMBBI);
122 case LoongArch::PseudoLA_TLS_IE:
123 return expandLoadAddressTLSIE(
MBB,
MBBI, NextMBBI);
124 case LoongArch::PseudoLA_TLS_LD:
125 return expandLoadAddressTLSLD(
MBB,
MBBI, NextMBBI);
126 case LoongArch::PseudoLA_TLS_GD:
127 return expandLoadAddressTLSGD(
MBB,
MBBI, NextMBBI);
128 case LoongArch::PseudoLA_TLS_DESC_PC:
129 return expandLoadAddressTLSDesc(
MBB,
MBBI, NextMBBI);
134bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
137 unsigned SecondOpcode,
unsigned FlagsLo) {
155 if (
MI.hasOneMemOperand())
158 MI.eraseFromParent();
162bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
170 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
175bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
183 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
188bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
232 MI.eraseFromParent();
236bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
244 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
249bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
257 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
262bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
270 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
275bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
289 unsigned ADD = STI.is64Bit() ? LoongArch::ADD_D : LoongArch::ADD_W;
290 unsigned ADDI = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
291 unsigned LD = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
317 MI.eraseFromParent();
345 unsigned LastOpcode,
unsigned IdentifyingMO);
349 unsigned LastOpcode,
unsigned IdentifyingMO,
351 bool EraseFromParent);
376char LoongArchExpandPseudo::ID = 0;
405 switch (
MBBI->getOpcode()) {
406 case LoongArch::PseudoCopyCFR:
407 return expandCopyCFR(
MBB,
MBBI, NextMBBI);
408 case LoongArch::PseudoLA_PCREL_LARGE:
409 return expandLoadAddressPcrelLarge(
MBB,
MBBI, NextMBBI);
410 case LoongArch::PseudoLA_GOT_LARGE:
411 return expandLoadAddressGotLarge(
MBB,
MBBI, NextMBBI);
412 case LoongArch::PseudoLA_TLS_IE_LARGE:
413 return expandLoadAddressTLSIELarge(
MBB,
MBBI, NextMBBI);
414 case LoongArch::PseudoLA_TLS_LD_LARGE:
415 return expandLoadAddressTLSLDLarge(
MBB,
MBBI, NextMBBI);
416 case LoongArch::PseudoLA_TLS_GD_LARGE:
417 return expandLoadAddressTLSGDLarge(
MBB,
MBBI, NextMBBI);
418 case LoongArch::PseudoLA_TLS_DESC_PC_LARGE:
419 return expandLoadAddressTLSDescPcLarge(
MBB,
MBBI, NextMBBI);
420 case LoongArch::PseudoCALL:
421 case LoongArch::PseudoCALL_MEDIUM:
422 case LoongArch::PseudoCALL_LARGE:
423 return expandFunctionCALL(
MBB,
MBBI, NextMBBI,
false);
424 case LoongArch::PseudoTAIL:
425 case LoongArch::PseudoTAIL_MEDIUM:
426 case LoongArch::PseudoTAIL_LARGE:
427 return expandFunctionCALL(
MBB,
MBBI, NextMBBI,
true);
433bool LoongArchExpandPseudo::expandCopyCFR(
454 MF->
insert(++FalseBB->getIterator(), SinkBB);
465 BuildMI(FalseBB,
DL,
TII->get(LoongArch::SET_CFR_TRUE), DestReg);
467 FalseBB->addSuccessor(SinkBB);
469 SinkBB->splice(SinkBB->end(), &
MBB,
MI,
MBB.
end());
470 SinkBB->transferSuccessors(&
MBB);
476 MI.eraseFromParent();
486bool LoongArchExpandPseudo::expandLargeAddressLoad(
489 unsigned IdentifyingMO) {
491 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LastOpcode, IdentifyingMO,
492 MI.getOperand(2),
MI.getOperand(0).getReg(),
496bool LoongArchExpandPseudo::expandLargeAddressLoad(
500 bool EraseFromParent) {
509 unsigned MO0, MO1, MO2, MO3;
510 switch (IdentifyingMO) {
538 Register ScratchReg = LoongArch::R20;
541 "Large code model requires LA64");
556 const char *SymName = Symbol.getSymbolName();
557 Part0.addExternalSymbol(SymName, MO0);
558 Part1.addExternalSymbol(SymName, MO1);
559 Part2.addExternalSymbol(SymName, MO2);
560 Part3.addExternalSymbol(SymName, MO3);
562 Part0.addDisp(Symbol, 0, MO0);
563 Part1.addDisp(Symbol, 0, MO1);
564 Part2.addDisp(Symbol, 0, MO2);
565 Part3.addDisp(Symbol, 0, MO3);
569 MI.eraseFromParent();
574bool LoongArchExpandPseudo::expandLoadAddressPcrelLarge(
579 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LoongArch::ADD_D,
583bool LoongArchExpandPseudo::expandLoadAddressGotLarge(
588 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LoongArch::LDX_D,
592bool LoongArchExpandPseudo::expandLoadAddressTLSIELarge(
597 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LoongArch::LDX_D,
601bool LoongArchExpandPseudo::expandLoadAddressTLSLDLarge(
606 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LoongArch::ADD_D,
610bool LoongArchExpandPseudo::expandLoadAddressTLSGDLarge(
615 return expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LoongArch::ADD_D,
619bool LoongArchExpandPseudo::expandLoadAddressTLSDescPcLarge(
637 Register ScratchReg = LoongArch::R20;
640 "Large code model requires LA64");
666 MI.eraseFromParent();
671bool LoongArchExpandPseudo::expandFunctionCALL(
690 Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
702 IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
703 Register ScratchReg = IsTailCall ? LoongArch::R20 : LoongArch::R1;
721 IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
722 Register AddrReg = IsTailCall ? LoongArch::R19 : LoongArch::R1;
724 bool UseGOT = Func.isGlobal() && !Func.getGlobal()->isDSOLocal();
726 unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
727 expandLargeAddressLoad(
MBB,
MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
735 CALL.copyImplicitOps(
MI);
738 CALL.setMIFlags(
MI.getFlags());
740 MI.eraseFromParent();
755 return new LoongArchPreRAExpandPseudo();
758 return new LoongArchExpandPseudo();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static Expected< BitVector > expand(StringRef S, StringRef Original)
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME
#define LOONGARCH_EXPAND_PSEUDO_NAME
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
LLVM Basic Block Representation.
FunctionPass class - This class is used to implement most global optimizations.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
MachineOperand class - Representation of each machine instruction operand.
@ MO_ExternalSymbol
Name of external global symbol.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
CodeModel::Model getCodeModel() const
Returns the code model.
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &)
void initializeLoongArchExpandPseudoPass(PassRegistry &)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FunctionPass * createLoongArchPreRAExpandPseudoPass()
FunctionPass * createLoongArchExpandPseudoPass()
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().