54 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
55 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
57 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
58 "Expected inlined-at fields to agree");
61 false, Reg, Variable, Expr));
67 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
68 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
70 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
71 "Expected inlined-at fields to agree");
74 true, Reg, Variable, Expr));
80 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
81 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
83 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
84 "Expected inlined-at fields to agree");
88 .addMetadata(Variable)
95 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
96 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
98 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
99 "Expected inlined-at fields to agree");
102 auto *NumericConstant = [&] () ->
const Constant* {
103 if (
const auto *CE = dyn_cast<ConstantExpr>(&
C))
104 if (CE->getOpcode() == Instruction::IntToPtr)
105 return CE->getOperand(0);
109 if (
auto *CI = dyn_cast<ConstantInt>(NumericConstant)) {
110 if (CI->getBitWidth() > 64)
113 MIB.addImm(CI->getZExtValue());
114 }
else if (
auto *CFP = dyn_cast<ConstantFP>(NumericConstant)) {
116 }
else if (isa<ConstantPointerNull>(NumericConstant)) {
123 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
128 assert(isa<DILabel>(Label) &&
"not a label");
129 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.
DL) &&
130 "Expected inlined-at fields to agree");
131 auto MIB =
buildInstr(TargetOpcode::DBG_LABEL);
133 return MIB.addMetadata(Label);
140 auto MIB =
buildInstr(TargetOpcode::G_DYN_STACKALLOC);
142 Size.addSrcToMIB(MIB);
143 MIB.addImm(Alignment.
value());
150 auto MIB =
buildInstr(TargetOpcode::G_FRAME_INDEX);
152 MIB.addFrameIndex(
Idx);
161 "address space mismatch");
163 auto MIB =
buildInstr(TargetOpcode::G_GLOBAL_VALUE);
165 MIB.addGlobalAddress(GV);
172 auto MIB =
buildInstr(TargetOpcode::G_CONSTANT_POOL);
174 MIB.addConstantPoolIndex(
Idx);
180 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
181 .addJumpTableIndex(JTI);
186 assert((Res == Op0) &&
"type mismatch");
192 assert((Res == Op0 && Res == Op1) &&
"type mismatch");
198 assert((Res == Op0) &&
"type mismatch");
203 const SrcOp &Op1, std::optional<unsigned> Flags) {
208 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags);
211std::optional<MachineInstrBuilder>
214 assert(Res == 0 &&
"Res is a result argument");
233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
248 "Different vector element types");
250 "Op0 has more elements");
253 for (
auto Op : Unmerge.getInstr()->defs())
257 "Op0 has more size");
263 for (
unsigned i = 0; i < NumberOfPadElts; ++i)
278 "Different vector element types");
281 "Op0 has fewer elements");
305 "Table reg must be a pointer");
322 "creating constant with the wrong size");
325 "unexpected scalable vector in buildConstant");
328 auto Const =
buildInstr(TargetOpcode::G_CONSTANT)
334 auto Const =
buildInstr(TargetOpcode::G_CONSTANT);
345 ConstantInt *CI = ConstantInt::get(IntN, Val,
true);
356 "creating fconstant with the wrong size");
361 "unexpected scalable vector in buildFConstant");
364 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT)
371 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT);
374 Const.addFPImm(&Val);
396 auto *CFP = ConstantFP::get(Ctx, Val);
404 auto MIB =
buildInstr(TargetOpcode::G_BRCOND);
433 Addr.addSrcToMIB(MIB);
434 MIB.addMemOperand(&MMO);
446 return buildLoad(Dst, BasePtr, *OffsetMMO);
463 Addr.addSrcToMIB(MIB);
464 MIB.addMemOperand(&MMO);
499 switch (TLI->getBooleanContents(IsVec, IsFP)) {
501 return TargetOpcode::G_SEXT;
503 return TargetOpcode::G_ZEXT;
505 return TargetOpcode::G_ANYEXT;
521 switch (TLI->getBooleanContents(IsVector, IsFP)) {
536 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
537 TargetOpcode::G_SEXT == ExtOpc) &&
538 "Expecting Extending Opc");
544 unsigned Opcode = TargetOpcode::COPY;
546 Op.getLLTTy(*
getMRI()).getSizeInBits())
549 Op.getLLTTy(*
getMRI()).getSizeInBits())
550 Opcode = TargetOpcode::G_TRUNC;
590 Opcode = TargetOpcode::G_PTRTOINT;
592 Opcode = TargetOpcode::G_INTTOPTR;
595 Opcode = TargetOpcode::G_BITCAST;
611 "extracting off end of register");
615 assert(
Index == 0 &&
"insertion past the end of a register");
619 auto Extract =
buildInstr(TargetOpcode::G_EXTRACT);
620 Dst.addDefToMIB(*
getMRI(), Extract);
621 Src.addSrcToMIB(Extract);
622 Extract.addImm(
Index);
627 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
637 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
648 return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
653 std::initializer_list<SrcOp> Ops) {
655 return buildInstr(getOpcodeForMerge(Res, Ops), Res, Ops);
658unsigned MachineIRBuilder::getOpcodeForMerge(
const DstOp &
DstOp,
661 if (SrcOps[0].getLLTTy(*
getMRI()).isVector())
662 return TargetOpcode::G_CONCAT_VECTORS;
663 return TargetOpcode::G_BUILD_VECTOR;
666 return TargetOpcode::G_MERGE_VALUES;
676 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
683 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
693 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
702 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
711 for (
const auto &
Op : Ops)
713 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
719 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
729 if (TmpVec[0].getLLTTy(*
getMRI()).getSizeInBits() ==
731 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
732 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
739 "Expected Src to match Dst elt ty");
750 "Expected Src to match Dst elt ty");
751 return buildInstr(TargetOpcode::G_SPLAT_VECTOR, Res, Src);
769 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
770 .addShuffleMask(MaskAlloc);
779 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
788 "insertion past the end of a register");
791 Op.getLLTTy(*
getMRI()).getSizeInBits()) {
809 auto VScale =
buildInstr(TargetOpcode::G_VSCALE);
812 VScale.addCImm(&MinElts);
817 const APInt &MinElts) {
824 if (HasSideEffects && IsConvergent)
825 return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS;
827 return TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
829 return TargetOpcode::G_INTRINSIC_CONVERGENT;
830 return TargetOpcode::G_INTRINSIC;
836 bool HasSideEffects,
bool isConvergent) {
838 for (
unsigned ResultReg : ResultRegs)
839 MIB.addDef(ResultReg);
840 MIB.addIntrinsicID(
ID);
848 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
849 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);
860 MIB.addIntrinsicID(
ID);
867 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
868 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);
879 std::optional<unsigned> Flags) {
880 return buildInstr(TargetOpcode::G_FPTRUNC, Res,
Op, Flags);
887 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
894 std::optional<unsigned> Flags) {
896 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
902 std::optional<unsigned> Flags) {
904 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
911 return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,
918 return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,
925 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt,
Idx});
931 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val,
Idx});
948 assert(OldValResTy == CmpValTy &&
"type mismatch");
949 assert(OldValResTy == NewValTy &&
"type mismatch");
952 auto MIB =
buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS);
955 Addr.addSrcToMIB(MIB);
958 MIB.addMemOperand(&MMO);
975 assert(OldValResTy == CmpValTy &&
"type mismatch");
976 assert(OldValResTy == NewValTy &&
"type mismatch");
979 auto MIB =
buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG);
981 Addr.addSrcToMIB(MIB);
984 MIB.addMemOperand(&MMO);
989 unsigned Opcode,
const DstOp &OldValRes,
1000 assert(OldValResTy == ValTy &&
"type mismatch");
1006 Addr.addSrcToMIB(MIB);
1008 MIB.addMemOperand(&MMO);
1121 auto MIB =
buildInstr(TargetOpcode::G_PREFETCH);
1122 Addr.addSrcToMIB(MIB);
1123 MIB.addImm(RW).addImm(Locality).addImm(CacheType);
1124 MIB.addMemOperand(&MMO);
1141 assert(SrcTy.
isVector() &&
"mismatched cast between vector and non-vector");
1143 "different number of elements in a trunc/ext");
1149 "invalid narrowing extend");
1152 "invalid widening trunc");
1157 const LLT Op0Ty,
const LLT Op1Ty) {
1160 "invalid operand type");
1161 assert((ResTy == Op0Ty && ResTy == Op1Ty) &&
"type mismatch");
1175 std::optional<unsigned> Flags) {
1179 case TargetOpcode::G_SELECT: {
1180 assert(DstOps.
size() == 1 &&
"Invalid select");
1181 assert(SrcOps.
size() == 3 &&
"Invalid select");
1183 DstOps[0].getLLTTy(*
getMRI()), SrcOps[0].getLLTTy(*
getMRI()),
1184 SrcOps[1].getLLTTy(*
getMRI()), SrcOps[2].getLLTTy(*
getMRI()));
1187 case TargetOpcode::G_FNEG:
1188 case TargetOpcode::G_ABS:
1191 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1193 SrcOps[0].getLLTTy(*
getMRI()));
1195 case TargetOpcode::G_ADD:
1196 case TargetOpcode::G_AND:
1197 case TargetOpcode::G_MUL:
1198 case TargetOpcode::G_OR:
1199 case TargetOpcode::G_SUB:
1200 case TargetOpcode::G_XOR:
1201 case TargetOpcode::G_UDIV:
1202 case TargetOpcode::G_SDIV:
1203 case TargetOpcode::G_UREM:
1204 case TargetOpcode::G_SREM:
1205 case TargetOpcode::G_SMIN:
1206 case TargetOpcode::G_SMAX:
1207 case TargetOpcode::G_UMIN:
1208 case TargetOpcode::G_UMAX:
1209 case TargetOpcode::G_UADDSAT:
1210 case TargetOpcode::G_SADDSAT:
1211 case TargetOpcode::G_USUBSAT:
1212 case TargetOpcode::G_SSUBSAT: {
1215 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1217 SrcOps[0].getLLTTy(*
getMRI()),
1218 SrcOps[1].getLLTTy(*
getMRI()));
1221 case TargetOpcode::G_SHL:
1222 case TargetOpcode::G_ASHR:
1223 case TargetOpcode::G_LSHR:
1224 case TargetOpcode::G_USHLSAT:
1225 case TargetOpcode::G_SSHLSAT: {
1227 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1229 SrcOps[0].getLLTTy(*
getMRI()),
1230 SrcOps[1].getLLTTy(*
getMRI()));
1233 case TargetOpcode::G_SEXT:
1234 case TargetOpcode::G_ZEXT:
1235 case TargetOpcode::G_ANYEXT:
1237 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1239 SrcOps[0].getLLTTy(*
getMRI()),
true);
1241 case TargetOpcode::G_TRUNC:
1242 case TargetOpcode::G_FPTRUNC: {
1244 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1246 SrcOps[0].getLLTTy(*
getMRI()),
false);
1249 case TargetOpcode::G_BITCAST: {
1251 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1252 assert(DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1253 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
"invalid bitcast");
1256 case TargetOpcode::COPY:
1261 case TargetOpcode::G_FCMP:
1262 case TargetOpcode::G_ICMP: {
1263 assert(DstOps.
size() == 1 &&
"Invalid Dst Operands");
1264 assert(SrcOps.
size() == 3 &&
"Invalid Src Operands");
1268 "Expecting predicate");
1273 }() &&
"Invalid predicate");
1277 LLT Op0Ty = SrcOps[1].getLLTTy(*
getMRI());
1278 LLT DstTy = DstOps[0].getLLTTy(*
getMRI());
1284 }() &&
"Type Mismatch");
1287 case TargetOpcode::G_UNMERGE_VALUES: {
1288 assert(!DstOps.
empty() &&
"Invalid trivial sequence");
1289 assert(SrcOps.
size() == 1 &&
"Invalid src for Unmerge");
1293 DstOps[0].getLLTTy(*
getMRI());
1295 "type mismatch in output list");
1297 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1298 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1299 "input operands do not cover output register");
1302 case TargetOpcode::G_MERGE_VALUES: {
1303 assert(SrcOps.
size() >= 2 &&
"invalid trivial sequence");
1308 SrcOps[0].getLLTTy(*
getMRI());
1310 "type mismatch in input list");
1312 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1313 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1314 "input operands do not cover output register");
1316 "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");
1319 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1320 assert(DstOps.
size() == 1 &&
"Invalid Dst size");
1321 assert(SrcOps.
size() == 2 &&
"Invalid Src size");
1322 assert(SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1324 DstOps[0].getLLTTy(*
getMRI()).isPointer()) &&
1325 "Invalid operand type");
1326 assert(SrcOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand type");
1327 assert(SrcOps[0].getLLTTy(*
getMRI()).getElementType() ==
1328 DstOps[0].getLLTTy(*
getMRI()) &&
1332 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1333 assert(DstOps.
size() == 1 &&
"Invalid dst size");
1334 assert(SrcOps.
size() == 3 &&
"Invalid src size");
1336 SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1337 assert(DstOps[0].getLLTTy(*
getMRI()).getElementType() ==
1338 SrcOps[1].getLLTTy(*
getMRI()) &&
1340 assert(SrcOps[2].getLLTTy(*
getMRI()).isScalar() &&
"Invalid index");
1341 assert(DstOps[0].getLLTTy(*
getMRI()).getElementCount() ==
1342 SrcOps[0].getLLTTy(*
getMRI()).getElementCount() &&
1346 case TargetOpcode::G_BUILD_VECTOR: {
1348 "Must have at least 2 operands");
1349 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1351 "Res type must be a vector");
1355 SrcOps[0].getLLTTy(*
getMRI());
1357 "type mismatch in input list");
1359 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1360 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1361 "input scalars do not exactly cover the output vector register");
1364 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1366 "Must have at least 2 operands");
1367 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1369 "Res type must be a vector");
1373 SrcOps[0].getLLTTy(*
getMRI());
1375 "type mismatch in input list");
1378 case TargetOpcode::G_CONCAT_VECTORS: {
1379 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1381 "Must have at least 2 operands");
1384 return (
Op.getLLTTy(*
getMRI()).isVector() &&
1386 SrcOps[0].getLLTTy(*
getMRI()));
1388 "type mismatch in input list");
1390 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1391 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1392 "input vectors do not exactly cover the output vector register");
1395 case TargetOpcode::G_UADDE: {
1396 assert(DstOps.
size() == 2 &&
"Invalid no of dst operands");
1397 assert(SrcOps.
size() == 3 &&
"Invalid no of src operands");
1398 assert(DstOps[0].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1400 (DstOps[0].getLLTTy(*
getMRI()) == SrcOps[1].getLLTTy(*
getMRI())) &&
1402 assert(DstOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1410 for (
const DstOp &
Op : DstOps)
1412 for (
const SrcOp &
Op : SrcOps)
1413 Op.addSrcToMIB(MIB);
1415 MIB->setFlags(*Flags);
Function Alias Analysis Results
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static Function * getFunction(Constant *C)
static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent)
This file declares the MachineIRBuilder class.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
This file describes how to lower LLVM code to machine code.
const fltSemantics & getSemantics() const
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
The address of a basic block.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isFPPredicate() const
bool isIntPredicate() const
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
PointerType * getType() const
Global values are always pointers.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBundleIterator< MachineInstr > iterator
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)
Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)
Build and insert Res = G_VSCALE MinElts.
MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MDNode * getMMRAMetadata()
Get the current instruction's MMRA metadata.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)
Build and insert G_PREFETCH Addr, RW, Locality, CacheType.
MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)
Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)
Build and insert Res = G_SPLAT_VECTOR Val.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
A description of a memory reference used in the backend.
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Flags
Flags values. These may be or'd together.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Wrapper class representing virtual and physical registers.
void reserve(size_type N)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
void addSrcToMIB(MachineInstrBuilder &MIB) const
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
LLVM Value Representation.
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
DWARFExpression::Operation Op
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
MachineFunction * MF
MachineFunction under construction.
MDNode * MMRA
MMRA Metadata to be set on any instruction we create.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...