LLVM  10.0.0svn
RegisterClassInfo.cpp
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1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee-saved vs. caller-saved and
11 // reserved registers depend on calling conventions and other dynamic
12 // information, so some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Debug.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "regalloc"
36 
37 static cl::opt<unsigned>
38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
39  cl::desc("Limit all regclasses to N registers"));
40 
42 
44  bool Update = false;
45  MF = &mf;
46 
47  // Allocate new array the first time we see a new target.
48  if (MF->getSubtarget().getRegisterInfo() != TRI) {
49  TRI = MF->getSubtarget().getRegisterInfo();
50  RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
51  Update = true;
52  }
53 
54  // Does this MF have different CSRs?
55  assert(TRI && "no register info set");
56 
57  // Get the callee saved registers.
58  const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
59  if (Update || CSR != CalleeSavedRegs) {
60  // Build a CSRAlias map. Every CSR alias saves the last
61  // overlapping CSR.
62  CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
63  for (const MCPhysReg *I = CSR; *I; ++I)
64  for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
65  CalleeSavedAliases[*AI] = *I;
66 
67  Update = true;
68  }
69  CalleeSavedRegs = CSR;
70 
71  // Different reserved registers?
72  const BitVector &RR = MF->getRegInfo().getReservedRegs();
73  if (Reserved.size() != RR.size() || RR != Reserved) {
74  Update = true;
75  Reserved = RR;
76  }
77 
78  // Invalidate cached information from previous function.
79  if (Update) {
80  unsigned NumPSets = TRI->getNumRegPressureSets();
81  PSetLimits.reset(new unsigned[NumPSets]);
82  std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
83  ++Tag;
84  }
85 }
86 
87 /// compute - Compute the preferred allocation order for RC with reserved
88 /// registers filtered out. Volatile registers come first followed by CSR
89 /// aliases ordered according to the CSR order specified by the target.
90 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
91  assert(RC && "no register class given");
92  RCInfo &RCI = RegClass[RC->getID()];
93  auto &STI = MF->getSubtarget();
94 
95  // Raw register count, including all reserved regs.
96  unsigned NumRegs = RC->getNumRegs();
97 
98  if (!RCI.Order)
99  RCI.Order.reset(new MCPhysReg[NumRegs]);
100 
101  unsigned N = 0;
103  unsigned MinCost = 0xff;
104  unsigned LastCost = ~0u;
105  unsigned LastCostChange = 0;
106 
107  // FIXME: Once targets reserve registers instead of removing them from the
108  // allocation order, we can simply use begin/end here.
109  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
110  for (unsigned i = 0; i != RawOrder.size(); ++i) {
111  unsigned PhysReg = RawOrder[i];
112  // Remove reserved registers from the allocation order.
113  if (Reserved.test(PhysReg))
114  continue;
115  unsigned Cost = TRI->getCostPerUse(PhysReg);
116  MinCost = std::min(MinCost, Cost);
117 
118  if (CalleeSavedAliases[PhysReg] &&
119  !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
120  // PhysReg aliases a CSR, save it for later.
121  CSRAlias.push_back(PhysReg);
122  else {
123  if (Cost != LastCost)
124  LastCostChange = N;
125  RCI.Order[N++] = PhysReg;
126  LastCost = Cost;
127  }
128  }
129  RCI.NumRegs = N + CSRAlias.size();
130  assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
131 
132  // CSR aliases go after the volatile registers, preserve the target's order.
133  for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
134  unsigned PhysReg = CSRAlias[i];
135  unsigned Cost = TRI->getCostPerUse(PhysReg);
136  if (Cost != LastCost)
137  LastCostChange = N;
138  RCI.Order[N++] = PhysReg;
139  LastCost = Cost;
140  }
141 
142  // Register allocator stress test. Clip register class to N registers.
143  if (StressRA && RCI.NumRegs > StressRA)
144  RCI.NumRegs = StressRA;
145 
146  // Check if RC is a proper sub-class.
147  if (const TargetRegisterClass *Super =
148  TRI->getLargestLegalSuperClass(RC, *MF))
149  if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
150  RCI.ProperSubClass = true;
151 
152  RCI.MinCost = uint8_t(MinCost);
153  RCI.LastCostChange = LastCostChange;
154 
155  LLVM_DEBUG({
156  dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
157  for (unsigned I = 0; I != RCI.NumRegs; ++I)
158  dbgs() << ' ' << printReg(RCI.Order[I], TRI);
159  dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
160  });
161 
162  // RCI is now up-to-date.
163  RCI.Tag = Tag;
164 }
165 
166 /// This is not accurate because two overlapping register sets may have some
167 /// nonoverlapping reserved registers. However, computing the allocation order
168 /// for all register classes would be too expensive.
169 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
170  const TargetRegisterClass *RC = nullptr;
171  unsigned NumRCUnits = 0;
172  for (const TargetRegisterClass *C : TRI->regclasses()) {
173  const int *PSetID = TRI->getRegClassPressureSets(C);
174  for (; *PSetID != -1; ++PSetID) {
175  if ((unsigned)*PSetID == Idx)
176  break;
177  }
178  if (*PSetID == -1)
179  continue;
180 
181  // Found a register class that counts against this pressure set.
182  // For efficiency, only compute the set order for the largest set.
183  unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
184  if (!RC || NUnits > NumRCUnits) {
185  RC = C;
186  NumRCUnits = NUnits;
187  }
188  }
189  compute(RC);
190  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
191  return TRI->getRegPressureSetLimit(*MF, Idx) -
192  TRI->getRegClassWeight(RC).RegWeight * NReserved;
193 }
uint64_t CallInst * C
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getNumRegs() const
Return the number of registers in this class.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
bool test(unsigned Idx) const
Definition: BitVector.h:501
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
iterator_range< regclass_iterator > regclasses() const
unsigned getID() const
Return the register class ID number.
unsigned getNumRegClasses() const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
size_t size() const
Definition: SmallVector.h:52
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:169
static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
void resize(size_type N)
Definition: SmallVector.h:344