LLVM  12.0.0git
llvm::CSEMIRBuilder Member List

This is the complete list of members for llvm::CSEMIRBuilder, including all inherited members.

buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilderinline
buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildAnyExt(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildBitcast(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilderinline
buildBlockAddress(Register Res, const BlockAddress *BA)llvm::MachineIRBuilder
buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)llvm::MachineIRBuilder
buildBr(MachineBasicBlock &Dest)llvm::MachineIRBuilder
buildBrCond(Register Tst, MachineBasicBlock &Dest)llvm::MachineIRBuilder
buildBrIndirect(Register Tgt)llvm::MachineIRBuilder
buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)llvm::MachineIRBuilder
buildBSwap(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)llvm::MachineIRBuilder
buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)llvm::MachineIRBuilder
buildCast(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilder
buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)llvm::MachineIRBuilder
buildConstant(const DstOp &Res, const ConstantInt &Val) overridellvm::CSEMIRBuildervirtual
llvm::MachineIRBuilder::buildConstant(const DstOp &Res, int64_t Val)llvm::MachineIRBuilder
llvm::MachineIRBuilder::buildConstant(const DstOp &Res, const APInt &Val)llvm::MachineIRBuilder
buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)llvm::MachineIRBuilder
buildCopy(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildCTLZ(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildCTPOP(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildCTTZ(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildDbgLabel(const MDNode *Label)llvm::MachineIRBuilder
buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)llvm::MachineIRBuilder
buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)llvm::MachineIRBuilder
buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)llvm::MachineIRBuilder
buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)llvm::MachineIRBuilder
buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)llvm::MachineIRBuilder
buildFConstant(const DstOp &Res, const ConstantFP &Val) overridellvm::CSEMIRBuildervirtual
llvm::MachineIRBuilder::buildFConstant(const DstOp &Res, double Val)llvm::MachineIRBuilder
llvm::MachineIRBuilder::buildFConstant(const DstOp &Res, const APFloat &Val)llvm::MachineIRBuilder
buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildFence(unsigned Ordering, unsigned Scope)llvm::MachineIRBuilder
buildFExp2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)llvm::MachineIRBuilder
buildFLog(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFLog2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)llvm::MachineIRBuilder
buildFrameIndex(const DstOp &Res, int Idx)llvm::MachineIRBuilder
buildFreeze(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilderinline
buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildGlobalValue(const DstOp &Res, const GlobalValue *GV)llvm::MachineIRBuilder
buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilder
buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)llvm::MachineIRBuilder
buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)llvm::MachineIRBuilder
buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)llvm::MachineIRBuilder
buildInstr(unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, Optional< unsigned > Flag=None) overridellvm::CSEMIRBuildervirtual
llvm::MachineIRBuilder::buildInstr(unsigned Opcode)llvm::MachineIRBuilderinline
buildInstrNoInsert(unsigned Opcode)llvm::MachineIRBuilder
buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)llvm::MachineIRBuilder
buildIntrinsic(Intrinsic::ID ID, ArrayRef< DstOp > Res, bool HasSideEffects)llvm::MachineIRBuilder
buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildIntToPtr(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilderinline
buildJumpTable(const LLT PtrTy, unsigned JTI)llvm::MachineIRBuilder
buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)llvm::MachineIRBuilder
buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)llvm::MachineIRBuilder
buildMerge(const DstOp &Res, ArrayRef< Register > Ops)llvm::MachineIRBuilder
buildMerge(const DstOp &Res, std::initializer_list< SrcOp > Ops)llvm::MachineIRBuilder
buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildNot(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilder
buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilderinline
buildPtrToInt(const DstOp &Dst, const SrcOp &Src)llvm::MachineIRBuilderinline
buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)llvm::MachineIRBuilderinline
buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilderinline
buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)llvm::MachineIRBuilder
buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)llvm::MachineIRBuilder
buildSExt(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)llvm::MachineIRBuilderinline
buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildSITOFP(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildSplatVector(const DstOp &Res, const SrcOp &Src)llvm::MachineIRBuilder
buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)llvm::MachineIRBuilderinline
buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilderinline
buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)llvm::MachineIRBuilder
buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildTrunc(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)llvm::MachineIRBuilderinline
buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilderinline
buildUITOFP(const DstOp &Dst, const SrcOp &Src0)llvm::MachineIRBuilderinline
buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)llvm::MachineIRBuilderinline
buildUndef(const DstOp &Res)llvm::MachineIRBuilder
buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)llvm::MachineIRBuilder
buildUnmerge(ArrayRef< Register > Res, const SrcOp &Op)llvm::MachineIRBuilder
buildUnmerge(LLT Res, const SrcOp &Op)llvm::MachineIRBuilder
buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)llvm::MachineIRBuilderinline
buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)llvm::MachineIRBuilderinline
buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)llvm::MachineIRBuilderinline
buildZExt(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)llvm::MachineIRBuilder
getBoolExtOp(bool IsVec, bool IsFP) constllvm::MachineIRBuilder
getCSEInfo()llvm::MachineIRBuilderinline
getCSEInfo() constllvm::MachineIRBuilderinline
getDataLayout() constllvm::MachineIRBuilderinline
getDebugLoc()llvm::MachineIRBuilderinline
getDL()llvm::MachineIRBuilderinline
getInsertPt()llvm::MachineIRBuilderinline
getMBB() constllvm::MachineIRBuilderinline
getMBB()llvm::MachineIRBuilderinline
getMF()llvm::MachineIRBuilderinline
getMF() constllvm::MachineIRBuilderinline
getMRI()llvm::MachineIRBuilderinline
getMRI() constllvm::MachineIRBuilderinline
getState()llvm::MachineIRBuilderinline
getTII()llvm::MachineIRBuilderinline
insertInstr(MachineInstrBuilder MIB)llvm::MachineIRBuilder
MachineIRBuilder()=defaultllvm::MachineIRBuilder
MachineIRBuilder(MachineFunction &MF)llvm::MachineIRBuilderinline
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)llvm::MachineIRBuilderinline
MachineIRBuilder(MachineInstr &MI)llvm::MachineIRBuilderinline
MachineIRBuilder(const MachineIRBuilderState &BState)llvm::MachineIRBuilderinline
materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)llvm::MachineIRBuilder
recordInsertion(MachineInstr *InsertedInstr) constllvm::MachineIRBuilderinlineprotected
setChangeObserver(GISelChangeObserver &Observer)llvm::MachineIRBuilderinline
setCSEInfo(GISelCSEInfo *Info)llvm::MachineIRBuilderinline
setDebugLoc(const DebugLoc &DL)llvm::MachineIRBuilderinline
setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)llvm::MachineIRBuilderinline
setInstr(MachineInstr &MI)llvm::MachineIRBuilderinline
setInstrAndDebugLoc(MachineInstr &MI)llvm::MachineIRBuilderinline
setMBB(MachineBasicBlock &MBB)llvm::MachineIRBuilderinline
setMF(MachineFunction &MF)llvm::MachineIRBuilder
stopObservingChanges()llvm::MachineIRBuilderinline
validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)llvm::MachineIRBuilderprotected
validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)llvm::MachineIRBuilderprotected
validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)llvm::MachineIRBuilderprotected
validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)llvm::MachineIRBuilderprotected
~MachineIRBuilder()=defaultllvm::MachineIRBuildervirtual