AMDGPU Instruction Syntax¶
An instruction has the following syntax:
The order of operands and modifiers is fixed. Most modifiers are optional and may be omitted.
VOPDX and VOPDY instructions must be concatenated with the :: operator to form a single VOPD instruction:
> :: <VOPDY instruction
v_dual_add_f32 v255, v255, v2 :: v_dual_fmaak_f32 v6, v2, v3, 1.0
Note that VOPDX and VOPDY instructions cannot be used as separate opcodes.
Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:
Most instructions which operate on packed data have a _pk suffix. Unless otherwise noted, these instructions operate on and produce packed data composed of two values. The type of values is indicated by type suffices.
For example, the following instruction sums up two pairs of f16 values and produces a pair of f16 values:
v_pk_add_f16 v1, v2, v3 // Each operand has f16x2 type
Instructions which operate with data have an implied type of data operands. This data type is specified as a suffix of instruction mnemonic.
There are instructions which have 2 type suffices: the first is the data type of the destination operand, the second is the data type of source data operand(s).
Note that data type specified by an instruction does not apply to other kinds of operands such as addresses, offsets and so on.
The following table enumerates the most frequently used type suffices.
_b512, _b256, _b128, _b64, _b32, _b16, _b8
_u64, _u32, _u16, _u8
_i64, _i32, _i16, _i8
_f64, _f32, _f16
_b16, _u16, _i16, _f16
Packed (b16x2, u16x2, etc).
Instructions which have no type suffices are assumed to operate with typeless data. The size of typeless data is specified by size suffices:
Implied data type
Required register size in dwords
2 for GFX8.0, 1 for GFX8.1 and GFX9+
3 for GFX8.0, 2 for GFX8.1 and GFX9+
4 for GFX8.0, 2 for GFX8.1 and GFX9+
There are exceptions to the rules described above. Operands which have a type different from the type specified by the opcode are tagged in the description.
Examples of instructions with different types of source and destination operands:
Examples of instructions with one data type:
Examples of instructions which operate with packed data:
v_pk_add_u16 v_pk_add_i16 v_pk_add_f16
Examples of typeless instructions which operate on b128 data:
Most VOP1, VOP2 and VOPC instructions have several variants: they may also be encoded in VOP3, DPP and SDWA formats.
The assembler selects an optimal encoding automatically based on instruction operands and modifiers, unless a specific encoding is explicitly requested. To force specific encoding, one can add a suffix to the opcode of the instruction:
VOP1, VOP2 and VOPC (32-bit) encoding
VOP3 (64-bit) encoding
VOP3 DPP encoding
This reference uses encoding suffices to specify which encoding is implied. When no suffix is specified, native instruction encoding is assumed.
The syntax of generic operands is described in this document.
For detailed information about operands, follow operand links in GPU-specific documents.
The syntax of modifiers is described in this document.
Information about modifiers supported for individual instructions may be found in GPU-specific documents.