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MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
105
106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return RegInfo->getRegClass(RC).getRegister(RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 MCRegister Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2);
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 MCRegister Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 MCRegister Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 MCRegister Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 MCRegister Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (RegNo > 31)
223 return MCDisassembler::Fail;
224
225 MCRegister Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
226 Inst.addOperand(MCOperand::createReg(Reg));
227 return MCDisassembler::Success;
228}
229
230static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address,
232 const MCDisassembler *Decoder) {
233 if (RegNo > 31)
234 return MCDisassembler::Fail;
235
236 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
237 Inst.addOperand(MCOperand::createReg(Reg));
238 return MCDisassembler::Success;
239}
240
241static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
242 uint64_t Address,
243 const MCDisassembler *Decoder) {
244 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
245 Mips::S5, Mips::S6, Mips::S7, Mips::FP};
246 unsigned RegNum;
247
248 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
249
250 // Empty register lists are not allowed.
251 if (RegLst == 0)
252 return MCDisassembler::Fail;
253
254 RegNum = RegLst & 0xf;
255
256 // RegLst values 10-15, and 26-31 are reserved.
257 if (RegNum > 9)
258 return MCDisassembler::Fail;
259
260 for (unsigned i = 0; i < RegNum; i++)
261 Inst.addOperand(MCOperand::createReg(Regs[i]));
262
263 if (RegLst & 0x10)
264 Inst.addOperand(MCOperand::createReg(Mips::RA));
265
266 return MCDisassembler::Success;
267}
268
269static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
270 uint64_t Address,
271 const MCDisassembler *Decoder) {
272 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
273 unsigned RegLst;
274 switch (Inst.getOpcode()) {
275 default:
276 RegLst = fieldFromInstruction(Insn, 4, 2);
277 break;
278 case Mips::LWM16_MMR6:
279 case Mips::SWM16_MMR6:
280 RegLst = fieldFromInstruction(Insn, 8, 2);
281 break;
282 }
283 unsigned RegNum = RegLst & 0x3;
284
285 for (unsigned i = 0; i <= RegNum; i++)
286 Inst.addOperand(MCOperand::createReg(Regs[i]));
287
288 Inst.addOperand(MCOperand::createReg(Mips::RA));
289
290 return MCDisassembler::Success;
291}
292
293template <typename InsnType>
294static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
295 const MCDisassembler *Decoder) {
296 using DecodeFN =
297 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
298
299 // The size of the n field depends on the element size
300 // The register class also depends on this.
301 InsnType tmp = fieldFromInstruction(insn, 17, 5);
302 unsigned NSize = 0;
303 DecodeFN RegDecoder = nullptr;
304 if ((tmp & 0x18) == 0x00) { // INSVE_B
305 NSize = 4;
306 RegDecoder = DecodeMSA128BRegisterClass;
307 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
308 NSize = 3;
309 RegDecoder = DecodeMSA128HRegisterClass;
310 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
311 NSize = 2;
312 RegDecoder = DecodeMSA128WRegisterClass;
313 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
314 NSize = 1;
315 RegDecoder = DecodeMSA128DRegisterClass;
316 } else
317 llvm_unreachable("Invalid encoding");
318
319 assert(NSize != 0 && RegDecoder != nullptr);
320
321 // $wd
322 tmp = fieldFromInstruction(insn, 6, 5);
323 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
324 return MCDisassembler::Fail;
325 // $wd_in
326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
327 return MCDisassembler::Fail;
328 // $n
329 tmp = fieldFromInstruction(insn, 16, NSize);
330 MI.addOperand(MCOperand::createImm(tmp));
331 // $ws
332 tmp = fieldFromInstruction(insn, 11, 5);
333 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
334 return MCDisassembler::Fail;
335 // $n2
336 MI.addOperand(MCOperand::createImm(0));
337
338 return MCDisassembler::Success;
339}
340
341template <typename InsnType>
342static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
343 const MCDisassembler *Decoder) {
344 InsnType Rs = fieldFromInstruction(insn, 21, 5);
345 InsnType Imm = fieldFromInstruction(insn, 0, 16);
346 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
347 Rs)));
348 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
349 Rs)));
350 MI.addOperand(MCOperand::createImm(Imm));
351
352 return MCDisassembler::Success;
353}
354
355template <typename InsnType>
356static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
357 uint64_t Address,
358 const MCDisassembler *Decoder) {
359 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
360 // (otherwise we would have matched the ADDI instruction from the earlier
361 // ISA's instead).
362 //
363 // We have:
364 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
365 // BOVC if rs >= rt
366 // BEQZALC if rs == 0 && rt != 0
367 // BEQC if rs < rt && rs != 0
368
369 InsnType Rs = fieldFromInstruction(insn, 21, 5);
370 InsnType Rt = fieldFromInstruction(insn, 16, 5);
371 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
372 bool HasRs = false;
373
374 if (Rs >= Rt) {
375 MI.setOpcode(Mips::BOVC);
376 HasRs = true;
377 } else if (Rs != 0 && Rs < Rt) {
378 MI.setOpcode(Mips::BEQC);
379 HasRs = true;
380 } else
381 MI.setOpcode(Mips::BEQZALC);
382
383 if (HasRs)
384 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
385 Rs)));
386
387 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
388 Rt)));
389 MI.addOperand(MCOperand::createImm(Imm));
390
391 return MCDisassembler::Success;
392}
393
394template <typename InsnType>
395static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
396 uint64_t Address,
397 const MCDisassembler *Decoder) {
398 InsnType Rt = fieldFromInstruction(insn, 21, 5);
399 InsnType Rs = fieldFromInstruction(insn, 16, 5);
400 int64_t Imm = 0;
401
402 if (Rs >= Rt) {
403 MI.setOpcode(Mips::BOVC_MMR6);
404 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
405 Rt)));
406 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
407 Rs)));
408 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
409 } else if (Rs != 0 && Rs < Rt) {
410 MI.setOpcode(Mips::BEQC_MMR6);
411 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
412 Rs)));
413 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
414 Rt)));
415 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
416 } else {
417 MI.setOpcode(Mips::BEQZALC_MMR6);
418 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
419 Rt)));
420 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
421 }
422
423 MI.addOperand(MCOperand::createImm(Imm));
424
425 return MCDisassembler::Success;
426}
427
428template <typename InsnType>
429static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
430 uint64_t Address,
431 const MCDisassembler *Decoder) {
432 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
433 // (otherwise we would have matched the ADDI instruction from the earlier
434 // ISA's instead).
435 //
436 // We have:
437 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
438 // BNVC if rs >= rt
439 // BNEZALC if rs == 0 && rt != 0
440 // BNEC if rs < rt && rs != 0
441
442 InsnType Rs = fieldFromInstruction(insn, 21, 5);
443 InsnType Rt = fieldFromInstruction(insn, 16, 5);
444 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
445 bool HasRs = false;
446
447 if (Rs >= Rt) {
448 MI.setOpcode(Mips::BNVC);
449 HasRs = true;
450 } else if (Rs != 0 && Rs < Rt) {
451 MI.setOpcode(Mips::BNEC);
452 HasRs = true;
453 } else
454 MI.setOpcode(Mips::BNEZALC);
455
456 if (HasRs)
457 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
458 Rs)));
459
460 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
461 Rt)));
462 MI.addOperand(MCOperand::createImm(Imm));
463
464 return MCDisassembler::Success;
465}
466
467template <typename InsnType>
468static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
469 uint64_t Address,
470 const MCDisassembler *Decoder) {
471 InsnType Rt = fieldFromInstruction(insn, 21, 5);
472 InsnType Rs = fieldFromInstruction(insn, 16, 5);
473 int64_t Imm = 0;
474
475 if (Rs >= Rt) {
476 MI.setOpcode(Mips::BNVC_MMR6);
477 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
478 Rt)));
479 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
480 Rs)));
481 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
482 } else if (Rs != 0 && Rs < Rt) {
483 MI.setOpcode(Mips::BNEC_MMR6);
484 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
485 Rs)));
486 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
487 Rt)));
488 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
489 } else {
490 MI.setOpcode(Mips::BNEZALC_MMR6);
491 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
492 Rt)));
493 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
494 }
495
496 MI.addOperand(MCOperand::createImm(Imm));
497
498 return MCDisassembler::Success;
499}
500
501template <typename InsnType>
502static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
503 uint64_t Address,
504 const MCDisassembler *Decoder) {
505 // We have:
506 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
507 // Invalid if rt == 0
508 // BGTZC_MMR6 if rs == 0 && rt != 0
509 // BLTZC_MMR6 if rs == rt && rt != 0
510 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
511
512 InsnType Rt = fieldFromInstruction(insn, 21, 5);
513 InsnType Rs = fieldFromInstruction(insn, 16, 5);
514 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
515 bool HasRs = false;
516
517 if (Rt == 0)
518 return MCDisassembler::Fail;
519 else if (Rs == 0)
520 MI.setOpcode(Mips::BGTZC_MMR6);
521 else if (Rs == Rt)
522 MI.setOpcode(Mips::BLTZC_MMR6);
523 else {
524 MI.setOpcode(Mips::BLTC_MMR6);
525 HasRs = true;
526 }
527
528 if (HasRs)
529 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
530 Rs)));
531
532 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
533 Rt)));
534
535 MI.addOperand(MCOperand::createImm(Imm));
536
537 return MCDisassembler::Success;
538}
539
540template <typename InsnType>
541static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
542 uint64_t Address,
543 const MCDisassembler *Decoder) {
544 // We have:
545 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
546 // Invalid if rt == 0
547 // BLEZC_MMR6 if rs == 0 && rt != 0
548 // BGEZC_MMR6 if rs == rt && rt != 0
549 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
550
551 InsnType Rt = fieldFromInstruction(insn, 21, 5);
552 InsnType Rs = fieldFromInstruction(insn, 16, 5);
553 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
554 bool HasRs = false;
555
556 if (Rt == 0)
557 return MCDisassembler::Fail;
558 else if (Rs == 0)
559 MI.setOpcode(Mips::BLEZC_MMR6);
560 else if (Rs == Rt)
561 MI.setOpcode(Mips::BGEZC_MMR6);
562 else {
563 HasRs = true;
564 MI.setOpcode(Mips::BGEC_MMR6);
565 }
566
567 if (HasRs)
568 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
569 Rs)));
570
571 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
572 Rt)));
573
574 MI.addOperand(MCOperand::createImm(Imm));
575
576 return MCDisassembler::Success;
577}
578
579template <typename InsnType>
580static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
581 uint64_t Address,
582 const MCDisassembler *Decoder) {
583 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
584 // (otherwise we would have matched the BLEZL instruction from the earlier
585 // ISA's instead).
586 //
587 // We have:
588 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
589 // Invalid if rs == 0
590 // BLEZC if rs == 0 && rt != 0
591 // BGEZC if rs == rt && rt != 0
592 // BGEC if rs != rt && rs != 0 && rt != 0
593
594 InsnType Rs = fieldFromInstruction(insn, 21, 5);
595 InsnType Rt = fieldFromInstruction(insn, 16, 5);
596 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
597 bool HasRs = false;
598
599 if (Rt == 0)
600 return MCDisassembler::Fail;
601 else if (Rs == 0)
602 MI.setOpcode(Mips::BLEZC);
603 else if (Rs == Rt)
604 MI.setOpcode(Mips::BGEZC);
605 else {
606 HasRs = true;
607 MI.setOpcode(Mips::BGEC);
608 }
609
610 if (HasRs)
611 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
612 Rs)));
613
614 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
615 Rt)));
616
617 MI.addOperand(MCOperand::createImm(Imm));
618
619 return MCDisassembler::Success;
620}
621
622template <typename InsnType>
623static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
624 uint64_t Address,
625 const MCDisassembler *Decoder) {
626 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
627 // (otherwise we would have matched the BGTZL instruction from the earlier
628 // ISA's instead).
629 //
630 // We have:
631 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
632 // Invalid if rs == 0
633 // BGTZC if rs == 0 && rt != 0
634 // BLTZC if rs == rt && rt != 0
635 // BLTC if rs != rt && rs != 0 && rt != 0
636
637 bool HasRs = false;
638
639 InsnType Rs = fieldFromInstruction(insn, 21, 5);
640 InsnType Rt = fieldFromInstruction(insn, 16, 5);
641 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
642
643 if (Rt == 0)
644 return MCDisassembler::Fail;
645 else if (Rs == 0)
646 MI.setOpcode(Mips::BGTZC);
647 else if (Rs == Rt)
648 MI.setOpcode(Mips::BLTZC);
649 else {
650 MI.setOpcode(Mips::BLTC);
651 HasRs = true;
652 }
653
654 if (HasRs)
655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
656 Rs)));
657
658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rt)));
660
661 MI.addOperand(MCOperand::createImm(Imm));
662
663 return MCDisassembler::Success;
664}
665
666template <typename InsnType>
667static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
668 uint64_t Address,
669 const MCDisassembler *Decoder) {
670 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
671 // (otherwise we would have matched the BGTZ instruction from the earlier
672 // ISA's instead).
673 //
674 // We have:
675 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
676 // BGTZ if rt == 0
677 // BGTZALC if rs == 0 && rt != 0
678 // BLTZALC if rs != 0 && rs == rt
679 // BLTUC if rs != 0 && rs != rt
680
681 InsnType Rs = fieldFromInstruction(insn, 21, 5);
682 InsnType Rt = fieldFromInstruction(insn, 16, 5);
683 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
684 bool HasRs = false;
685 bool HasRt = false;
686
687 if (Rt == 0) {
688 MI.setOpcode(Mips::BGTZ);
689 HasRs = true;
690 } else if (Rs == 0) {
691 MI.setOpcode(Mips::BGTZALC);
692 HasRt = true;
693 } else if (Rs == Rt) {
694 MI.setOpcode(Mips::BLTZALC);
695 HasRs = true;
696 } else {
697 MI.setOpcode(Mips::BLTUC);
698 HasRs = true;
699 HasRt = true;
700 }
701
702 if (HasRs)
703 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
704 Rs)));
705
706 if (HasRt)
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
708 Rt)));
709
710 MI.addOperand(MCOperand::createImm(Imm));
711
712 return MCDisassembler::Success;
713}
714
715template <typename InsnType>
716static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
717 uint64_t Address,
718 const MCDisassembler *Decoder) {
719 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
720 // (otherwise we would have matched the BLEZL instruction from the earlier
721 // ISA's instead).
722 //
723 // We have:
724 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
725 // Invalid if rs == 0
726 // BLEZALC if rs == 0 && rt != 0
727 // BGEZALC if rs == rt && rt != 0
728 // BGEUC if rs != rt && rs != 0 && rt != 0
729
730 InsnType Rs = fieldFromInstruction(insn, 21, 5);
731 InsnType Rt = fieldFromInstruction(insn, 16, 5);
732 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
733 bool HasRs = false;
734
735 if (Rt == 0)
736 return MCDisassembler::Fail;
737 else if (Rs == 0)
738 MI.setOpcode(Mips::BLEZALC);
739 else if (Rs == Rt)
740 MI.setOpcode(Mips::BGEZALC);
741 else {
742 HasRs = true;
743 MI.setOpcode(Mips::BGEUC);
744 }
745
746 if (HasRs)
747 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
748 Rs)));
749 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
750 Rt)));
751
752 MI.addOperand(MCOperand::createImm(Imm));
753
754 return MCDisassembler::Success;
755}
756
757// Override the generated disassembler to produce DEXT all the time. This is
758// for feature / behaviour parity with binutils.
759template <typename InsnType>
760static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
761 const MCDisassembler *Decoder) {
762 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
763 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
764 unsigned Size = 0;
765 unsigned Pos = 0;
766
767 switch (MI.getOpcode()) {
768 case Mips::DEXT:
769 Pos = Lsb;
770 Size = Msbd + 1;
771 break;
772 case Mips::DEXTM:
773 Pos = Lsb;
774 Size = Msbd + 1 + 32;
775 break;
776 case Mips::DEXTU:
777 Pos = Lsb + 32;
778 Size = Msbd + 1;
779 break;
780 default:
781 llvm_unreachable("Unknown DEXT instruction!");
782 }
783
784 MI.setOpcode(Mips::DEXT);
785
786 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
787 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
788
789 MI.addOperand(
790 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
791 MI.addOperand(
792 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
793 MI.addOperand(MCOperand::createImm(Pos));
794 MI.addOperand(MCOperand::createImm(Size));
795
796 return MCDisassembler::Success;
797}
798
799// Override the generated disassembler to produce DINS all the time. This is
800// for feature / behaviour parity with binutils.
801template <typename InsnType>
802static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
803 const MCDisassembler *Decoder) {
804 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
805 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
806 unsigned Size = 0;
807 unsigned Pos = 0;
808
809 switch (MI.getOpcode()) {
810 case Mips::DINS:
811 Pos = Lsb;
812 Size = Msbd + 1 - Pos;
813 break;
814 case Mips::DINSM:
815 Pos = Lsb;
816 Size = Msbd + 33 - Pos;
817 break;
818 case Mips::DINSU:
819 Pos = Lsb + 32;
820 // mbsd = pos + size - 33
821 // mbsd - pos + 33 = size
822 Size = Msbd + 33 - Pos;
823 break;
824 default:
825 llvm_unreachable("Unknown DINS instruction!");
826 }
827
828 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
829 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
830
831 MI.setOpcode(Mips::DINS);
832 MI.addOperand(
833 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
834 MI.addOperand(
835 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
836 MI.addOperand(MCOperand::createImm(Pos));
837 MI.addOperand(MCOperand::createImm(Size));
838
839 return MCDisassembler::Success;
840}
841
842// Auto-generated decoder wouldn't add the third operand for CRC32*.
843template <typename InsnType>
844static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
845 const MCDisassembler *Decoder) {
846 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
847 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
848 MI.addOperand(
849 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
850 MI.addOperand(
851 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
852 MI.addOperand(
853 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
854 return MCDisassembler::Success;
855}
856
857static DecodeStatus
858DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
859 const MCDisassembler *Decoder) {
860 return MCDisassembler::Fail;
861}
862
863static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
864 uint64_t Address,
865 const MCDisassembler *Decoder) {
866 if (RegNo > 31)
867 return MCDisassembler::Fail;
868
869 MCRegister Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
870 Inst.addOperand(MCOperand::createReg(Reg));
871 return MCDisassembler::Success;
872}
873
874static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
875 uint64_t Address,
876 const MCDisassembler *Decoder) {
877 if (RegNo > 7)
878 return MCDisassembler::Fail;
879 MCRegister Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
880 Inst.addOperand(MCOperand::createReg(Reg));
881 return MCDisassembler::Success;
882}
883
884static DecodeStatus
885DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
886 const MCDisassembler *Decoder) {
887 if (RegNo > 7)
888 return MCDisassembler::Fail;
889 MCRegister Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
890 Inst.addOperand(MCOperand::createReg(Reg));
891 return MCDisassembler::Success;
892}
893
894static DecodeStatus
895DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
896 const MCDisassembler *Decoder) {
897 if (RegNo > 7)
898 return MCDisassembler::Fail;
899 MCRegister Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
900 Inst.addOperand(MCOperand::createReg(Reg));
901 return MCDisassembler::Success;
902}
903
904// Tablegen emits references to these unimplemented functions due to usage of
905// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
906// unused, which in turn use these register class decoders.
907static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
908 uint64_t Address,
909 const MCDisassembler *Decoder) {
910 llvm_unreachable("this is unused");
911}
912
913static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
914 uint64_t Address,
915 const MCDisassembler *Decoder) {
916 llvm_unreachable("this is unused");
917}
918
919static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
920 uint64_t Address,
921 const MCDisassembler *Decoder) {
922 llvm_unreachable("this is unused");
923}
924
925static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
926 uint64_t Address,
927 const MCDisassembler *Decoder) {
928 llvm_unreachable("this is unused");
929}
930
931static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
932 uint64_t Address,
933 const MCDisassembler *Decoder) {
934 if (RegNo > 31)
935 return MCDisassembler::Fail;
936 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
937 Inst.addOperand(MCOperand::createReg(Reg));
938 return MCDisassembler::Success;
939}
940
941static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
942 uint64_t Address,
943 const MCDisassembler *Decoder) {
944 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
945 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
946
947 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
948}
949
950static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
951 uint64_t Address,
952 const MCDisassembler *Decoder) {
953 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
954}
955
956static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
957 uint64_t Address,
958 const MCDisassembler *Decoder) {
959 if (RegNo > 31)
960 return MCDisassembler::Fail;
961
962 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
963 Inst.addOperand(MCOperand::createReg(Reg));
964 return MCDisassembler::Success;
965}
966
967static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
968 uint64_t Address,
969 const MCDisassembler *Decoder) {
970 if (RegNo > 31)
971 return MCDisassembler::Fail;
972
973 MCRegister Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
974 Inst.addOperand(MCOperand::createReg(Reg));
975 return MCDisassembler::Success;
976}
977
978static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
979 uint64_t Address,
980 const MCDisassembler *Decoder) {
981 if (RegNo > 31)
982 return MCDisassembler::Fail;
983 MCRegister Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
984 Inst.addOperand(MCOperand::createReg(Reg));
985 return MCDisassembler::Success;
986}
987
988static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
989 uint64_t Address,
990 const MCDisassembler *Decoder) {
991 if (RegNo > 7)
992 return MCDisassembler::Fail;
993 MCRegister Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
994 Inst.addOperand(MCOperand::createReg(Reg));
995 return MCDisassembler::Success;
996}
997
998static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
999 const MCDisassembler *Decoder) {
1000 int Offset = SignExtend32<16>(Insn & 0xffff);
1001 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1002 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1003
1004 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1005 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1006
1007 if (Inst.getOpcode() == Mips::SC || Inst.getOpcode() == Mips::SC64 ||
1008 Inst.getOpcode() == Mips::SCD)
1009 Inst.addOperand(MCOperand::createReg(Reg));
1010
1011 Inst.addOperand(MCOperand::createReg(Reg));
1012 Inst.addOperand(MCOperand::createReg(Base));
1013 Inst.addOperand(MCOperand::createImm(Offset));
1014
1015 return MCDisassembler::Success;
1016}
1017
1018static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1019 const MCDisassembler *Decoder) {
1020 int Offset = SignExtend32<9>(Insn >> 7);
1021 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1022 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1023
1024 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1025 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1026
1027 if (Inst.getOpcode() == Mips::SCE)
1028 Inst.addOperand(MCOperand::createReg(Reg));
1029
1030 Inst.addOperand(MCOperand::createReg(Reg));
1031 Inst.addOperand(MCOperand::createReg(Base));
1032 Inst.addOperand(MCOperand::createImm(Offset));
1033
1034 return MCDisassembler::Success;
1035}
1036
1037static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1038 uint64_t Address,
1039 const MCDisassembler *Decoder) {
1040 int Offset = SignExtend32<16>(Insn & 0xffff);
1041 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1042 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1043
1044 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1045 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1046
1047 Inst.addOperand(MCOperand::createReg(Reg));
1048 Inst.addOperand(MCOperand::createReg(Base));
1049 Inst.addOperand(MCOperand::createImm(Offset));
1050
1051 return MCDisassembler::Success;
1052}
1053
1054static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1055 const MCDisassembler *Decoder) {
1056 int Offset = SignExtend32<16>(Insn & 0xffff);
1057 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1058 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1059
1060 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1061
1062 Inst.addOperand(MCOperand::createReg(Base));
1063 Inst.addOperand(MCOperand::createImm(Offset));
1064 Inst.addOperand(MCOperand::createImm(Hint));
1065
1066 return MCDisassembler::Success;
1067}
1068
1069static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1070 uint64_t Address,
1071 const MCDisassembler *Decoder) {
1072 int Offset = SignExtend32<12>(Insn & 0xfff);
1073 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1074 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1075
1076 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1077
1078 Inst.addOperand(MCOperand::createReg(Base));
1079 Inst.addOperand(MCOperand::createImm(Offset));
1080 Inst.addOperand(MCOperand::createImm(Hint));
1081
1082 return MCDisassembler::Success;
1083}
1084
1085static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1086 uint64_t Address,
1087 const MCDisassembler *Decoder) {
1088 int Offset = SignExtend32<9>(Insn & 0x1ff);
1089 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1090 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1091
1092 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1093
1094 Inst.addOperand(MCOperand::createReg(Base));
1095 Inst.addOperand(MCOperand::createImm(Offset));
1096 Inst.addOperand(MCOperand::createImm(Hint));
1097
1098 return MCDisassembler::Success;
1099}
1100
1101static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1102 uint64_t Address,
1103 const MCDisassembler *Decoder) {
1104 int Offset = SignExtend32<9>(Insn >> 7);
1105 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1106 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1107
1108 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1109
1110 Inst.addOperand(MCOperand::createReg(Base));
1111 Inst.addOperand(MCOperand::createImm(Offset));
1112 Inst.addOperand(MCOperand::createImm(Hint));
1113
1114 return MCDisassembler::Success;
1115}
1116
1117static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1118 const MCDisassembler *Decoder) {
1119 int Offset = SignExtend32<16>(Insn & 0xffff);
1120 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1121
1122 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1123
1124 Inst.addOperand(MCOperand::createReg(Base));
1125 Inst.addOperand(MCOperand::createImm(Offset));
1126
1127 return MCDisassembler::Success;
1128}
1129
1130static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1131 uint64_t Address,
1132 const MCDisassembler *Decoder) {
1133 int Offset = SignExtend32<16>(Insn & 0xffff);
1134 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1135
1136 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1137
1138 Inst.addOperand(MCOperand::createReg(Base));
1139 Inst.addOperand(MCOperand::createImm(Offset));
1140
1141 return MCDisassembler::Success;
1142}
1143
1144static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1145 const MCDisassembler *Decoder) {
1146 int Immediate = SignExtend32<16>(Insn & 0xffff);
1147 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1148
1149 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1150
1151 Inst.addOperand(MCOperand::createReg(Base));
1152 Inst.addOperand(MCOperand::createImm(Immediate));
1153
1154 return MCDisassembler::Success;
1155}
1156
1157static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1158 uint64_t Address,
1159 const MCDisassembler *Decoder) {
1160 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1161 unsigned RegNo = fieldFromInstruction(Insn, 6, 5);
1162 unsigned BaseNo = fieldFromInstruction(Insn, 11, 5);
1163
1164 MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1165 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1166
1167 Inst.addOperand(MCOperand::createReg(Reg));
1168 Inst.addOperand(MCOperand::createReg(Base));
1169
1170 // The immediate field of an LD/ST instruction is scaled which means it must
1171 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1172 // data format.
1173 // .b - 1 byte
1174 // .h - 2 bytes
1175 // .w - 4 bytes
1176 // .d - 8 bytes
1177 switch(Inst.getOpcode())
1178 {
1179 default:
1180 assert(false && "Unexpected instruction");
1181 return MCDisassembler::Fail;
1182 break;
1183 case Mips::LD_B:
1184 case Mips::ST_B:
1185 Inst.addOperand(MCOperand::createImm(Offset));
1186 break;
1187 case Mips::LD_H:
1188 case Mips::ST_H:
1189 Inst.addOperand(MCOperand::createImm(Offset * 2));
1190 break;
1191 case Mips::LD_W:
1192 case Mips::ST_W:
1193 Inst.addOperand(MCOperand::createImm(Offset * 4));
1194 break;
1195 case Mips::LD_D:
1196 case Mips::ST_D:
1197 Inst.addOperand(MCOperand::createImm(Offset * 8));
1198 break;
1199 }
1200
1201 return MCDisassembler::Success;
1202}
1203
1204static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1205 uint64_t Address,
1206 const MCDisassembler *Decoder) {
1207 unsigned Offset = Insn & 0xf;
1208 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1209 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1210
1211 switch (Inst.getOpcode()) {
1212 case Mips::LBU16_MM:
1213 case Mips::LHU16_MM:
1214 case Mips::LW16_MM:
1215 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1216 == MCDisassembler::Fail)
1217 return MCDisassembler::Fail;
1218 break;
1219 case Mips::SB16_MM:
1220 case Mips::SB16_MMR6:
1221 case Mips::SH16_MM:
1222 case Mips::SH16_MMR6:
1223 case Mips::SW16_MM:
1224 case Mips::SW16_MMR6:
1225 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1226 == MCDisassembler::Fail)
1227 return MCDisassembler::Fail;
1228 break;
1229 }
1230
1231 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1232 == MCDisassembler::Fail)
1233 return MCDisassembler::Fail;
1234
1235 switch (Inst.getOpcode()) {
1236 case Mips::LBU16_MM:
1237 if (Offset == 0xf)
1238 Inst.addOperand(MCOperand::createImm(-1));
1239 else
1240 Inst.addOperand(MCOperand::createImm(Offset));
1241 break;
1242 case Mips::SB16_MM:
1243 case Mips::SB16_MMR6:
1244 Inst.addOperand(MCOperand::createImm(Offset));
1245 break;
1246 case Mips::LHU16_MM:
1247 case Mips::SH16_MM:
1248 case Mips::SH16_MMR6:
1249 Inst.addOperand(MCOperand::createImm(Offset << 1));
1250 break;
1251 case Mips::LW16_MM:
1252 case Mips::SW16_MM:
1253 case Mips::SW16_MMR6:
1254 Inst.addOperand(MCOperand::createImm(Offset << 2));
1255 break;
1256 }
1257
1258 return MCDisassembler::Success;
1259}
1260
1261static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1262 uint64_t Address,
1263 const MCDisassembler *Decoder) {
1264 unsigned Offset = Insn & 0x1F;
1265 unsigned RegNo = fieldFromInstruction(Insn, 5, 5);
1266
1267 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1268
1269 Inst.addOperand(MCOperand::createReg(Reg));
1270 Inst.addOperand(MCOperand::createReg(Mips::SP));
1271 Inst.addOperand(MCOperand::createImm(Offset << 2));
1272
1273 return MCDisassembler::Success;
1274}
1275
1276static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1277 uint64_t Address,
1278 const MCDisassembler *Decoder) {
1279 unsigned Offset = Insn & 0x7F;
1280 unsigned RegNo = fieldFromInstruction(Insn, 7, 3);
1281
1282 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1283
1284 Inst.addOperand(MCOperand::createReg(Reg));
1285 Inst.addOperand(MCOperand::createReg(Mips::GP));
1286 Inst.addOperand(MCOperand::createImm(Offset << 2));
1287
1288 return MCDisassembler::Success;
1289}
1290
1291static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1292 uint64_t Address,
1293 const MCDisassembler *Decoder) {
1294 int Offset;
1295 switch (Inst.getOpcode()) {
1296 case Mips::LWM16_MMR6:
1297 case Mips::SWM16_MMR6:
1298 Offset = fieldFromInstruction(Insn, 4, 4);
1299 break;
1300 default:
1301 Offset = SignExtend32<4>(Insn & 0xf);
1302 break;
1303 }
1304
1305 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1306 == MCDisassembler::Fail)
1307 return MCDisassembler::Fail;
1308
1309 Inst.addOperand(MCOperand::createReg(Mips::SP));
1310 Inst.addOperand(MCOperand::createImm(Offset << 2));
1311
1312 return MCDisassembler::Success;
1313}
1314
1315static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1316 uint64_t Address,
1317 const MCDisassembler *Decoder) {
1318 int Offset = SignExtend32<9>(Insn & 0x1ff);
1319 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1320 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1321
1322 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1323 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1324
1325 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1326 Inst.addOperand(MCOperand::createReg(Reg));
1327
1328 Inst.addOperand(MCOperand::createReg(Reg));
1329 Inst.addOperand(MCOperand::createReg(Base));
1330 Inst.addOperand(MCOperand::createImm(Offset));
1331
1332 return MCDisassembler::Success;
1333}
1334
1335static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1336 uint64_t Address,
1337 const MCDisassembler *Decoder) {
1338 int Offset = SignExtend32<12>(Insn & 0x0fff);
1339 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1340 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1341
1342 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1343 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1344
1345 switch (Inst.getOpcode()) {
1346 case Mips::SWM32_MM:
1347 case Mips::LWM32_MM:
1348 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1349 == MCDisassembler::Fail)
1350 return MCDisassembler::Fail;
1351 Inst.addOperand(MCOperand::createReg(Base));
1352 Inst.addOperand(MCOperand::createImm(Offset));
1353 break;
1354 case Mips::SC_MM:
1355 Inst.addOperand(MCOperand::createReg(Reg));
1356 [[fallthrough]];
1357 default:
1358 Inst.addOperand(MCOperand::createReg(Reg));
1359 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1360 Inst.addOperand(MCOperand::createReg(Reg+1));
1361
1362 Inst.addOperand(MCOperand::createReg(Base));
1363 Inst.addOperand(MCOperand::createImm(Offset));
1364 }
1365
1366 return MCDisassembler::Success;
1367}
1368
1369static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1370 uint64_t Address,
1371 const MCDisassembler *Decoder) {
1372 int Offset = SignExtend32<16>(Insn & 0xffff);
1373 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1374 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1375
1376 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1377 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1378
1379 Inst.addOperand(MCOperand::createReg(Reg));
1380 Inst.addOperand(MCOperand::createReg(Base));
1381 Inst.addOperand(MCOperand::createImm(Offset));
1382
1383 return MCDisassembler::Success;
1384}
1385
1386static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1387 const MCDisassembler *Decoder) {
1388 int Offset = SignExtend32<16>(Insn & 0xffff);
1389 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1390 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1391
1392 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1393 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1394
1395 Inst.addOperand(MCOperand::createReg(Reg));
1396 Inst.addOperand(MCOperand::createReg(Base));
1397 Inst.addOperand(MCOperand::createImm(Offset));
1398
1399 return MCDisassembler::Success;
1400}
1401
1402static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1403 uint64_t Address,
1404 const MCDisassembler *Decoder) {
1405 // This function is the same as DecodeFMem but with the Reg and Base fields
1406 // swapped according to microMIPS spec.
1407 int Offset = SignExtend32<16>(Insn & 0xffff);
1408 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1409 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1410
1411 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1412 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1413
1414 Inst.addOperand(MCOperand::createReg(Reg));
1415 Inst.addOperand(MCOperand::createReg(Base));
1416 Inst.addOperand(MCOperand::createImm(Offset));
1417
1418 return MCDisassembler::Success;
1419}
1420
1421static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1422 const MCDisassembler *Decoder) {
1423 int Offset = SignExtend32<16>(Insn & 0xffff);
1424 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1425 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1426
1427 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1428 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1429
1430 Inst.addOperand(MCOperand::createReg(Reg));
1431 Inst.addOperand(MCOperand::createReg(Base));
1432 Inst.addOperand(MCOperand::createImm(Offset));
1433
1434 return MCDisassembler::Success;
1435}
1436
1437static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1438 const MCDisassembler *Decoder) {
1439 int Offset = SignExtend32<16>(Insn & 0xffff);
1440 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1441 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1442
1443 MCRegister Reg = getReg(Decoder, Mips::COP3RegClassID, RegNo);
1444 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1445
1446 Inst.addOperand(MCOperand::createReg(Reg));
1447 Inst.addOperand(MCOperand::createReg(Base));
1448 Inst.addOperand(MCOperand::createImm(Offset));
1449
1450 return MCDisassembler::Success;
1451}
1452
1453static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1454 uint64_t Address,
1455 const MCDisassembler *Decoder) {
1456 int Offset = SignExtend32<11>(Insn & 0x07ff);
1457 unsigned RegNo = fieldFromInstruction(Insn, 16, 5);
1458 unsigned BaseNo = fieldFromInstruction(Insn, 11, 5);
1459
1460 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1461 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1462
1463 Inst.addOperand(MCOperand::createReg(Reg));
1464 Inst.addOperand(MCOperand::createReg(Base));
1465 Inst.addOperand(MCOperand::createImm(Offset));
1466
1467 return MCDisassembler::Success;
1468}
1469
1470static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1471 uint64_t Address,
1472 const MCDisassembler *Decoder) {
1473 int Offset = SignExtend32<11>(Insn & 0x07ff);
1474 unsigned RegNo = fieldFromInstruction(Insn, 21, 5);
1475 unsigned BaseNo = fieldFromInstruction(Insn, 16, 5);
1476
1477 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1478 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1479
1480 Inst.addOperand(MCOperand::createReg(Reg));
1481 Inst.addOperand(MCOperand::createReg(Base));
1482 Inst.addOperand(MCOperand::createImm(Offset));
1483
1484 return MCDisassembler::Success;
1485}
1486
1487static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1488 uint64_t Address,
1489 const MCDisassembler *Decoder) {
1490 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1491 unsigned RtNo = fieldFromInstruction(Insn, 16, 5);
1492 unsigned BaseNo = fieldFromInstruction(Insn, 21, 5);
1493
1494 MCRegister Rt = getReg(Decoder, Mips::GPR32RegClassID, RtNo);
1495 MCRegister Base = getReg(Decoder, Mips::GPR32RegClassID, BaseNo);
1496
1497 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1498 Inst.addOperand(MCOperand::createReg(Rt));
1499 }
1500
1501 Inst.addOperand(MCOperand::createReg(Rt));
1502 Inst.addOperand(MCOperand::createReg(Base));
1503 Inst.addOperand(MCOperand::createImm(Offset));
1504
1505 return MCDisassembler::Success;
1506}
1507
1508static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1509 uint64_t Address,
1510 const MCDisassembler *Decoder) {
1511 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1512 Inst.addOperand(MCOperand::createImm(BranchOffset));
1513 return MCDisassembler::Success;
1514}
1515
1516static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1517 uint64_t Address,
1518 const MCDisassembler *Decoder) {
1519 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
1520 Inst.addOperand(MCOperand::createImm(BranchOffset));
1521 return MCDisassembler::Success;
1522}
1523
1524static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1525 uint64_t Address,
1526 const MCDisassembler *Decoder) {
1527 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1528 Inst.addOperand(MCOperand::createImm(JumpOffset));
1529 return MCDisassembler::Success;
1530}
1531
1532static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1533 uint64_t Address,
1534 const MCDisassembler *Decoder) {
1535 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1536
1537 Inst.addOperand(MCOperand::createImm(BranchOffset));
1538 return MCDisassembler::Success;
1539}
1540
1541static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1542 uint64_t Address,
1543 const MCDisassembler *Decoder) {
1544 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1545
1546 Inst.addOperand(MCOperand::createImm(BranchOffset));
1547 return MCDisassembler::Success;
1548}
1549
1550static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1551 uint64_t Address,
1552 const MCDisassembler *Decoder) {
1553 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
1554
1555 Inst.addOperand(MCOperand::createImm(BranchOffset));
1556 return MCDisassembler::Success;
1557}
1558
1559static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1560 uint64_t Address,
1561 const MCDisassembler *Decoder) {
1562 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
1563 Inst.addOperand(MCOperand::createImm(BranchOffset));
1564 return MCDisassembler::Success;
1565}
1566
1567static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1568 uint64_t Address,
1569 const MCDisassembler *Decoder) {
1570 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
1571 Inst.addOperand(MCOperand::createImm(BranchOffset));
1572 return MCDisassembler::Success;
1573}
1574
1575static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1576 uint64_t Address,
1577 const MCDisassembler *Decoder) {
1578 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
1579 Inst.addOperand(MCOperand::createImm(BranchOffset));
1580 return MCDisassembler::Success;
1581}
1582
1583static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1584 uint64_t Address,
1585 const MCDisassembler *Decoder) {
1586 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
1587
1588 Inst.addOperand(MCOperand::createImm(BranchOffset));
1589 return MCDisassembler::Success;
1590}
1591
1592static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1593 uint64_t Address,
1594 const MCDisassembler *Decoder) {
1595 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1596 Inst.addOperand(MCOperand::createImm(JumpOffset));
1597 return MCDisassembler::Success;
1598}
1599
1600static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1601 uint64_t Address,
1602 const MCDisassembler *Decoder) {
1603 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1604 Inst.addOperand(MCOperand::createImm(JumpOffset));
1605 return MCDisassembler::Success;
1606}
1607
1608static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1609 uint64_t Address,
1610 const MCDisassembler *Decoder) {
1611 if (Value == 0)
1612 Inst.addOperand(MCOperand::createImm(1));
1613 else if (Value == 0x7)
1614 Inst.addOperand(MCOperand::createImm(-1));
1615 else
1616 Inst.addOperand(MCOperand::createImm(Value << 2));
1617 return MCDisassembler::Success;
1618}
1619
1620static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1621 uint64_t Address,
1622 const MCDisassembler *Decoder) {
1623 if (Value == 0x7F)
1624 Inst.addOperand(MCOperand::createImm(-1));
1625 else
1626 Inst.addOperand(MCOperand::createImm(Value));
1627 return MCDisassembler::Success;
1628}
1629
1630static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1631 uint64_t Address,
1632 const MCDisassembler *Decoder) {
1633 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1634 return MCDisassembler::Success;
1635}
1636
1637template <unsigned Bits, int Offset, int Scale>
1638static DecodeStatus
1639DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1640 const MCDisassembler *Decoder) {
1641 Value &= ((1 << Bits) - 1);
1642 Value *= Scale;
1643 Inst.addOperand(MCOperand::createImm(Value + Offset));
1644 return MCDisassembler::Success;
1645}
1646
1647template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1648static DecodeStatus
1649DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1650 const MCDisassembler *Decoder) {
1651 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1652 Inst.addOperand(MCOperand::createImm(Imm + Offset));
1653 return MCDisassembler::Success;
1654}
1655
1656template <unsigned Bits, int Offset>
1657static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1658 uint64_t Address,
1659 const MCDisassembler *Decoder) {
1660 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1661 Decoder);
1662}
1663
1664static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1665 const MCDisassembler *Decoder) {
1666 // First we need to grab the pos(lsb) from MCInst.
1667 // This function only handles the 32 bit variants of ins, as dins
1668 // variants are handled differently.
1669 int Pos = Inst.getOperand(2).getImm();
1670 int Size = (int) Insn - Pos + 1;
1671 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1672 return MCDisassembler::Success;
1673}
1674
1675static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1676 uint64_t Address,
1677 const MCDisassembler *Decoder) {
1678 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1679 return MCDisassembler::Success;
1680}
1681
1682static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1683 uint64_t Address,
1684 const MCDisassembler *Decoder) {
1685 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1686 return MCDisassembler::Success;
1687}
1688
1689static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1690 const MCDisassembler *Decoder) {
1691 int32_t DecodedValue;
1692 switch (Insn) {
1693 case 0: DecodedValue = 256; break;
1694 case 1: DecodedValue = 257; break;
1695 case 510: DecodedValue = -258; break;
1696 case 511: DecodedValue = -257; break;
1697 default: DecodedValue = SignExtend32<9>(Insn); break;
1698 }
1699 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1700 return MCDisassembler::Success;
1701}
1702
1703static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1704 uint64_t Address,
1705 const MCDisassembler *Decoder) {
1706 // Insn must be >= 0, since it is unsigned that condition is always true.
1707 assert(Insn < 16);
1708 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1709 16, 31, 32, 63, 64, 255, 32768, 65535};
1710 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1711 return MCDisassembler::Success;
1712}
1713
1714static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1715 uint64_t Address,
1716 const MCDisassembler *Decoder) {
1717 switch (RegPair) {
1718 default:
1719 return MCDisassembler::Fail;
1720 case 0:
1721 Inst.addOperand(MCOperand::createReg(Mips::A1));
1722 Inst.addOperand(MCOperand::createReg(Mips::A2));
1723 break;
1724 case 1:
1725 Inst.addOperand(MCOperand::createReg(Mips::A1));
1726 Inst.addOperand(MCOperand::createReg(Mips::A3));
1727 break;
1728 case 2:
1729 Inst.addOperand(MCOperand::createReg(Mips::A2));
1730 Inst.addOperand(MCOperand::createReg(Mips::A3));
1731 break;
1732 case 3:
1733 Inst.addOperand(MCOperand::createReg(Mips::A0));
1734 Inst.addOperand(MCOperand::createReg(Mips::S5));
1735 break;
1736 case 4:
1737 Inst.addOperand(MCOperand::createReg(Mips::A0));
1738 Inst.addOperand(MCOperand::createReg(Mips::S6));
1739 break;
1740 case 5:
1741 Inst.addOperand(MCOperand::createReg(Mips::A0));
1742 Inst.addOperand(MCOperand::createReg(Mips::A1));
1743 break;
1744 case 6:
1745 Inst.addOperand(MCOperand::createReg(Mips::A0));
1746 Inst.addOperand(MCOperand::createReg(Mips::A2));
1747 break;
1748 case 7:
1749 Inst.addOperand(MCOperand::createReg(Mips::A0));
1750 Inst.addOperand(MCOperand::createReg(Mips::A3));
1751 break;
1752 }
1753
1754 return MCDisassembler::Success;
1755}
1756
1757static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1758 uint64_t Address,
1759 const MCDisassembler *Decoder) {
1760 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1761 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1762 MCDisassembler::Fail)
1763 return MCDisassembler::Fail;
1764
1765 unsigned RegRs;
1766 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1767 RegRs = fieldFromInstruction(Insn, 0, 2) |
1768 (fieldFromInstruction(Insn, 3, 1) << 2);
1769 else
1770 RegRs = fieldFromInstruction(Insn, 1, 3);
1771 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
1772 MCDisassembler::Fail)
1773 return MCDisassembler::Fail;
1774
1775 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
1776 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
1777 MCDisassembler::Fail)
1778 return MCDisassembler::Fail;
1779
1780 return MCDisassembler::Success;
1781}
1782
1783static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1784 uint64_t Address,
1785 const MCDisassembler *Decoder) {
1786 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1787 return MCDisassembler::Success;
1788}
1789
1790template <typename InsnType>
1791static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1792 uint64_t Address,
1793 const MCDisassembler *Decoder) {
1794 // We have:
1795 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1796 // Invalid if rt == 0
1797 // BGTZALC_MMR6 if rs == 0 && rt != 0
1798 // BLTZALC_MMR6 if rs != 0 && rs == rt
1799 // BLTUC_MMR6 if rs != 0 && rs != rt
1800
1801 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1802 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1803 InsnType Imm = 0;
1804 bool HasRs = false;
1805 bool HasRt = false;
1806
1807 if (Rt == 0)
1808 return MCDisassembler::Fail;
1809 else if (Rs == 0) {
1810 MI.setOpcode(Mips::BGTZALC_MMR6);
1811 HasRt = true;
1812 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1813 }
1814 else if (Rs == Rt) {
1815 MI.setOpcode(Mips::BLTZALC_MMR6);
1816 HasRs = true;
1817 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1818 }
1819 else {
1820 MI.setOpcode(Mips::BLTUC_MMR6);
1821 HasRs = true;
1822 HasRt = true;
1823 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1824 }
1825
1826 if (HasRs)
1827 MI.addOperand(
1828 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1829
1830 if (HasRt)
1831 MI.addOperand(
1832 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1833
1834 MI.addOperand(MCOperand::createImm(Imm));
1835
1836 return MCDisassembler::Success;
1837}
1838
1839template <typename InsnType>
1840static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1841 uint64_t Address,
1842 const MCDisassembler *Decoder) {
1843 // We have:
1844 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1845 // Invalid if rt == 0
1846 // BLEZALC_MMR6 if rs == 0 && rt != 0
1847 // BGEZALC_MMR6 if rs == rt && rt != 0
1848 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1849
1850 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1851 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1852 InsnType Imm = 0;
1853 bool HasRs = false;
1854
1855 if (Rt == 0)
1856 return MCDisassembler::Fail;
1857 else if (Rs == 0) {
1858 MI.setOpcode(Mips::BLEZALC_MMR6);
1859 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1860 }
1861 else if (Rs == Rt) {
1862 MI.setOpcode(Mips::BGEZALC_MMR6);
1863 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1864 }
1865 else {
1866 HasRs = true;
1867 MI.setOpcode(Mips::BGEUC_MMR6);
1868 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1869 }
1870
1871 if (HasRs)
1872 MI.addOperand(
1873 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1874 MI.addOperand(
1875 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1876
1877 MI.addOperand(MCOperand::createImm(Imm));
1878
1879 return MCDisassembler::Success;
1880}
1881
1882// This instruction does not have a working decoder, and needs to be
1883// fixed. This "fixme" function was introduced to keep the backend compiling,
1884// while making changes to tablegen code.
1885static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1886 uint64_t Address,
1887 const MCDisassembler *Decoder) {
1888 return MCDisassembler::Fail;
1889}
1890
1891#include "MipsGenDisassemblerTables.inc"
1892
1893/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1894/// according to the given endianness.
1895static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1896 uint64_t &Size, uint32_t &Insn,
1897 bool IsBigEndian) {
1898 // We want to read exactly 2 Bytes of data.
1899 if (Bytes.size() < 2) {
1900 Size = 0;
1901 return MCDisassembler::Fail;
1902 }
1903
1904 if (IsBigEndian) {
1905 Insn = (Bytes[0] << 8) | Bytes[1];
1906 } else {
1907 Insn = (Bytes[1] << 8) | Bytes[0];
1908 }
1909
1910 return MCDisassembler::Success;
1911}
1912
1913/// Read four bytes from the ArrayRef and return 32 bit word sorted
1914/// according to the given endianness.
1915static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1916 uint64_t &Size, uint32_t &Insn,
1917 bool IsBigEndian, bool IsMicroMips) {
1918 // We want to read exactly 4 Bytes of data.
1919 if (Bytes.size() < 4) {
1920 Size = 0;
1921 return MCDisassembler::Fail;
1922 }
1923
1924 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1925 // always precede the low 16 bits in the instruction stream (that is, they
1926 // are placed at lower addresses in the instruction stream).
1927 //
1928 // microMIPS byte ordering:
1929 // Big-endian: 0 | 1 | 2 | 3
1930 // Little-endian: 1 | 0 | 3 | 2
1931
1932 if (IsBigEndian) {
1933 // Encoded as a big-endian 32-bit word in the stream.
1934 Insn =
1935 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1936 } else {
1937 if (IsMicroMips) {
1938 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1939 (Bytes[1] << 24);
1940 } else {
1941 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1942 (Bytes[3] << 24);
1943 }
1944 }
1945
1946 return MCDisassembler::Success;
1947}
1948
1949DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1950 ArrayRef<uint8_t> Bytes,
1951 uint64_t Address,
1952 raw_ostream &CStream) const {
1953 uint32_t Insn;
1954 DecodeStatus Result;
1955 Size = 0;
1956
1957 if (IsMicroMips) {
1958 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1959 if (Result == MCDisassembler::Fail)
1960 return MCDisassembler::Fail;
1961
1962 if (hasMips32r6()) {
1963 LLVM_DEBUG(
1964 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1965 // Calling the auto-generated decoder function for microMIPS32R6
1966 // 16-bit instructions.
1967 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1968 Address, this, STI);
1969 if (Result != MCDisassembler::Fail) {
1970 Size = 2;
1971 return Result;
1972 }
1973 }
1974
1975 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1976 // Calling the auto-generated decoder function for microMIPS 16-bit
1977 // instructions.
1978 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1979 this, STI);
1980 if (Result != MCDisassembler::Fail) {
1981 Size = 2;
1982 return Result;
1983 }
1984
1985 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1986 if (Result == MCDisassembler::Fail)
1987 return MCDisassembler::Fail;
1988
1989 if (hasMips32r6()) {
1990 LLVM_DEBUG(
1991 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1992 // Calling the auto-generated decoder function.
1993 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1994 Address, this, STI);
1995 if (Result != MCDisassembler::Fail) {
1996 Size = 4;
1997 return Result;
1998 }
1999 }
2000
2001 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
2002 // Calling the auto-generated decoder function.
2003 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
2004 this, STI);
2005 if (Result != MCDisassembler::Fail) {
2006 Size = 4;
2007 return Result;
2008 }
2009
2010 if (isFP64()) {
2011 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
2012 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
2013 Address, this, STI);
2014 if (Result != MCDisassembler::Fail) {
2015 Size = 4;
2016 return Result;
2017 }
2018 }
2019
2020 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
2021 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
2022 // could form a valid instruction. The two bytes we rejected as an
2023 // instruction could have actually beeen an inline constant pool that is
2024 // unconditionally branched over.
2025 Size = 2;
2026 return MCDisassembler::Fail;
2027 }
2028
2029 // Attempt to read the instruction so that we can attempt to decode it. If
2030 // the buffer is not 4 bytes long, let the higher level logic figure out
2031 // what to do with a size of zero and MCDisassembler::Fail.
2032 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
2033 if (Result == MCDisassembler::Fail)
2034 return MCDisassembler::Fail;
2035
2036 // The only instruction size for standard encoded MIPS.
2037 Size = 4;
2038
2039 if (hasCOP3()) {
2040 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
2041 Result =
2042 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
2043 if (Result != MCDisassembler::Fail)
2044 return Result;
2045 }
2046
2047 if (hasMips32r6() && isGP64()) {
2048 LLVM_DEBUG(
2049 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
2050 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
2051 Address, this, STI);
2052 if (Result != MCDisassembler::Fail)
2053 return Result;
2054 }
2055
2056 if (hasMips32r6() && isPTR64()) {
2057 LLVM_DEBUG(
2058 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2059 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
2060 Address, this, STI);
2061 if (Result != MCDisassembler::Fail)
2062 return Result;
2063 }
2064
2065 if (hasMips32r6()) {
2066 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
2067 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
2068 Address, this, STI);
2069 if (Result != MCDisassembler::Fail)
2070 return Result;
2071 }
2072
2073 if (hasMips2() && isPTR64()) {
2074 LLVM_DEBUG(
2075 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
2076 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
2077 Address, this, STI);
2078 if (Result != MCDisassembler::Fail)
2079 return Result;
2080 }
2081
2082 if (hasCnMips()) {
2083 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
2084 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this,
2085 STI);
2086 if (Result != MCDisassembler::Fail)
2087 return Result;
2088 }
2089
2090 if (hasCnMipsP()) {
2091 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
2092 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address,
2093 this, STI);
2094 if (Result != MCDisassembler::Fail)
2095 return Result;
2096 }
2097
2098 if (isGP64()) {
2099 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
2100 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this,
2101 STI);
2102 if (Result != MCDisassembler::Fail)
2103 return Result;
2104 }
2105
2106 if (isFP64()) {
2107 LLVM_DEBUG(
2108 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
2109 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address,
2110 this, STI);
2111 if (Result != MCDisassembler::Fail)
2112 return Result;
2113 }
2114
2115 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
2116 // Calling the auto-generated decoder function.
2117 Result =
2118 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
2119 if (Result != MCDisassembler::Fail)
2120 return Result;
2121
2122 return MCDisassembler::Fail;
2123}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:539
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:540
Decoder
unsigned const MCDisassembler * Decoder
Definition AMDGPUDisassembler.cpp:541
readInstruction16
static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:80
readInstruction32
static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:52
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:215
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:863
Reg
Register Reg
Definition MachineSink.cpp:2127
T
#define T
Definition Mips16ISelLowering.cpp:274
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1630
DecodeFMemCop2MMR6
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1470
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1675
DecodeMemEVA
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1018
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:623
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:241
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition MipsDisassembler.cpp:1915
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1532
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1600
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:967
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:978
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:230
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:988
DecodeCacheOpMM
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1069
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition MipsDisassembler.cpp:1895
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:874
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1649
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1783
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:895
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1516
DecodeMemMMImm9
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1315
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1757
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:844
getReg
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition MipsDisassembler.cpp:106
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:541
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:802
DecodeMSA128Mem
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1157
DecodePrefeOpMM
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1085
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:858
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:186
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1550
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:110
DecodeFMem
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1386
DecodeCacheOp
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1054
DecodeSyncI_MM
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1130
DecodeLoadByte15
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1037
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1689
DecodeFMem2
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1421
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1639
DecodeMemMMImm12
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1335
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:760
DecodeGPRMM16ZeroRegisterClass
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:885
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1620
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition MipsDisassembler.cpp:87
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1682
DecodeFMem3
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1437
DecodeSP64RegisterClass
static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:925
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:580
DecodeCOP0RegisterClass
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:219
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1508
DecodeMemMMReglistImm4Lsl2
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1291
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:667
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1575
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:395
DecodeFIXMEInstruction
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1885
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1567
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1703
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:197
DecodeSP32RegisterClass
static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:919
DecodeMemMMImm4
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1204
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition MipsDisassembler.cpp:81
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:931
DecodeMSA128BRegisterClass
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:164
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:429
DecodeMovePRegPair
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1714
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1541
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1583
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:120
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:342
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:153
DecodeSpecial3LlSc
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1487
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:142
DecodeSynciR6
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1144
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:941
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1657
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:269
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:356
DecodeMemMMSPImm5Lsl2
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1261
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1608
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:208
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:175
DecodeFMemMMR2
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1402
DecodeCacheeOp_CacheOpR6
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1101
DecodeMemMMImm16
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1369
DecodeGP64RegisterClass
static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:913
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1559
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:956
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:863
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1840
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1592
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:468
DecodeSyncI
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1117
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1524
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:131
DecodeFMemCop2R6
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1453
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1791
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:502
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:950
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1664
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:716
DecodeMem
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:998
DecodeGP32RegisterClass
static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:907
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:294
DecodeMemMMGPImm7Lsl2
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1276
LLVMInitializeMipsDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition MipsDisassembler.cpp:94
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:119
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:272
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:188
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:138
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition MipsTargetInfo.cpp:22
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition MipsTargetInfo.cpp:26
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition MipsTargetInfo.cpp:18
llvm::SignExtend32
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:549
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:567
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition MipsTargetInfo.cpp:14
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:900
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