LLVM 24.0.0git
MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "TargetInfo/MipsTargetInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33using namespace llvm::MCD;
34
35#define DEBUG_TYPE "mips-disassembler"
36
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39namespace {
40
41class MipsDisassembler : public MCDisassembler {
42 bool IsMicroMips;
43 bool IsBigEndian;
44
45public:
46 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
47 : MCDisassembler(STI, Ctx),
48 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
49 IsBigEndian(IsBigEndian) {}
50
51 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
52 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
53 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
54
55 bool hasMips32r6() const {
56 return STI.hasFeature(Mips::FeatureMips32r6);
57 }
58
59 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
60
61 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
62
63 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
64
65 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
66
67 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
68
69 bool hasCOP3() const {
70 // Only present in MIPS-I and MIPS-II
71 return !hasMips32() && !hasMips3();
72 }
73
74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75 ArrayRef<uint8_t> Bytes, uint64_t Address,
76 raw_ostream &CStream) const override;
77};
78
79} // end anonymous namespace
80
81static MCDisassembler *createMipsDisassembler(const Target &T,
82 const MCSubtargetInfo &STI,
83 MCContext &Ctx) {
84 return new MipsDisassembler(STI, Ctx, true);
85}
86
87static MCDisassembler *createMipselDisassembler(const Target &T,
88 const MCSubtargetInfo &STI,
89 MCContext &Ctx) {
90 return new MipsDisassembler(STI, Ctx, false);
91}
92
93extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
105
106static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
107 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
108 return RegInfo->getRegClass(RC).getRegister(RegNo);
109}
110static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 // Currently only hardware register 29 is supported.
114 if (RegNo != 29)
115 return MCDisassembler::Fail;
116 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 if (RegNo > 30 || RegNo % 2)
124 return MCDisassembler::Fail;
125
126 MCRegister Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo / 2);
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 4)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 4)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
149 Inst.addOperand(MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 4)
157 return MCDisassembler::Fail;
158
159 MCRegister Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
160 Inst.addOperand(MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo > 31)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
171 Inst.addOperand(MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo > 31)
179 return MCDisassembler::Fail;
180
181 MCRegister Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo > 31)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (RegNo > 31)
201 return MCDisassembler::Fail;
202
203 MCRegister Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
204 Inst.addOperand(MCOperand::createReg(Reg));
205 return MCDisassembler::Success;
206}
207
208static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
209 uint64_t Address,
210 const MCDisassembler *Decoder) {
211 if (RegNo > 7)
212 return MCDisassembler::Fail;
213
214 MCRegister Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
215 Inst.addOperand(MCOperand::createReg(Reg));
216 return MCDisassembler::Success;
217}
218
219static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
220 uint64_t Address,
221 const MCDisassembler *Decoder) {
222 if (MIPS_MC::getCOP0RegNum(RegNo) >= 32 || MIPS_MC::getCOP0Sel(RegNo) >= 8)
223 return MCDisassembler::Fail;
224
225 MCRegister Reg =
226 MIPS_MC::getCOP0Register(*Decoder->getContext().getRegisterInfo(), RegNo);
227 Inst.addOperand(MCOperand::createReg(Reg));
228 return MCDisassembler::Success;
229}
230
231static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
232 uint64_t Address,
233 const MCDisassembler *Decoder) {
234 if (RegNo > 31)
235 return MCDisassembler::Fail;
236
237 MCRegister Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
238 Inst.addOperand(MCOperand::createReg(Reg));
239 return MCDisassembler::Success;
240}
241
242static DecodeStatus DecodeCOP3RegisterClass(MCInst &Inst, unsigned RegNo,
243 uint64_t Address,
244 const MCDisassembler *Decoder) {
245 if (RegNo > 31)
246 return MCDisassembler::Fail;
247 Inst.addOperand(
248 MCOperand::createReg(getReg(Decoder, Mips::COP3RegClassID, RegNo)));
249 return MCDisassembler::Success;
250}
251
252static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned RegListEncoding,
253 uint64_t Address,
254 const MCDisassembler *Decoder) {
255 unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19, Mips::R20,
256 Mips::R21, Mips::R22, Mips::R23, Mips::FP};
257 unsigned RegNum;
258
259 unsigned RegLst = RegListEncoding;
260
261 // Empty register lists are not allowed.
262 if (RegLst == 0)
263 return MCDisassembler::Fail;
264
265 RegNum = RegLst & 0xf;
266
267 // RegLst values 10-15, and 26-31 are reserved.
268 if (RegNum > 9)
269 return MCDisassembler::Fail;
270
271 for (unsigned i = 0; i < RegNum; i++)
272 Inst.addOperand(MCOperand::createReg(Regs[i]));
273
274 if (RegLst & 0x10)
275 Inst.addOperand(MCOperand::createReg(Mips::RA));
276
277 return MCDisassembler::Success;
278}
279
280static DecodeStatus DecodeRegListOperand16(MCInst &Inst,
281 unsigned RegListEncoding,
282 uint64_t Address,
283 const MCDisassembler *Decoder) {
284 unsigned Regs[] = {Mips::R16, Mips::R17, Mips::R18, Mips::R19};
285 unsigned RegLst = RegListEncoding;
286 unsigned RegNum = RegLst & 0x3;
287
288 for (unsigned i = 0; i <= RegNum; i++)
289 Inst.addOperand(MCOperand::createReg(Regs[i]));
290
291 Inst.addOperand(MCOperand::createReg(Mips::RA));
292
293 return MCDisassembler::Success;
294}
295
296template <typename InsnType>
297static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
298 const MCDisassembler *Decoder) {
299 using DecodeFN =
300 DecodeStatus (*)(MCInst &, unsigned, uint64_t, const MCDisassembler *);
301
302 // The size of the n field depends on the element size
303 // The register class also depends on this.
304 InsnType tmp = fieldFromInstruction(insn, 17, 5);
305 unsigned NSize = 0;
306 DecodeFN RegDecoder = nullptr;
307 if ((tmp & 0x18) == 0x00) { // INSVE_B
308 NSize = 4;
309 RegDecoder = DecodeMSA128BRegisterClass;
310 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
311 NSize = 3;
312 RegDecoder = DecodeMSA128HRegisterClass;
313 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
314 NSize = 2;
315 RegDecoder = DecodeMSA128WRegisterClass;
316 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
317 NSize = 1;
318 RegDecoder = DecodeMSA128DRegisterClass;
319 } else
320 llvm_unreachable("Invalid encoding");
321
322 assert(NSize != 0 && RegDecoder != nullptr);
323
324 // $wd
325 tmp = fieldFromInstruction(insn, 6, 5);
326 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
327 return MCDisassembler::Fail;
328 // $wd_in
329 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
330 return MCDisassembler::Fail;
331 // $n
332 tmp = fieldFromInstruction(insn, 16, NSize);
333 MI.addOperand(MCOperand::createImm(tmp));
334 // $ws
335 tmp = fieldFromInstruction(insn, 11, 5);
336 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
337 return MCDisassembler::Fail;
338 // $n2
339 MI.addOperand(MCOperand::createImm(0));
340
341 return MCDisassembler::Success;
342}
343
344template <typename InsnType>
345static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
346 const MCDisassembler *Decoder) {
347 InsnType Rs = fieldFromInstruction(insn, 21, 5);
348 InsnType Imm = fieldFromInstruction(insn, 0, 16);
349 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
350 Rs)));
351 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
352 Rs)));
353 MI.addOperand(MCOperand::createImm(Imm));
354
355 return MCDisassembler::Success;
356}
357
358template <typename InsnType>
359static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
360 uint64_t Address,
361 const MCDisassembler *Decoder) {
362 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
363 // (otherwise we would have matched the ADDI instruction from the earlier
364 // ISA's instead).
365 //
366 // We have:
367 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
368 // BOVC if rs >= rt
369 // BEQZALC if rs == 0 && rt != 0
370 // BEQC if rs < rt && rs != 0
371
372 InsnType Rs = fieldFromInstruction(insn, 21, 5);
373 InsnType Rt = fieldFromInstruction(insn, 16, 5);
374 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
375 bool HasRs = false;
376
377 if (Rs >= Rt) {
378 MI.setOpcode(Mips::BOVC);
379 HasRs = true;
380 } else if (Rs != 0 && Rs < Rt) {
381 MI.setOpcode(Mips::BEQC);
382 HasRs = true;
383 } else
384 MI.setOpcode(Mips::BEQZALC);
385
386 if (HasRs)
387 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
388 Rs)));
389
390 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
391 Rt)));
392 MI.addOperand(MCOperand::createImm(Imm));
393
394 return MCDisassembler::Success;
395}
396
397template <typename InsnType>
398static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
399 uint64_t Address,
400 const MCDisassembler *Decoder) {
401 InsnType Rt = fieldFromInstruction(insn, 21, 5);
402 InsnType Rs = fieldFromInstruction(insn, 16, 5);
403 int64_t Imm = 0;
404
405 if (Rs >= Rt) {
406 MI.setOpcode(Mips::BOVC_MMR6);
407 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
408 Rt)));
409 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
410 Rs)));
411 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
412 } else if (Rs != 0 && Rs < Rt) {
413 MI.setOpcode(Mips::BEQC_MMR6);
414 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
415 Rs)));
416 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
417 Rt)));
418 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
419 } else {
420 MI.setOpcode(Mips::BEQZALC_MMR6);
421 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
422 Rt)));
423 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
424 }
425
426 MI.addOperand(MCOperand::createImm(Imm));
427
428 return MCDisassembler::Success;
429}
430
431template <typename InsnType>
432static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
433 uint64_t Address,
434 const MCDisassembler *Decoder) {
435 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
436 // (otherwise we would have matched the ADDI instruction from the earlier
437 // ISA's instead).
438 //
439 // We have:
440 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
441 // BNVC if rs >= rt
442 // BNEZALC if rs == 0 && rt != 0
443 // BNEC if rs < rt && rs != 0
444
445 InsnType Rs = fieldFromInstruction(insn, 21, 5);
446 InsnType Rt = fieldFromInstruction(insn, 16, 5);
447 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
448 bool HasRs = false;
449
450 if (Rs >= Rt) {
451 MI.setOpcode(Mips::BNVC);
452 HasRs = true;
453 } else if (Rs != 0 && Rs < Rt) {
454 MI.setOpcode(Mips::BNEC);
455 HasRs = true;
456 } else
457 MI.setOpcode(Mips::BNEZALC);
458
459 if (HasRs)
460 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
461 Rs)));
462
463 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
464 Rt)));
465 MI.addOperand(MCOperand::createImm(Imm));
466
467 return MCDisassembler::Success;
468}
469
470template <typename InsnType>
471static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
472 uint64_t Address,
473 const MCDisassembler *Decoder) {
474 InsnType Rt = fieldFromInstruction(insn, 21, 5);
475 InsnType Rs = fieldFromInstruction(insn, 16, 5);
476 int64_t Imm = 0;
477
478 if (Rs >= Rt) {
479 MI.setOpcode(Mips::BNVC_MMR6);
480 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
481 Rt)));
482 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
483 Rs)));
484 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
485 } else if (Rs != 0 && Rs < Rt) {
486 MI.setOpcode(Mips::BNEC_MMR6);
487 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
488 Rs)));
489 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
490 Rt)));
491 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
492 } else {
493 MI.setOpcode(Mips::BNEZALC_MMR6);
494 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
495 Rt)));
496 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
497 }
498
499 MI.addOperand(MCOperand::createImm(Imm));
500
501 return MCDisassembler::Success;
502}
503
504template <typename InsnType>
505static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
506 uint64_t Address,
507 const MCDisassembler *Decoder) {
508 // We have:
509 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
510 // Invalid if rt == 0
511 // BGTZC_MMR6 if rs == 0 && rt != 0
512 // BLTZC_MMR6 if rs == rt && rt != 0
513 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
514
515 InsnType Rt = fieldFromInstruction(insn, 21, 5);
516 InsnType Rs = fieldFromInstruction(insn, 16, 5);
517 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
518 bool HasRs = false;
519
520 if (Rt == 0)
521 return MCDisassembler::Fail;
522 else if (Rs == 0)
523 MI.setOpcode(Mips::BGTZC_MMR6);
524 else if (Rs == Rt)
525 MI.setOpcode(Mips::BLTZC_MMR6);
526 else {
527 MI.setOpcode(Mips::BLTC_MMR6);
528 HasRs = true;
529 }
530
531 if (HasRs)
532 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
533 Rs)));
534
535 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
536 Rt)));
537
538 MI.addOperand(MCOperand::createImm(Imm));
539
540 return MCDisassembler::Success;
541}
542
543template <typename InsnType>
544static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
545 uint64_t Address,
546 const MCDisassembler *Decoder) {
547 // We have:
548 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
549 // Invalid if rt == 0
550 // BLEZC_MMR6 if rs == 0 && rt != 0
551 // BGEZC_MMR6 if rs == rt && rt != 0
552 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
553
554 InsnType Rt = fieldFromInstruction(insn, 21, 5);
555 InsnType Rs = fieldFromInstruction(insn, 16, 5);
556 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
557 bool HasRs = false;
558
559 if (Rt == 0)
560 return MCDisassembler::Fail;
561 else if (Rs == 0)
562 MI.setOpcode(Mips::BLEZC_MMR6);
563 else if (Rs == Rt)
564 MI.setOpcode(Mips::BGEZC_MMR6);
565 else {
566 HasRs = true;
567 MI.setOpcode(Mips::BGEC_MMR6);
568 }
569
570 if (HasRs)
571 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
572 Rs)));
573
574 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
575 Rt)));
576
577 MI.addOperand(MCOperand::createImm(Imm));
578
579 return MCDisassembler::Success;
580}
581
582template <typename InsnType>
583static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
584 uint64_t Address,
585 const MCDisassembler *Decoder) {
586 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
587 // (otherwise we would have matched the BLEZL instruction from the earlier
588 // ISA's instead).
589 //
590 // We have:
591 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
592 // Invalid if rs == 0
593 // BLEZC if rs == 0 && rt != 0
594 // BGEZC if rs == rt && rt != 0
595 // BGEC if rs != rt && rs != 0 && rt != 0
596
597 InsnType Rs = fieldFromInstruction(insn, 21, 5);
598 InsnType Rt = fieldFromInstruction(insn, 16, 5);
599 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
600 bool HasRs = false;
601
602 if (Rt == 0)
603 return MCDisassembler::Fail;
604 else if (Rs == 0)
605 MI.setOpcode(Mips::BLEZC);
606 else if (Rs == Rt)
607 MI.setOpcode(Mips::BGEZC);
608 else {
609 HasRs = true;
610 MI.setOpcode(Mips::BGEC);
611 }
612
613 if (HasRs)
614 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
615 Rs)));
616
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
618 Rt)));
619
620 MI.addOperand(MCOperand::createImm(Imm));
621
622 return MCDisassembler::Success;
623}
624
625template <typename InsnType>
626static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
627 uint64_t Address,
628 const MCDisassembler *Decoder) {
629 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
630 // (otherwise we would have matched the BGTZL instruction from the earlier
631 // ISA's instead).
632 //
633 // We have:
634 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
635 // Invalid if rs == 0
636 // BGTZC if rs == 0 && rt != 0
637 // BLTZC if rs == rt && rt != 0
638 // BLTC if rs != rt && rs != 0 && rt != 0
639
640 bool HasRs = false;
641
642 InsnType Rs = fieldFromInstruction(insn, 21, 5);
643 InsnType Rt = fieldFromInstruction(insn, 16, 5);
644 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
645
646 if (Rt == 0)
647 return MCDisassembler::Fail;
648 else if (Rs == 0)
649 MI.setOpcode(Mips::BGTZC);
650 else if (Rs == Rt)
651 MI.setOpcode(Mips::BLTZC);
652 else {
653 MI.setOpcode(Mips::BLTC);
654 HasRs = true;
655 }
656
657 if (HasRs)
658 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rs)));
660
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
662 Rt)));
663
664 MI.addOperand(MCOperand::createImm(Imm));
665
666 return MCDisassembler::Success;
667}
668
669template <typename InsnType>
670static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
671 uint64_t Address,
672 const MCDisassembler *Decoder) {
673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
674 // (otherwise we would have matched the BGTZ instruction from the earlier
675 // ISA's instead).
676 //
677 // We have:
678 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
679 // BGTZ if rt == 0
680 // BGTZALC if rs == 0 && rt != 0
681 // BLTZALC if rs != 0 && rs == rt
682 // BLTUC if rs != 0 && rs != rt
683
684 InsnType Rs = fieldFromInstruction(insn, 21, 5);
685 InsnType Rt = fieldFromInstruction(insn, 16, 5);
686 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
687 bool HasRs = false;
688 bool HasRt = false;
689
690 if (Rt == 0) {
691 MI.setOpcode(Mips::BGTZ);
692 HasRs = true;
693 } else if (Rs == 0) {
694 MI.setOpcode(Mips::BGTZALC);
695 HasRt = true;
696 } else if (Rs == Rt) {
697 MI.setOpcode(Mips::BLTZALC);
698 HasRs = true;
699 } else {
700 MI.setOpcode(Mips::BLTUC);
701 HasRs = true;
702 HasRt = true;
703 }
704
705 if (HasRs)
706 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
707 Rs)));
708
709 if (HasRt)
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
711 Rt)));
712
713 MI.addOperand(MCOperand::createImm(Imm));
714
715 return MCDisassembler::Success;
716}
717
718template <typename InsnType>
719static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
720 uint64_t Address,
721 const MCDisassembler *Decoder) {
722 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
723 // (otherwise we would have matched the BLEZL instruction from the earlier
724 // ISA's instead).
725 //
726 // We have:
727 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
728 // Invalid if rs == 0
729 // BLEZALC if rs == 0 && rt != 0
730 // BGEZALC if rs == rt && rt != 0
731 // BGEUC if rs != rt && rs != 0 && rt != 0
732
733 InsnType Rs = fieldFromInstruction(insn, 21, 5);
734 InsnType Rt = fieldFromInstruction(insn, 16, 5);
735 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
736 bool HasRs = false;
737
738 if (Rt == 0)
739 return MCDisassembler::Fail;
740 else if (Rs == 0)
741 MI.setOpcode(Mips::BLEZALC);
742 else if (Rs == Rt)
743 MI.setOpcode(Mips::BGEZALC);
744 else {
745 HasRs = true;
746 MI.setOpcode(Mips::BGEUC);
747 }
748
749 if (HasRs)
750 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
751 Rs)));
752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
753 Rt)));
754
755 MI.addOperand(MCOperand::createImm(Imm));
756
757 return MCDisassembler::Success;
758}
759
760// Override the generated disassembler to produce DEXT all the time. This is
761// for feature / behaviour parity with binutils.
762template <typename InsnType>
763static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
764 const MCDisassembler *Decoder) {
765 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
766 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
767 unsigned Size = 0;
768 unsigned Pos = 0;
769
770 switch (MI.getOpcode()) {
771 case Mips::DEXT:
772 Pos = Lsb;
773 Size = Msbd + 1;
774 break;
775 case Mips::DEXTM:
776 Pos = Lsb;
777 Size = Msbd + 1 + 32;
778 break;
779 case Mips::DEXTU:
780 Pos = Lsb + 32;
781 Size = Msbd + 1;
782 break;
783 default:
784 llvm_unreachable("Unknown DEXT instruction!");
785 }
786
787 MI.setOpcode(Mips::DEXT);
788
789 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
790 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
791
792 MI.addOperand(
793 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
794 MI.addOperand(
795 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
796 MI.addOperand(MCOperand::createImm(Pos));
797 MI.addOperand(MCOperand::createImm(Size));
798
799 return MCDisassembler::Success;
800}
801
802// Override the generated disassembler to produce DINS all the time. This is
803// for feature / behaviour parity with binutils.
804template <typename InsnType>
805static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
806 const MCDisassembler *Decoder) {
807 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
808 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
809 unsigned Size = 0;
810 unsigned Pos = 0;
811
812 switch (MI.getOpcode()) {
813 case Mips::DINS:
814 Pos = Lsb;
815 Size = Msbd + 1 - Pos;
816 break;
817 case Mips::DINSM:
818 Pos = Lsb;
819 Size = Msbd + 33 - Pos;
820 break;
821 case Mips::DINSU:
822 Pos = Lsb + 32;
823 // mbsd = pos + size - 33
824 // mbsd - pos + 33 = size
825 Size = Msbd + 33 - Pos;
826 break;
827 default:
828 llvm_unreachable("Unknown DINS instruction!");
829 }
830
831 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
832 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
833
834 MI.setOpcode(Mips::DINS);
835 MI.addOperand(
836 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
837 MI.addOperand(
838 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
839 MI.addOperand(MCOperand::createImm(Pos));
840 MI.addOperand(MCOperand::createImm(Size));
841
842 return MCDisassembler::Success;
843}
844
845// Auto-generated decoder wouldn't add the third operand for CRC32*.
846template <typename InsnType>
847static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
848 const MCDisassembler *Decoder) {
849 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
850 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
851 MI.addOperand(
852 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
853 MI.addOperand(
854 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
855 MI.addOperand(
856 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
857 return MCDisassembler::Success;
858}
859
860static DecodeStatus
861DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
862 const MCDisassembler *Decoder) {
863 return MCDisassembler::Fail;
864}
865
866static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
867 uint64_t Address,
868 const MCDisassembler *Decoder) {
869 if (RegNo > 31)
870 return MCDisassembler::Fail;
871
872 MCRegister Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
873 Inst.addOperand(MCOperand::createReg(Reg));
874 return MCDisassembler::Success;
875}
876
877static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
878 uint64_t Address,
879 const MCDisassembler *Decoder) {
880 if (RegNo > 7)
881 return MCDisassembler::Fail;
882 MCRegister Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
883 Inst.addOperand(MCOperand::createReg(Reg));
884 return MCDisassembler::Success;
885}
886
887static DecodeStatus
888DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
889 const MCDisassembler *Decoder) {
890 if (RegNo > 7)
891 return MCDisassembler::Fail;
892 MCRegister Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
893 Inst.addOperand(MCOperand::createReg(Reg));
894 return MCDisassembler::Success;
895}
896
897static DecodeStatus
898DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
899 const MCDisassembler *Decoder) {
900 if (RegNo > 7)
901 return MCDisassembler::Fail;
902 MCRegister Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
903 Inst.addOperand(MCOperand::createReg(Reg));
904 return MCDisassembler::Success;
905}
906
907// Tablegen emits references to these unimplemented functions due to usage of
908// RegClassByHwMode - it does not detect that the RegClassByHwMode decoders are
909// unused, which in turn use these register class decoders.
910static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
911 uint64_t Address,
912 const MCDisassembler *Decoder) {
913 llvm_unreachable("this is unused");
914}
915
916static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
917 uint64_t Address,
918 const MCDisassembler *Decoder) {
919 llvm_unreachable("this is unused");
920}
921
922static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
923 uint64_t Address,
924 const MCDisassembler *Decoder) {
925 llvm_unreachable("this is unused");
926}
927
928static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
929 uint64_t Address,
930 const MCDisassembler *Decoder) {
931 llvm_unreachable("this is unused");
932}
933
934static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
935 uint64_t Address,
936 const MCDisassembler *Decoder) {
937 if (RegNo > 31)
938 return MCDisassembler::Fail;
939 MCRegister Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
940 Inst.addOperand(MCOperand::createReg(Reg));
941 return MCDisassembler::Success;
942}
943
944static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
945 uint64_t Address,
946 const MCDisassembler *Decoder) {
947 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
948 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
949
950 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
951}
952
953template <unsigned RegNo>
954static DecodeStatus DecodeFixedPtrRegister(MCInst &Inst,
955 const MCDisassembler *Decoder) {
956 return DecodePtrRegisterClass(Inst, RegNo, 0, Decoder);
957}
958
959static DecodeStatus DecodeLBU16Offset(MCInst &Inst, unsigned Value,
960 uint64_t Address,
961 const MCDisassembler *Decoder) {
962 Inst.addOperand(MCOperand::createImm(Value == 15 ? -1 : int64_t(Value)));
963 return MCDisassembler::Success;
964}
965
966static DecodeStatus DecodeGPR32Pair(MCInst &Inst, unsigned RegNo,
967 uint64_t Address,
968 const MCDisassembler *Decoder) {
969 if (RegNo >= 31)
970 return MCDisassembler::Fail;
971 DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
972 return DecodeGPR32RegisterClass(Inst, RegNo + 1, Address, Decoder);
973}
974
975static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
976 uint64_t Address,
977 const MCDisassembler *Decoder) {
978 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
979}
980
981static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
982 uint64_t Address,
983 const MCDisassembler *Decoder) {
984 if (RegNo > 31)
985 return MCDisassembler::Fail;
986
987 MCRegister Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
988 Inst.addOperand(MCOperand::createReg(Reg));
989 return MCDisassembler::Success;
990}
991
992static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
993 uint64_t Address,
994 const MCDisassembler *Decoder) {
995 if (RegNo > 31)
996 return MCDisassembler::Fail;
997
998 MCRegister Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
999 Inst.addOperand(MCOperand::createReg(Reg));
1000 return MCDisassembler::Success;
1001}
1002
1003static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
1004 uint64_t Address,
1005 const MCDisassembler *Decoder) {
1006 if (RegNo > 31)
1007 return MCDisassembler::Fail;
1008 MCRegister Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1009 Inst.addOperand(MCOperand::createReg(Reg));
1010 return MCDisassembler::Success;
1011}
1012
1013static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1014 uint64_t Address,
1015 const MCDisassembler *Decoder) {
1016 if (RegNo > 7)
1017 return MCDisassembler::Fail;
1018 MCRegister Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1019 Inst.addOperand(MCOperand::createReg(Reg));
1020 return MCDisassembler::Success;
1021}
1022
1023static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
1024 uint64_t Address,
1025 const MCDisassembler *Decoder) {
1026 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1027 Inst.addOperand(MCOperand::createImm(BranchOffset));
1028 return MCDisassembler::Success;
1029}
1030
1031static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
1032 uint64_t Address,
1033 const MCDisassembler *Decoder) {
1034 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
1035 Inst.addOperand(MCOperand::createImm(BranchOffset));
1036 return MCDisassembler::Success;
1037}
1038
1039static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
1040 uint64_t Address,
1041 const MCDisassembler *Decoder) {
1042 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1043 Inst.addOperand(MCOperand::createImm(JumpOffset));
1044 return MCDisassembler::Success;
1045}
1046
1047static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
1048 uint64_t Address,
1049 const MCDisassembler *Decoder) {
1050 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1051
1052 Inst.addOperand(MCOperand::createImm(BranchOffset));
1053 return MCDisassembler::Success;
1054}
1055
1056static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
1057 uint64_t Address,
1058 const MCDisassembler *Decoder) {
1059 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
1060
1061 Inst.addOperand(MCOperand::createImm(BranchOffset));
1062 return MCDisassembler::Success;
1063}
1064
1065static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
1066 uint64_t Address,
1067 const MCDisassembler *Decoder) {
1068 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
1069
1070 Inst.addOperand(MCOperand::createImm(BranchOffset));
1071 return MCDisassembler::Success;
1072}
1073
1074static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
1075 uint64_t Address,
1076 const MCDisassembler *Decoder) {
1077 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
1078 Inst.addOperand(MCOperand::createImm(BranchOffset));
1079 return MCDisassembler::Success;
1080}
1081
1082static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
1083 uint64_t Address,
1084 const MCDisassembler *Decoder) {
1085 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
1086 Inst.addOperand(MCOperand::createImm(BranchOffset));
1087 return MCDisassembler::Success;
1088}
1089
1090static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
1091 uint64_t Address,
1092 const MCDisassembler *Decoder) {
1093 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
1094 Inst.addOperand(MCOperand::createImm(BranchOffset));
1095 return MCDisassembler::Success;
1096}
1097
1098static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
1099 uint64_t Address,
1100 const MCDisassembler *Decoder) {
1101 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
1102
1103 Inst.addOperand(MCOperand::createImm(BranchOffset));
1104 return MCDisassembler::Success;
1105}
1106
1107static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
1108 uint64_t Address,
1109 const MCDisassembler *Decoder) {
1110 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1111 Inst.addOperand(MCOperand::createImm(JumpOffset));
1112 return MCDisassembler::Success;
1113}
1114
1115static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
1116 uint64_t Address,
1117 const MCDisassembler *Decoder) {
1118 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1119 Inst.addOperand(MCOperand::createImm(JumpOffset));
1120 return MCDisassembler::Success;
1121}
1122
1123static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
1124 uint64_t Address,
1125 const MCDisassembler *Decoder) {
1126 if (Value == 0)
1127 Inst.addOperand(MCOperand::createImm(1));
1128 else if (Value == 0x7)
1129 Inst.addOperand(MCOperand::createImm(-1));
1130 else
1131 Inst.addOperand(MCOperand::createImm(Value << 2));
1132 return MCDisassembler::Success;
1133}
1134
1135static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
1136 uint64_t Address,
1137 const MCDisassembler *Decoder) {
1138 if (Value == 0x7F)
1139 Inst.addOperand(MCOperand::createImm(-1));
1140 else
1141 Inst.addOperand(MCOperand::createImm(Value));
1142 return MCDisassembler::Success;
1143}
1144
1145static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
1146 uint64_t Address,
1147 const MCDisassembler *Decoder) {
1148 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1149 return MCDisassembler::Success;
1150}
1151
1152template <unsigned Bits, int Offset, int Scale>
1153static DecodeStatus
1154DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1155 const MCDisassembler *Decoder) {
1156 Value &= ((1 << Bits) - 1);
1157 Value *= Scale;
1158 Inst.addOperand(MCOperand::createImm(Value + Offset));
1159 return MCDisassembler::Success;
1160}
1161
1162template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
1163static DecodeStatus
1164DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
1165 const MCDisassembler *Decoder) {
1166 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
1167 Inst.addOperand(MCOperand::createImm(Imm + Offset));
1168 return MCDisassembler::Success;
1169}
1170
1171template <unsigned Bits, int Offset>
1172static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
1173 uint64_t Address,
1174 const MCDisassembler *Decoder) {
1175 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
1176 Decoder);
1177}
1178
1179static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
1180 const MCDisassembler *Decoder) {
1181 // First we need to grab the pos(lsb) from MCInst.
1182 // This function only handles the 32 bit variants of ins, as dins
1183 // variants are handled differently.
1184 int Pos = Inst.getOperand(2).getImm();
1185 int Size = (int) Insn - Pos + 1;
1186 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1187 return MCDisassembler::Success;
1188}
1189
1190static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1191 uint64_t Address,
1192 const MCDisassembler *Decoder) {
1193 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1194 return MCDisassembler::Success;
1195}
1196
1197static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1198 uint64_t Address,
1199 const MCDisassembler *Decoder) {
1200 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1201 return MCDisassembler::Success;
1202}
1203
1204static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
1205 const MCDisassembler *Decoder) {
1206 int32_t DecodedValue;
1207 switch (Insn) {
1208 case 0: DecodedValue = 256; break;
1209 case 1: DecodedValue = 257; break;
1210 case 510: DecodedValue = -258; break;
1211 case 511: DecodedValue = -257; break;
1212 default: DecodedValue = SignExtend32<9>(Insn); break;
1213 }
1214 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1215 return MCDisassembler::Success;
1216}
1217
1218static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1219 uint64_t Address,
1220 const MCDisassembler *Decoder) {
1221 // Insn must be >= 0, since it is unsigned that condition is always true.
1222 assert(Insn < 16);
1223 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15,
1224 16, 31, 32, 63, 64, 255, 32768, 65535};
1225 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1226 return MCDisassembler::Success;
1227}
1228
1229static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
1230 uint64_t Address,
1231 const MCDisassembler *Decoder) {
1232 switch (RegPair) {
1233 default:
1234 return MCDisassembler::Fail;
1235 case 0:
1236 Inst.addOperand(MCOperand::createReg(Mips::R5));
1237 Inst.addOperand(MCOperand::createReg(Mips::R6));
1238 break;
1239 case 1:
1240 Inst.addOperand(MCOperand::createReg(Mips::R5));
1241 Inst.addOperand(MCOperand::createReg(Mips::R7));
1242 break;
1243 case 2:
1244 Inst.addOperand(MCOperand::createReg(Mips::R6));
1245 Inst.addOperand(MCOperand::createReg(Mips::R7));
1246 break;
1247 case 3:
1248 Inst.addOperand(MCOperand::createReg(Mips::R4));
1249 Inst.addOperand(MCOperand::createReg(Mips::R21));
1250 break;
1251 case 4:
1252 Inst.addOperand(MCOperand::createReg(Mips::R4));
1253 Inst.addOperand(MCOperand::createReg(Mips::R22));
1254 break;
1255 case 5:
1256 Inst.addOperand(MCOperand::createReg(Mips::R4));
1257 Inst.addOperand(MCOperand::createReg(Mips::R5));
1258 break;
1259 case 6:
1260 Inst.addOperand(MCOperand::createReg(Mips::R4));
1261 Inst.addOperand(MCOperand::createReg(Mips::R6));
1262 break;
1263 case 7:
1264 Inst.addOperand(MCOperand::createReg(Mips::R4));
1265 Inst.addOperand(MCOperand::createReg(Mips::R7));
1266 break;
1267 }
1268
1269 return MCDisassembler::Success;
1270}
1271
1272static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
1273 uint64_t Address,
1274 const MCDisassembler *Decoder) {
1275 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1276 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
1277 MCDisassembler::Fail)
1278 return MCDisassembler::Fail;
1279
1280 unsigned RegRs;
1281 if (static_cast<const MipsDisassembler *>(Decoder)->hasMips32r6())
1282 RegRs = fieldFromInstruction(Insn, 0, 2) |
1283 (fieldFromInstruction(Insn, 3, 1) << 2);
1284 else
1285 RegRs = fieldFromInstruction(Insn, 1, 3);
1286 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
1287 MCDisassembler::Fail)
1288 return MCDisassembler::Fail;
1289
1290 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
1291 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
1292 MCDisassembler::Fail)
1293 return MCDisassembler::Fail;
1294
1295 return MCDisassembler::Success;
1296}
1297
1298static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1299 uint64_t Address,
1300 const MCDisassembler *Decoder) {
1301 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
1302 return MCDisassembler::Success;
1303}
1304
1305template <typename InsnType>
1306static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
1307 uint64_t Address,
1308 const MCDisassembler *Decoder) {
1309 // We have:
1310 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
1311 // Invalid if rt == 0
1312 // BGTZALC_MMR6 if rs == 0 && rt != 0
1313 // BLTZALC_MMR6 if rs != 0 && rs == rt
1314 // BLTUC_MMR6 if rs != 0 && rs != rt
1315
1316 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1317 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1318 InsnType Imm = 0;
1319 bool HasRs = false;
1320 bool HasRt = false;
1321
1322 if (Rt == 0)
1323 return MCDisassembler::Fail;
1324 else if (Rs == 0) {
1325 MI.setOpcode(Mips::BGTZALC_MMR6);
1326 HasRt = true;
1327 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1328 }
1329 else if (Rs == Rt) {
1330 MI.setOpcode(Mips::BLTZALC_MMR6);
1331 HasRs = true;
1332 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1333 }
1334 else {
1335 MI.setOpcode(Mips::BLTUC_MMR6);
1336 HasRs = true;
1337 HasRt = true;
1338 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1339 }
1340
1341 if (HasRs)
1342 MI.addOperand(
1343 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1344
1345 if (HasRt)
1346 MI.addOperand(
1347 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1348
1349 MI.addOperand(MCOperand::createImm(Imm));
1350
1351 return MCDisassembler::Success;
1352}
1353
1354template <typename InsnType>
1355static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
1356 uint64_t Address,
1357 const MCDisassembler *Decoder) {
1358 // We have:
1359 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
1360 // Invalid if rt == 0
1361 // BLEZALC_MMR6 if rs == 0 && rt != 0
1362 // BGEZALC_MMR6 if rs == rt && rt != 0
1363 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
1364
1365 InsnType Rt = fieldFromInstruction(insn, 21, 5);
1366 InsnType Rs = fieldFromInstruction(insn, 16, 5);
1367 InsnType Imm = 0;
1368 bool HasRs = false;
1369
1370 if (Rt == 0)
1371 return MCDisassembler::Fail;
1372 else if (Rs == 0) {
1373 MI.setOpcode(Mips::BLEZALC_MMR6);
1374 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1375 }
1376 else if (Rs == Rt) {
1377 MI.setOpcode(Mips::BGEZALC_MMR6);
1378 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
1379 }
1380 else {
1381 HasRs = true;
1382 MI.setOpcode(Mips::BGEUC_MMR6);
1383 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1384 }
1385
1386 if (HasRs)
1387 MI.addOperand(
1388 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
1389 MI.addOperand(
1390 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
1391
1392 MI.addOperand(MCOperand::createImm(Imm));
1393
1394 return MCDisassembler::Success;
1395}
1396
1397// This instruction does not have a working decoder, and needs to be
1398// fixed. This "fixme" function was introduced to keep the backend compiling,
1399// while making changes to tablegen code.
1400static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1401 uint64_t Address,
1402 const MCDisassembler *Decoder) {
1403 return MCDisassembler::Fail;
1404}
1405
1406#include "MipsGenDisassemblerTables.inc"
1407
1408/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1409/// according to the given endianness.
1410static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
1411 uint64_t &Size, uint32_t &Insn,
1412 bool IsBigEndian) {
1413 // We want to read exactly 2 Bytes of data.
1414 if (Bytes.size() < 2) {
1415 Size = 0;
1416 return MCDisassembler::Fail;
1417 }
1418
1419 if (IsBigEndian) {
1420 Insn = (Bytes[0] << 8) | Bytes[1];
1421 } else {
1422 Insn = (Bytes[1] << 8) | Bytes[0];
1423 }
1424
1425 return MCDisassembler::Success;
1426}
1427
1428/// Read four bytes from the ArrayRef and return 32 bit word sorted
1429/// according to the given endianness.
1430static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
1431 uint64_t &Size, uint32_t &Insn,
1432 bool IsBigEndian, bool IsMicroMips) {
1433 // We want to read exactly 4 Bytes of data.
1434 if (Bytes.size() < 4) {
1435 Size = 0;
1436 return MCDisassembler::Fail;
1437 }
1438
1439 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1440 // always precede the low 16 bits in the instruction stream (that is, they
1441 // are placed at lower addresses in the instruction stream).
1442 //
1443 // microMIPS byte ordering:
1444 // Big-endian: 0 | 1 | 2 | 3
1445 // Little-endian: 1 | 0 | 3 | 2
1446
1447 if (IsBigEndian) {
1448 // Encoded as a big-endian 32-bit word in the stream.
1449 Insn =
1450 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1451 } else {
1452 if (IsMicroMips) {
1453 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1454 (Bytes[1] << 24);
1455 } else {
1456 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1457 (Bytes[3] << 24);
1458 }
1459 }
1460
1461 return MCDisassembler::Success;
1462}
1463
1464DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1465 ArrayRef<uint8_t> Bytes,
1466 uint64_t Address,
1467 raw_ostream &CStream) const {
1468 uint32_t Insn;
1469 DecodeStatus Result;
1470 Size = 0;
1471
1472 if (IsMicroMips) {
1473 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1474 if (Result == MCDisassembler::Fail)
1475 return MCDisassembler::Fail;
1476
1477 if (hasMips32r6()) {
1478 LLVM_DEBUG(
1479 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1480 // Calling the auto-generated decoder function for microMIPS32R6
1481 // 16-bit instructions.
1482 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1483 Address, this, STI);
1484 if (Result != MCDisassembler::Fail) {
1485 Size = 2;
1486 return Result;
1487 }
1488 }
1489
1490 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1491 // Calling the auto-generated decoder function for microMIPS 16-bit
1492 // instructions.
1493 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1494 this, STI);
1495 if (Result != MCDisassembler::Fail) {
1496 Size = 2;
1497 return Result;
1498 }
1499
1500 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1501 if (Result == MCDisassembler::Fail)
1502 return MCDisassembler::Fail;
1503
1504 if (hasMips32r6()) {
1505 LLVM_DEBUG(
1506 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1507 // Calling the auto-generated decoder function.
1508 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1509 Address, this, STI);
1510 if (Result != MCDisassembler::Fail) {
1511 Size = 4;
1512 return Result;
1513 }
1514 }
1515
1516 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1517 // Calling the auto-generated decoder function.
1518 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1519 this, STI);
1520 if (Result != MCDisassembler::Fail) {
1521 Size = 4;
1522 return Result;
1523 }
1524
1525 if (isFP64()) {
1526 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1527 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1528 Address, this, STI);
1529 if (Result != MCDisassembler::Fail) {
1530 Size = 4;
1531 return Result;
1532 }
1533 }
1534
1535 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1536 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1537 // could form a valid instruction. The two bytes we rejected as an
1538 // instruction could have actually beeen an inline constant pool that is
1539 // unconditionally branched over.
1540 Size = 2;
1541 return MCDisassembler::Fail;
1542 }
1543
1544 // Attempt to read the instruction so that we can attempt to decode it. If
1545 // the buffer is not 4 bytes long, let the higher level logic figure out
1546 // what to do with a size of zero and MCDisassembler::Fail.
1547 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1548 if (Result == MCDisassembler::Fail)
1549 return MCDisassembler::Fail;
1550
1551 // The only instruction size for standard encoded MIPS.
1552 Size = 4;
1553
1554 if (hasCOP3()) {
1555 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1556 Result =
1557 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1558 if (Result != MCDisassembler::Fail)
1559 return Result;
1560 }
1561
1562 if (hasMips32r6() && isGP64()) {
1563 LLVM_DEBUG(
1564 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1565 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1566 Address, this, STI);
1567 if (Result != MCDisassembler::Fail)
1568 return Result;
1569 }
1570
1571 if (hasMips32r6() && isPTR64()) {
1572 LLVM_DEBUG(
1573 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1574 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1575 Address, this, STI);
1576 if (Result != MCDisassembler::Fail)
1577 return Result;
1578 }
1579
1580 if (hasMips32r6()) {
1581 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1582 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1583 Address, this, STI);
1584 if (Result != MCDisassembler::Fail)
1585 return Result;
1586 }
1587
1588 if (hasMips2() && isPTR64()) {
1589 LLVM_DEBUG(
1590 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1591 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1592 Address, this, STI);
1593 if (Result != MCDisassembler::Fail)
1594 return Result;
1595 }
1596
1597 if (hasCnMips()) {
1598 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1599 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this,
1600 STI);
1601 if (Result != MCDisassembler::Fail)
1602 return Result;
1603 }
1604
1605 if (hasCnMipsP()) {
1606 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1607 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address,
1608 this, STI);
1609 if (Result != MCDisassembler::Fail)
1610 return Result;
1611 }
1612
1613 if (isGP64()) {
1614 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1615 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this,
1616 STI);
1617 if (Result != MCDisassembler::Fail)
1618 return Result;
1619 }
1620
1621 if (isFP64()) {
1622 LLVM_DEBUG(
1623 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1624 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address,
1625 this, STI);
1626 if (Result != MCDisassembler::Fail)
1627 return Result;
1628 }
1629
1630 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1631 // Calling the auto-generated decoder function.
1632 Result =
1633 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1634 if (Result != MCDisassembler::Fail)
1635 return Result;
1636
1637 return MCDisassembler::Fail;
1638}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t
uint64_t uint64_t
Definition AMDGPUDisassembler.cpp:553
Imm
uint64_t Imm
Definition AMDGPUDisassembler.cpp:552
Decoder
uint64_t const MCDisassembler * Decoder
Definition AMDGPUDisassembler.cpp:554
readInstruction16
static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:80
readInstruction32
static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:52
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:211
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:870
Reg
Register Reg
Definition MachineSink.cpp:2127
T
#define T
Definition Mips16ISelLowering.cpp:274
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1145
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1190
DecodeCOP3RegisterClass
static DecodeStatus DecodeCOP3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:242
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:626
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition MipsDisassembler.cpp:1430
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1047
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1115
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:992
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1003
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:231
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1013
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition MipsDisassembler.cpp:1410
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:877
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1164
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1298
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:898
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1031
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1272
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:847
getReg
static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition MipsDisassembler.cpp:106
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:544
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:805
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:861
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:186
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1065
DecodeFixedPtrRegister
static DecodeStatus DecodeFixedPtrRegister(MCInst &Inst, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:954
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:110
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1204
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1154
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:763
DecodeGPRMM16ZeroRegisterClass
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:888
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1135
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition MipsDisassembler.cpp:87
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1197
DecodeSP64RegisterClass
static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:928
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:583
DecodeCOP0RegisterClass
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:219
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1023
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:670
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1090
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:398
DecodeFIXMEInstruction
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1400
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1082
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1218
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:197
DecodeSP32RegisterClass
static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:922
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition MipsDisassembler.cpp:81
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:934
DecodeMSA128BRegisterClass
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:164
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:432
DecodeMovePRegPair
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1229
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1056
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1098
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:120
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:345
DecodeGPR32Pair
static DecodeStatus DecodeGPR32Pair(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:966
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:153
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:142
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:944
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1172
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:359
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1123
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:208
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:175
DecodeGP64RegisterClass
static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:916
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1074
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:981
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:866
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1355
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1107
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:471
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1039
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned RegListEncoding, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:252
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:131
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1306
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:505
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:975
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:1179
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:719
DecodeLBU16Offset
static DecodeStatus DecodeLBU16Offset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:959
DecodeGP32RegisterClass
static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:910
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:297
LLVMInitializeMipsDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition MipsDisassembler.cpp:94
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned RegListEncoding, uint64_t Address, const MCDisassembler *Decoder)
Definition MipsDisassembler.cpp:280
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:119
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:296
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:142
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:193
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:138
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
llvm::MIPS_MC::getCOP0Register
MCRegister getCOP0Register(const MCRegisterInfo &MRI, unsigned Encoding)
Definition MipsMCTargetDesc.cpp:56
llvm::MIPS_MC::getCOP0RegNum
constexpr unsigned getCOP0RegNum(unsigned Encoding)
Definition MipsMCTargetDesc.h:68
llvm::MIPS_MC::getCOP0Sel
constexpr unsigned getCOP0Sel(unsigned Encoding)
Definition MipsMCTargetDesc.h:69
llvm::Mips::FP
constexpr MCPhysReg FP
Definition MipsMCTargetDesc.h:96
llvm::Mips::RA
constexpr MCPhysReg RA
Definition MipsMCTargetDesc.h:97
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition MipsTargetInfo.cpp:22
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition MipsTargetInfo.cpp:26
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition MipsTargetInfo.cpp:18
llvm::SignExtend32
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:554
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:572
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition MipsTargetInfo.cpp:14
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:900
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