LLVM 24.0.0git
MipsSEInstrInfo.cpp
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1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSEInstrInfo.h"
14#include "MipsAnalyzeImmediate.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/MC/TargetRegistry.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/MathExtras.h"
21
22using namespace llvm;
23
24static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
25 if (STI.inMicroMipsMode())
26 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
27 return STI.isPositionIndependent() ? Mips::B : Mips::J;
28}
29
32
33/// isLoadFromStackSlot - If the specified machine instruction is a direct
34/// load from a stack slot, return the virtual or physical register number of
35/// the destination along with the FrameIndex of the loaded stack slot. If
36/// not, return 0. This predicate must return 0 if the instruction has
37/// any side effects other than loading from the stack slot.
38Register MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
39 int &FrameIndex) const {
40 unsigned Opc = MI.getOpcode();
41
42 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
43 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
44 if ((MI.getOperand(1).isFI()) && // is a stack slot
45 (MI.getOperand(2).isImm()) && // the imm is zero
46 (isZeroImm(MI.getOperand(2)))) {
47 FrameIndex = MI.getOperand(1).getIndex();
48 return MI.getOperand(0).getReg();
49 }
50 }
51
52 return 0;
53}
54
55/// isStoreToStackSlot - If the specified machine instruction is a direct
56/// store to a stack slot, return the virtual or physical register number of
57/// the source reg along with the FrameIndex of the loaded stack slot. If
58/// not, return 0. This predicate must return 0 if the instruction has
59/// any side effects other than storing to the stack slot.
60Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
61 int &FrameIndex) const {
62 unsigned Opc = MI.getOpcode();
63
64 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
65 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
66 if ((MI.getOperand(1).isFI()) && // is a stack slot
67 (MI.getOperand(2).isImm()) && // the imm is zero
68 (isZeroImm(MI.getOperand(2)))) {
69 FrameIndex = MI.getOperand(1).getIndex();
70 return MI.getOperand(0).getReg();
71 }
72 }
73 return 0;
74}
75
76void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator I,
78 const DebugLoc &DL, Register DestReg,
79 Register SrcReg, bool KillSrc,
80 bool RenamableDest, bool RenamableSrc) const {
81 unsigned Opc = 0, ZeroReg = 0;
82 bool isMicroMips = Subtarget.inMicroMipsMode();
83
84 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
85 if (Mips::GPR32RegClass.contains(SrcReg)) {
86 if (isMicroMips)
87 Opc = Mips::MOVE16_MM;
88 else
89 Opc = Mips::OR, ZeroReg = Mips::ZERO;
90 } else if (Mips::CCRRegClass.contains(SrcReg))
91 Opc = Mips::CFC1;
92 else if (Mips::FGR32RegClass.contains(SrcReg))
93 Opc = Mips::MFC1;
94 else if (Mips::HI32RegClass.contains(SrcReg)) {
95 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
96 SrcReg = 0;
97 } else if (Mips::LO32RegClass.contains(SrcReg)) {
98 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
99 SrcReg = 0;
100 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
101 Opc = Mips::MFHI_DSP;
102 else if (Mips::LO32DSPRegClass.contains(SrcReg))
103 Opc = Mips::MFLO_DSP;
104 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
105 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
106 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
107 return;
108 } else if (Mips::MSACtrlRegClass.contains(SrcReg)) {
109 Opc = Mips::CFCMSA;
110 }
111 }
112 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
113 if (Mips::CCRRegClass.contains(DestReg))
114 Opc = Mips::CTC1;
115 else if (Mips::FGR32RegClass.contains(DestReg))
116 Opc = Mips::MTC1;
117 else if (Mips::HI32RegClass.contains(DestReg))
118 Opc = Mips::MTHI, DestReg = 0;
119 else if (Mips::LO32RegClass.contains(DestReg))
120 Opc = Mips::MTLO, DestReg = 0;
121 else if (Mips::HI32DSPRegClass.contains(DestReg))
122 Opc = Mips::MTHI_DSP;
123 else if (Mips::LO32DSPRegClass.contains(DestReg))
124 Opc = Mips::MTLO_DSP;
125 else if (Mips::DSPCCRegClass.contains(DestReg)) {
126 BuildMI(MBB, I, DL, get(Mips::WRDSP))
127 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
128 .addReg(DestReg, RegState::ImplicitDefine);
129 return;
130 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
131 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
132 .addReg(DestReg)
133 .addReg(SrcReg, getKillRegState(KillSrc));
134 return;
135 }
136 }
137 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
138 Opc = Mips::FMOV_S;
139 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
140 Opc = Mips::FMOV_D32;
141 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_D64;
143 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
144 if (Mips::GPR64RegClass.contains(SrcReg))
145 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
146 else if (Mips::HI64RegClass.contains(SrcReg))
147 Opc = Mips::MFHI64, SrcReg = 0;
148 else if (Mips::LO64RegClass.contains(SrcReg))
149 Opc = Mips::MFLO64, SrcReg = 0;
150 else if (Mips::FGR64RegClass.contains(SrcReg))
151 Opc = Mips::DMFC1;
152 }
153 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
154 if (Mips::HI64RegClass.contains(DestReg))
155 Opc = Mips::MTHI64, DestReg = 0;
156 else if (Mips::LO64RegClass.contains(DestReg))
157 Opc = Mips::MTLO64, DestReg = 0;
158 else if (Mips::FGR64RegClass.contains(DestReg))
159 Opc = Mips::DMTC1;
160 } else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
161 if (Mips::MSA128BRegClass.contains(SrcReg))
162 Opc = Mips::MOVE_V;
163 }
164
165 assert(Opc && "Cannot copy registers");
166
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
168
169 if (DestReg)
170 MIB.addReg(DestReg, RegState::Define);
171
172 if (SrcReg)
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
174
175 if (ZeroReg)
176 MIB.addReg(ZeroReg);
177}
178
179static bool isORCopyInst(const MachineInstr &MI) {
180 switch (MI.getOpcode()) {
181 default:
182 break;
183 case Mips::OR_MM:
184 case Mips::OR:
185 if (MI.getOperand(2).getReg() == Mips::ZERO)
186 return true;
187 break;
188 case Mips::OR64:
189 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
190 return true;
191 break;
192 }
193 return false;
194}
195
196/// We check for the common case of 'or', as it's MIPS' preferred instruction
197/// for GPRs but we have to check the operands to ensure that is the case.
198/// Other move instructions for MIPS are directly identifiable.
199std::optional<DestSourcePair>
200MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
201 if (MI.isMoveReg() || isORCopyInst(MI))
202 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
203
204 return std::nullopt;
205}
206
207void MipsSEInstrInfo::storeRegToStack(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator I,
209 Register SrcReg, bool isKill, int FI,
210 const TargetRegisterClass *RC,
211 int64_t Offset,
212 MachineInstr::MIFlag Flags) const {
213 DebugLoc DL;
214 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
215
216 unsigned Opc = 0;
217
218 if (Mips::GPR32RegClass.hasSubClassEq(RC))
219 Opc = Mips::SW;
220 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
221 Opc = Mips::SD;
222 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
223 Opc = Mips::STORE_ACC64;
224 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
225 Opc = Mips::STORE_ACC64DSP;
226 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
227 Opc = Mips::STORE_ACC128;
228 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
229 Opc = Mips::STORE_CCOND_DSP;
230 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
231 Opc = Mips::SWC1;
232 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
233 Opc = Mips::SDC1;
234 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
235 Opc = Mips::SDC164;
236 else if (RI.isTypeLegalForClass(*RC, MVT::v16i8))
237 Opc = Mips::ST_B;
238 else if (RI.isTypeLegalForClass(*RC, MVT::v8i16) ||
239 RI.isTypeLegalForClass(*RC, MVT::v8f16))
240 Opc = Mips::ST_H;
241 else if (RI.isTypeLegalForClass(*RC, MVT::v4i32) ||
242 RI.isTypeLegalForClass(*RC, MVT::v4f32))
243 Opc = Mips::ST_W;
244 else if (RI.isTypeLegalForClass(*RC, MVT::v2i64) ||
245 RI.isTypeLegalForClass(*RC, MVT::v2f64))
246 Opc = Mips::ST_D;
247 else if (Mips::LO32RegClass.hasSubClassEq(RC))
248 Opc = Mips::SW;
249 else if (Mips::LO64RegClass.hasSubClassEq(RC))
250 Opc = Mips::SD;
251 else if (Mips::HI32RegClass.hasSubClassEq(RC))
252 Opc = Mips::SW;
253 else if (Mips::HI64RegClass.hasSubClassEq(RC))
254 Opc = Mips::SD;
255 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
256 Opc = Mips::SWDSP;
257
258 // Hi, Lo are normally caller save but they are callee save
259 // for interrupt handling.
260 const Function &Func = MBB.getParent()->getFunction();
261 if (Func.hasFnAttribute("interrupt")) {
262 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
263 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
264 SrcReg = Mips::K0;
265 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
266 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
267 SrcReg = Mips::K0_64;
268 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
269 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
270 SrcReg = Mips::K0;
271 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
272 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
273 SrcReg = Mips::K0_64;
274 }
275 }
276
277 assert(Opc && "Register class not handled!");
278 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
279 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
280}
281
282void MipsSEInstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator I,
284 Register DestReg, int FI,
285 const TargetRegisterClass *RC,
286 int64_t Offset,
287 MachineInstr::MIFlag Flags) const {
288 DebugLoc DL;
289 if (I != MBB.end()) DL = I->getDebugLoc();
290 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
291 unsigned Opc = 0;
292
293 const Function &Func = MBB.getParent()->getFunction();
294 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
295 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
296 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
297
298 if (Mips::GPR32RegClass.hasSubClassEq(RC))
299 Opc = Mips::LW;
300 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
301 Opc = Mips::LD;
302 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
303 Opc = Mips::LOAD_ACC64;
304 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
305 Opc = Mips::LOAD_ACC64DSP;
306 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
307 Opc = Mips::LOAD_ACC128;
308 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
309 Opc = Mips::LOAD_CCOND_DSP;
310 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
311 Opc = Mips::LWC1;
312 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
313 Opc = Mips::LDC1;
314 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
315 Opc = Mips::LDC164;
316 else if (RI.isTypeLegalForClass(*RC, MVT::v16i8))
317 Opc = Mips::LD_B;
318 else if (RI.isTypeLegalForClass(*RC, MVT::v8i16) ||
319 RI.isTypeLegalForClass(*RC, MVT::v8f16))
320 Opc = Mips::LD_H;
321 else if (RI.isTypeLegalForClass(*RC, MVT::v4i32) ||
322 RI.isTypeLegalForClass(*RC, MVT::v4f32))
323 Opc = Mips::LD_W;
324 else if (RI.isTypeLegalForClass(*RC, MVT::v2i64) ||
325 RI.isTypeLegalForClass(*RC, MVT::v2f64))
326 Opc = Mips::LD_D;
327 else if (Mips::HI32RegClass.hasSubClassEq(RC))
328 Opc = Mips::LW;
329 else if (Mips::HI64RegClass.hasSubClassEq(RC))
330 Opc = Mips::LD;
331 else if (Mips::LO32RegClass.hasSubClassEq(RC))
332 Opc = Mips::LW;
333 else if (Mips::LO64RegClass.hasSubClassEq(RC))
334 Opc = Mips::LD;
335 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
336 Opc = Mips::LWDSP;
337
338 assert(Opc && "Register class not handled!");
339
340 if (!ReqIndirectLoad)
341 BuildMI(MBB, I, DL, get(Opc), DestReg)
342 .addFrameIndex(FI)
343 .addImm(Offset)
344 .addMemOperand(MMO);
345 else {
346 // Load HI/LO through K0. Notably the DestReg is encoded into the
347 // instruction itself.
348 unsigned Reg = Mips::K0;
349 unsigned LdOp = Mips::MTLO;
350 if (DestReg == Mips::HI0)
351 LdOp = Mips::MTHI;
352
353 if (Subtarget.getABI().ArePtrs64bit()) {
354 Reg = Mips::K0_64;
355 if (DestReg == Mips::HI0_64)
356 LdOp = Mips::MTHI64;
357 else
358 LdOp = Mips::MTLO64;
359 }
360
361 BuildMI(MBB, I, DL, get(Opc), Reg)
362 .addFrameIndex(FI)
363 .addImm(Offset)
364 .addMemOperand(MMO);
365 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
366 }
367}
368
369bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
370 MachineBasicBlock &MBB = *MI.getParent();
371 bool isMicroMips = Subtarget.inMicroMipsMode();
372 unsigned Opc;
373
374 switch (MI.getDesc().getOpcode()) {
375 default:
376 return false;
377 case Mips::RetRA:
378 expandRetRA(MBB, MI);
379 break;
380 case Mips::ERet:
381 expandERet(MBB, MI);
382 break;
383 case Mips::PseudoMFHI:
384 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
385 break;
386 case Mips::PseudoMFHI_MM:
387 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
388 break;
389 case Mips::PseudoMFLO:
390 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
391 break;
392 case Mips::PseudoMFLO_MM:
393 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
394 break;
395 case Mips::PseudoMFHI64:
396 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
397 break;
398 case Mips::PseudoMFLO64:
399 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
400 break;
401 case Mips::PseudoMTLOHI:
402 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
403 break;
404 case Mips::PseudoMTLOHI64:
405 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
406 break;
407 case Mips::PseudoMTLOHI_DSP:
408 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
409 break;
410 case Mips::PseudoMTLOHI_MM:
411 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
412 break;
413 case Mips::PseudoCVT_S_W:
414 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
415 break;
416 case Mips::PseudoCVT_D32_W:
417 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
418 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
419 break;
420 case Mips::PseudoCVT_S_L:
421 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
422 break;
423 case Mips::PseudoCVT_D64_W:
424 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
425 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
426 break;
427 case Mips::PseudoCVT_D64_L:
428 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
429 break;
430 case Mips::BuildPairF64:
431 expandBuildPairF64(MBB, MI, isMicroMips, false);
432 break;
433 case Mips::BuildPairF64_FPR:
434 MI.eraseFromParent();
435 return true;
436 case Mips::BuildPairF64_64:
437 expandBuildPairF64(MBB, MI, isMicroMips, true);
438 break;
439 case Mips::ExtractElementF64:
440 expandExtractElementF64(MBB, MI, isMicroMips, false);
441 break;
442 case Mips::ExtractElementF64_64:
443 expandExtractElementF64(MBB, MI, isMicroMips, true);
444 break;
445 case Mips::MIPSeh_return32:
446 case Mips::MIPSeh_return64:
447 expandEhReturn(MBB, MI);
448 break;
449 }
450
451 MBB.erase(MI);
452 return true;
453}
454
455/// isBranchWithImm - Return true if the branch contains an immediate
456/// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp).
457bool MipsSEInstrInfo::isBranchWithImm(unsigned Opc) const {
458 switch (Opc) {
459 default:
460 return false;
461 case Mips::BBIT0:
462 case Mips::BBIT1:
463 case Mips::BBIT032:
464 case Mips::BBIT132:
465 return true;
466 }
467}
468
469/// getOppositeBranchOpc - Return the inverse of the specified
470/// opcode, e.g. turning BEQ to BNE.
471unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
472 switch (Opc) {
473 default: llvm_unreachable("Illegal opcode!");
474 case Mips::BEQ: return Mips::BNE;
475 case Mips::BEQ_MM: return Mips::BNE_MM;
476 case Mips::BNE: return Mips::BEQ;
477 case Mips::BNE_MM: return Mips::BEQ_MM;
478 case Mips::BGTZ: return Mips::BLEZ;
479 case Mips::BGEZ: return Mips::BLTZ;
480 case Mips::BLTZ: return Mips::BGEZ;
481 case Mips::BLEZ: return Mips::BGTZ;
482 case Mips::BGTZ_MM: return Mips::BLEZ_MM;
483 case Mips::BGEZ_MM: return Mips::BLTZ_MM;
484 case Mips::BLTZ_MM: return Mips::BGEZ_MM;
485 case Mips::BLEZ_MM: return Mips::BGTZ_MM;
486 case Mips::BEQ64: return Mips::BNE64;
487 case Mips::BNE64: return Mips::BEQ64;
488 case Mips::BGTZ64: return Mips::BLEZ64;
489 case Mips::BGEZ64: return Mips::BLTZ64;
490 case Mips::BLTZ64: return Mips::BGEZ64;
491 case Mips::BLEZ64: return Mips::BGTZ64;
492 case Mips::BC1T: return Mips::BC1F;
493 case Mips::BC1F: return Mips::BC1T;
494 case Mips::BC1T_MM: return Mips::BC1F_MM;
495 case Mips::BC1F_MM: return Mips::BC1T_MM;
496 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
497 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
498 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
499 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
500 case Mips::BEQZC: return Mips::BNEZC;
501 case Mips::BNEZC: return Mips::BEQZC;
502 case Mips::BLEZC: return Mips::BGTZC;
503 case Mips::BGEZC: return Mips::BLTZC;
504 case Mips::BGEC: return Mips::BLTC;
505 case Mips::BGTZC: return Mips::BLEZC;
506 case Mips::BLTZC: return Mips::BGEZC;
507 case Mips::BLTC: return Mips::BGEC;
508 case Mips::BGEUC: return Mips::BLTUC;
509 case Mips::BLTUC: return Mips::BGEUC;
510 case Mips::BEQC: return Mips::BNEC;
511 case Mips::BNEC: return Mips::BEQC;
512 case Mips::BC1EQZ: return Mips::BC1NEZ;
513 case Mips::BC1NEZ: return Mips::BC1EQZ;
514 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
515 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
516 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
517 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
518 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
519 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
520 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
521 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
522 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
523 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
524 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
525 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
526 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
527 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
528 case Mips::BEQZC64: return Mips::BNEZC64;
529 case Mips::BNEZC64: return Mips::BEQZC64;
530 case Mips::BEQC64: return Mips::BNEC64;
531 case Mips::BNEC64: return Mips::BEQC64;
532 case Mips::BGEC64: return Mips::BLTC64;
533 case Mips::BGEUC64: return Mips::BLTUC64;
534 case Mips::BLTC64: return Mips::BGEC64;
535 case Mips::BLTUC64: return Mips::BGEUC64;
536 case Mips::BGTZC64: return Mips::BLEZC64;
537 case Mips::BGEZC64: return Mips::BLTZC64;
538 case Mips::BLTZC64: return Mips::BGEZC64;
539 case Mips::BLEZC64: return Mips::BGTZC64;
540 case Mips::BBIT0: return Mips::BBIT1;
541 case Mips::BBIT1: return Mips::BBIT0;
542 case Mips::BBIT032: return Mips::BBIT132;
543 case Mips::BBIT132: return Mips::BBIT032;
544 case Mips::BZ_B: return Mips::BNZ_B;
545 case Mips::BZ_H: return Mips::BNZ_H;
546 case Mips::BZ_W: return Mips::BNZ_W;
547 case Mips::BZ_D: return Mips::BNZ_D;
548 case Mips::BZ_V: return Mips::BNZ_V;
549 case Mips::BNZ_B: return Mips::BZ_B;
550 case Mips::BNZ_H: return Mips::BZ_H;
551 case Mips::BNZ_W: return Mips::BZ_W;
552 case Mips::BNZ_D: return Mips::BZ_D;
553 case Mips::BNZ_V: return Mips::BZ_V;
554 }
555}
556
557/// Adjust SP by Amount bytes.
558void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
559 MachineBasicBlock &MBB,
560 MachineBasicBlock::iterator I) const {
561 MipsABIInfo ABI = Subtarget.getABI();
562 DebugLoc DL;
563 unsigned ADDiu = ABI.GetPtrAddiuOp();
564
565 if (Amount == 0)
566 return;
567
568 if (isInt<16>(Amount)) {
569 // addi sp, sp, amount
570 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
571 } else {
572 // For numbers which are not 16bit integers we synthesize Amount inline
573 // then add or subtract it from sp.
574 unsigned Opc = ABI.GetPtrAdduOp();
575 if (Amount < 0) {
576 Opc = ABI.GetPtrSubuOp();
577 Amount = -Amount;
578 }
579 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
580 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
581 }
582}
583
584/// This function generates the sequence of instructions needed to get the
585/// result of adding register REG and immediate IMM.
586unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
587 MachineBasicBlock::iterator II,
588 const DebugLoc &DL,
589 unsigned *NewImm) const {
590 MipsAnalyzeImmediate AnalyzeImm;
591 const MipsSubtarget &STI = Subtarget;
592 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
593 unsigned Size = STI.isABI_N64() ? 64 : 32;
594 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
595 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
596 const TargetRegisterClass *RC = STI.isABI_N64() ?
597 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
598 bool LastInstrIsADDiu = NewImm;
599
600 const MipsAnalyzeImmediate::InstSeq &Seq =
601 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
602 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
603
604 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
605
606 // The first instruction can be a LUi, which is different from other
607 // instructions (ADDiu, ORI and SLL) in that it does not have a register
608 // operand.
609 Register Reg = RegInfo.createVirtualRegister(RC);
610
611 if (Inst->Opc == LUi)
612 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
613 else
614 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
615 .addImm(SignExtend64<16>(Inst->ImmOpnd));
616
617 // Build the remaining instructions in Seq.
618 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
619 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
620 .addImm(SignExtend64<16>(Inst->ImmOpnd));
621
622 if (LastInstrIsADDiu)
623 *NewImm = Inst->ImmOpnd;
624
625 return Reg;
626}
627
628unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
629 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
630 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
631 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
632 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
633 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
634 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
635 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
636 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
637 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
638 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
639 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
640 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
641 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
642 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
643 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
644 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
645 Opc == Mips::BC1EQZ || Opc == Mips::BC1NEZ || Opc == Mips::BBIT0 ||
646 Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || Opc == Mips::BBIT132 ||
647 Opc == Mips::BC_MMR6 || Opc == Mips::BEQC_MMR6 ||
648 Opc == Mips::BNEC_MMR6 || Opc == Mips::BLTC_MMR6 ||
649 Opc == Mips::BGEC_MMR6 || Opc == Mips::BLTUC_MMR6 ||
650 Opc == Mips::BGEUC_MMR6 || Opc == Mips::BGTZC_MMR6 ||
651 Opc == Mips::BLEZC_MMR6 || Opc == Mips::BGEZC_MMR6 ||
652 Opc == Mips::BLTZC_MMR6 || Opc == Mips::BEQZC_MMR6 ||
653 Opc == Mips::BNEZC_MMR6 || Opc == Mips::BC1EQZC_MMR6 ||
654 Opc == Mips::BC1NEZC_MMR6)
655 ? Opc
656 : 0;
657}
658
659void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator I) const {
661
662 MachineInstrBuilder MIB;
663 if (Subtarget.isGP64bit())
664 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
665 .addReg(Mips::RA_64, RegState::Undef);
666 else
667 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
668 .addReg(Mips::RA, RegState::Undef);
669
670 // Retain any imp-use flags.
671 for (auto & MO : I->operands()) {
672 if (MO.isImplicit())
673 MIB.add(MO);
674 }
675}
676
677void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
678 MachineBasicBlock::iterator I) const {
679 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
680}
681
682std::pair<bool, bool>
683MipsSEInstrInfo::compareOpndSize(unsigned Opc,
684 const MachineFunction &MF) const {
685 const MCInstrDesc &Desc = get(Opc);
686 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
687 const MipsRegisterInfo *RI = &getRegisterInfo();
688 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0));
689 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1));
690
691 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
692}
693
694void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
695 MachineBasicBlock::iterator I,
696 unsigned NewOpc) const {
697 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
698}
699
700void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
701 MachineBasicBlock::iterator I,
702 unsigned LoOpc,
703 unsigned HiOpc,
704 bool HasExplicitDef) const {
705 // Expand
706 // lo_hi pseudomtlohi $gpr0, $gpr1
707 // to these two instructions:
708 // mtlo $gpr0
709 // mthi $gpr1
710
711 DebugLoc DL = I->getDebugLoc();
712 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
713 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
714 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
715
716 // Add lo/hi registers if the mtlo/hi instructions created have explicit
717 // def registers.
718 if (HasExplicitDef) {
719 Register DstReg = I->getOperand(0).getReg();
720 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
721 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
722 LoInst.addReg(DstLo, RegState::Define);
723 HiInst.addReg(DstHi, RegState::Define);
724 }
725
726 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
727 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
728}
729
730void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
731 MachineBasicBlock::iterator I,
732 unsigned CvtOpc, unsigned MovOpc,
733 bool IsI64) const {
734 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
735 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
736 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
737 RegState KillSrc = getKillRegState(Src.isKill());
738 DebugLoc DL = I->getDebugLoc();
739 bool DstIsLarger, SrcIsLarger;
740
741 std::tie(DstIsLarger, SrcIsLarger) =
742 compareOpndSize(CvtOpc, *MBB.getParent());
743
744 if (DstIsLarger)
745 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
746
747 if (SrcIsLarger)
748 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
749
750 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
751 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
752}
753
754void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
755 MachineBasicBlock::iterator I,
756 bool isMicroMips,
757 bool FP64) const {
758 Register DstReg = I->getOperand(0).getReg();
759 Register SrcReg = I->getOperand(1).getReg();
760 unsigned N = I->getOperand(2).getImm();
761 DebugLoc dl = I->getDebugLoc();
762
763 assert(N < 2 && "Invalid immediate");
764 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
765 Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
766
767 // FPXX/FP64 without MFHC1 should have been handled with a spill/reload
768 // in MipsSEFrameLowering.cpp.
769 assert(!((Subtarget.isABI_FPXX() || FP64) && !Subtarget.hasMTHC1()));
770
771 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
772 // in MipsSEFrameLowering.cpp.
773 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
774
775 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
776 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
777 // claim to read the whole 64-bits as part of a white lie used to
778 // temporarily work around a widespread bug in the -mfp64 support.
779 // The problem is that none of the 32-bit fpu ops mention the fact
780 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
781 // requires a major overhaul of the FPU implementation which can't
782 // be done right now due to time constraints.
783 // MFHC1 is one of two instructions that are affected since they are
784 // the only instructions that don't read the lower 32-bits.
785 // We therefore pretend that it reads the bottom 32-bits to
786 // artificially create a dependency and prevent the scheduler
787 // changing the behaviour of the code.
788 BuildMI(MBB, I, dl,
789 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
790 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
791 DstReg)
792 .addReg(SrcReg);
793 } else
794 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
795}
796
797void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
798 MachineBasicBlock::iterator I,
799 bool isMicroMips, bool FP64) const {
800 Register DstReg = I->getOperand(0).getReg();
801 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
802 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
803 DebugLoc dl = I->getDebugLoc();
804 const TargetRegisterInfo &TRI = getRegisterInfo();
805
806 // When mthc1 is available, use:
807 // mtc1 Lo, $fp
808 // mthc1 Hi, $fp
809 //
810 // Otherwise, for FPXX/FP64:
811 // spill + reload via ldc1
812 // This case is handled by the frame lowering code.
813 //
814 // Otherwise, for FP32:
815 // mtc1 Lo, $fp
816 // mtc1 Hi, $fp + 1
817 //
818 // The case where 64-bit GPRs can be used doesn't need to be handled here
819 // because it never creates a BuildPairF64 node.
820
821 // FPXX/FP64 without MTHC1 should have been handled with a spill/reload
822 // in MipsSEFrameLowering.cpp.
823 assert(!((Subtarget.isABI_FPXX() || FP64) && !Subtarget.hasMTHC1()));
824
825 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
826 // in MipsSEFrameLowering.cpp.
827 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
828
829 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
830 .addReg(LoReg);
831
832 if (Subtarget.hasMTHC1()) {
833 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
834 // around a widespread bug in the -mfp64 support.
835 // The problem is that none of the 32-bit fpu ops mention the fact
836 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
837 // requires a major overhaul of the FPU implementation which can't
838 // be done right now due to time constraints.
839 // MTHC1 is one of two instructions that are affected since they are
840 // the only instructions that don't read the lower 32-bits.
841 // We therefore pretend that it reads the bottom 32-bits to
842 // artificially create a dependency and prevent the scheduler
843 // changing the behaviour of the code.
844 BuildMI(MBB, I, dl,
845 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
846 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
847 DstReg)
848 .addReg(DstReg)
849 .addReg(HiReg);
850 } else if (Subtarget.isABI_FPXX())
851 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
852 else
853 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
854 .addReg(HiReg);
855}
856
857void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
858 MachineBasicBlock::iterator I) const {
859 // This pseudo instruction is generated as part of the lowering of
860 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
861 // indirect jump to TargetReg
862 MipsABIInfo ABI = Subtarget.getABI();
863 unsigned ADDU = ABI.GetPtrAdduOp();
864 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
865 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
866 unsigned T9 = ABI.getTempReg(9, Subtarget.isGP64bit());
867 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
868 Register OffsetReg = I->getOperand(0).getReg();
869 Register TargetReg = I->getOperand(1).getReg();
870
871 // addu $ra, $v0, $zero
872 // addu $sp, $sp, $v1
873 // jr $ra (via RetRA)
874 const TargetMachine &TM = MBB.getParent()->getTarget();
875 if (TM.isPositionIndependent())
876 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
877 .addReg(TargetReg)
878 .addReg(ZERO);
879 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
880 .addReg(TargetReg)
881 .addReg(ZERO);
882 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
883 expandRetRA(MBB, I);
884}
885
886const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
887 return new MipsSEInstrInfo(STI);
888}
getRegClass
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
Definition AArch64InstrInfo.cpp:5518
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:539
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
BlockExecWeight::ZERO
@ ZERO
Special weight used for cases with exact zero probability.
Definition BranchProbabilityInfo.cpp:146
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:863
I
#define I(x, y, z)
Definition MD5.cpp:57
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
isORCopyInst
static bool isORCopyInst(const MachineInstr &MI)
Definition MipsSEInstrInfo.cpp:179
getUnconditionalBranch
static unsigned getUnconditionalBranch(const MipsSubtarget &STI)
Definition MipsSEInstrInfo.cpp:24
isMicroMips
static bool isMicroMips(const MCSubtargetInfo *STI)
Definition MipsTargetStreamer.cpp:34
II
uint64_t IntrinsicInst * II
Definition NVVMIntrRange.cpp:46
RA
SI optimize exec mask operations pre RA
Definition SIOptimizeExecMaskingPreRA.cpp:77
contains
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition Value.cpp:484
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:322
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:340
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition MachineFunction.h:774
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition MachineInstrBuilder.h:254
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition MachineInstrBuilder.h:304
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:141
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition MachineMemOperand.h:148
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition MachineMemOperand.h:150
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition MachineOperand.h:375
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:55
llvm::MipsAnalyzeImmediate::Analyze
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
Definition MipsAnalyzeImmediate.cpp:129
llvm::MipsAnalyzeImmediate::InstSeq
SmallVector< Inst, 7 > InstSeq
Definition MipsAnalyzeImmediate.h:24
llvm::MipsInstrInfo::Subtarget
const MipsSubtarget & Subtarget
Definition MipsInstrInfo.h:46
llvm::MipsInstrInfo::GetMemOperand
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Definition MipsInstrInfo.cpp:95
llvm::MipsInstrInfo::isZeroImm
bool isZeroImm(const MachineOperand &op) const
Definition MipsInstrInfo.cpp:60
llvm::MipsInstrInfo::MipsInstrInfo
MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)
Definition MipsInstrInfo.cpp:42
llvm::MipsSEInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Definition MipsSEInstrInfo.cpp:76
llvm::MipsSEInstrInfo::isLoadFromStackSlot
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition MipsSEInstrInfo.cpp:38
llvm::MipsSEInstrInfo::isStoreToStackSlot
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition MipsSEInstrInfo.cpp:60
llvm::MipsSEInstrInfo::adjustStackPtr
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
Definition MipsSEInstrInfo.cpp:558
llvm::MipsSEInstrInfo::isCopyInstrImpl
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition MipsSEInstrInfo.cpp:200
llvm::MipsSEInstrInfo::loadImmediate
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
Definition MipsSEInstrInfo.cpp:586
llvm::MipsSEInstrInfo::isBranchWithImm
bool isBranchWithImm(unsigned Opc) const override
isBranchWithImm - Return true if the branch contains an immediate operand (
Definition MipsSEInstrInfo.cpp:457
llvm::MipsSEInstrInfo::MipsSEInstrInfo
MipsSEInstrInfo(const MipsSubtarget &STI)
Definition MipsSEInstrInfo.cpp:30
llvm::MipsSEInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition MipsSEInstrInfo.cpp:369
llvm::MipsSEInstrInfo::loadRegFromStack
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition MipsSEInstrInfo.cpp:282
llvm::MipsSEInstrInfo::storeRegToStack
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition MipsSEInstrInfo.cpp:207
llvm::MipsSEInstrInfo::getOppositeBranchOpc
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
Definition MipsSEInstrInfo.cpp:471
llvm::MipsSEInstrInfo::getRegisterInfo
const MipsSERegisterInfo & getRegisterInfo() const
Definition MipsSEInstrInfo.h:27
llvm::MipsSubtarget::inMicroMipsMode
bool inMicroMipsMode() const
Definition MipsSubtarget.h:338
llvm::MipsSubtarget::isPositionIndependent
bool isPositionIndependent() const
Definition MipsSubtarget.cpp:201
llvm::MipsSubtarget::isGP64bit
bool isGP64bit() const
Definition MipsSubtarget.h:318
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition TargetMachine.cpp:174
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:35
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::createMipsSEInstrInfo
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
Definition MipsSEInstrInfo.cpp:886
llvm::RegState
RegState
Flags to represent properties of register accesses.
Definition MachineInstrBuilder.h:50
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition MachineInstrBuilder.h:59
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:25
llvm::get
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Definition PointerIntPair.h:256
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:567
llvm::TargetRegisterClass
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
N
#define N
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