LLVM 22.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63#ifndef NDEBUG
64 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
65 unsigned Size = 0;
66 for (auto &MBB : MF)
67 for (auto &MI : MBB)
68 Size += TII->getInstSizeInBytes(MI);
69 return Size;
70 }
71#endif
72};
73
74char RISCVExpandPseudo::ID = 0;
75
76bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
77 STI = &MF.getSubtarget<RISCVSubtarget>();
78 TII = STI->getInstrInfo();
79
80#ifndef NDEBUG
81 const unsigned OldSize = getInstSizeInBytes(MF);
82#endif
83
84 bool Modified = false;
85 for (auto &MBB : MF)
86 Modified |= expandMBB(MBB);
87
88#ifndef NDEBUG
89 const unsigned NewSize = getInstSizeInBytes(MF);
90 assert(OldSize >= NewSize);
91#endif
92 return Modified;
93}
94
95bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
96 bool Modified = false;
97
98 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
99 while (MBBI != E) {
100 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
101 Modified |= expandMI(MBB, MBBI, NMBBI);
102 MBBI = NMBBI;
103 }
104
105 return Modified;
106}
107
108bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI,
110 MachineBasicBlock::iterator &NextMBBI) {
111 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
112 // expanded instructions for each pseudo is correct in the Size field of the
113 // tablegen definition for the pseudo.
114 switch (MBBI->getOpcode()) {
115 case RISCV::PseudoMV_FPR16INX:
116 return expandMV_FPR16INX(MBB, MBBI);
117 case RISCV::PseudoMV_FPR32INX:
118 return expandMV_FPR32INX(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxSD:
120 return expandRV32ZdinxStore(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxLD:
122 return expandRV32ZdinxLoad(MBB, MBBI);
123 case RISCV::PseudoCCMOVGPRNoX0:
124 case RISCV::PseudoCCMOVGPR:
125 case RISCV::PseudoCCADD:
126 case RISCV::PseudoCCSUB:
127 case RISCV::PseudoCCAND:
128 case RISCV::PseudoCCOR:
129 case RISCV::PseudoCCXOR:
130 case RISCV::PseudoCCMAX:
131 case RISCV::PseudoCCMAXU:
132 case RISCV::PseudoCCMIN:
133 case RISCV::PseudoCCMINU:
134 case RISCV::PseudoCCMUL:
135 case RISCV::PseudoCCADDW:
136 case RISCV::PseudoCCSUBW:
137 case RISCV::PseudoCCSLL:
138 case RISCV::PseudoCCSRL:
139 case RISCV::PseudoCCSRA:
140 case RISCV::PseudoCCADDI:
141 case RISCV::PseudoCCSLLI:
142 case RISCV::PseudoCCSRLI:
143 case RISCV::PseudoCCSRAI:
144 case RISCV::PseudoCCANDI:
145 case RISCV::PseudoCCORI:
146 case RISCV::PseudoCCXORI:
147 case RISCV::PseudoCCSLLW:
148 case RISCV::PseudoCCSRLW:
149 case RISCV::PseudoCCSRAW:
150 case RISCV::PseudoCCADDIW:
151 case RISCV::PseudoCCSLLIW:
152 case RISCV::PseudoCCSRLIW:
153 case RISCV::PseudoCCSRAIW:
154 case RISCV::PseudoCCANDN:
155 case RISCV::PseudoCCORN:
156 case RISCV::PseudoCCXNOR:
157 case RISCV::PseudoCCNDS_BFOS:
158 case RISCV::PseudoCCNDS_BFOZ:
159 return expandCCOp(MBB, MBBI, NextMBBI);
160 case RISCV::PseudoVMCLR_M_B1:
161 case RISCV::PseudoVMCLR_M_B2:
162 case RISCV::PseudoVMCLR_M_B4:
163 case RISCV::PseudoVMCLR_M_B8:
164 case RISCV::PseudoVMCLR_M_B16:
165 case RISCV::PseudoVMCLR_M_B32:
166 case RISCV::PseudoVMCLR_M_B64:
167 // vmclr.m vd => vmxor.mm vd, vd, vd
168 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
169 case RISCV::PseudoVMSET_M_B1:
170 case RISCV::PseudoVMSET_M_B2:
171 case RISCV::PseudoVMSET_M_B4:
172 case RISCV::PseudoVMSET_M_B8:
173 case RISCV::PseudoVMSET_M_B16:
174 case RISCV::PseudoVMSET_M_B32:
175 case RISCV::PseudoVMSET_M_B64:
176 // vmset.m vd => vmxnor.mm vd, vd, vd
177 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
178 case RISCV::PseudoReadVLENBViaVSETVLIX0:
179 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
180 }
181
182 return false;
183}
184
185bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MBBI,
187 MachineBasicBlock::iterator &NextMBBI) {
188 // First try expanding to a Conditional Move rather than a branch+mv
189 if (expandCCOpToCMov(MBB, MBBI))
190 return true;
191
192 MachineFunction *MF = MBB.getParent();
193 MachineInstr &MI = *MBBI;
194 DebugLoc DL = MI.getDebugLoc();
195
196 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
197 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
198
199 MF->insert(++MBB.getIterator(), TrueBB);
200 MF->insert(++TrueBB->getIterator(), MergeBB);
201
202 // We want to copy the "true" value when the condition is true which means
203 // we need to invert the branch condition to jump over TrueBB when the
204 // condition is false.
205 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
206 CC = RISCVCC::getInverseBranchCondition(CC);
207
208 // Insert branch instruction.
209 BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
210 .addReg(MI.getOperand(1).getReg())
211 .addReg(MI.getOperand(2).getReg())
212 .addMBB(MergeBB);
213
214 Register DestReg = MI.getOperand(0).getReg();
215 assert(MI.getOperand(4).getReg() == DestReg);
216
217 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
218 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
219 // Add MV.
220 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
221 .add(MI.getOperand(5))
222 .addImm(0);
223 } else {
224 unsigned NewOpc;
225 // clang-format off
226 switch (MI.getOpcode()) {
227 default:
228 llvm_unreachable("Unexpected opcode!");
229 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
230 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
231 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
232 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
233 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
234 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
235 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
236 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
237 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
238 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
239 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
240 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
241 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
242 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
243 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
244 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
245 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
246 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
247 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
248 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
249 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
250 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
251 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
252 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
253 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
254 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
255 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
256 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
257 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
258 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
259 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
260 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
261 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
262 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
263 }
264 // clang-format on
265
266 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
267 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
268 .add(MI.getOperand(5))
269 .add(MI.getOperand(6))
270 .add(MI.getOperand(7));
271 } else {
272 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
273 .add(MI.getOperand(5))
274 .add(MI.getOperand(6));
275 }
276 }
277
278 TrueBB->addSuccessor(MergeBB);
279
280 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
281 MergeBB->transferSuccessors(&MBB);
282
283 MBB.addSuccessor(TrueBB);
284 MBB.addSuccessor(MergeBB);
285
286 NextMBBI = MBB.end();
287 MI.eraseFromParent();
288
289 // Make sure live-ins are correctly attached to this new basic block.
290 LivePhysRegs LiveRegs;
291 computeAndAddLiveIns(LiveRegs, *TrueBB);
292 computeAndAddLiveIns(LiveRegs, *MergeBB);
293
294 return true;
295}
296
297bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator MBBI) {
299 MachineInstr &MI = *MBBI;
300 DebugLoc DL = MI.getDebugLoc();
301
302 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
303 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
304 return false;
305
306 if (!STI->hasVendorXqcicm())
307 return false;
308
309 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
310 if (MI.getOperand(1).getReg() == RISCV::X0 ||
311 MI.getOperand(4).getReg() == RISCV::X0 ||
312 MI.getOperand(5).getReg() == RISCV::X0)
313 return false;
314
315 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
316
317 unsigned CMovOpcode, CMovIOpcode;
318 switch (CC) {
319 default:
320 llvm_unreachable("Unhandled CC");
321 case RISCVCC::COND_EQ:
322 CMovOpcode = RISCV::QC_MVEQ;
323 CMovIOpcode = RISCV::QC_MVEQI;
324 break;
325 case RISCVCC::COND_NE:
326 CMovOpcode = RISCV::QC_MVNE;
327 CMovIOpcode = RISCV::QC_MVNEI;
328 break;
329 case RISCVCC::COND_LT:
330 CMovOpcode = RISCV::QC_MVLT;
331 CMovIOpcode = RISCV::QC_MVLTI;
332 break;
333 case RISCVCC::COND_GE:
334 CMovOpcode = RISCV::QC_MVGE;
335 CMovIOpcode = RISCV::QC_MVGEI;
336 break;
337 case RISCVCC::COND_LTU:
338 CMovOpcode = RISCV::QC_MVLTU;
339 CMovIOpcode = RISCV::QC_MVLTUI;
340 break;
341 case RISCVCC::COND_GEU:
342 CMovOpcode = RISCV::QC_MVGEU;
343 CMovIOpcode = RISCV::QC_MVGEUI;
344 break;
345 }
346
347 if (MI.getOperand(2).getReg() == RISCV::X0) {
348 // $dst = PseudoCCMOVGPR $lhs, X0, $cc, $falsev (=$dst), $truev
349 // $dst = PseudoCCMOVGPRNoX0 $lhs, X0, $cc, $falsev (=$dst), $truev
350 // =>
351 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
352 BuildMI(MBB, MBBI, DL, TII->get(CMovIOpcode))
353 .addDef(MI.getOperand(0).getReg())
354 .addReg(MI.getOperand(4).getReg())
355 .addReg(MI.getOperand(1).getReg())
356 .addImm(0)
357 .addReg(MI.getOperand(5).getReg());
358
359 MI.eraseFromParent();
360 return true;
361 }
362
363 // $dst = PseudoCCMOVGPR $lhs, $rhs, $cc, $falsev (=$dst), $truev
364 // $dst = PseudoCCMOVGPRNoX0 $lhs, $rhs, $cc, $falsev (=$dst), $truev
365 // =>
366 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
367 BuildMI(MBB, MBBI, DL, TII->get(CMovOpcode))
368 .addDef(MI.getOperand(0).getReg())
369 .addReg(MI.getOperand(4).getReg())
370 .addReg(MI.getOperand(1).getReg())
371 .addReg(MI.getOperand(2).getReg())
372 .addReg(MI.getOperand(5).getReg());
373 MI.eraseFromParent();
374 return true;
375}
376
377bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator MBBI,
379 unsigned Opcode) {
380 DebugLoc DL = MBBI->getDebugLoc();
381 Register DstReg = MBBI->getOperand(0).getReg();
382 const MCInstrDesc &Desc = TII->get(Opcode);
383 BuildMI(MBB, MBBI, DL, Desc, DstReg)
384 .addReg(DstReg, RegState::Undef)
385 .addReg(DstReg, RegState::Undef);
386 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
387 return true;
388}
389
390bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator MBBI) {
392 DebugLoc DL = MBBI->getDebugLoc();
393 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
394 Register DstReg = TRI->getMatchingSuperReg(
395 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
396 Register SrcReg = TRI->getMatchingSuperReg(
397 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
398
399 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
400 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
401 .addImm(0);
402
403 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
404 return true;
405}
406
407bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
408 MachineBasicBlock::iterator MBBI) {
409 DebugLoc DL = MBBI->getDebugLoc();
410 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
411 Register DstReg = TRI->getMatchingSuperReg(
412 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
413 Register SrcReg = TRI->getMatchingSuperReg(
414 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
415
416 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
417 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
418 .addImm(0);
419
420 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
421 return true;
422}
423
424// This function expands the PseudoRV32ZdinxSD for storing a double-precision
425// floating-point value into memory by generating an equivalent instruction
426// sequence for RV32.
427bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator MBBI) {
429 DebugLoc DL = MBBI->getDebugLoc();
430 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
431 Register Lo =
432 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
433 Register Hi =
434 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
435 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
436 Hi = RISCV::X0;
437
438 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
439 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
440 .addReg(MBBI->getOperand(1).getReg())
441 .add(MBBI->getOperand(2));
442
443 MachineInstrBuilder MIBHi;
444 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
445 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
446 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
447 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
448 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
449 .add(MBBI->getOperand(1))
450 .add(MBBI->getOperand(2));
451 } else {
452 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
453 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
454 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
455 .add(MBBI->getOperand(1))
456 .addImm(MBBI->getOperand(2).getImm() + 4);
457 }
458
459 MachineFunction *MF = MBB.getParent();
460 SmallVector<MachineMemOperand *> NewLoMMOs;
461 SmallVector<MachineMemOperand *> NewHiMMOs;
462 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
463 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
464 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
465 }
466 MIBLo.setMemRefs(NewLoMMOs);
467 MIBHi.setMemRefs(NewHiMMOs);
468
469 MBBI->eraseFromParent();
470 return true;
471}
472
473// This function expands PseudoRV32ZdinxLoad for loading a double-precision
474// floating-point value from memory into an equivalent instruction sequence for
475// RV32.
476bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
477 MachineBasicBlock::iterator MBBI) {
478 DebugLoc DL = MBBI->getDebugLoc();
479 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
480 Register Lo =
481 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
482 Register Hi =
483 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
484 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
485
486 MachineInstrBuilder MIBLo, MIBHi;
487
488 // If the register of operand 1 is equal to the Lo register, then swap the
489 // order of loading the Lo and Hi statements.
490 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
491 // Order: Lo, Hi
492 if (!IsOp1EqualToLo) {
493 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
494 .addReg(MBBI->getOperand(1).getReg())
495 .add(MBBI->getOperand(2));
496 }
497
498 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
499 auto Offset = MBBI->getOperand(2).getOffset();
500 assert(Offset % 8 == 0);
501 MBBI->getOperand(2).setOffset(Offset + 4);
502 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
503 .addReg(MBBI->getOperand(1).getReg())
504 .add(MBBI->getOperand(2));
505 MBBI->getOperand(2).setOffset(Offset);
506 } else {
507 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
508 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
509 .addReg(MBBI->getOperand(1).getReg())
510 .addImm(MBBI->getOperand(2).getImm() + 4);
511 }
512
513 // Order: Hi, Lo
514 if (IsOp1EqualToLo) {
515 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
516 .addReg(MBBI->getOperand(1).getReg())
517 .add(MBBI->getOperand(2));
518 }
519
520 MachineFunction *MF = MBB.getParent();
521 SmallVector<MachineMemOperand *> NewLoMMOs;
522 SmallVector<MachineMemOperand *> NewHiMMOs;
523 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
524 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
525 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
526 }
527 MIBLo.setMemRefs(NewLoMMOs);
528 MIBHi.setMemRefs(NewHiMMOs);
529
530 MBBI->eraseFromParent();
531 return true;
532}
533
534bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
535 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
536 DebugLoc DL = MBBI->getDebugLoc();
537 Register Dst = MBBI->getOperand(0).getReg();
538 unsigned Mul = MBBI->getOperand(1).getImm();
539 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
540 unsigned VTypeImm = RISCVVType::encodeVTYPE(
541 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
542
543 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
544 .addReg(Dst, RegState::Define)
545 .addReg(RISCV::X0, RegState::Kill)
546 .addImm(VTypeImm);
547
548 MBBI->eraseFromParent();
549 return true;
550}
551
552class RISCVPreRAExpandPseudo : public MachineFunctionPass {
553public:
554 const RISCVSubtarget *STI;
555 const RISCVInstrInfo *TII;
556 static char ID;
557
558 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
559
560 bool runOnMachineFunction(MachineFunction &MF) override;
561
562 void getAnalysisUsage(AnalysisUsage &AU) const override {
563 AU.setPreservesCFG();
564 MachineFunctionPass::getAnalysisUsage(AU);
565 }
566 StringRef getPassName() const override {
567 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
568 }
569
570private:
571 bool expandMBB(MachineBasicBlock &MBB);
572 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
573 MachineBasicBlock::iterator &NextMBBI);
574 bool expandAuipcInstPair(MachineBasicBlock &MBB,
575 MachineBasicBlock::iterator MBBI,
576 MachineBasicBlock::iterator &NextMBBI,
577 unsigned FlagsHi, unsigned SecondOpcode);
578 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator MBBI,
580 MachineBasicBlock::iterator &NextMBBI);
581 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
582 MachineBasicBlock::iterator MBBI,
583 MachineBasicBlock::iterator &NextMBBI);
584 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
585 MachineBasicBlock::iterator MBBI,
586 MachineBasicBlock::iterator &NextMBBI);
587 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
588 MachineBasicBlock::iterator MBBI,
589 MachineBasicBlock::iterator &NextMBBI);
590 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
591 MachineBasicBlock::iterator MBBI,
592 MachineBasicBlock::iterator &NextMBBI);
593
594#ifndef NDEBUG
595 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
596 unsigned Size = 0;
597 for (auto &MBB : MF)
598 for (auto &MI : MBB)
599 Size += TII->getInstSizeInBytes(MI);
600 return Size;
601 }
602#endif
603};
604
605char RISCVPreRAExpandPseudo::ID = 0;
606
607bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
608 STI = &MF.getSubtarget<RISCVSubtarget>();
609 TII = STI->getInstrInfo();
610
611#ifndef NDEBUG
612 const unsigned OldSize = getInstSizeInBytes(MF);
613#endif
614
615 bool Modified = false;
616 for (auto &MBB : MF)
617 Modified |= expandMBB(MBB);
618
619#ifndef NDEBUG
620 const unsigned NewSize = getInstSizeInBytes(MF);
621 assert(OldSize >= NewSize);
622#endif
623 return Modified;
624}
625
626bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
627 bool Modified = false;
628
629 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
630 while (MBBI != E) {
631 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
632 Modified |= expandMI(MBB, MBBI, NMBBI);
633 MBBI = NMBBI;
634 }
635
636 return Modified;
637}
638
639bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
640 MachineBasicBlock::iterator MBBI,
641 MachineBasicBlock::iterator &NextMBBI) {
642
643 switch (MBBI->getOpcode()) {
644 case RISCV::PseudoLLA:
645 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
646 case RISCV::PseudoLGA:
647 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
648 case RISCV::PseudoLA_TLS_IE:
649 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
650 case RISCV::PseudoLA_TLS_GD:
651 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
652 case RISCV::PseudoLA_TLSDESC:
653 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
654 }
655 return false;
656}
657
658bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
659 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
660 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
661 unsigned SecondOpcode) {
662 MachineFunction *MF = MBB.getParent();
663 MachineInstr &MI = *MBBI;
664 DebugLoc DL = MI.getDebugLoc();
665
666 Register DestReg = MI.getOperand(0).getReg();
667 Register ScratchReg =
668 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
669
670 MachineOperand &Symbol = MI.getOperand(1);
671 Symbol.setTargetFlags(FlagsHi);
672 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
673
674 MachineInstr *MIAUIPC =
675 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
676 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
677
678 MachineInstr *SecondMI =
679 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
680 .addReg(ScratchReg)
681 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
682
683 if (MI.hasOneMemOperand())
684 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
685
686 MI.eraseFromParent();
687 return true;
688}
689
690bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
691 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
692 MachineBasicBlock::iterator &NextMBBI) {
693 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
694 RISCV::ADDI);
695}
696
697bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
698 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
699 MachineBasicBlock::iterator &NextMBBI) {
700 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
701 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
702 SecondOpcode);
703}
704
705bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
706 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
707 MachineBasicBlock::iterator &NextMBBI) {
708 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
709 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
710 SecondOpcode);
711}
712
713bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
714 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
715 MachineBasicBlock::iterator &NextMBBI) {
716 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
717 RISCV::ADDI);
718}
719
720bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
721 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
722 MachineBasicBlock::iterator &NextMBBI) {
723 MachineFunction *MF = MBB.getParent();
724 MachineInstr &MI = *MBBI;
725 DebugLoc DL = MI.getDebugLoc();
726
727 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
728 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
729
730 Register FinalReg = MI.getOperand(0).getReg();
731 Register DestReg =
732 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
733 Register ScratchReg =
734 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
735
736 MachineOperand &Symbol = MI.getOperand(1);
737 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
738 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
739
740 MachineInstr *MIAUIPC =
741 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
742 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
743
744 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
745 .addReg(ScratchReg)
746 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
747
748 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
749 .addReg(ScratchReg)
750 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
751
752 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
753 .addReg(DestReg)
754 .addImm(0)
755 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
756
757 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
758 .addReg(RISCV::X10)
759 .addReg(RISCV::X4);
760
761 MI.eraseFromParent();
762 return true;
763}
764
765} // end of anonymous namespace
766
767INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
768 RISCV_EXPAND_PSEUDO_NAME, false, false)
769
770INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
771 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
772
773namespace llvm {
774
775FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
776FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
777
778} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2118
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:124
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:395
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:210
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:935
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:816
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1156
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:341
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:184
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:762
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:536
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:719
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:772
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:499
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1003
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:237
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:160
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:253
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:295
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:126
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:175
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:145
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:478
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:383
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:48
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:142
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:141
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:19
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:417
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1203
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:381
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVCC::getInverseBranchCondition
CondCode getInverseBranchCondition(CondCode)
Definition RISCVInstrInfo.cpp:1168
llvm::RISCVCC::getBrCond
unsigned getBrCond(CondCode CC, unsigned SelectOpc=0)
Definition RISCVInstrInfo.cpp:1057
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:113
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:161
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:47
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:51
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:55
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:369
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:165
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:998
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition MachineInstrBuilder.h:543
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:775
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:776
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