LLVM 24.0.0git
Namespaces | Macros | Enumerations | Functions
RISCVInstrInfo.cpp File Reference
#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
namespace  llvm::RISCVVPseudosTable
namespace  llvm::RISCV

Macros

#define GEN_CHECK_COMPRESS_INSTR
#define GET_INSTRINFO_CTOR_DTOR
#define DEBUG_TYPE   "riscv-instr-info"
#define GET_RISCVVPseudosTable_IMPL
#define GET_RISCVMaskedPseudosTable_IMPL
#define GET_INSTRINFO_HELPERS
#define OPCODE_LMUL_CASE(OPC)
#define OPCODE_LMUL_MASK_CASE(OPC)
#define RVV_OPC_LMUL_CASE(OPC, INV)
#define RVV_OPC_LMUL_MASK_CASE(OPC, INV)
#define CASE_OPERAND_UIMM(NUM)
#define CASE_OPERAND_UIMM_LSB_ZEROS(BITS, SUFFIX)
#define CASE_OPERAND_SIMM(NUM)
#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP)
#define CASE_RVV_OPCODE_UNMASK(OP)
#define CASE_RVV_OPCODE_MASK_WIDEN(OP)
#define CASE_RVV_OPCODE_MASK(OP)
#define CASE_RVV_OPCODE_WIDEN(OP)
#define CASE_RVV_OPCODE(OP)
#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL)
#define CASE_VMA_OPCODE_LMULS(OP, TYPE)
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW)
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_VV(OP)
#define CASE_VFMA_SPLATS(OP)
#define CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP)
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
#define CASE_WIDEOP_OPCODE_LMULS(OP)
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW)
#define CASE_FP_WIDEOP_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_OPCODE_LMULS_ALT(OP)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT(OP)

Enumerations

enum  MachineOutlinerConstructionID { MachineOutlinerTailCall , MachineOutlinerDefault , MachineOutlinerRegSave }

Functions

 STATISTIC (NumVRegSpilled, "Number of registers within vector register groups spilled")
 STATISTIC (NumVRegReloaded, "Number of registers within vector register groups reloaded")
static std::optional< unsigned > getLMULForRVVWholeLoadStore (unsigned Opcode)
static bool forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
static bool isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVVType::VLMUL LMul)
std::optional< unsigned > getFoldedOpcode (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, const RISCVSubtarget &ST)
static unsigned getLoadPredicatedOpcode (unsigned Opcode)
static void parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned getInverseXqcicmOpcode (unsigned Opcode)
static bool isLoadImm (const MachineInstr *MI, int64_t &Imm)
static bool isJumpTableLoad (const MachineInstr &MI)
static int getJumpTableIndexFromBase (const MachineRegisterInfo &MRI, Register Reg)
static int getJumpTableIndexFromLoadAddr (const MachineRegisterInfo &MRI, Register Reg)
unsigned getPredicatedOpcode (unsigned Opcode)
static MachineInstr * canFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII, const RISCVSubtarget &STI)
 Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.
static bool isFADD (unsigned Opc)
static bool isFSUB (unsigned Opc)
static bool isFMUL (unsigned Opc)
static bool canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
static bool getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static bool getFPPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static const MachineInstr * canCombine (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned CombineOpc)
 Utility routine that checks if.
static bool canCombineShiftIntoShXAdd (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned OuterShiftAmt)
 Utility routine that checks if.
static unsigned getSHXADDShiftAmount (unsigned Opc)
static unsigned getSHXADDUWShiftAmount (unsigned Opc)
static bool getSHXADDPatterns (const MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static unsigned getFPFusedMultiplyOpcode (unsigned RootOpc, unsigned Pattern)
static unsigned getAddendOperandIdx (unsigned Pattern)
static void combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
static void genShXAddAddShift (MachineInstr &Root, unsigned AddOpIdx, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg)
static bool memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
static bool isCandidatePatchable (const MachineBasicBlock &MBB)
static bool isMIReadsReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)
static bool isMIModifiesReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)
static bool cannotInsertTailCall (const MachineBasicBlock &MBB)
static Register findRegisterToSaveX5To (outliner::Candidate &C, const TargetRegisterInfo &TRI)
static std::optional< int64_t > getEffectiveImm (const MachineRegisterInfo &MRI, const MachineOperand &MO)

Macro Definition Documentation

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON ( OP,
LMUL,
SEW )
Value:
case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED: \
NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW; \
break;
_
#define _
Definition HexagonMCCodeEmitter.cpp:46
OP
#define OP(OPC)
Definition Instruction.h:46

Definition at line 4993 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS ( OP)
Value:
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON
#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)
Definition RISCVInstrInfo.cpp:4993
llvm::M1
unsigned M1(unsigned Val)
Definition VE.h:377

Definition at line 4998 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT ( OP)
Value:
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16)

Definition at line 5016 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_OPCODE_COMMON

#define CASE_FP_WIDEOP_OPCODE_COMMON ( OP,
LMUL,
SEW )
Value:
RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED

Definition at line 4979 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_OPCODE_LMULS

#define CASE_FP_WIDEOP_OPCODE_LMULS ( OP)
Value:
CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E32): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32) \
CASE_FP_WIDEOP_OPCODE_COMMON
#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW)
Definition RISCVInstrInfo.cpp:4979

Definition at line 4982 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_OPCODE_LMULS_ALT

#define CASE_FP_WIDEOP_OPCODE_LMULS_ALT ( OP)
Value:
CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16)

Definition at line 5009 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_OPERAND_SIMM

#define CASE_OPERAND_SIMM ( NUM)
Value:
case RISCVOp::OPERAND_SIMM##NUM: \
Ok = isInt<NUM>(Imm); \
break;
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:539
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166

Referenced by llvm::RISCVInstrInfo::verifyInstruction().

◆ CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM ( NUM)
Value:
case RISCVOp::OPERAND_UIMM##NUM: \
Ok = isUInt<NUM>(Imm); \
break;
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190

Referenced by llvm::RISCVInstrInfo::verifyInstruction().

◆ CASE_OPERAND_UIMM_LSB_ZEROS

#define CASE_OPERAND_UIMM_LSB_ZEROS ( BITS,
SUFFIX )
Value:
case RISCVOp::OPERAND_UIMM##BITS##_LSB##SUFFIX: { \
constexpr size_t NumZeros = sizeof(#SUFFIX) - 1; \
Ok = isShiftedUInt<BITS - NumZeros, NumZeros>(Imm); \
break; \
}
llvm::isShiftedUInt
constexpr bool isShiftedUInt(uint64_t x)
Checks if a unsigned integer is an N bit number shifted left by S.
Definition MathExtras.h:199

Referenced by llvm::RISCVInstrInfo::verifyInstruction().

◆ CASE_RVV_OPCODE

#define CASE_RVV_OPCODE ( OP)
Value:
CASE_RVV_OPCODE_UNMASK(OP): \
case CASE_RVV_OPCODE_MASK(OP)
CASE_RVV_OPCODE_UNMASK
#define CASE_RVV_OPCODE_UNMASK(OP)
Definition RISCVInstrInfo.cpp:4238
CASE_RVV_OPCODE_MASK
#define CASE_RVV_OPCODE_MASK(OP)
Definition RISCVInstrInfo.cpp:4250

Definition at line 4258 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_RVV_OPCODE_LMUL

#define CASE_RVV_OPCODE_LMUL ( OP,
LMUL )
Value:
CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
CASE_RVV_OPCODE_UNMASK_LMUL
#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)
Definition RISCVInstrInfo.cpp:4220
CASE_RVV_OPCODE_MASK_LMUL
#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
Definition RISCVInstrInfo.cpp:4223

Definition at line 4226 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_RVV_OPCODE_MASK

#define CASE_RVV_OPCODE_MASK ( OP)
Value:
CASE_RVV_OPCODE_MASK_WIDEN(OP): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, M8)
CASE_RVV_OPCODE_MASK_WIDEN
#define CASE_RVV_OPCODE_MASK_WIDEN(OP)
Definition RISCVInstrInfo.cpp:4242

Definition at line 4250 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_RVV_OPCODE_MASK_LMUL

#define CASE_RVV_OPCODE_MASK_LMUL ( OP,
LMUL )
Value:
RISCV::Pseudo##OP##_##LMUL##_MASK

Definition at line 4223 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_MASK_WIDEN

#define CASE_RVV_OPCODE_MASK_WIDEN ( OP)
Value:
CASE_RVV_OPCODE_MASK_LMUL(OP, MF8): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, MF4): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, MF2): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, M1): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, M2): \
case CASE_RVV_OPCODE_MASK_LMUL(OP, M4)

Definition at line 4242 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_UNMASK

#define CASE_RVV_OPCODE_UNMASK ( OP)
Value:
CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M8)
CASE_RVV_OPCODE_UNMASK_WIDEN
#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP)
Definition RISCVInstrInfo.cpp:4230

Definition at line 4238 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_RVV_OPCODE_UNMASK_LMUL

#define CASE_RVV_OPCODE_UNMASK_LMUL ( OP,
LMUL )
Value:
RISCV::Pseudo##OP##_##LMUL

Definition at line 4220 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_UNMASK_WIDEN

#define CASE_RVV_OPCODE_UNMASK_WIDEN ( OP)
Value:
CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF8): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF4): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF2): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M1): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M2): \
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M4)

Definition at line 4230 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_WIDEN

#define CASE_RVV_OPCODE_WIDEN ( OP)
Value:
CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
case CASE_RVV_OPCODE_MASK_WIDEN(OP)

Definition at line 4254 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON ( OLDOP,
NEWOP,
TYPE,
LMUL,
SEW )
Value:
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW: \
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_##SEW; \
break;

Definition at line 4519 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1 ( OLDOP,
NEWOP,
TYPE,
SEW )
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1, SEW) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2, SEW) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4, SEW) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8, SEW)
CASE_VFMA_CHANGE_OPCODE_COMMON
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)
Definition RISCVInstrInfo.cpp:4519

Definition at line 4524 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 ( OLDOP,
NEWOP,
TYPE,
SEW )
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)

Definition at line 4530 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( OLDOP,
NEWOP,
TYPE,
SEW )
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)

Definition at line 4534 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS ( OLDOP,
NEWOP )
Value:
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VFPR16, E16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32, E32) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64, E64)
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)
Definition RISCVInstrInfo.cpp:4534

Definition at line 4544 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VFMA_CHANGE_OPCODE_VV

#define CASE_VFMA_CHANGE_OPCODE_VV ( OLDOP,
NEWOP )
Value:
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VV, E16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)

Definition at line 4538 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON ( OP,
TYPE,
LMUL,
SEW )
Value:
RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW

Definition at line 4277 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1 ( OP,
TYPE,
SEW )
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1, SEW): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2, SEW): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4, SEW): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8, SEW)
CASE_VFMA_OPCODE_COMMON
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW)
Definition RISCVInstrInfo.cpp:4277

Definition at line 4280 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2 ( OP,
TYPE,
SEW )
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2, SEW): \
case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
CASE_VFMA_OPCODE_LMULS_M1
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
Definition RISCVInstrInfo.cpp:4280

Definition at line 4286 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4 ( OP,
TYPE,
SEW )
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4, SEW): \
case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
CASE_VFMA_OPCODE_LMULS_MF2
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
Definition RISCVInstrInfo.cpp:4286

Definition at line 4290 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_VV

#define CASE_VFMA_OPCODE_VV ( OP)
Value:
CASE_VFMA_OPCODE_LMULS_MF4(OP, VV, E16): \
case CASE_VFMA_OPCODE_LMULS_MF4(OP##_ALT, VV, E16): \
case CASE_VFMA_OPCODE_LMULS_MF2(OP, VV, E32): \
case CASE_VFMA_OPCODE_LMULS_M1(OP, VV, E64)
CASE_VFMA_OPCODE_LMULS_MF4
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)
Definition RISCVInstrInfo.cpp:4290

Definition at line 4294 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl(), and llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS ( OP)
Value:
CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16, E16): \
case CASE_VFMA_OPCODE_LMULS_MF4(OP##_ALT, VFPR16, E16): \
case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32, E32): \
case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64, E64)

Definition at line 4300 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl(), and llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_VMA_CHANGE_OPCODE_COMMON

#define CASE_VMA_CHANGE_OPCODE_COMMON ( OLDOP,
NEWOP,
TYPE,
LMUL )
Value:
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
break;

Definition at line 4504 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_CHANGE_OPCODE_LMULS

#define CASE_VMA_CHANGE_OPCODE_LMULS ( OLDOP,
NEWOP,
TYPE )
Value:
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
CASE_VMA_CHANGE_OPCODE_COMMON
#define CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
Definition RISCVInstrInfo.cpp:4504

Definition at line 4509 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VMA_OPCODE_COMMON

#define CASE_VMA_OPCODE_COMMON ( OP,
TYPE,
LMUL )
Value:
RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 4264 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_OPCODE_LMULS

#define CASE_VMA_OPCODE_LMULS ( OP,
TYPE )
Value:
CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4): \
case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)
CASE_VMA_OPCODE_COMMON
#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL)
Definition RISCVInstrInfo.cpp:4264

Definition at line 4267 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl(), and llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON ( OP,
LMUL )
Value:
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
break;

Definition at line 4965 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS ( OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
CASE_WIDEOP_CHANGE_OPCODE_COMMON
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
Definition RISCVInstrInfo.cpp:4965

Definition at line 4970 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON ( OP,
LMUL )
Value:
RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 4954 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS ( OP)
Value:
CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
case CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \
case CASE_WIDEOP_OPCODE_COMMON(OP, M4)
CASE_WIDEOP_OPCODE_COMMON
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
Definition RISCVInstrInfo.cpp:4954

Definition at line 4957 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-instr-info"

Definition at line 46 of file RISCVInstrInfo.cpp.

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 40 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 43 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 73 of file RISCVInstrInfo.cpp.

◆ GET_RISCVMaskedPseudosTable_IMPL

#define GET_RISCVMaskedPseudosTable_IMPL

Definition at line 63 of file RISCVInstrInfo.cpp.

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 56 of file RISCVInstrInfo.cpp.

◆ OPCODE_LMUL_CASE

#define OPCODE_LMUL_CASE ( OPC)
Value:
case RISCV::OPC##_M1: \
case RISCV::OPC##_M2: \
case RISCV::OPC##_M4: \
case RISCV::OPC##_M8: \
case RISCV::OPC##_MF2: \
case RISCV::OPC##_MF4: \
case RISCV::OPC##_MF8

◆ OPCODE_LMUL_MASK_CASE

#define OPCODE_LMUL_MASK_CASE ( OPC)
Value:
case RISCV::OPC##_M1_MASK: \
case RISCV::OPC##_M2_MASK: \
case RISCV::OPC##_M4_MASK: \
case RISCV::OPC##_M8_MASK: \
case RISCV::OPC##_MF2_MASK: \
case RISCV::OPC##_MF4_MASK: \
case RISCV::OPC##_MF8_MASK

◆ RVV_OPC_LMUL_CASE

#define RVV_OPC_LMUL_CASE ( OPC,
INV )
Value:
case RISCV::OPC##_M1: \
return RISCV::INV##_M1; \
case RISCV::OPC##_M2: \
return RISCV::INV##_M2; \
case RISCV::OPC##_M4: \
return RISCV::INV##_M4; \
case RISCV::OPC##_M8: \
return RISCV::INV##_M8; \
case RISCV::OPC##_MF2: \
return RISCV::INV##_MF2; \
case RISCV::OPC##_MF4: \
return RISCV::INV##_MF4; \
case RISCV::OPC##_MF8: \
return RISCV::INV##_MF8

Referenced by llvm::RISCVInstrInfo::getInverseOpcode().

◆ RVV_OPC_LMUL_MASK_CASE

#define RVV_OPC_LMUL_MASK_CASE ( OPC,
INV )
Value:
case RISCV::OPC##_M1_MASK: \
return RISCV::INV##_M1_MASK; \
case RISCV::OPC##_M2_MASK: \
return RISCV::INV##_M2_MASK; \
case RISCV::OPC##_M4_MASK: \
return RISCV::INV##_M4_MASK; \
case RISCV::OPC##_M8_MASK: \
return RISCV::INV##_M8_MASK; \
case RISCV::OPC##_MF2_MASK: \
return RISCV::INV##_MF2_MASK; \
case RISCV::OPC##_MF4_MASK: \
return RISCV::INV##_MF4_MASK; \
case RISCV::OPC##_MF8_MASK: \
return RISCV::INV##_MF8_MASK

Referenced by llvm::RISCVInstrInfo::getInverseOpcode().

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

enum MachineOutlinerConstructionID
Enumerator
MachineOutlinerTailCall 
MachineOutlinerDefault 
MachineOutlinerRegSave 

Definition at line 3780 of file RISCVInstrInfo.cpp.

Function Documentation

◆ canCombine()

const MachineInstr * canCombine ( const MachineBasicBlock & MBB,
const MachineOperand & MO,
unsigned CombineOpc )
static

Utility routine that checks if.

Parameters
MOis defined by an
CombineOpcinstruction in the basic block
MBB

Definition at line 2819 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, and MI.

◆ canCombineFPFusedMultiply()

bool canCombineFPFusedMultiply ( const MachineInstr & Root,
const MachineOperand & MO,
bool DoRegPressureReduce )
static

Definition at line 2761 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::RISCV::hasEqualFRM(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), isFMUL(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), and MI.

Referenced by getFPFusedMultiplyPatterns().

◆ canCombineShiftIntoShXAdd()

bool canCombineShiftIntoShXAdd ( const MachineBasicBlock & MBB,
const MachineOperand & MO,
unsigned OuterShiftAmt )
static

Utility routine that checks if.

Parameters
MOis defined by a SLLI in
MBBthat can be combined by splitting across 2 SHXADD instructions. The first SHXADD shift amount is given by
OuterShiftAmt.

Definition at line 2840 of file RISCVInstrInfo.cpp.

References canCombine(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and MBB.

Referenced by getSHXADDPatterns().

◆ canFoldAsPredicatedOp()

MachineInstr * canFoldAsPredicatedOp ( Register Reg,
const MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
const RISCVSubtarget & STI )
static

Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

Definition at line 1994 of file RISCVInstrInfo.cpp.

References llvm::drop_begin(), getPredicatedOpcode(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineRegisterInfo::isConstantPhysReg(), MI, Reg, and TII.

Referenced by llvm::RISCVInstrInfo::optimizeSelect().

◆ cannotInsertTailCall()

bool cannotInsertTailCall ( const MachineBasicBlock & MBB)
static

Definition at line 3810 of file RISCVInstrInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getTailExpandUseRegNo(), llvm::RISCVMachineFunctionInfo::hasCFProtectionBranch(), isCandidatePatchable(), isMIModifiesReg(), isMIReadsReg(), MBB, and MI.

Referenced by llvm::RISCVInstrInfo::analyzeCandidate(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

◆ combineFPFusedMultiply()

void combineFPFusedMultiply ( MachineInstr & Root,
MachineInstr & Prev,
unsigned Pattern,
SmallVectorImpl< MachineInstr * > & InsInstrs,
SmallVectorImpl< MachineInstr * > & DelInstrs )
static

Definition at line 2972 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), getAddendOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), getFPFusedMultiplyOpcode(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::DILocation::getMergedLocation(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isKill(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

◆ findRegisterToSaveX5To()

Register findRegisterToSaveX5To ( outliner::Candidate & C,
const TargetRegisterInfo & TRI )
static

Definition at line 3838 of file RISCVInstrInfo.cpp.

References C(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::isReserved(), Reg, Register, and TRI.

Referenced by llvm::RISCVInstrInfo::analyzeCandidate(), and llvm::RISCVInstrInfo::insertOutlinedCall().

◆ forwardCopyWillClobberTuple()

bool forwardCopyWillClobberTuple ( unsigned DstReg,
unsigned SrcReg,
unsigned NumRegs )
static

Definition at line 236 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector().

◆ genShXAddAddShift()

void genShXAddAddShift ( MachineInstr & Root,
unsigned AddOpIdx,
SmallVectorImpl< MachineInstr * > & InsInstrs,
SmallVectorImpl< MachineInstr * > & DelInstrs,
DenseMap< Register, unsigned > & InstrIdxForVirtReg )
static

Definition at line 3018 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getSHXADDShiftAmount(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::DenseMapBase< StorageT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::Kill, llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TII, X, and Y.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

◆ getAddendOperandIdx()

unsigned getAddendOperandIdx ( unsigned Pattern)
static

Definition at line 2959 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getEffectiveImm()

std::optional< int64_t > getEffectiveImm ( const MachineRegisterInfo & MRI,
const MachineOperand & MO )
static

Definition at line 5455 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), Imm, llvm::MachineOperand::isImm(), isLoadImm(), and llvm::Register::isVirtual().

Referenced by llvm::RISCV::isVLKnownLE().

◆ getFoldedOpcode()

std::optional< unsigned > getFoldedOpcode ( MachineFunction & MF,
MachineInstr & MI,
ArrayRef< unsigned > Ops,
const RISCVSubtarget & ST )

Definition at line 845 of file RISCVInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineFunction::getDataLayout(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::DataLayout::isBigEndian(), llvm_unreachable, and MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ getFPFusedMultiplyOpcode()

unsigned getFPFusedMultiplyOpcode ( unsigned RootOpc,
unsigned Pattern )
static

Definition at line 2937 of file RISCVInstrInfo.cpp.

References llvm::FMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getFPFusedMultiplyPatterns()

bool getFPFusedMultiplyPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns,
bool DoRegPressureReduce )
static

Definition at line 2788 of file RISCVInstrInfo.cpp.

References canCombineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isFADD(), isFSUB(), Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by getFPPatterns().

◆ getFPPatterns()

bool getFPPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns,
bool DoRegPressureReduce )
static

Definition at line 2811 of file RISCVInstrInfo.cpp.

References getFPFusedMultiplyPatterns().

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getInverseXqcicmOpcode()

unsigned getInverseXqcicmOpcode ( unsigned Opcode)
static

Definition at line 1151 of file RISCVInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ getJumpTableIndexFromBase()

int getJumpTableIndexFromBase ( const MachineRegisterInfo & MRI,
Register Reg )
static

Definition at line 1825 of file RISCVInstrInfo.cpp.

References llvm::MachineRegisterInfo::getUniqueVRegDef(), MI, and Reg.

Referenced by llvm::RISCVInstrInfo::getJumpTableIndex(), and getJumpTableIndexFromLoadAddr().

◆ getJumpTableIndexFromLoadAddr()

int getJumpTableIndexFromLoadAddr ( const MachineRegisterInfo & MRI,
Register Reg )
static

Definition at line 1842 of file RISCVInstrInfo.cpp.

References getJumpTableIndexFromBase(), llvm::MachineRegisterInfo::getUniqueVRegDef(), MI, and Reg.

◆ getLMULForRVVWholeLoadStore()

std::optional< unsigned > getLMULForRVVWholeLoadStore ( unsigned Opcode)
static

Definition at line 91 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::RISCV::isRVVSpill(), and llvm::RISCVInstrInfo::isStoreToStackSlot().

◆ getLoadPredicatedOpcode()

unsigned getLoadPredicatedOpcode ( unsigned Opcode)
static

Definition at line 932 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ getPredicatedOpcode()

unsigned getPredicatedOpcode ( unsigned Opcode)

Definition at line 1941 of file RISCVInstrInfo.cpp.

Referenced by canFoldAsPredicatedOp(), and llvm::RISCVInstrInfo::optimizeSelect().

◆ getSHXADDPatterns()

bool getSHXADDPatterns ( const MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Definition at line 2886 of file RISCVInstrInfo.cpp.

References canCombine(), canCombineShiftIntoShXAdd(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getSHXADDShiftAmount(), MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getSHXADDShiftAmount()

unsigned getSHXADDShiftAmount ( unsigned Opc)
static

Definition at line 2856 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by genShXAddAddShift(), getSHXADDPatterns(), and llvm::RISCVInstrInfo::simplifyInstruction().

◆ getSHXADDUWShiftAmount()

unsigned getSHXADDUWShiftAmount ( unsigned Opc)
static

Definition at line 2871 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by llvm::RISCVInstrInfo::simplifyInstruction().

◆ isCandidatePatchable()

bool isCandidatePatchable ( const MachineBasicBlock & MBB)
static

Definition at line 3791 of file RISCVInstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), and MBB.

Referenced by cannotInsertTailCall().

◆ isConvertibleToVMV_V_V()

bool isConvertibleToVMV_V_V ( const RISCVSubtarget & STI,
const MachineBasicBlock & MBB,
MachineBasicBlock::const_iterator MBBI,
MachineBasicBlock::const_iterator & DefMBBI,
RISCVVType::VLMUL LMul )
static

Definition at line 241 of file RISCVInstrInfo.cpp.

References assert(), llvm::RISCVSubtarget::getCLOpts(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVVType::getSEW(), llvm::RISCVVType::getVLMUL(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVII::isRVVWideningReduction(), llvm::RISCVVType::isTailAgnostic(), MBB, MBBI, TRI, and uint64_t.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector().

◆ isFADD()

bool isFADD ( unsigned Opc)
static

Definition at line 2362 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by getFPFusedMultiplyPatterns(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFMUL()

bool isFMUL ( unsigned Opc)
static

Definition at line 2384 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

◆ isFSUB()

bool isFSUB ( unsigned Opc)
static

Definition at line 2373 of file RISCVInstrInfo.cpp.

References Opc.

Referenced by getFPFusedMultiplyPatterns().

◆ isJumpTableLoad()

bool isJumpTableLoad ( const MachineInstr & MI)
static

Definition at line 1816 of file RISCVInstrInfo.cpp.

References llvm::any_of(), and MI.

◆ isLoadImm()

bool isLoadImm ( const MachineInstr * MI,
int64_t & Imm )
static

Definition at line 1602 of file RISCVInstrInfo.cpp.

References Imm, and MI.

Referenced by getEffectiveImm(), llvm::RISCVInstrInfo::isFromLoadImm(), and llvm::RISCVInstrInfo::optimizeCondBranch().

◆ isMIModifiesReg()

bool isMIModifiesReg ( const MachineInstr & MI,
const TargetRegisterInfo * TRI,
MCRegister RegNo )
static

Definition at line 3804 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by cannotInsertTailCall(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

◆ isMIReadsReg()

bool isMIReadsReg ( const MachineInstr & MI,
const TargetRegisterInfo * TRI,
MCRegister RegNo )
static

Definition at line 3798 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by cannotInsertTailCall().

◆ memOpsHaveSameBasePtr()

bool memOpsHaveSameBasePtr ( const MachineInstr & MI1,
ArrayRef< const MachineOperand * > BaseOps1,
const MachineInstr & MI2,
ArrayRef< const MachineOperand * > BaseOps2 )
static

Definition at line 3606 of file RISCVInstrInfo.cpp.

References llvm::ArrayRef< T >::front(), llvm::getUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), llvm::isa(), and llvm::MachineInstr::memoperands_begin().

◆ parseCondBranch()

void parseCondBranch ( MachineInstr & LastInst,
MachineBasicBlock *& Target,
SmallVectorImpl< MachineOperand > & Cond )
static

Definition at line 1140 of file RISCVInstrInfo.cpp.

References assert(), Cond, llvm::MachineOperand::CreateImm(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MCInstrDesc::isConditionalBranch().

◆ STATISTIC() [1/2]

STATISTIC ( NumVRegReloaded ,
"Number of registers within vector register groups reloaded"  )

◆ STATISTIC() [2/2]

STATISTIC ( NumVRegSpilled ,
"Number of registers within vector register groups spilled"  )
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