30#include "llvm/IR/IntrinsicsAArch64.h"
33#include <initializer_list>
35#define DEBUG_TYPE "aarch64-legalinfo"
38using namespace LegalizeActions;
39using namespace LegalizeMutations;
40using namespace LegalityPredicates;
41using namespace MIPatternMatch;
45 using namespace TargetOpcode;
64 std::initializer_list<LLT> PackedVectorAllTypeList = {
70 std::initializer_list<LLT> ScalarAndPtrTypesList = {s8, s16, s32, s64, p0};
77 if (!ST.hasNEON() || !ST.hasFPARMv8()) {
84 const bool HasFP16 = ST.hasFullFP16();
85 const LLT &MinFPScalar = HasFP16 ? s16 : s32;
87 const bool HasCSSC = ST.hasCSSC();
88 const bool HasRCPC3 = ST.hasRCPC3();
91 {G_IMPLICIT_DEF, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
92 .legalFor({p0, s8, s16, s32, s64})
93 .legalFor(PackedVectorAllTypeList)
105 .legalFor(PackedVectorAllTypeList)
116 .
legalFor({s32, s64, v4s16, v8s16, v2s32, v4s32, v2s64})
118 .clampScalar(0, s32, s64)
119 .clampNumElements(0, v4s16, v8s16)
120 .clampNumElements(0, v2s32, v4s32)
121 .clampNumElements(0, v2s64, v2s64)
122 .moreElementsToNextPow2(0);
125 .legalFor({s32, s64, v2s32, v2s64, v4s32, v4s16, v8s16, v16s8, v8s8})
126 .widenScalarToNextPow2(0)
134 return Query.
Types[0].getNumElements() <= 2;
139 return Query.
Types[0].getNumElements() <= 4;
144 return Query.
Types[0].getNumElements() <= 16;
151 const auto &SrcTy = Query.
Types[0];
152 const auto &AmtTy = Query.
Types[1];
153 return !SrcTy.isVector() && SrcTy.getSizeInBits() == 32 &&
154 AmtTy.getSizeInBits() == 32;
168 .widenScalarToNextPow2(0)
179 .
legalFor({{p0, s64}, {v2p0, v2s64}})
180 .clampScalarOrElt(1, s64, s64)
186 .legalFor({s32, s64})
188 .clampScalar(0, s32, s64)
193 .lowerFor({s8, s16, s32, s64, v2s64, v4s32, v2s32})
195 .clampScalarOrElt(0, s32, s64)
196 .clampNumElements(0, v2s32, v4s32)
197 .clampNumElements(0, v2s64, v2s64)
198 .moreElementsToNextPow2(0);
202 .widenScalarToNextPow2(0, 32)
207 .legalFor({s64, v8s16, v16s8, v4s32})
211 {G_SMIN, G_SMAX, G_UMIN, G_UMAX});
214 .
legalFor({s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
221 .
legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32});
232 {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
233 .legalFor({{s32, s32}, {s64, s32}})
234 .clampScalar(0, s32, s64)
239 G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM,
240 G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR,
241 G_FRINT, G_FNEARBYINT, G_INTRINSIC_TRUNC,
242 G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
243 .legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
245 const auto &Ty = Query.
Types[0];
246 return (Ty == v8s16 || Ty == v4s16) && HasFP16;
249 .minScalarOrElt(0, MinFPScalar)
261 .legalFor({{s64, MinFPScalar}, {s64, s32}, {s64, s64}})
262 .libcallFor({{s64, s128}})
263 .minScalarOrElt(1, MinFPScalar);
266 {G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2, G_FLOG10,
267 G_FEXP, G_FEXP2, G_FEXP10})
272 .libcallFor({s32, s64});
300 for (
unsigned Op : {G_SEXTLOAD, G_ZEXTLOAD}) {
303 if (
Op == G_SEXTLOAD)
308 .legalForTypesWithMemDesc({{s32, p0, s8, 8},
316 {v2s32, p0, s64, 8}})
317 .widenScalarToNextPow2(0)
318 .clampScalar(0, s32, s64)
321 .unsupportedIfMemSizeNotPow2()
333 return HasRCPC3 && Query.
Types[0] == s128 &&
337 return Query.
Types[0] == s128 &&
340 .legalForTypesWithMemDesc({{s8, p0, s8, 8},
347 {v16s8, p0, s128, 8},
349 {v8s16, p0, s128, 8},
351 {v4s32, p0, s128, 8},
352 {v2s64, p0, s128, 8}})
354 .legalForTypesWithMemDesc(
355 {{s32, p0, s8, 8}, {s32, p0, s16, 8}, {s64, p0, s32, 8}})
356 .widenScalarToNextPow2(0, 8)
367 return Query.
Types[0].isScalar() &&
369 Query.
Types[0].getSizeInBits() > 32;
378 .customIf(IsPtrVecPred)
383 return HasRCPC3 && Query.
Types[0] == s128 &&
387 return Query.
Types[0] == s128 &&
390 .legalForTypesWithMemDesc(
391 {{s8, p0, s8, 8}, {s16, p0, s8, 8},
394 {s16, p0, s16, 8}, {s32, p0, s16, 8},
396 {s32, p0, s8, 8}, {s32, p0, s16, 8}, {s32, p0, s32, 8},
397 {s64, p0, s64, 8}, {s64, p0, s32, 8},
398 {p0, p0, s64, 8}, {s128, p0, s128, 8}, {v16s8, p0, s128, 8},
399 {v8s8, p0, s64, 8}, {v4s16, p0, s64, 8}, {v8s16, p0, s128, 8},
400 {v2s32, p0, s64, 8}, {v4s32, p0, s128, 8}, {v2s64, p0, s128, 8}})
401 .clampScalar(0, s8, s64)
403 return Query.
Types[0].isScalar() &&
407 .clampMaxNumElements(0, s8, 16)
419 .customIf(IsPtrVecPred)
435 {p0, v16s8, v16s8, 8},
436 {p0, v4s16, v4s16, 8},
437 {p0, v8s16, v8s16, 8},
438 {p0, v2s32, v2s32, 8},
439 {p0, v4s32, v4s32, 8},
440 {p0, v2s64, v2s64, 8},
446 auto IndexedLoadBasicPred = [=](
const LegalityQuery &Query) {
474 return MemTy == s8 || MemTy == s16;
476 return MemTy == s8 || MemTy == s16 || MemTy == s32;
484 .widenScalarToNextPow2(0)
488 const auto &Ty = Query.
Types[0];
489 if (HasFP16 && Ty == s16)
491 return Ty == s32 || Ty == s64 || Ty == s128;
493 .clampScalar(0, MinFPScalar, s128);
497 .
legalFor({{s32, s32}, {s32, s64}, {s32, p0}})
499 .clampScalar(1, s32, s64)
500 .clampScalar(0, s32, s32)
501 .minScalarEltSameAsIf(
516 .clampNumElements(1, v8s8, v16s8)
517 .clampNumElements(1, v4s16, v8s16)
518 .clampNumElements(1, v2s32, v4s32)
519 .clampNumElements(1, v2s64, v2s64)
530 const auto &Ty = Query.
Types[1];
531 return (Ty == v8s16 || Ty == v4s16) && Ty == Query.
Types[0] && HasFP16;
534 .clampScalar(0, s32, s32)
535 .clampScalarOrElt(1, MinFPScalar, s64)
536 .minScalarEltSameAsIf(
544 .clampNumElements(1, v4s16, v8s16)
545 .clampNumElements(1, v2s32, v4s32)
546 .clampMaxNumElements(1, s64, 2)
547 .moreElementsToNextPow2(1);
551 unsigned DstSize = Query.
Types[0].getSizeInBits();
554 if (Query.
Types[0].isVector())
557 if (DstSize < 8 || DstSize >= 128 || !
isPowerOf2_32(DstSize))
572 .legalIf(ExtLegalFunc)
573 .
legalFor({{v2s64, v2s32}, {v4s32, v4s16}, {v8s16, v8s8}})
574 .clampScalar(0, s64, s64)
581 return (Query.
Types[0].getScalarSizeInBits() >
582 Query.
Types[1].getScalarSizeInBits() * 2) &&
583 Query.
Types[0].isVector() &&
584 (Query.
Types[1].getScalarSizeInBits() == 8 ||
585 Query.
Types[1].getScalarSizeInBits() == 16);
587 .clampMinNumElements(1, s8, 8)
591 .
legalFor({{v2s32, v2s64}, {v4s16, v4s32}, {v8s8, v8s16}})
593 .clampMaxNumElements(0, s8, 8)
594 .clampMaxNumElements(0, s16, 4)
595 .clampMaxNumElements(0, s32, 2)
605 .clampMinNumElements(0, s8, 8)
606 .clampMinNumElements(0, s16, 4)
611 .legalFor(PackedVectorAllTypeList)
622 {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
623 .clampNumElements(0, v4s16, v4s16)
629 {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
630 .clampNumElements(0, v4s32, v4s32)
636 .legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
639 (Query.
Types[1] == s16 || Query.
Types[1] == v4s16 ||
640 Query.
Types[1] == v8s16) &&
641 (Query.
Types[0] == s32 || Query.
Types[0] == s64 ||
642 Query.
Types[0] == v4s16 || Query.
Types[0] == v8s16);
644 .widenScalarToNextPow2(0)
651 return Query.
Types[0].getScalarSizeInBits() >
652 Query.
Types[1].getScalarSizeInBits();
657 return Query.
Types[0].getScalarSizeInBits() <
658 Query.
Types[1].getScalarSizeInBits();
661 .clampNumElements(0, v4s16, v8s16)
666 .legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
669 (Query.
Types[0] == s16 || Query.
Types[0] == v4s16 ||
670 Query.
Types[0] == v8s16) &&
671 (Query.
Types[1] == s32 || Query.
Types[1] == s64 ||
672 Query.
Types[1] == v4s16 || Query.
Types[1] == v8s16);
674 .widenScalarToNextPow2(1)
681 return Query.
Types[0].getScalarSizeInBits() <
682 Query.
Types[1].getScalarSizeInBits();
687 return Query.
Types[0].getScalarSizeInBits() >
688 Query.
Types[1].getScalarSizeInBits();
691 .clampNumElements(0, v4s16, v8s16)
698 .clampScalar(0, s32, s32);
702 .
legalFor({{s32, s32}, {s64, s32}, {p0, s32}})
703 .widenScalarToNextPow2(0)
718 .
legalFor({{s64, p0}, {v2s64, v2p0}})
719 .widenScalarToNextPow2(0, 64)
724 return Query.
Types[0].getSizeInBits() != Query.
Types[1].getSizeInBits();
726 .legalFor({{p0, s64}, {v2p0, v2s64}});
733 .legalForCartesianProduct({s64, v8s8, v4s16, v2s32})
734 .legalForCartesianProduct({s128, v16s8, v8s16, v4s32, v2s64, v2p0})
736 return Query.
Types[0].isVector() != Query.
Types[1].isVector();
739 .clampNumElements(0, v8s8, v16s8)
740 .clampNumElements(0, v4s16, v8s16)
741 .clampNumElements(0, v2s32, v4s32)
750 .clampScalar(0, s8, s64)
758 return ST.outlineAtomics() && !ST.hasLSE();
766 return Query.
Types[0].getSizeInBits() == 128 &&
767 !UseOutlineAtomics(Query);
774 G_ATOMICRMW_SUB, G_ATOMICRMW_AND, G_ATOMICRMW_OR,
785 {G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX})
792 for (
unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
793 unsigned BigTyIdx =
Op == G_MERGE_VALUES ? 0 : 1;
794 unsigned LitTyIdx =
Op == G_MERGE_VALUES ? 1 : 0;
801 switch (Q.
Types[BigTyIdx].getSizeInBits()) {
809 switch (Q.
Types[LitTyIdx].getSizeInBits()) {
823 const LLT &EltTy = Query.
Types[1].getElementType();
824 return Query.
Types[0] != EltTy;
829 return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 ||
830 VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32 ||
831 VecTy == v8s8 || VecTy == v16s8 || VecTy == v2p0;
837 return Query.
Types[1].getNumElements() <= 2;
842 return Query.
Types[1].getNumElements() <= 4;
847 return Query.
Types[1].getNumElements() <= 8;
852 return Query.
Types[1].getNumElements() <= 16;
855 .minScalarOrElt(0, s8)
865 typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
883 .clampNumElements(0, v4s32, v4s32)
893 {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
895 .widenScalarToNextPow2(1, 32)
896 .clampScalar(1, s32, s64)
897 .scalarSameSizeAs(0, 1);
903 .widenScalarToNextPow2(0, 32)
914 return (HasCSSC &&
typeInSet(0, {s32, s64})(Query));
917 return (!HasCSSC &&
typeInSet(0, {s32, s64})(Query));
929 {v2s64, v2p0, v2s32, v4s32, v4s16, v16s8, v8s8, v8s16}, DstTy);
934 return !Query.
Types[1].isVector();
938 return Query.
Types[0].isVector() && Query.
Types[1].isVector() &&
939 Query.
Types[0].getNumElements() >
940 Query.
Types[1].getNumElements();
946 return Query.
Types[0].isVector() && Query.
Types[1].isVector() &&
947 Query.
Types[0].getNumElements() <
948 Query.
Types[1].getNumElements();
951 .widenScalarOrEltToNextPow2OrMinSize(0, 8)
952 .clampNumElements(0, v8s8, v16s8)
953 .clampNumElements(0, v4s16, v8s16)
954 .clampNumElements(0, v4s32, v4s32)
955 .clampNumElements(0, v2s64, v2s64);
958 .
legalFor({{v4s32, v2s32}, {v8s16, v4s16}, {v16s8, v8s8}});
975 .customForCartesianProduct({p0}, {s8}, {s64})
979 .legalForCartesianProduct({p0}, {p0}, {s64})
995 .legalFor({s32, s64});
996 ABSActions.legalFor(PackedVectorAllTypeList)
1004 [=](
const LegalityQuery &Query) {
return std::make_pair(0, v4s16); })
1007 [=](
const LegalityQuery &Query) {
return std::make_pair(0, v2s32); })
1008 .clampNumElements(0, v8s8, v16s8)
1009 .clampNumElements(0, v4s16, v8s16)
1010 .clampNumElements(0, v2s32, v4s32)
1011 .clampNumElements(0, v2s64, v2s64)
1012 .moreElementsToNextPow2(0)
1019 .
legalFor({{s32, v2s32}, {s32, v4s32}, {s64, v2s64}})
1021 const auto &Ty = Query.
Types[1];
1022 return (Ty == v4s16 || Ty == v8s16) && HasFP16;
1024 .minScalarOrElt(0, MinFPScalar)
1055 .clampMaxNumElements(1, s64, 2)
1062 G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
1063 .legalFor({{s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
1065 const auto &Ty = Query.
Types[1];
1066 return Query.
Types[0] == s16 && (Ty == v8s16 || Ty == v4s16) && HasFP16;
1068 .minScalarOrElt(0, MinFPScalar)
1082 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
1083 .legalFor({{s8, v8s8},
1091 return Query.
Types[1].isVector() &&
1092 Query.
Types[1].getElementType() != s8 &&
1093 Query.
Types[1].getNumElements() & 1;
1096 .clampMaxNumElements(1, s64, 2)
1104 {G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
1120 return std::make_pair(1, SrcTy.
divide(2));
1126 .customFor({{s32, s32}, {s32, s64}, {s64, s64}})
1130 .
legalFor({{s32, s64}, {s64, s64}})
1132 return Q.
Types[0].isScalar() && Q.
Types[1].getScalarSizeInBits() < 64;
1138 .customFor({{s32, s32}, {s64, s64}});
1144 .legalFor({{s32, s32},
1148 .customFor({{s128, s128},
1156 .legalFor({{v8s8, v8s8},
1158 .customFor({{s32, s32},
1167 .clampScalar(0, s32, s128)
1168 .widenScalarToNextPow2(0)
1169 .minScalarEltSameAsIf(always, 1, 0)
1170 .maxScalarEltSameAsIf(always, 1, 0);
1173 .legalFor({v2s64, v2s32, v4s32, v4s16, v8s16, v8s8, v16s8})
1174 .clampNumElements(0, v8s8, v16s8)
1184 .legalFor({{s64, s32}, {s64, s64}});
1200 G_GET_FPMODE, G_SET_FPMODE, G_RESET_FPMODE})
1208 verify(*ST.getInstrInfo());
1217 switch (
MI.getOpcode()) {
1221 case TargetOpcode::G_VAARG:
1222 return legalizeVaArg(
MI,
MRI, MIRBuilder);
1223 case TargetOpcode::G_LOAD:
1224 case TargetOpcode::G_STORE:
1225 return legalizeLoadStore(
MI,
MRI, MIRBuilder, Observer);
1226 case TargetOpcode::G_SHL:
1227 case TargetOpcode::G_ASHR:
1228 case TargetOpcode::G_LSHR:
1229 return legalizeShlAshrLshr(
MI,
MRI, MIRBuilder, Observer);
1230 case TargetOpcode::G_GLOBAL_VALUE:
1231 return legalizeSmallCMGlobalValue(
MI,
MRI, MIRBuilder, Observer);
1232 case TargetOpcode::G_SBFX:
1233 case TargetOpcode::G_UBFX:
1234 return legalizeBitfieldExtract(
MI,
MRI, Helper);
1235 case TargetOpcode::G_FSHL:
1236 case TargetOpcode::G_FSHR:
1237 return legalizeFunnelShift(
MI,
MRI, MIRBuilder, Observer, Helper);
1238 case TargetOpcode::G_ROTR:
1239 return legalizeRotate(
MI,
MRI, Helper);
1240 case TargetOpcode::G_CTPOP:
1241 return legalizeCTPOP(
MI,
MRI, Helper);
1242 case TargetOpcode::G_ATOMIC_CMPXCHG:
1243 return legalizeAtomicCmpxchg128(
MI,
MRI, Helper);
1244 case TargetOpcode::G_CTTZ:
1245 return legalizeCTTZ(
MI, Helper);
1246 case TargetOpcode::G_BZERO:
1247 case TargetOpcode::G_MEMCPY:
1248 case TargetOpcode::G_MEMMOVE:
1249 case TargetOpcode::G_MEMSET:
1250 return legalizeMemOps(
MI, Helper);
1251 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1252 return legalizeExtractVectorElt(
MI,
MRI, Helper);
1253 case TargetOpcode::G_DYN_STACKALLOC:
1254 return legalizeDynStackAlloc(
MI, Helper);
1255 case TargetOpcode::G_PREFETCH:
1256 return legalizePrefetch(
MI, Helper);
1257 case TargetOpcode::G_ABS:
1259 case TargetOpcode::G_ICMP:
1260 return legalizeICMP(
MI,
MRI, MIRBuilder);
1271 assert(
MI.getOpcode() == TargetOpcode::G_FSHL ||
1272 MI.getOpcode() == TargetOpcode::G_FSHR);
1276 Register ShiftNo =
MI.getOperand(3).getReg();
1277 LLT ShiftTy =
MRI.getType(ShiftNo);
1282 LLT OperationTy =
MRI.getType(
MI.getOperand(0).getReg());
1286 if (!VRegAndVal || VRegAndVal->Value.urem(
BitWidth) == 0)
1292 Amount =
MI.getOpcode() == TargetOpcode::G_FSHL ?
BitWidth - Amount : Amount;
1296 if (ShiftTy.
getSizeInBits() == 64 &&
MI.getOpcode() == TargetOpcode::G_FSHR &&
1303 if (
MI.getOpcode() == TargetOpcode::G_FSHR) {
1305 MI.getOperand(3).setReg(Cast64.getReg(0));
1310 else if (
MI.getOpcode() == TargetOpcode::G_FSHL) {
1312 {
MI.getOperand(1).
getReg(),
MI.getOperand(2).getReg(),
1314 MI.eraseFromParent();
1323 Register SrcReg1 =
MI.getOperand(2).getReg();
1324 Register SrcReg2 =
MI.getOperand(3).getReg();
1325 LLT DstTy =
MRI.getType(DstReg);
1326 LLT SrcTy =
MRI.getType(SrcReg1);
1343 MIRBuilder.
buildNot(DstReg, CmpReg);
1345 MI.eraseFromParent();
1355 LLT AmtTy =
MRI.getType(AmtReg);
1361 MI.getOperand(2).setReg(NewAmt.getReg(0));
1366bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
1369 assert(
MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
1374 auto &GlobalOp =
MI.getOperand(1);
1376 if (GlobalOp.isSymbol())
1378 const auto* GV = GlobalOp.getGlobal();
1379 if (GV->isThreadLocal())
1388 auto Offset = GlobalOp.getOffset();
1393 MRI.setRegClass(
ADRP.getReg(0), &AArch64::GPR64RegClass);
1410 "Should not have folded in an offset for a tagged global!");
1412 .addGlobalAddress(GV, 0x100000000,
1415 MRI.setRegClass(
ADRP.getReg(0), &AArch64::GPR64RegClass);
1419 .addGlobalAddress(GV,
Offset,
1421 MI.eraseFromParent();
1428 switch (IntrinsicID) {
1429 case Intrinsic::vacopy: {
1431 unsigned VaListSize =
1443 VaListSize,
Align(PtrSize)));
1447 VaListSize,
Align(PtrSize)));
1448 MI.eraseFromParent();
1451 case Intrinsic::get_dynamic_area_offset: {
1454 MI.eraseFromParent();
1457 case Intrinsic::aarch64_mops_memset_tag: {
1458 assert(
MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
1462 auto &
Value =
MI.getOperand(3);
1464 Value.setReg(ExtValueReg);
1467 case Intrinsic::aarch64_prefetch: {
1469 auto &AddrVal =
MI.getOperand(1);
1471 int64_t IsWrite =
MI.getOperand(2).getImm();
1472 int64_t
Target =
MI.getOperand(3).getImm();
1473 int64_t IsStream =
MI.getOperand(4).getImm();
1474 int64_t IsData =
MI.getOperand(5).getImm();
1476 unsigned PrfOp = (IsWrite << 4) |
1482 MI.eraseFromParent();
1485 case Intrinsic::aarch64_neon_uaddv:
1486 case Intrinsic::aarch64_neon_saddv:
1487 case Intrinsic::aarch64_neon_umaxv:
1488 case Intrinsic::aarch64_neon_smaxv:
1489 case Intrinsic::aarch64_neon_uminv:
1490 case Intrinsic::aarch64_neon_sminv: {
1493 bool IsSigned = IntrinsicID == Intrinsic::aarch64_neon_saddv ||
1494 IntrinsicID == Intrinsic::aarch64_neon_smaxv ||
1495 IntrinsicID == Intrinsic::aarch64_neon_sminv;
1497 auto OldDst =
MI.getOperand(0).getReg();
1498 auto OldDstTy =
MRI.getType(OldDst);
1499 LLT NewDstTy =
MRI.getType(
MI.getOperand(2).getReg()).getElementType();
1500 if (OldDstTy == NewDstTy)
1503 auto NewDst =
MRI.createGenericVirtualRegister(NewDstTy);
1506 MI.getOperand(0).setReg(NewDst);
1510 MIB.
buildExtOrTrunc(IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT,
1515 case Intrinsic::aarch64_neon_uaddlp:
1516 case Intrinsic::aarch64_neon_saddlp: {
1519 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlp
1521 : AArch64::G_SADDLP;
1523 MI.eraseFromParent();
1527 case Intrinsic::aarch64_neon_uaddlv:
1528 case Intrinsic::aarch64_neon_saddlv: {
1532 unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlv
1534 : AArch64::G_SADDLV;
1537 LLT DstTy =
MRI.getType(DstReg);
1561 MI.eraseFromParent();
1565 case Intrinsic::aarch64_neon_smax:
1566 case Intrinsic::aarch64_neon_smin:
1567 case Intrinsic::aarch64_neon_umax:
1568 case Intrinsic::aarch64_neon_umin:
1569 case Intrinsic::aarch64_neon_fmax:
1570 case Intrinsic::aarch64_neon_fmin:
1571 case Intrinsic::aarch64_neon_fmaxnm:
1572 case Intrinsic::aarch64_neon_fminnm: {
1574 if (IntrinsicID == Intrinsic::aarch64_neon_smax)
1576 else if (IntrinsicID == Intrinsic::aarch64_neon_smin)
1578 else if (IntrinsicID == Intrinsic::aarch64_neon_umax)
1580 else if (IntrinsicID == Intrinsic::aarch64_neon_umin)
1582 else if (IntrinsicID == Intrinsic::aarch64_neon_fmax)
1583 MIB.
buildInstr(TargetOpcode::G_FMAXIMUM, {
MI.getOperand(0)},
1584 {
MI.getOperand(2),
MI.getOperand(3)});
1585 else if (IntrinsicID == Intrinsic::aarch64_neon_fmin)
1586 MIB.
buildInstr(TargetOpcode::G_FMINIMUM, {
MI.getOperand(0)},
1587 {
MI.getOperand(2),
MI.getOperand(3)});
1588 else if (IntrinsicID == Intrinsic::aarch64_neon_fmaxnm)
1589 MIB.
buildInstr(TargetOpcode::G_FMAXNUM, {
MI.getOperand(0)},
1590 {
MI.getOperand(2),
MI.getOperand(3)});
1591 else if (IntrinsicID == Intrinsic::aarch64_neon_fminnm)
1592 MIB.
buildInstr(TargetOpcode::G_FMINNUM, {
MI.getOperand(0)},
1593 {
MI.getOperand(2),
MI.getOperand(3)});
1594 MI.eraseFromParent();
1597 case Intrinsic::vector_reverse:
1605bool AArch64LegalizerInfo::legalizeShlAshrLshr(
1608 assert(
MI.getOpcode() == TargetOpcode::G_ASHR ||
1609 MI.getOpcode() == TargetOpcode::G_LSHR ||
1610 MI.getOpcode() == TargetOpcode::G_SHL);
1623 MI.getOperand(2).setReg(ExtCst.getReg(0));
1636 isShiftedInt<7, 3>(NewOffset)) {
1644bool AArch64LegalizerInfo::legalizeLoadStore(
1647 assert(
MI.getOpcode() == TargetOpcode::G_STORE ||
1648 MI.getOpcode() == TargetOpcode::G_LOAD);
1659 const LLT ValTy =
MRI.getType(ValReg);
1664 bool IsLoad =
MI.getOpcode() == TargetOpcode::G_LOAD;
1668 ST->hasLSE2() && ST->hasRCPC3() && (IsLoadAcquire || IsStoreRelease);
1674 Opcode = IsLoad ? AArch64::LDIAPPX : AArch64::STILPX;
1680 assert(ST->hasLSE2() &&
"ldp/stp not single copy atomic without +lse2");
1682 Opcode = IsLoad ? AArch64::LDPXi : AArch64::STPXi;
1687 NewI = MIRBuilder.
buildInstr(Opcode, {s64, s64}, {});
1693 Opcode, {}, {
Split->getOperand(0),
Split->getOperand(1)});
1697 NewI.
addUse(
MI.getOperand(1).getReg());
1708 *
MRI.getTargetRegisterInfo(),
1710 MI.eraseFromParent();
1716 LLVM_DEBUG(
dbgs() <<
"Tried to do custom legalization on wrong load/store");
1722 auto &MMO = **
MI.memoperands_begin();
1725 if (
MI.getOpcode() == TargetOpcode::G_STORE) {
1729 auto NewLoad = MIRBuilder.
buildLoad(NewTy,
MI.getOperand(1), MMO);
1732 MI.eraseFromParent();
1740 Align Alignment(
MI.getOperand(2).getImm());
1742 Register ListPtr =
MI.getOperand(1).getReg();
1744 LLT PtrTy =
MRI.getType(ListPtr);
1755 if (Alignment > PtrAlign) {
1759 auto ListTmp = MIRBuilder.
buildPtrAdd(PtrTy,
List, AlignMinus1.getReg(0));
1764 LLT ValTy =
MRI.getType(Dst);
1769 ValTy, std::max(Alignment, PtrAlign)));
1780 MI.eraseFromParent();
1784bool AArch64LegalizerInfo::legalizeBitfieldExtract(
1818 LLT Ty =
MRI.getType(Val);
1822 "Expected src and dst to have the same type!");
1830 auto Add = MIRBuilder.
buildAdd(s64, CTPOP1, CTPOP2);
1833 MI.eraseFromParent();
1837 if (!ST->hasNEON() ||
1838 MI.getMF()->getFunction().hasFnAttribute(Attribute::NoImplicitFloat)) {
1850 assert((
Size == 32 ||
Size == 64 ||
Size == 128) &&
"Expected only 32, 64, or 128 bit scalars!");
1865 Opc = Intrinsic::aarch64_neon_uaddlv;
1868 Opc = Intrinsic::aarch64_neon_uaddlp;
1871 Opc = Intrinsic::aarch64_neon_uaddlp;
1875 Opc = Intrinsic::aarch64_neon_uaddlp;
1880 Opc = Intrinsic::aarch64_neon_uaddlp;
1883 Opc = Intrinsic::aarch64_neon_uaddlp;
1889 for (
LLT HTy : HAddTys) {
1899 MI.eraseFromParent();
1903bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
1907 auto Addr =
MI.getOperand(1).getReg();
1908 auto DesiredI = MIRBuilder.
buildUnmerge({s64, s64},
MI.getOperand(2));
1909 auto NewI = MIRBuilder.
buildUnmerge({s64, s64},
MI.getOperand(3));
1910 auto DstLo =
MRI.createGenericVirtualRegister(s64);
1911 auto DstHi =
MRI.createGenericVirtualRegister(s64);
1924 auto Ordering = (*
MI.memoperands_begin())->getMergedOrdering();
1928 Opcode = AArch64::CASPAX;
1931 Opcode = AArch64::CASPLX;
1935 Opcode = AArch64::CASPALX;
1938 Opcode = AArch64::CASPX;
1943 auto CASDst =
MRI.createGenericVirtualRegister(s128);
1944 auto CASDesired =
MRI.createGenericVirtualRegister(s128);
1945 auto CASNew =
MRI.createGenericVirtualRegister(s128);
1946 MIRBuilder.
buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {})
1947 .addUse(DesiredI->getOperand(0).getReg())
1949 .
addUse(DesiredI->getOperand(1).getReg())
1950 .
addImm(AArch64::subo64);
1951 MIRBuilder.
buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {})
1955 .
addImm(AArch64::subo64);
1957 CAS = MIRBuilder.
buildInstr(Opcode, {CASDst}, {CASDesired, CASNew,
Addr});
1965 auto Ordering = (*
MI.memoperands_begin())->getMergedOrdering();
1969 Opcode = AArch64::CMP_SWAP_128_ACQUIRE;
1972 Opcode = AArch64::CMP_SWAP_128_RELEASE;
1976 Opcode = AArch64::CMP_SWAP_128;
1979 Opcode = AArch64::CMP_SWAP_128_MONOTONIC;
1983 auto Scratch =
MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1984 CAS = MIRBuilder.
buildInstr(Opcode, {DstLo, DstHi, Scratch},
1985 {
Addr, DesiredI->getOperand(0),
1986 DesiredI->getOperand(1), NewI->
getOperand(0),
1992 *
MRI.getTargetRegisterInfo(),
1996 MI.eraseFromParent();
2004 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
2006 MIRBuilder.
buildCTLZ(
MI.getOperand(0).getReg(), BitReverse);
2007 MI.eraseFromParent();
2016 if (
MI.getOpcode() == TargetOpcode::G_MEMSET) {
2019 auto &
Value =
MI.getOperand(1);
2022 Value.setReg(ExtValueReg);
2029bool AArch64LegalizerInfo::legalizeExtractVectorElt(
2031 assert(
MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT);
2040bool AArch64LegalizerInfo::legalizeDynStackAlloc(
2056 Register AllocSize =
MI.getOperand(1).getReg();
2060 "Unexpected type for dynamic alloca");
2062 "Unexpected type for dynamic alloca");
2064 LLT PtrTy =
MRI.getType(Dst);
2070 MIRBuilder.
buildInstr(AArch64::PROBED_STACKALLOC_DYN, {}, {SPTmp});
2071 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass);
2072 MIRBuilder.
setInsertPt(*NewMI->getParent(), NewMI);
2075 MI.eraseFromParent();
2082 auto &AddrVal =
MI.getOperand(0);
2084 int64_t IsWrite =
MI.getOperand(1).getImm();
2085 int64_t Locality =
MI.getOperand(2).getImm();
2086 int64_t
IsData =
MI.getOperand(3).getImm();
2088 bool IsStream = Locality == 0;
2089 if (Locality != 0) {
2090 assert(Locality <= 3 &&
"Prefetch locality out-of-range");
2094 Locality = 3 - Locality;
2097 unsigned PrfOp = (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream;
2100 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static void matchLDPSTPAddrMode(Register Root, Register &Base, int &Offset, MachineRegisterInfo &MRI)
This file declares the targeting of the Machinelegalizer class for AArch64.
This file declares the targeting of the RegisterBankInfo class for AArch64.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Interface for Targets to specify which operations they can successfully select and how the others sho...
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
AArch64LegalizerInfo(const AArch64Subtarget &ST)
bool isTargetWindows() const
const AArch64InstrInfo * getInstrInfo() const override
bool isTargetDarwin() const
bool isTargetILP32() const
const AArch64TargetLowering * getTargetLowering() const override
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const RegisterBankInfo * getRegBankInfo() const override
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
int64_t getSExtValue() const
Get sign extended value.
StringRef getValueAsString() const
Return the attribute's value as a string.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
This class represents an Operation in the Expression.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Abstract class that contains various methods for clients to notify about changes.
virtual void changingInstr(MachineInstr &MI)=0
This instruction is about to be mutated in some way.
virtual void changedInstr(MachineInstr &MI)=0
This instruction was mutated in some way.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
constexpr bool isPointerVector() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr LLT divide(int Factor) const
Return a type that is Factor times smaller.
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & minScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at least as wide as Ty.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & unsupported()
The instruction is unsupported.
LegalizeRuleSet & scalarSameSizeAs(unsigned TypeIdx, unsigned SameSizeIdx)
Change the type TypeIdx to have the same scalar size as type SameSizeIdx.
LegalizeRuleSet & clampScalarOrElt(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & bitcastIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
The specified type index is coerced if predicate is true.
LegalizeRuleSet & libcallFor(std::initializer_list< LLT > Types)
LegalizeRuleSet & maxScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at most as wide as Ty.
LegalizeRuleSet & minScalarOrElt(unsigned TypeIdx, const LLT Ty)
Ensure the scalar or element is at least as wide as Ty.
LegalizeRuleSet & clampMaxNumElements(unsigned TypeIdx, const LLT EltTy, unsigned MaxElements)
Limit the number of elements in EltTy vectors to at most MaxElements.
LegalizeRuleSet & clampMinNumElements(unsigned TypeIdx, const LLT EltTy, unsigned MinElements)
Limit the number of elements in EltTy vectors to at least MinElements.
LegalizeRuleSet & widenVectorEltsToVectorMinSize(unsigned TypeIdx, unsigned VectorSize)
Ensure the vector size is at least as wide as VectorSize by promoting the element.
LegalizeRuleSet & lowerIfMemSizeNotPow2()
Lower a memory operation if the memory size, rounded to bytes, is not a power of 2.
LegalizeRuleSet & minScalarEltSameAsIf(LegalityPredicate Predicate, unsigned TypeIdx, unsigned LargeTypeIdx)
Conditionally widen the scalar or elt to match the size of another.
LegalizeRuleSet & customForCartesianProduct(std::initializer_list< LLT > Types)
LegalizeRuleSet & lowerIfMemSizeNotByteSizePow2()
Lower a memory operation if the memory access size is not a round power of 2 byte size.
LegalizeRuleSet & moreElementsToNextPow2(unsigned TypeIdx)
Add more elements to the vector to reach the next power of two.
LegalizeRuleSet & narrowScalarIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Narrow the scalar to the one selected by the mutation if the predicate is true.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & moreElementsIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Add more elements to reach the type selected by the mutation if the predicate is true.
LegalizeRuleSet & scalarizeIf(LegalityPredicate Predicate, unsigned TypeIdx)
LegalizeRuleSet & lowerIf(LegalityPredicate Predicate)
The instruction is lowered if predicate is true.
LegalizeRuleSet & clampScalar(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & minScalarSameAs(unsigned TypeIdx, unsigned LargeTypeIdx)
Widen the scalar to match the size of another.
LegalizeRuleSet & unsupportedIf(LegalityPredicate Predicate)
LegalizeRuleSet & minScalarOrEltIf(LegalityPredicate Predicate, unsigned TypeIdx, const LLT Ty)
Ensure the scalar or element is at least as wide as Ty.
LegalizeRuleSet & widenScalarIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Widen the scalar to the one selected by the mutation if the predicate is true.
LegalizeRuleSet & clampNumElements(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the number of elements for the given vectors to at least MinTy's number of elements and at most...
LegalizeRuleSet & maxScalarIf(LegalityPredicate Predicate, unsigned TypeIdx, const LLT Ty)
Conditionally limit the maximum size of the scalar.
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & widenScalarToNextPow2(unsigned TypeIdx, unsigned MinSize=0)
Widen the scalar to the next power of two that is at least MinSize.
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalForTypesWithMemDesc(std::initializer_list< LegalityPredicates::TypePairAndMemDesc > TypesAndMemDesc)
The instruction is legal when type indexes 0 and 1 along with the memory size and minimum alignment i...
LegalizeRuleSet & libcallIf(LegalityPredicate Predicate)
Like legalIf, but for the Libcall action.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
LegalizeResult lowerDynStackAlloc(MachineInstr &MI)
LegalizeResult lowerBitCount(MachineInstr &MI)
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI)
Lower a vector extract or insert by writing the vector to a stack temporary and reloading the element...
LegalizeResult lowerAbsToCNeg(MachineInstr &MI)
const TargetLowering & getTargetLowering() const
LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI)
@ Legalized
Instruction has been legalized and the MachineFunction changed.
@ UnableToLegalize
Some kind of error has occurred and we could not legalize this instruction.
GISelChangeObserver & Observer
To keep track of changes made by the LegalizerHelper.
Register getDynStackAllocTargetPtr(Register SPReg, Register AllocSize, Align Alignment, LLT PtrTy)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ZEXT Op.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_TRUNC Op.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Wrapper class representing virtual and physical registers.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
const TargetMachine & getTargetMachine() const
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Primary interface to the complete machine description for the target machine.
Target - Wrapper for Target specific information.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
LegalityPredicate smallerThan(unsigned TypeIdx0, unsigned TypeIdx1)
True iff the first type index has a smaller total bit size than second type index.
LegalityPredicate atomicOrderingAtLeastOrStrongerThan(unsigned MMOIdx, AtomicOrdering Ordering)
True iff the specified MMO index has at an atomic ordering of at Ordering or stronger.
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
LegalityPredicate typeIs(unsigned TypeIdx, LLT TypesInit)
True iff the given type index is the specified type.
Predicate predNot(Predicate P)
True iff P is false.
@ Bitcast
Perform the operation on a different, but equivalently sized type.
LegalizeMutation moreElementsToNextPow2(unsigned TypeIdx, unsigned Min=0)
Add more elements to the type for the given type index to the next power of.
LegalizeMutation scalarize(unsigned TypeIdx)
Break up the vector type for the given type index into the element type.
LegalizeMutation widenScalarOrEltToNextPow2(unsigned TypeIdx, unsigned Min=0)
Widen the scalar type or vector element type for the given type index to the next power of 2.
LegalizeMutation changeTo(unsigned TypeIdx, LLT Ty)
Select this specific type for the given type index.
LegalizeMutation changeElementSizeTo(unsigned TypeIdx, unsigned FromTypeIdx)
Change the scalar size or element size to have the same scalar size as type index FromIndex.
operand_type_match m_Reg()
ConstantMatch< APInt > m_ICst(APInt &Cst)
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
BinaryOp_match< LHS, RHS, TargetOpcode::G_PTR_ADD, false > m_GPtrAdd(const LHS &L, const RHS &R)
This is an optimization pass for GlobalISel generic memory operations.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
constexpr unsigned BitWidth
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
unsigned Log2(Align A)
Returns the log2 of the alignment.
std::function< bool(const LegalityQuery &)> LegalityPredicate
This struct is a compact representation of a valid (non-zero power of two) alignment.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...
ArrayRef< MemDesc > MMODescrs
Operations which require memory can use this to place requirements on the memory type for each MMO.
This class contains a discriminated union of information about pointers in memory operands,...