32#include "llvm/IR/IntrinsicsAArch64.h"
38#define GET_TARGET_REGBANK_IMPL
39#include "AArch64GenRegisterBank.inc"
42#include "AArch64GenRegisterBankInfo.def"
50 static auto InitializeRegisterBankOnce = [&]() {
59 assert(&AArch64::GPRRegBank == &RBGPR &&
60 "The order in RegBanks is messed up");
64 assert(&AArch64::FPRRegBank == &RBFPR &&
65 "The order in RegBanks is messed up");
69 assert(&AArch64::CCRegBank == &RBCCR &&
70 "The order in RegBanks is messed up");
75 "Subclass not added?");
77 "GPRs should hold up to 128-bit");
82 "Subclass not added?");
84 "Subclass not added?");
86 "FPRs should hold up to 512-bit via QQQQ sequence");
91 "CCR should hold up to 32-bit");
97 "PartialMappingIdx's are incorrectly ordered");
101 "PartialMappingIdx's are incorrectly ordered");
104#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
107 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
108 #Idx " is incorrectly initialized"); \
122#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
124 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
125 PartialMappingIdx::PMI_First##RBName, Size, \
127 #RBName #Size " " #Offset " is incorrectly initialized"); \
130#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
144#define CHECK_VALUEMAP_3OPS(RBName, Size) \
146 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
147 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
148 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
160#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
162 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
163 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
164 (void)PartialMapDstIdx; \
165 (void)PartialMapSrcIdx; \
166 const ValueMapping *Map = getCopyMapping( \
167 AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
169 assert(Map[0].BreakDown == \
170 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
171 Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
172 " Dst is incorrectly initialized"); \
173 assert(Map[1].BreakDown == \
174 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
175 Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
176 " Src is incorrectly initialized"); \
189#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
191 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
192 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
193 (void)PartialMapDstIdx; \
194 (void)PartialMapSrcIdx; \
195 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
197 assert(Map[0].BreakDown == \
198 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
199 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
200 " Dst is incorrectly initialized"); \
201 assert(Map[1].BreakDown == \
202 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
203 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
204 " Src is incorrectly initialized"); \
216 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
230 if (&
A == &AArch64::GPRRegBank && &
B == &AArch64::FPRRegBank)
233 if (&
A == &AArch64::FPRRegBank && &
B == &AArch64::GPRRegBank)
243 switch (RC.
getID()) {
244 case AArch64::FPR8RegClassID:
245 case AArch64::FPR16RegClassID:
246 case AArch64::FPR16_loRegClassID:
247 case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
248 case AArch64::FPR32RegClassID:
249 case AArch64::FPR64RegClassID:
250 case AArch64::FPR128RegClassID:
251 case AArch64::FPR64_loRegClassID:
252 case AArch64::FPR128_loRegClassID:
253 case AArch64::FPR128_0to7RegClassID:
254 case AArch64::DDRegClassID:
255 case AArch64::DDDRegClassID:
256 case AArch64::DDDDRegClassID:
257 case AArch64::QQRegClassID:
258 case AArch64::QQQRegClassID:
259 case AArch64::QQQQRegClassID:
261 case AArch64::GPR32commonRegClassID:
262 case AArch64::GPR32RegClassID:
263 case AArch64::GPR32spRegClassID:
264 case AArch64::GPR32sponlyRegClassID:
265 case AArch64::GPR32argRegClassID:
266 case AArch64::GPR32allRegClassID:
267 case AArch64::GPR64commonRegClassID:
268 case AArch64::GPR64RegClassID:
269 case AArch64::GPR64spRegClassID:
270 case AArch64::GPR64sponlyRegClassID:
271 case AArch64::GPR64argRegClassID:
272 case AArch64::GPR64allRegClassID:
273 case AArch64::GPR64noipRegClassID:
274 case AArch64::GPR64common_and_GPR64noipRegClassID:
275 case AArch64::GPR64noip_and_tcGPR64RegClassID:
276 case AArch64::tcGPR64RegClassID:
277 case AArch64::tcGPRx16x17RegClassID:
278 case AArch64::tcGPRx17RegClassID:
279 case AArch64::tcGPRnotx16RegClassID:
280 case AArch64::WSeqPairsClassRegClassID:
281 case AArch64::XSeqPairsClassRegClassID:
282 case AArch64::MatrixIndexGPR32_8_11RegClassID:
283 case AArch64::MatrixIndexGPR32_12_15RegClassID:
284 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID:
285 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
287 case AArch64::CCRRegClassID:
302 switch (
MI.getOpcode()) {
303 case TargetOpcode::G_OR: {
312 if (
MI.getNumOperands() != 3)
326 case TargetOpcode::G_BITCAST: {
333 if (
MI.getNumOperands() != 2)
348 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
355 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
366 case TargetOpcode::G_LOAD: {
373 if (
MI.getNumOperands() != 2)
400void AArch64RegisterBankInfo::applyMappingImpl(
405 switch (
MI.getOpcode()) {
406 case TargetOpcode::G_OR:
407 case TargetOpcode::G_BITCAST:
408 case TargetOpcode::G_LOAD:
410 assert((OpdMapper.getInstrMapping().getID() >= 1 &&
411 OpdMapper.getInstrMapping().getID() <= 4) &&
412 "Don't know how to handle that ID");
414 case TargetOpcode::G_INSERT_VECTOR_ELT: {
418 MRI.setRegBank(Ext.getReg(0),
getRegBank(AArch64::GPRRegBankID));
419 MI.getOperand(2).setReg(Ext.getReg(0));
428AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
430 const unsigned Opc =
MI.getOpcode();
434 unsigned NumOperands =
MI.getNumOperands();
435 assert(NumOperands <= 3 &&
436 "This code is for instructions with 3 or less operands");
438 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
453 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
454 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
459 "Operand has incompatible size");
462 assert(IsFPR == OpIsFPR &&
"Operand has incompatible type");
477 case Intrinsic::aarch64_neon_uaddlv:
478 case Intrinsic::aarch64_neon_uaddv:
479 case Intrinsic::aarch64_neon_saddv:
480 case Intrinsic::aarch64_neon_umaxv:
481 case Intrinsic::aarch64_neon_smaxv:
482 case Intrinsic::aarch64_neon_uminv:
483 case Intrinsic::aarch64_neon_sminv:
484 case Intrinsic::aarch64_neon_faddv:
485 case Intrinsic::aarch64_neon_fmaxv:
486 case Intrinsic::aarch64_neon_fminv:
487 case Intrinsic::aarch64_neon_fmaxnmv:
488 case Intrinsic::aarch64_neon_fminnmv:
490 case Intrinsic::aarch64_neon_saddlv: {
491 const LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
498bool AArch64RegisterBankInfo::hasFPConstraints(
const MachineInstr &
MI,
501 unsigned Depth)
const {
502 unsigned Op =
MI.getOpcode();
512 if (
Op != TargetOpcode::COPY && !
MI.isPHI() &&
518 if (RB == &AArch64::FPRRegBank)
520 if (RB == &AArch64::GPRRegBank)
527 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
532 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
539 unsigned Depth)
const {
540 switch (
MI.getOpcode()) {
541 case TargetOpcode::G_FPTOSI:
542 case TargetOpcode::G_FPTOUI:
543 case TargetOpcode::G_FCMP:
544 case TargetOpcode::G_LROUND:
545 case TargetOpcode::G_LLROUND:
553bool AArch64RegisterBankInfo::onlyDefinesFP(
const MachineInstr &
MI,
556 unsigned Depth)
const {
557 switch (
MI.getOpcode()) {
559 case TargetOpcode::G_SITOFP:
560 case TargetOpcode::G_UITOFP:
561 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
562 case TargetOpcode::G_INSERT_VECTOR_ELT:
563 case TargetOpcode::G_BUILD_VECTOR:
564 case TargetOpcode::G_BUILD_VECTOR_TRUNC:
566 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
568 case Intrinsic::aarch64_neon_ld1x2:
569 case Intrinsic::aarch64_neon_ld1x3:
570 case Intrinsic::aarch64_neon_ld1x4:
571 case Intrinsic::aarch64_neon_ld2:
572 case Intrinsic::aarch64_neon_ld2lane:
573 case Intrinsic::aarch64_neon_ld2r:
574 case Intrinsic::aarch64_neon_ld3:
575 case Intrinsic::aarch64_neon_ld3lane:
576 case Intrinsic::aarch64_neon_ld3r:
577 case Intrinsic::aarch64_neon_ld4:
578 case Intrinsic::aarch64_neon_ld4lane:
579 case Intrinsic::aarch64_neon_ld4r:
591bool AArch64RegisterBankInfo::isLoadFromFPType(
const MachineInstr &
MI)
const {
593 auto *
MemOp = cast<GMemOperation>(&
MI);
594 const Value *LdVal =
MemOp->getMMO().getValue();
598 Type *EltTy =
nullptr;
599 if (
const GlobalValue *GV = dyn_cast<GlobalValue>(LdVal)) {
600 EltTy = GV->getValueType();
603 while (
StructType *StructEltTy = dyn_cast<StructType>(EltTy)) {
604 if (StructEltTy->getNumElements() == 0)
606 EltTy = StructEltTy->getTypeAtIndex(0U);
609 if (isa<ArrayType>(EltTy))
614 for (
const auto *LdUser : LdVal->
users()) {
615 if (isa<LoadInst>(LdUser)) {
616 EltTy = LdUser->getType();
619 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
620 EltTy = LdUser->getOperand(0)->getType();
630 const unsigned Opc =
MI.getOpcode();
635 Opc == TargetOpcode::G_PHI) {
650 case TargetOpcode::G_ADD:
651 case TargetOpcode::G_SUB:
652 case TargetOpcode::G_PTR_ADD:
653 case TargetOpcode::G_MUL:
654 case TargetOpcode::G_SDIV:
655 case TargetOpcode::G_UDIV:
657 case TargetOpcode::G_AND:
658 case TargetOpcode::G_OR:
659 case TargetOpcode::G_XOR:
661 case TargetOpcode::G_FADD:
662 case TargetOpcode::G_FSUB:
663 case TargetOpcode::G_FMUL:
664 case TargetOpcode::G_FDIV:
665 case TargetOpcode::G_FMAXIMUM:
666 case TargetOpcode::G_FMINIMUM:
667 return getSameKindOfOperandsMapping(
MI);
668 case TargetOpcode::G_FPEXT: {
669 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
670 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
677 case TargetOpcode::G_SHL:
678 case TargetOpcode::G_LSHR:
679 case TargetOpcode::G_ASHR: {
680 LLT ShiftAmtTy =
MRI.getType(
MI.getOperand(2).getReg());
681 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
685 return getSameKindOfOperandsMapping(
MI);
687 case TargetOpcode::COPY: {
691 if ((DstReg.
isPhysical() || !
MRI.getType(DstReg).isValid()) ||
701 assert(DstRB && SrcRB &&
"Both RegBank were nullptr");
712 case TargetOpcode::G_BITCAST: {
713 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
714 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
719 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
721 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
726 Opc == TargetOpcode::G_BITCAST ? 2 : 1);
732 unsigned NumOperands =
MI.getNumOperands();
738 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
739 auto &MO =
MI.getOperand(
Idx);
740 if (!MO.isReg() || !MO.getReg())
743 LLT Ty =
MRI.getType(MO.getReg());
761 case AArch64::G_DUP: {
762 Register ScalarReg =
MI.getOperand(1).getReg();
763 LLT ScalarTy =
MRI.getType(ScalarReg);
764 auto ScalarDef =
MRI.getVRegDef(ScalarReg);
766 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
771 onlyDefinesFP(*ScalarDef,
MRI,
TRI)))
777 case TargetOpcode::G_TRUNC: {
778 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
783 case TargetOpcode::G_SITOFP:
784 case TargetOpcode::G_UITOFP: {
785 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
796 case TargetOpcode::G_FPTOSI:
797 case TargetOpcode::G_FPTOUI:
798 case TargetOpcode::G_INTRINSIC_LRINT:
799 case TargetOpcode::G_INTRINSIC_LLRINT:
800 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
804 case TargetOpcode::G_FCMP: {
809 OpRegBankIdx = {Idx0,
813 case TargetOpcode::G_BITCAST:
815 if (OpRegBankIdx[0] != OpRegBankIdx[1])
821 case TargetOpcode::G_LOAD: {
833 if (cast<GLoad>(
MI).isAtomic()) {
840 if (isLoadFromFPType(
MI)) {
848 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
857 return onlyUsesFP(UseMI, MRI, TRI) ||
858 onlyDefinesFP(UseMI, MRI, TRI);
863 case TargetOpcode::G_STORE:
875 case TargetOpcode::G_INDEXED_STORE:
886 case TargetOpcode::G_INDEXED_SEXTLOAD:
887 case TargetOpcode::G_INDEXED_ZEXTLOAD:
891 case TargetOpcode::G_INDEXED_LOAD: {
892 if (isLoadFromFPType(
MI))
896 case TargetOpcode::G_SELECT: {
903 LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
920 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
952 case TargetOpcode::G_UNMERGE_VALUES: {
958 LLT SrcTy =
MRI.getType(
MI.getOperand(
MI.getNumOperands()-1).getReg());
962 any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
965 for (
unsigned Idx = 0, NumOperands =
MI.getNumOperands();
971 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
979 case TargetOpcode::G_INSERT_VECTOR_ELT:
989 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
998 case TargetOpcode::G_EXTRACT: {
1000 auto Src =
MI.getOperand(1).getReg();
1001 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
1004 auto Idx =
MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
1007 OpRegBankIdx[0] =
Idx;
1008 OpRegBankIdx[1] =
Idx;
1011 case TargetOpcode::G_BUILD_VECTOR: {
1027 const LLT SrcTy =
MRI.getType(VReg);
1029 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1030 TargetOpcode::G_CONSTANT;
1038 unsigned NumOperands =
MI.getNumOperands();
1039 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx)
1044 case TargetOpcode::G_VECREDUCE_FADD:
1045 case TargetOpcode::G_VECREDUCE_FMUL:
1046 case TargetOpcode::G_VECREDUCE_FMAX:
1047 case TargetOpcode::G_VECREDUCE_FMIN:
1048 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1049 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1050 case TargetOpcode::G_VECREDUCE_ADD:
1051 case TargetOpcode::G_VECREDUCE_MUL:
1052 case TargetOpcode::G_VECREDUCE_AND:
1053 case TargetOpcode::G_VECREDUCE_OR:
1054 case TargetOpcode::G_VECREDUCE_XOR:
1055 case TargetOpcode::G_VECREDUCE_SMAX:
1056 case TargetOpcode::G_VECREDUCE_SMIN:
1057 case TargetOpcode::G_VECREDUCE_UMAX:
1058 case TargetOpcode::G_VECREDUCE_UMIN:
1063 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1064 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
1069 case TargetOpcode::G_INTRINSIC:
1070 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1075 for (
const auto &
Op :
MI.defs()) {
1081 Idx +=
MI.getNumExplicitDefs();
1084 for (
const auto &
Op :
MI.explicit_uses()) {
1091 case TargetOpcode::G_LROUND:
1092 case TargetOpcode::G_LLROUND: {
1101 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
1102 if (
MI.getOperand(
Idx).isReg() &&
MI.getOperand(
Idx).getReg()) {
1103 LLT Ty =
MRI.getType(
MI.getOperand(
Idx).getReg());
1107 if (!Mapping->isValid())
1110 OpdsMapping[
Idx] = Mapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static unsigned getIntrinsicID(const SDNode *N)
#define CHECK_VALUEMAP(RBName, Size)
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define CHECK_VALUEMAP_3OPS(RBName, Size)
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
This file declares the targeting of the RegisterBankInfo class for AArch64.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static const RegisterBankInfo::PartialMapping PartMappings[]
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static const RegisterBankInfo::ValueMapping ValMappings[]
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
This class represents an Operation in the Expression.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Class to represent struct types.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
Type * getArrayElementType() const
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
LLVM Value Representation.
iterator_range< user_iterator > users()
constexpr ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
The llvm::once_flag structure.