28#include "llvm/IR/IntrinsicsLoongArch.h"
37#define DEBUG_TYPE "loongarch-isel-lowering"
42 cl::desc(
"Trap on integer division by zero."),
54 if (Subtarget.hasBasicF())
56 if (Subtarget.hasBasicD())
60 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64};
62 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64};
64 if (Subtarget.hasExtLSX())
68 if (Subtarget.hasExtLASX())
69 for (
MVT VT : LASXVTs)
170 if (Subtarget.hasBasicF()) {
190 if (!Subtarget.hasBasicD()) {
201 if (Subtarget.hasBasicD()) {
226 if (Subtarget.hasExtLSX()) {
241 for (
MVT VT : LSXVTs) {
253 for (
MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
268 for (
MVT VT : {MVT::v4i32, MVT::v2i64}) {
272 for (
MVT VT : {MVT::v4f32, MVT::v2f64}) {
286 if (Subtarget.hasExtLASX()) {
287 for (
MVT VT : LASXVTs) {
299 for (
MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
314 for (
MVT VT : {MVT::v8i32, MVT::v4i32, MVT::v4i64}) {
318 for (
MVT VT : {MVT::v8f32, MVT::v4f64}) {
338 if (Subtarget.hasExtLSX())
372 switch (
Op.getOpcode()) {
374 return lowerATOMIC_FENCE(
Op, DAG);
376 return lowerEH_DWARF_CFA(
Op, DAG);
378 return lowerGlobalAddress(
Op, DAG);
380 return lowerGlobalTLSAddress(
Op, DAG);
382 return lowerINTRINSIC_WO_CHAIN(
Op, DAG);
384 return lowerINTRINSIC_W_CHAIN(
Op, DAG);
386 return lowerINTRINSIC_VOID(
Op, DAG);
388 return lowerBlockAddress(
Op, DAG);
390 return lowerJumpTable(
Op, DAG);
392 return lowerShiftLeftParts(
Op, DAG);
394 return lowerShiftRightParts(
Op, DAG,
true);
396 return lowerShiftRightParts(
Op, DAG,
false);
398 return lowerConstantPool(
Op, DAG);
400 return lowerFP_TO_SINT(
Op, DAG);
402 return lowerBITCAST(
Op, DAG);
404 return lowerUINT_TO_FP(
Op, DAG);
406 return lowerSINT_TO_FP(
Op, DAG);
408 return lowerVASTART(
Op, DAG);
410 return lowerFRAMEADDR(
Op, DAG);
412 return lowerRETURNADDR(
Op, DAG);
414 return lowerWRITE_REGISTER(
Op, DAG);
416 return lowerINSERT_VECTOR_ELT(
Op, DAG);
418 return lowerEXTRACT_VECTOR_ELT(
Op, DAG);
420 return lowerBUILD_VECTOR(
Op, DAG);
422 return lowerVECTOR_SHUFFLE(
Op, DAG);
436 if (isa<ConstantSDNode>(
Op))
438 if (isa<ConstantFPSDNode>(
Op))
453 EVT ResTy =
Op->getValueType(0);
455 APInt SplatValue, SplatUndef;
456 unsigned SplatBitSize;
461 if ((!Subtarget.hasExtLSX() || !Is128Vec) &&
462 (!Subtarget.hasExtLASX() || !Is256Vec))
465 if (
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
467 SplatBitSize <= 64) {
469 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
475 switch (SplatBitSize) {
479 ViaVecTy = Is128Vec ? MVT::v16i8 : MVT::v32i8;
482 ViaVecTy = Is128Vec ? MVT::v8i16 : MVT::v16i16;
485 ViaVecTy = Is128Vec ? MVT::v4i32 : MVT::v8i32;
488 ViaVecTy = Is128Vec ? MVT::v2i64 : MVT::v4i64;
496 if (ViaVecTy != ResTy)
509 EVT ResTy =
Node->getValueType(0);
515 for (
unsigned i = 0; i < NumElts; ++i) {
527LoongArchTargetLowering::lowerEXTRACT_VECTOR_ELT(
SDValue Op,
529 EVT VecTy =
Op->getOperand(0)->getValueType(0);
534 if (isa<ConstantSDNode>(
Idx) &&
535 (EltTy == MVT::i32 || EltTy == MVT::i64 || EltTy == MVT::f32 ||
536 EltTy == MVT::f64 ||
Idx->getAsZExtVal() < NumElts / 2))
543LoongArchTargetLowering::lowerINSERT_VECTOR_ELT(
SDValue Op,
545 if (isa<ConstantSDNode>(
Op->getOperand(2)))
569 if (Subtarget.
is64Bit() &&
Op.getOperand(2).getValueType() == MVT::i32) {
571 "On LA64, only 64-bit registers can be written.");
572 return Op.getOperand(0);
575 if (!Subtarget.
is64Bit() &&
Op.getOperand(2).getValueType() == MVT::i64) {
577 "On LA32, only 32-bit registers can be written.");
578 return Op.getOperand(0);
586 if (!isa<ConstantSDNode>(
Op.getOperand(0))) {
588 "be a constant integer");
595 EVT VT =
Op.getValueType();
598 unsigned Depth =
Op.getConstantOperandVal(0);
599 int GRLenInBytes = Subtarget.
getGRLen() / 8;
602 int Offset = -(GRLenInBytes * 2);
617 if (
Op.getConstantOperandVal(0) != 0) {
619 "return address can only be determined for the current frame");
653 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
661 !Subtarget.hasBasicD() &&
"unexpected target features");
666 auto *
C = dyn_cast<ConstantSDNode>(Op0.
getOperand(1));
667 if (
C &&
C->getZExtValue() < UINT64_C(0xFFFFFFFF))
677 dyn_cast<VTSDNode>(Op0.
getOperand(1))->getVT().bitsLT(MVT::i32))
681 EVT RetVT =
Op.getValueType();
683 MakeLibCallOptions CallOptions;
684 CallOptions.setTypeListBeforeSoften(OpVT, RetVT,
true);
687 std::tie(Result, Chain) =
695 !Subtarget.hasBasicD() &&
"unexpected target features");
702 dyn_cast<VTSDNode>(Op0.
getOperand(1))->getVT().bitsLE(MVT::i32))
706 EVT RetVT =
Op.getValueType();
708 MakeLibCallOptions CallOptions;
709 CallOptions.setTypeListBeforeSoften(OpVT, RetVT,
true);
712 std::tie(Result, Chain) =
723 if (
Op.getValueType() == MVT::f32 && Op0.
getValueType() == MVT::i32 &&
724 Subtarget.
is64Bit() && Subtarget.hasBasicF()) {
736 if (
Op.getValueSizeInBits() > 32 && Subtarget.hasBasicF() &&
737 !Subtarget.hasBasicD()) {
762 N->getOffset(), Flags);
770template <
class NodeTy>
773 bool IsLocal)
const {
783 assert(Subtarget.
is64Bit() &&
"Large code model requires LA64");
819 return getAddr(cast<BlockAddressSDNode>(
Op), DAG,
825 return getAddr(cast<JumpTableSDNode>(
Op), DAG,
831 return getAddr(cast<ConstantPoolSDNode>(
Op), DAG,
838 assert(
N->getOffset() == 0 &&
"unexpected offset in global node");
842 if (GV->
isDSOLocal() && isa<GlobalVariable>(GV)) {
843 if (
auto GCM = dyn_cast<GlobalVariable>(GV)->
getCodeModel())
893 Args.push_back(Entry);
925LoongArchTargetLowering::lowerGlobalTLSAddress(
SDValue Op,
932 assert((!Large || Subtarget.
is64Bit()) &&
"Large code model requires LA64");
935 assert(
N->getOffset() == 0 &&
"unexpected offset in global node");
945 return getDynamicTLSAddr(
N, DAG,
946 Large ? LoongArch::PseudoLA_TLS_GD_LARGE
947 : LoongArch::PseudoLA_TLS_GD,
954 return getDynamicTLSAddr(
N, DAG,
955 Large ? LoongArch::PseudoLA_TLS_LD_LARGE
956 : LoongArch::PseudoLA_TLS_LD,
961 return getStaticTLSAddr(
N, DAG,
962 Large ? LoongArch::PseudoLA_TLS_IE_LARGE
963 : LoongArch::PseudoLA_TLS_IE,
970 return getStaticTLSAddr(
N, DAG, LoongArch::PseudoLA_TLS_LE);
973 return getTLSDescAddr(
N, DAG,
974 Large ? LoongArch::PseudoLA_TLS_DESC_PC_LARGE
975 : LoongArch::PseudoLA_TLS_DESC_PC,
982 auto *CImm = cast<ConstantSDNode>(
Op->getOperand(ImmOp));
984 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) ||
985 (!IsSigned && !isUInt<N>(CImm->getZExtValue()))) {
987 ": argument out of range.");
994LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(
SDValue Op,
997 switch (
Op.getConstantOperandVal(0)) {
1000 case Intrinsic::thread_pointer: {
1004 case Intrinsic::loongarch_lsx_vpickve2gr_d:
1005 case Intrinsic::loongarch_lsx_vpickve2gr_du:
1006 case Intrinsic::loongarch_lsx_vreplvei_d:
1007 case Intrinsic::loongarch_lasx_xvrepl128vei_d:
1008 return checkIntrinsicImmArg<1>(
Op, 2, DAG);
1009 case Intrinsic::loongarch_lsx_vreplvei_w:
1010 case Intrinsic::loongarch_lasx_xvrepl128vei_w:
1011 case Intrinsic::loongarch_lasx_xvpickve2gr_d:
1012 case Intrinsic::loongarch_lasx_xvpickve2gr_du:
1013 case Intrinsic::loongarch_lasx_xvpickve_d:
1014 case Intrinsic::loongarch_lasx_xvpickve_d_f:
1015 return checkIntrinsicImmArg<2>(
Op, 2, DAG);
1016 case Intrinsic::loongarch_lasx_xvinsve0_d:
1017 return checkIntrinsicImmArg<2>(
Op, 3, DAG);
1018 case Intrinsic::loongarch_lsx_vsat_b:
1019 case Intrinsic::loongarch_lsx_vsat_bu:
1020 case Intrinsic::loongarch_lsx_vrotri_b:
1021 case Intrinsic::loongarch_lsx_vsllwil_h_b:
1022 case Intrinsic::loongarch_lsx_vsllwil_hu_bu:
1023 case Intrinsic::loongarch_lsx_vsrlri_b:
1024 case Intrinsic::loongarch_lsx_vsrari_b:
1025 case Intrinsic::loongarch_lsx_vreplvei_h:
1026 case Intrinsic::loongarch_lasx_xvsat_b:
1027 case Intrinsic::loongarch_lasx_xvsat_bu:
1028 case Intrinsic::loongarch_lasx_xvrotri_b:
1029 case Intrinsic::loongarch_lasx_xvsllwil_h_b:
1030 case Intrinsic::loongarch_lasx_xvsllwil_hu_bu:
1031 case Intrinsic::loongarch_lasx_xvsrlri_b:
1032 case Intrinsic::loongarch_lasx_xvsrari_b:
1033 case Intrinsic::loongarch_lasx_xvrepl128vei_h:
1034 case Intrinsic::loongarch_lasx_xvpickve_w:
1035 case Intrinsic::loongarch_lasx_xvpickve_w_f:
1036 return checkIntrinsicImmArg<3>(
Op, 2, DAG);
1037 case Intrinsic::loongarch_lasx_xvinsve0_w:
1038 return checkIntrinsicImmArg<3>(
Op, 3, DAG);
1039 case Intrinsic::loongarch_lsx_vsat_h:
1040 case Intrinsic::loongarch_lsx_vsat_hu:
1041 case Intrinsic::loongarch_lsx_vrotri_h:
1042 case Intrinsic::loongarch_lsx_vsllwil_w_h:
1043 case Intrinsic::loongarch_lsx_vsllwil_wu_hu:
1044 case Intrinsic::loongarch_lsx_vsrlri_h:
1045 case Intrinsic::loongarch_lsx_vsrari_h:
1046 case Intrinsic::loongarch_lsx_vreplvei_b:
1047 case Intrinsic::loongarch_lasx_xvsat_h:
1048 case Intrinsic::loongarch_lasx_xvsat_hu:
1049 case Intrinsic::loongarch_lasx_xvrotri_h:
1050 case Intrinsic::loongarch_lasx_xvsllwil_w_h:
1051 case Intrinsic::loongarch_lasx_xvsllwil_wu_hu:
1052 case Intrinsic::loongarch_lasx_xvsrlri_h:
1053 case Intrinsic::loongarch_lasx_xvsrari_h:
1054 case Intrinsic::loongarch_lasx_xvrepl128vei_b:
1055 return checkIntrinsicImmArg<4>(
Op, 2, DAG);
1056 case Intrinsic::loongarch_lsx_vsrlni_b_h:
1057 case Intrinsic::loongarch_lsx_vsrani_b_h:
1058 case Intrinsic::loongarch_lsx_vsrlrni_b_h:
1059 case Intrinsic::loongarch_lsx_vsrarni_b_h:
1060 case Intrinsic::loongarch_lsx_vssrlni_b_h:
1061 case Intrinsic::loongarch_lsx_vssrani_b_h:
1062 case Intrinsic::loongarch_lsx_vssrlni_bu_h:
1063 case Intrinsic::loongarch_lsx_vssrani_bu_h:
1064 case Intrinsic::loongarch_lsx_vssrlrni_b_h:
1065 case Intrinsic::loongarch_lsx_vssrarni_b_h:
1066 case Intrinsic::loongarch_lsx_vssrlrni_bu_h:
1067 case Intrinsic::loongarch_lsx_vssrarni_bu_h:
1068 case Intrinsic::loongarch_lasx_xvsrlni_b_h:
1069 case Intrinsic::loongarch_lasx_xvsrani_b_h:
1070 case Intrinsic::loongarch_lasx_xvsrlrni_b_h:
1071 case Intrinsic::loongarch_lasx_xvsrarni_b_h:
1072 case Intrinsic::loongarch_lasx_xvssrlni_b_h:
1073 case Intrinsic::loongarch_lasx_xvssrani_b_h:
1074 case Intrinsic::loongarch_lasx_xvssrlni_bu_h:
1075 case Intrinsic::loongarch_lasx_xvssrani_bu_h:
1076 case Intrinsic::loongarch_lasx_xvssrlrni_b_h:
1077 case Intrinsic::loongarch_lasx_xvssrarni_b_h:
1078 case Intrinsic::loongarch_lasx_xvssrlrni_bu_h:
1079 case Intrinsic::loongarch_lasx_xvssrarni_bu_h:
1080 return checkIntrinsicImmArg<4>(
Op, 3, DAG);
1081 case Intrinsic::loongarch_lsx_vsat_w:
1082 case Intrinsic::loongarch_lsx_vsat_wu:
1083 case Intrinsic::loongarch_lsx_vrotri_w:
1084 case Intrinsic::loongarch_lsx_vsllwil_d_w:
1085 case Intrinsic::loongarch_lsx_vsllwil_du_wu:
1086 case Intrinsic::loongarch_lsx_vsrlri_w:
1087 case Intrinsic::loongarch_lsx_vsrari_w:
1088 case Intrinsic::loongarch_lsx_vslei_bu:
1089 case Intrinsic::loongarch_lsx_vslei_hu:
1090 case Intrinsic::loongarch_lsx_vslei_wu:
1091 case Intrinsic::loongarch_lsx_vslei_du:
1092 case Intrinsic::loongarch_lsx_vslti_bu:
1093 case Intrinsic::loongarch_lsx_vslti_hu:
1094 case Intrinsic::loongarch_lsx_vslti_wu:
1095 case Intrinsic::loongarch_lsx_vslti_du:
1096 case Intrinsic::loongarch_lsx_vbsll_v:
1097 case Intrinsic::loongarch_lsx_vbsrl_v:
1098 case Intrinsic::loongarch_lasx_xvsat_w:
1099 case Intrinsic::loongarch_lasx_xvsat_wu:
1100 case Intrinsic::loongarch_lasx_xvrotri_w:
1101 case Intrinsic::loongarch_lasx_xvsllwil_d_w:
1102 case Intrinsic::loongarch_lasx_xvsllwil_du_wu:
1103 case Intrinsic::loongarch_lasx_xvsrlri_w:
1104 case Intrinsic::loongarch_lasx_xvsrari_w:
1105 case Intrinsic::loongarch_lasx_xvslei_bu:
1106 case Intrinsic::loongarch_lasx_xvslei_hu:
1107 case Intrinsic::loongarch_lasx_xvslei_wu:
1108 case Intrinsic::loongarch_lasx_xvslei_du:
1109 case Intrinsic::loongarch_lasx_xvslti_bu:
1110 case Intrinsic::loongarch_lasx_xvslti_hu:
1111 case Intrinsic::loongarch_lasx_xvslti_wu:
1112 case Intrinsic::loongarch_lasx_xvslti_du:
1113 case Intrinsic::loongarch_lasx_xvbsll_v:
1114 case Intrinsic::loongarch_lasx_xvbsrl_v:
1115 return checkIntrinsicImmArg<5>(
Op, 2, DAG);
1116 case Intrinsic::loongarch_lsx_vseqi_b:
1117 case Intrinsic::loongarch_lsx_vseqi_h:
1118 case Intrinsic::loongarch_lsx_vseqi_w:
1119 case Intrinsic::loongarch_lsx_vseqi_d:
1120 case Intrinsic::loongarch_lsx_vslei_b:
1121 case Intrinsic::loongarch_lsx_vslei_h:
1122 case Intrinsic::loongarch_lsx_vslei_w:
1123 case Intrinsic::loongarch_lsx_vslei_d:
1124 case Intrinsic::loongarch_lsx_vslti_b:
1125 case Intrinsic::loongarch_lsx_vslti_h:
1126 case Intrinsic::loongarch_lsx_vslti_w:
1127 case Intrinsic::loongarch_lsx_vslti_d:
1128 case Intrinsic::loongarch_lasx_xvseqi_b:
1129 case Intrinsic::loongarch_lasx_xvseqi_h:
1130 case Intrinsic::loongarch_lasx_xvseqi_w:
1131 case Intrinsic::loongarch_lasx_xvseqi_d:
1132 case Intrinsic::loongarch_lasx_xvslei_b:
1133 case Intrinsic::loongarch_lasx_xvslei_h:
1134 case Intrinsic::loongarch_lasx_xvslei_w:
1135 case Intrinsic::loongarch_lasx_xvslei_d:
1136 case Intrinsic::loongarch_lasx_xvslti_b:
1137 case Intrinsic::loongarch_lasx_xvslti_h:
1138 case Intrinsic::loongarch_lasx_xvslti_w:
1139 case Intrinsic::loongarch_lasx_xvslti_d:
1140 return checkIntrinsicImmArg<5>(
Op, 2, DAG,
true);
1141 case Intrinsic::loongarch_lsx_vsrlni_h_w:
1142 case Intrinsic::loongarch_lsx_vsrani_h_w:
1143 case Intrinsic::loongarch_lsx_vsrlrni_h_w:
1144 case Intrinsic::loongarch_lsx_vsrarni_h_w:
1145 case Intrinsic::loongarch_lsx_vssrlni_h_w:
1146 case Intrinsic::loongarch_lsx_vssrani_h_w:
1147 case Intrinsic::loongarch_lsx_vssrlni_hu_w:
1148 case Intrinsic::loongarch_lsx_vssrani_hu_w:
1149 case Intrinsic::loongarch_lsx_vssrlrni_h_w:
1150 case Intrinsic::loongarch_lsx_vssrarni_h_w:
1151 case Intrinsic::loongarch_lsx_vssrlrni_hu_w:
1152 case Intrinsic::loongarch_lsx_vssrarni_hu_w:
1153 case Intrinsic::loongarch_lsx_vfrstpi_b:
1154 case Intrinsic::loongarch_lsx_vfrstpi_h:
1155 case Intrinsic::loongarch_lasx_xvsrlni_h_w:
1156 case Intrinsic::loongarch_lasx_xvsrani_h_w:
1157 case Intrinsic::loongarch_lasx_xvsrlrni_h_w:
1158 case Intrinsic::loongarch_lasx_xvsrarni_h_w:
1159 case Intrinsic::loongarch_lasx_xvssrlni_h_w:
1160 case Intrinsic::loongarch_lasx_xvssrani_h_w:
1161 case Intrinsic::loongarch_lasx_xvssrlni_hu_w:
1162 case Intrinsic::loongarch_lasx_xvssrani_hu_w:
1163 case Intrinsic::loongarch_lasx_xvssrlrni_h_w:
1164 case Intrinsic::loongarch_lasx_xvssrarni_h_w:
1165 case Intrinsic::loongarch_lasx_xvssrlrni_hu_w:
1166 case Intrinsic::loongarch_lasx_xvssrarni_hu_w:
1167 case Intrinsic::loongarch_lasx_xvfrstpi_b:
1168 case Intrinsic::loongarch_lasx_xvfrstpi_h:
1169 return checkIntrinsicImmArg<5>(
Op, 3, DAG);
1170 case Intrinsic::loongarch_lsx_vsat_d:
1171 case Intrinsic::loongarch_lsx_vsat_du:
1172 case Intrinsic::loongarch_lsx_vrotri_d:
1173 case Intrinsic::loongarch_lsx_vsrlri_d:
1174 case Intrinsic::loongarch_lsx_vsrari_d:
1175 case Intrinsic::loongarch_lasx_xvsat_d:
1176 case Intrinsic::loongarch_lasx_xvsat_du:
1177 case Intrinsic::loongarch_lasx_xvrotri_d:
1178 case Intrinsic::loongarch_lasx_xvsrlri_d:
1179 case Intrinsic::loongarch_lasx_xvsrari_d:
1180 return checkIntrinsicImmArg<6>(
Op, 2, DAG);
1181 case Intrinsic::loongarch_lsx_vsrlni_w_d:
1182 case Intrinsic::loongarch_lsx_vsrani_w_d:
1183 case Intrinsic::loongarch_lsx_vsrlrni_w_d:
1184 case Intrinsic::loongarch_lsx_vsrarni_w_d:
1185 case Intrinsic::loongarch_lsx_vssrlni_w_d:
1186 case Intrinsic::loongarch_lsx_vssrani_w_d:
1187 case Intrinsic::loongarch_lsx_vssrlni_wu_d:
1188 case Intrinsic::loongarch_lsx_vssrani_wu_d:
1189 case Intrinsic::loongarch_lsx_vssrlrni_w_d:
1190 case Intrinsic::loongarch_lsx_vssrarni_w_d:
1191 case Intrinsic::loongarch_lsx_vssrlrni_wu_d:
1192 case Intrinsic::loongarch_lsx_vssrarni_wu_d:
1193 case Intrinsic::loongarch_lasx_xvsrlni_w_d:
1194 case Intrinsic::loongarch_lasx_xvsrani_w_d:
1195 case Intrinsic::loongarch_lasx_xvsrlrni_w_d:
1196 case Intrinsic::loongarch_lasx_xvsrarni_w_d:
1197 case Intrinsic::loongarch_lasx_xvssrlni_w_d:
1198 case Intrinsic::loongarch_lasx_xvssrani_w_d:
1199 case Intrinsic::loongarch_lasx_xvssrlni_wu_d:
1200 case Intrinsic::loongarch_lasx_xvssrani_wu_d:
1201 case Intrinsic::loongarch_lasx_xvssrlrni_w_d:
1202 case Intrinsic::loongarch_lasx_xvssrarni_w_d:
1203 case Intrinsic::loongarch_lasx_xvssrlrni_wu_d:
1204 case Intrinsic::loongarch_lasx_xvssrarni_wu_d:
1205 return checkIntrinsicImmArg<6>(
Op, 3, DAG);
1206 case Intrinsic::loongarch_lsx_vsrlni_d_q:
1207 case Intrinsic::loongarch_lsx_vsrani_d_q:
1208 case Intrinsic::loongarch_lsx_vsrlrni_d_q:
1209 case Intrinsic::loongarch_lsx_vsrarni_d_q:
1210 case Intrinsic::loongarch_lsx_vssrlni_d_q:
1211 case Intrinsic::loongarch_lsx_vssrani_d_q:
1212 case Intrinsic::loongarch_lsx_vssrlni_du_q:
1213 case Intrinsic::loongarch_lsx_vssrani_du_q:
1214 case Intrinsic::loongarch_lsx_vssrlrni_d_q:
1215 case Intrinsic::loongarch_lsx_vssrarni_d_q:
1216 case Intrinsic::loongarch_lsx_vssrlrni_du_q:
1217 case Intrinsic::loongarch_lsx_vssrarni_du_q:
1218 case Intrinsic::loongarch_lasx_xvsrlni_d_q:
1219 case Intrinsic::loongarch_lasx_xvsrani_d_q:
1220 case Intrinsic::loongarch_lasx_xvsrlrni_d_q:
1221 case Intrinsic::loongarch_lasx_xvsrarni_d_q:
1222 case Intrinsic::loongarch_lasx_xvssrlni_d_q:
1223 case Intrinsic::loongarch_lasx_xvssrani_d_q:
1224 case Intrinsic::loongarch_lasx_xvssrlni_du_q:
1225 case Intrinsic::loongarch_lasx_xvssrani_du_q:
1226 case Intrinsic::loongarch_lasx_xvssrlrni_d_q:
1227 case Intrinsic::loongarch_lasx_xvssrarni_d_q:
1228 case Intrinsic::loongarch_lasx_xvssrlrni_du_q:
1229 case Intrinsic::loongarch_lasx_xvssrarni_du_q:
1230 return checkIntrinsicImmArg<7>(
Op, 3, DAG);
1231 case Intrinsic::loongarch_lsx_vnori_b:
1232 case Intrinsic::loongarch_lsx_vshuf4i_b:
1233 case Intrinsic::loongarch_lsx_vshuf4i_h:
1234 case Intrinsic::loongarch_lsx_vshuf4i_w:
1235 case Intrinsic::loongarch_lasx_xvnori_b:
1236 case Intrinsic::loongarch_lasx_xvshuf4i_b:
1237 case Intrinsic::loongarch_lasx_xvshuf4i_h:
1238 case Intrinsic::loongarch_lasx_xvshuf4i_w:
1239 case Intrinsic::loongarch_lasx_xvpermi_d:
1240 return checkIntrinsicImmArg<8>(
Op, 2, DAG);
1241 case Intrinsic::loongarch_lsx_vshuf4i_d:
1242 case Intrinsic::loongarch_lsx_vpermi_w:
1243 case Intrinsic::loongarch_lsx_vbitseli_b:
1244 case Intrinsic::loongarch_lsx_vextrins_b:
1245 case Intrinsic::loongarch_lsx_vextrins_h:
1246 case Intrinsic::loongarch_lsx_vextrins_w:
1247 case Intrinsic::loongarch_lsx_vextrins_d:
1248 case Intrinsic::loongarch_lasx_xvshuf4i_d:
1249 case Intrinsic::loongarch_lasx_xvpermi_w:
1250 case Intrinsic::loongarch_lasx_xvpermi_q:
1251 case Intrinsic::loongarch_lasx_xvbitseli_b:
1252 case Intrinsic::loongarch_lasx_xvextrins_b:
1253 case Intrinsic::loongarch_lasx_xvextrins_h:
1254 case Intrinsic::loongarch_lasx_xvextrins_w:
1255 case Intrinsic::loongarch_lasx_xvextrins_d:
1256 return checkIntrinsicImmArg<8>(
Op, 3, DAG);
1257 case Intrinsic::loongarch_lsx_vrepli_b:
1258 case Intrinsic::loongarch_lsx_vrepli_h:
1259 case Intrinsic::loongarch_lsx_vrepli_w:
1260 case Intrinsic::loongarch_lsx_vrepli_d:
1261 case Intrinsic::loongarch_lasx_xvrepli_b:
1262 case Intrinsic::loongarch_lasx_xvrepli_h:
1263 case Intrinsic::loongarch_lasx_xvrepli_w:
1264 case Intrinsic::loongarch_lasx_xvrepli_d:
1265 return checkIntrinsicImmArg<10>(
Op, 1, DAG,
true);
1266 case Intrinsic::loongarch_lsx_vldi:
1267 case Intrinsic::loongarch_lasx_xvldi:
1268 return checkIntrinsicImmArg<13>(
Op, 1, DAG,
true);
1283LoongArchTargetLowering::lowerINTRINSIC_W_CHAIN(
SDValue Op,
1287 EVT VT =
Op.getValueType();
1289 const StringRef ErrorMsgOOR =
"argument out of range";
1290 const StringRef ErrorMsgReqLA64 =
"requires loongarch64";
1291 const StringRef ErrorMsgReqF =
"requires basic 'f' target feature";
1293 switch (
Op.getConstantOperandVal(1)) {
1296 case Intrinsic::loongarch_crc_w_b_w:
1297 case Intrinsic::loongarch_crc_w_h_w:
1298 case Intrinsic::loongarch_crc_w_w_w:
1299 case Intrinsic::loongarch_crc_w_d_w:
1300 case Intrinsic::loongarch_crcc_w_b_w:
1301 case Intrinsic::loongarch_crcc_w_h_w:
1302 case Intrinsic::loongarch_crcc_w_w_w:
1303 case Intrinsic::loongarch_crcc_w_d_w:
1305 case Intrinsic::loongarch_csrrd_w:
1306 case Intrinsic::loongarch_csrrd_d: {
1307 unsigned Imm =
Op.getConstantOperandVal(2);
1308 return !isUInt<14>(Imm)
1310 : DAG.getNode(LoongArchISD::
CSRRD,
DL, {GRLenVT, MVT::Other},
1313 case Intrinsic::loongarch_csrwr_w:
1314 case Intrinsic::loongarch_csrwr_d: {
1315 unsigned Imm =
Op.getConstantOperandVal(3);
1316 return !isUInt<14>(Imm)
1318 : DAG.getNode(LoongArchISD::
CSRWR,
DL, {GRLenVT, MVT::Other},
1319 {Chain,
Op.getOperand(2),
1322 case Intrinsic::loongarch_csrxchg_w:
1323 case Intrinsic::loongarch_csrxchg_d: {
1324 unsigned Imm =
Op.getConstantOperandVal(4);
1325 return !isUInt<14>(Imm)
1327 : DAG.getNode(LoongArchISD::
CSRXCHG,
DL, {GRLenVT, MVT::Other},
1328 {Chain,
Op.getOperand(2),
Op.getOperand(3),
1331 case Intrinsic::loongarch_iocsrrd_d: {
1336#define IOCSRRD_CASE(NAME, NODE) \
1337 case Intrinsic::loongarch_##NAME: { \
1338 return DAG.getNode(LoongArchISD::NODE, DL, {GRLenVT, MVT::Other}, \
1339 {Chain, Op.getOperand(2)}); \
1345 case Intrinsic::loongarch_cpucfg: {
1347 {Chain,
Op.getOperand(2)});
1349 case Intrinsic::loongarch_lddir_d: {
1350 unsigned Imm =
Op.getConstantOperandVal(3);
1351 return !isUInt<8>(Imm)
1355 case Intrinsic::loongarch_movfcsr2gr: {
1356 if (!Subtarget.hasBasicF())
1358 unsigned Imm =
Op.getConstantOperandVal(2);
1359 return !isUInt<2>(Imm)
1361 : DAG.getNode(LoongArchISD::
MOVFCSR2GR,
DL, {VT, MVT::Other},
1364 case Intrinsic::loongarch_lsx_vld:
1365 case Intrinsic::loongarch_lsx_vldrepl_b:
1366 case Intrinsic::loongarch_lasx_xvld:
1367 case Intrinsic::loongarch_lasx_xvldrepl_b:
1368 return !isInt<12>(cast<ConstantSDNode>(
Op.getOperand(3))->getSExtValue())
1371 case Intrinsic::loongarch_lsx_vldrepl_h:
1372 case Intrinsic::loongarch_lasx_xvldrepl_h:
1373 return !isShiftedInt<11, 1>(
1374 cast<ConstantSDNode>(
Op.getOperand(3))->getSExtValue())
1376 Op,
"argument out of range or not a multiple of 2", DAG)
1378 case Intrinsic::loongarch_lsx_vldrepl_w:
1379 case Intrinsic::loongarch_lasx_xvldrepl_w:
1380 return !isShiftedInt<10, 2>(
1381 cast<ConstantSDNode>(
Op.getOperand(3))->getSExtValue())
1383 Op,
"argument out of range or not a multiple of 4", DAG)
1385 case Intrinsic::loongarch_lsx_vldrepl_d:
1386 case Intrinsic::loongarch_lasx_xvldrepl_d:
1387 return !isShiftedInt<9, 3>(
1388 cast<ConstantSDNode>(
Op.getOperand(3))->getSExtValue())
1390 Op,
"argument out of range or not a multiple of 8", DAG)
1401 return Op.getOperand(0);
1409 uint64_t IntrinsicEnum =
Op.getConstantOperandVal(1);
1411 const StringRef ErrorMsgOOR =
"argument out of range";
1412 const StringRef ErrorMsgReqLA64 =
"requires loongarch64";
1413 const StringRef ErrorMsgReqLA32 =
"requires loongarch32";
1414 const StringRef ErrorMsgReqF =
"requires basic 'f' target feature";
1416 switch (IntrinsicEnum) {
1420 case Intrinsic::loongarch_cacop_d:
1421 case Intrinsic::loongarch_cacop_w: {
1422 if (IntrinsicEnum == Intrinsic::loongarch_cacop_d && !Subtarget.
is64Bit())
1424 if (IntrinsicEnum == Intrinsic::loongarch_cacop_w && Subtarget.
is64Bit())
1428 int Imm2 = cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue();
1429 if (!isUInt<5>(Imm1) || !isInt<12>(Imm2))
1433 case Intrinsic::loongarch_dbar: {
1435 return !isUInt<15>(Imm)
1440 case Intrinsic::loongarch_ibar: {
1442 return !isUInt<15>(Imm)
1447 case Intrinsic::loongarch_break: {
1449 return !isUInt<15>(Imm)
1454 case Intrinsic::loongarch_movgr2fcsr: {
1455 if (!Subtarget.hasBasicF())
1458 return !isUInt<2>(Imm)
1465 case Intrinsic::loongarch_syscall: {
1467 return !isUInt<15>(Imm)
1472#define IOCSRWR_CASE(NAME, NODE) \
1473 case Intrinsic::loongarch_##NAME: { \
1474 SDValue Op3 = Op.getOperand(3); \
1475 return Subtarget.is64Bit() \
1476 ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, \
1477 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
1478 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)) \
1479 : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2, \
1486 case Intrinsic::loongarch_iocsrwr_d: {
1494#define ASRT_LE_GT_CASE(NAME) \
1495 case Intrinsic::loongarch_##NAME: { \
1496 return !Subtarget.is64Bit() \
1497 ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG) \
1502#undef ASRT_LE_GT_CASE
1503 case Intrinsic::loongarch_ldpte_d: {
1504 unsigned Imm =
Op.getConstantOperandVal(3);
1510 case Intrinsic::loongarch_lsx_vst:
1511 case Intrinsic::loongarch_lasx_xvst:
1512 return !isInt<12>(cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue())
1515 case Intrinsic::loongarch_lasx_xvstelm_b:
1516 return (!isInt<8>(cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1517 !isUInt<5>(
Op.getConstantOperandVal(5)))
1520 case Intrinsic::loongarch_lsx_vstelm_b:
1521 return (!isInt<8>(cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1522 !isUInt<4>(
Op.getConstantOperandVal(5)))
1525 case Intrinsic::loongarch_lasx_xvstelm_h:
1526 return (!isShiftedInt<8, 1>(
1527 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1528 !isUInt<4>(
Op.getConstantOperandVal(5)))
1530 Op,
"argument out of range or not a multiple of 2", DAG)
1532 case Intrinsic::loongarch_lsx_vstelm_h:
1533 return (!isShiftedInt<8, 1>(
1534 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1535 !isUInt<3>(
Op.getConstantOperandVal(5)))
1537 Op,
"argument out of range or not a multiple of 2", DAG)
1539 case Intrinsic::loongarch_lasx_xvstelm_w:
1540 return (!isShiftedInt<8, 2>(
1541 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1542 !isUInt<3>(
Op.getConstantOperandVal(5)))
1544 Op,
"argument out of range or not a multiple of 4", DAG)
1546 case Intrinsic::loongarch_lsx_vstelm_w:
1547 return (!isShiftedInt<8, 2>(
1548 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1549 !isUInt<2>(
Op.getConstantOperandVal(5)))
1551 Op,
"argument out of range or not a multiple of 4", DAG)
1553 case Intrinsic::loongarch_lasx_xvstelm_d:
1554 return (!isShiftedInt<8, 3>(
1555 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1556 !isUInt<2>(
Op.getConstantOperandVal(5)))
1558 Op,
"argument out of range or not a multiple of 8", DAG)
1560 case Intrinsic::loongarch_lsx_vstelm_d:
1561 return (!isShiftedInt<8, 3>(
1562 cast<ConstantSDNode>(
Op.getOperand(4))->getSExtValue()) ||
1563 !isUInt<1>(
Op.getConstantOperandVal(5)))
1565 Op,
"argument out of range or not a multiple of 8", DAG)
1576 EVT VT =
Lo.getValueType();
1616 EVT VT =
Lo.getValueType();
1700 NewOp0 = DAG.
getNode(ExtOpc,
DL, MVT::i64,
N->getOperand(0));
1701 NewRes = DAG.
getNode(WOpcode,
DL, MVT::i64, NewOp0);
1705 NewOp0 = DAG.
getNode(ExtOpc,
DL, MVT::i64,
N->getOperand(0));
1707 NewRes = DAG.
getNode(WOpcode,
DL, MVT::i64, NewOp0, NewOp1);
1722 StringRef ErrorMsg,
bool WithChain =
true) {
1727 Results.push_back(
N->getOperand(0));
1730template <
unsigned N>
1735 const StringRef ErrorMsgOOR =
"argument out of range";
1736 unsigned Imm =
Node->getConstantOperandVal(2);
1737 if (!isUInt<N>(Imm)) {
1770 switch (
N->getConstantOperandVal(0)) {
1773 case Intrinsic::loongarch_lsx_vpickve2gr_b:
1774 replaceVPICKVE2GRResults<4>(
N,
Results, DAG, Subtarget,
1777 case Intrinsic::loongarch_lsx_vpickve2gr_h:
1778 case Intrinsic::loongarch_lasx_xvpickve2gr_w:
1779 replaceVPICKVE2GRResults<3>(
N,
Results, DAG, Subtarget,
1782 case Intrinsic::loongarch_lsx_vpickve2gr_w:
1783 replaceVPICKVE2GRResults<2>(
N,
Results, DAG, Subtarget,
1786 case Intrinsic::loongarch_lsx_vpickve2gr_bu:
1787 replaceVPICKVE2GRResults<4>(
N,
Results, DAG, Subtarget,
1790 case Intrinsic::loongarch_lsx_vpickve2gr_hu:
1791 case Intrinsic::loongarch_lasx_xvpickve2gr_wu:
1792 replaceVPICKVE2GRResults<3>(
N,
Results, DAG, Subtarget,
1795 case Intrinsic::loongarch_lsx_vpickve2gr_wu:
1796 replaceVPICKVE2GRResults<2>(
N,
Results, DAG, Subtarget,
1799 case Intrinsic::loongarch_lsx_bz_b:
1800 case Intrinsic::loongarch_lsx_bz_h:
1801 case Intrinsic::loongarch_lsx_bz_w:
1802 case Intrinsic::loongarch_lsx_bz_d:
1803 case Intrinsic::loongarch_lasx_xbz_b:
1804 case Intrinsic::loongarch_lasx_xbz_h:
1805 case Intrinsic::loongarch_lasx_xbz_w:
1806 case Intrinsic::loongarch_lasx_xbz_d:
1810 case Intrinsic::loongarch_lsx_bz_v:
1811 case Intrinsic::loongarch_lasx_xbz_v:
1815 case Intrinsic::loongarch_lsx_bnz_b:
1816 case Intrinsic::loongarch_lsx_bnz_h:
1817 case Intrinsic::loongarch_lsx_bnz_w:
1818 case Intrinsic::loongarch_lsx_bnz_d:
1819 case Intrinsic::loongarch_lasx_xbnz_b:
1820 case Intrinsic::loongarch_lasx_xbnz_h:
1821 case Intrinsic::loongarch_lasx_xbnz_w:
1822 case Intrinsic::loongarch_lasx_xbnz_d:
1826 case Intrinsic::loongarch_lsx_bnz_v:
1827 case Intrinsic::loongarch_lasx_xbnz_v:
1837 EVT VT =
N->getValueType(0);
1838 switch (
N->getOpcode()) {
1846 "Unexpected custom legalisation");
1854 if ((CN = dyn_cast<ConstantSDNode>(
N->getOperand(1)))) {
1861 "Unexpected custom legalisation");
1875 EVT OpVT = Src.getValueType();
1879 std::tie(Result, Chain) =
1886 EVT SrcVT = Src.getValueType();
1887 if (VT == MVT::i32 && SrcVT == MVT::f32 && Subtarget.
is64Bit() &&
1888 Subtarget.hasBasicF()) {
1897 "Unexpected custom legalisation");
1900 TLI.expandFP_TO_UINT(
N, Tmp1, Tmp2, DAG);
1906 assert((VT == MVT::i16 || VT == MVT::i32) &&
1907 "Unexpected custom legalization");
1928 assert((VT == MVT::i8 || (VT == MVT::i32 && Subtarget.
is64Bit())) &&
1929 "Unexpected custom legalization");
1949 "Unexpected custom legalisation");
1957 const StringRef ErrorMsgOOR =
"argument out of range";
1958 const StringRef ErrorMsgReqLA64 =
"requires loongarch64";
1959 const StringRef ErrorMsgReqF =
"requires basic 'f' target feature";
1961 switch (
N->getConstantOperandVal(1)) {
1964 case Intrinsic::loongarch_movfcsr2gr: {
1965 if (!Subtarget.hasBasicF()) {
1970 if (!isUInt<2>(Imm)) {
1982#define CRC_CASE_EXT_BINARYOP(NAME, NODE) \
1983 case Intrinsic::loongarch_##NAME: { \
1984 SDValue NODE = DAG.getNode( \
1985 LoongArchISD::NODE, DL, {MVT::i64, MVT::Other}, \
1986 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
1987 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))}); \
1988 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0))); \
1989 Results.push_back(NODE.getValue(1)); \
1998#undef CRC_CASE_EXT_BINARYOP
2000#define CRC_CASE_EXT_UNARYOP(NAME, NODE) \
2001 case Intrinsic::loongarch_##NAME: { \
2002 SDValue NODE = DAG.getNode( \
2003 LoongArchISD::NODE, DL, {MVT::i64, MVT::Other}, \
2005 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))}); \
2006 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0))); \
2007 Results.push_back(NODE.getValue(1)); \
2012#undef CRC_CASE_EXT_UNARYOP
2013#define CSR_CASE(ID) \
2014 case Intrinsic::loongarch_##ID: { \
2015 if (!Subtarget.is64Bit()) \
2016 emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64); \
2024 case Intrinsic::loongarch_csrrd_w: {
2026 if (!isUInt<14>(Imm)) {
2038 case Intrinsic::loongarch_csrwr_w: {
2039 unsigned Imm =
N->getConstantOperandVal(3);
2040 if (!isUInt<14>(Imm)) {
2053 case Intrinsic::loongarch_csrxchg_w: {
2054 unsigned Imm =
N->getConstantOperandVal(4);
2055 if (!isUInt<14>(Imm)) {
2069#define IOCSRRD_CASE(NAME, NODE) \
2070 case Intrinsic::loongarch_##NAME: { \
2071 SDValue IOCSRRDResults = \
2072 DAG.getNode(LoongArchISD::NODE, DL, {MVT::i64, MVT::Other}, \
2073 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)}); \
2074 Results.push_back( \
2075 DAG.getNode(ISD::TRUNCATE, DL, VT, IOCSRRDResults.getValue(0))); \
2076 Results.push_back(IOCSRRDResults.getValue(1)); \
2083 case Intrinsic::loongarch_cpucfg: {
2092 case Intrinsic::loongarch_lddir_d: {
2105 "On LA64, only 64-bit registers can be read.");
2108 "On LA32, only 32-bit registers can be read.");
2110 Results.push_back(
N->getOperand(0));
2126 SDValue FirstOperand =
N->getOperand(0);
2127 SDValue SecondOperand =
N->getOperand(1);
2128 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
2129 EVT ValTy =
N->getValueType(0);
2132 unsigned SMIdx, SMLen;
2138 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)) ||
2149 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
2190 NewOperand = FirstOperand;
2193 msb = lsb + SMLen - 1;
2197 if (FirstOperandOpc ==
ISD::SRA || FirstOperandOpc ==
ISD::SRL || lsb == 0)
2218 SDValue FirstOperand =
N->getOperand(0);
2220 EVT ValTy =
N->getValueType(0);
2223 unsigned MaskIdx, MaskLen;
2229 !(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
2234 if (!(CN = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
2238 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1)
2251 EVT ValTy =
N->getValueType(0);
2252 SDValue N0 =
N->getOperand(0), N1 =
N->getOperand(1);
2256 unsigned MaskIdx0, MaskLen0, MaskIdx1, MaskLen1;
2258 bool SwapAndRetried =
false;
2263 if (ValBits != 32 && ValBits != 64)
2273 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
2276 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2278 MaskIdx0 == MaskIdx1 && MaskLen0 == MaskLen1 &&
2279 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
2281 (MaskIdx0 + MaskLen0 <= ValBits)) {
2295 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
2298 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2300 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
2302 MaskLen0 == MaskLen1 && MaskIdx1 == 0 &&
2303 (MaskIdx0 + MaskLen0 <= ValBits)) {
2318 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
2320 (MaskIdx0 + MaskLen0 <= 64) &&
2321 (CN1 = dyn_cast<ConstantSDNode>(N1->getOperand(1))) &&
2328 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
2329 : (MaskIdx0 + MaskLen0 - 1),
2341 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
2343 MaskIdx0 == 0 && (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2345 (MaskIdx0 + MaskLen0 <= ValBits)) {
2360 (CN0 = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) &&
2362 (CN1 = dyn_cast<ConstantSDNode>(N1)) &&
2368 DAG.
getConstant(ValBits == 32 ? (MaskIdx0 + (MaskLen0 & 31) - 1)
2369 : (MaskIdx0 + MaskLen0 - 1),
2384 unsigned MaskIdx, MaskLen;
2385 if (N1.getOpcode() ==
ISD::SHL && N1.getOperand(0).getOpcode() ==
ISD::AND &&
2386 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
2388 MaskIdx == 0 && (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2410 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2412 N1.getOperand(0).getOpcode() ==
ISD::SHL &&
2413 (CNShamt = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) &&
2426 if (!SwapAndRetried) {
2428 SwapAndRetried =
true;
2432 SwapAndRetried =
false;
2444 (CNMask = dyn_cast<ConstantSDNode>(N1.getOperand(1))) &&
2458 if (!SwapAndRetried) {
2460 SwapAndRetried =
true;
2482template <
unsigned N>
2486 bool IsSigned =
false) {
2488 auto *CImm = cast<ConstantSDNode>(
Node->getOperand(ImmOp));
2490 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) ||
2491 (!IsSigned && !isUInt<N>(CImm->getZExtValue()))) {
2493 ": argument out of range.");
2499template <
unsigned N>
2503 EVT ResTy =
Node->getValueType(0);
2504 auto *CImm = cast<ConstantSDNode>(
Node->getOperand(ImmOp));
2507 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) ||
2508 (!IsSigned && !isUInt<N>(CImm->getZExtValue()))) {
2510 ": argument out of range.");
2515 IsSigned ? CImm->getSExtValue() : CImm->getZExtValue(), IsSigned),
2521 EVT ResTy =
Node->getValueType(0);
2529 EVT ResTy =
Node->getValueType(0);
2538template <
unsigned N>
2541 EVT ResTy =
Node->getValueType(0);
2542 auto *CImm = cast<ConstantSDNode>(
Node->getOperand(2));
2544 if (!isUInt<N>(CImm->getZExtValue())) {
2546 ": argument out of range.");
2556template <
unsigned N>
2559 EVT ResTy =
Node->getValueType(0);
2560 auto *CImm = cast<ConstantSDNode>(
Node->getOperand(2));
2562 if (!isUInt<N>(CImm->getZExtValue())) {
2564 ": argument out of range.");
2573template <
unsigned N>
2576 EVT ResTy =
Node->getValueType(0);
2577 auto *CImm = cast<ConstantSDNode>(
Node->getOperand(2));
2579 if (!isUInt<N>(CImm->getZExtValue())) {
2581 ": argument out of range.");
2595 switch (
N->getConstantOperandVal(0)) {
2598 case Intrinsic::loongarch_lsx_vadd_b:
2599 case Intrinsic::loongarch_lsx_vadd_h:
2600 case Intrinsic::loongarch_lsx_vadd_w:
2601 case Intrinsic::loongarch_lsx_vadd_d:
2602 case Intrinsic::loongarch_lasx_xvadd_b:
2603 case Intrinsic::loongarch_lasx_xvadd_h:
2604 case Intrinsic::loongarch_lasx_xvadd_w:
2605 case Intrinsic::loongarch_lasx_xvadd_d:
2608 case Intrinsic::loongarch_lsx_vaddi_bu:
2609 case Intrinsic::loongarch_lsx_vaddi_hu:
2610 case Intrinsic::loongarch_lsx_vaddi_wu:
2611 case Intrinsic::loongarch_lsx_vaddi_du:
2612 case Intrinsic::loongarch_lasx_xvaddi_bu:
2613 case Intrinsic::loongarch_lasx_xvaddi_hu:
2614 case Intrinsic::loongarch_lasx_xvaddi_wu:
2615 case Intrinsic::loongarch_lasx_xvaddi_du:
2617 lowerVectorSplatImm<5>(
N, 2, DAG));
2618 case Intrinsic::loongarch_lsx_vsub_b:
2619 case Intrinsic::loongarch_lsx_vsub_h:
2620 case Intrinsic::loongarch_lsx_vsub_w:
2621 case Intrinsic::loongarch_lsx_vsub_d:
2622 case Intrinsic::loongarch_lasx_xvsub_b:
2623 case Intrinsic::loongarch_lasx_xvsub_h:
2624 case Intrinsic::loongarch_lasx_xvsub_w:
2625 case Intrinsic::loongarch_lasx_xvsub_d:
2628 case Intrinsic::loongarch_lsx_vsubi_bu:
2629 case Intrinsic::loongarch_lsx_vsubi_hu:
2630 case Intrinsic::loongarch_lsx_vsubi_wu:
2631 case Intrinsic::loongarch_lsx_vsubi_du:
2632 case Intrinsic::loongarch_lasx_xvsubi_bu:
2633 case Intrinsic::loongarch_lasx_xvsubi_hu:
2634 case Intrinsic::loongarch_lasx_xvsubi_wu:
2635 case Intrinsic::loongarch_lasx_xvsubi_du:
2637 lowerVectorSplatImm<5>(
N, 2, DAG));
2638 case Intrinsic::loongarch_lsx_vneg_b:
2639 case Intrinsic::loongarch_lsx_vneg_h:
2640 case Intrinsic::loongarch_lsx_vneg_w:
2641 case Intrinsic::loongarch_lsx_vneg_d:
2642 case Intrinsic::loongarch_lasx_xvneg_b:
2643 case Intrinsic::loongarch_lasx_xvneg_h:
2644 case Intrinsic::loongarch_lasx_xvneg_w:
2645 case Intrinsic::loongarch_lasx_xvneg_d:
2649 APInt(
N->getValueType(0).getScalarType().getSizeInBits(), 0,
2651 SDLoc(
N),
N->getValueType(0)),
2653 case Intrinsic::loongarch_lsx_vmax_b:
2654 case Intrinsic::loongarch_lsx_vmax_h:
2655 case Intrinsic::loongarch_lsx_vmax_w:
2656 case Intrinsic::loongarch_lsx_vmax_d:
2657 case Intrinsic::loongarch_lasx_xvmax_b:
2658 case Intrinsic::loongarch_lasx_xvmax_h:
2659 case Intrinsic::loongarch_lasx_xvmax_w:
2660 case Intrinsic::loongarch_lasx_xvmax_d:
2663 case Intrinsic::loongarch_lsx_vmax_bu:
2664 case Intrinsic::loongarch_lsx_vmax_hu:
2665 case Intrinsic::loongarch_lsx_vmax_wu:
2666 case Intrinsic::loongarch_lsx_vmax_du:
2667 case Intrinsic::loongarch_lasx_xvmax_bu:
2668 case Intrinsic::loongarch_lasx_xvmax_hu:
2669 case Intrinsic::loongarch_lasx_xvmax_wu:
2670 case Intrinsic::loongarch_lasx_xvmax_du:
2673 case Intrinsic::loongarch_lsx_vmaxi_b:
2674 case Intrinsic::loongarch_lsx_vmaxi_h:
2675 case Intrinsic::loongarch_lsx_vmaxi_w:
2676 case Intrinsic::loongarch_lsx_vmaxi_d:
2677 case Intrinsic::loongarch_lasx_xvmaxi_b:
2678 case Intrinsic::loongarch_lasx_xvmaxi_h:
2679 case Intrinsic::loongarch_lasx_xvmaxi_w:
2680 case Intrinsic::loongarch_lasx_xvmaxi_d:
2682 lowerVectorSplatImm<5>(
N, 2, DAG,
true));
2683 case Intrinsic::loongarch_lsx_vmaxi_bu:
2684 case Intrinsic::loongarch_lsx_vmaxi_hu:
2685 case Intrinsic::loongarch_lsx_vmaxi_wu:
2686 case Intrinsic::loongarch_lsx_vmaxi_du:
2687 case Intrinsic::loongarch_lasx_xvmaxi_bu:
2688 case Intrinsic::loongarch_lasx_xvmaxi_hu:
2689 case Intrinsic::loongarch_lasx_xvmaxi_wu:
2690 case Intrinsic::loongarch_lasx_xvmaxi_du:
2692 lowerVectorSplatImm<5>(
N, 2, DAG));
2693 case Intrinsic::loongarch_lsx_vmin_b:
2694 case Intrinsic::loongarch_lsx_vmin_h:
2695 case Intrinsic::loongarch_lsx_vmin_w:
2696 case Intrinsic::loongarch_lsx_vmin_d:
2697 case Intrinsic::loongarch_lasx_xvmin_b:
2698 case Intrinsic::loongarch_lasx_xvmin_h:
2699 case Intrinsic::loongarch_lasx_xvmin_w:
2700 case Intrinsic::loongarch_lasx_xvmin_d:
2703 case Intrinsic::loongarch_lsx_vmin_bu:
2704 case Intrinsic::loongarch_lsx_vmin_hu:
2705 case Intrinsic::loongarch_lsx_vmin_wu:
2706 case Intrinsic::loongarch_lsx_vmin_du:
2707 case Intrinsic::loongarch_lasx_xvmin_bu:
2708 case Intrinsic::loongarch_lasx_xvmin_hu:
2709 case Intrinsic::loongarch_lasx_xvmin_wu:
2710 case Intrinsic::loongarch_lasx_xvmin_du:
2713 case Intrinsic::loongarch_lsx_vmini_b:
2714 case Intrinsic::loongarch_lsx_vmini_h:
2715 case Intrinsic::loongarch_lsx_vmini_w:
2716 case Intrinsic::loongarch_lsx_vmini_d:
2717 case Intrinsic::loongarch_lasx_xvmini_b:
2718 case Intrinsic::loongarch_lasx_xvmini_h:
2719 case Intrinsic::loongarch_lasx_xvmini_w:
2720 case Intrinsic::loongarch_lasx_xvmini_d:
2722 lowerVectorSplatImm<5>(
N, 2, DAG,
true));
2723 case Intrinsic::loongarch_lsx_vmini_bu:
2724 case Intrinsic::loongarch_lsx_vmini_hu:
2725 case Intrinsic::loongarch_lsx_vmini_wu:
2726 case Intrinsic::loongarch_lsx_vmini_du:
2727 case Intrinsic::loongarch_lasx_xvmini_bu:
2728 case Intrinsic::loongarch_lasx_xvmini_hu:
2729 case Intrinsic::loongarch_lasx_xvmini_wu:
2730 case Intrinsic::loongarch_lasx_xvmini_du:
2732 lowerVectorSplatImm<5>(
N, 2, DAG));
2733 case Intrinsic::loongarch_lsx_vmul_b:
2734 case Intrinsic::loongarch_lsx_vmul_h:
2735 case Intrinsic::loongarch_lsx_vmul_w:
2736 case Intrinsic::loongarch_lsx_vmul_d:
2737 case Intrinsic::loongarch_lasx_xvmul_b:
2738 case Intrinsic::loongarch_lasx_xvmul_h:
2739 case Intrinsic::loongarch_lasx_xvmul_w:
2740 case Intrinsic::loongarch_lasx_xvmul_d:
2743 case Intrinsic::loongarch_lsx_vmadd_b:
2744 case Intrinsic::loongarch_lsx_vmadd_h:
2745 case Intrinsic::loongarch_lsx_vmadd_w:
2746 case Intrinsic::loongarch_lsx_vmadd_d:
2747 case Intrinsic::loongarch_lasx_xvmadd_b:
2748 case Intrinsic::loongarch_lasx_xvmadd_h:
2749 case Intrinsic::loongarch_lasx_xvmadd_w:
2750 case Intrinsic::loongarch_lasx_xvmadd_d: {
2751 EVT ResTy =
N->getValueType(0);
2756 case Intrinsic::loongarch_lsx_vmsub_b:
2757 case Intrinsic::loongarch_lsx_vmsub_h:
2758 case Intrinsic::loongarch_lsx_vmsub_w:
2759 case Intrinsic::loongarch_lsx_vmsub_d:
2760 case Intrinsic::loongarch_lasx_xvmsub_b:
2761 case Intrinsic::loongarch_lasx_xvmsub_h:
2762 case Intrinsic::loongarch_lasx_xvmsub_w:
2763 case Intrinsic::loongarch_lasx_xvmsub_d: {
2764 EVT ResTy =
N->getValueType(0);
2769 case Intrinsic::loongarch_lsx_vdiv_b:
2770 case Intrinsic::loongarch_lsx_vdiv_h:
2771 case Intrinsic::loongarch_lsx_vdiv_w:
2772 case Intrinsic::loongarch_lsx_vdiv_d:
2773 case Intrinsic::loongarch_lasx_xvdiv_b:
2774 case Intrinsic::loongarch_lasx_xvdiv_h:
2775 case Intrinsic::loongarch_lasx_xvdiv_w:
2776 case Intrinsic::loongarch_lasx_xvdiv_d:
2779 case Intrinsic::loongarch_lsx_vdiv_bu:
2780 case Intrinsic::loongarch_lsx_vdiv_hu:
2781 case Intrinsic::loongarch_lsx_vdiv_wu:
2782 case Intrinsic::loongarch_lsx_vdiv_du:
2783 case Intrinsic::loongarch_lasx_xvdiv_bu:
2784 case Intrinsic::loongarch_lasx_xvdiv_hu:
2785 case Intrinsic::loongarch_lasx_xvdiv_wu:
2786 case Intrinsic::loongarch_lasx_xvdiv_du:
2789 case Intrinsic::loongarch_lsx_vmod_b:
2790 case Intrinsic::loongarch_lsx_vmod_h:
2791 case Intrinsic::loongarch_lsx_vmod_w:
2792 case Intrinsic::loongarch_lsx_vmod_d:
2793 case Intrinsic::loongarch_lasx_xvmod_b:
2794 case Intrinsic::loongarch_lasx_xvmod_h:
2795 case Intrinsic::loongarch_lasx_xvmod_w:
2796 case Intrinsic::loongarch_lasx_xvmod_d:
2799 case Intrinsic::loongarch_lsx_vmod_bu:
2800 case Intrinsic::loongarch_lsx_vmod_hu:
2801 case Intrinsic::loongarch_lsx_vmod_wu:
2802 case Intrinsic::loongarch_lsx_vmod_du:
2803 case Intrinsic::loongarch_lasx_xvmod_bu:
2804 case Intrinsic::loongarch_lasx_xvmod_hu:
2805 case Intrinsic::loongarch_lasx_xvmod_wu:
2806 case Intrinsic::loongarch_lasx_xvmod_du:
2809 case Intrinsic::loongarch_lsx_vand_v:
2810 case Intrinsic::loongarch_lasx_xvand_v:
2813 case Intrinsic::loongarch_lsx_vor_v:
2814 case Intrinsic::loongarch_lasx_xvor_v:
2817 case Intrinsic::loongarch_lsx_vxor_v:
2818 case Intrinsic::loongarch_lasx_xvxor_v:
2821 case Intrinsic::loongarch_lsx_vnor_v:
2822 case Intrinsic::loongarch_lasx_xvnor_v: {
2827 case Intrinsic::loongarch_lsx_vandi_b:
2828 case Intrinsic::loongarch_lasx_xvandi_b:
2830 lowerVectorSplatImm<8>(
N, 2, DAG));
2831 case Intrinsic::loongarch_lsx_vori_b:
2832 case Intrinsic::loongarch_lasx_xvori_b:
2834 lowerVectorSplatImm<8>(
N, 2, DAG));
2835 case Intrinsic::loongarch_lsx_vxori_b:
2836 case Intrinsic::loongarch_lasx_xvxori_b:
2838 lowerVectorSplatImm<8>(
N, 2, DAG));
2839 case Intrinsic::loongarch_lsx_vsll_b:
2840 case Intrinsic::loongarch_lsx_vsll_h:
2841 case Intrinsic::loongarch_lsx_vsll_w:
2842 case Intrinsic::loongarch_lsx_vsll_d:
2843 case Intrinsic::loongarch_lasx_xvsll_b:
2844 case Intrinsic::loongarch_lasx_xvsll_h:
2845 case Intrinsic::loongarch_lasx_xvsll_w:
2846 case Intrinsic::loongarch_lasx_xvsll_d:
2849 case Intrinsic::loongarch_lsx_vslli_b:
2850 case Intrinsic::loongarch_lasx_xvslli_b:
2852 lowerVectorSplatImm<3>(
N, 2, DAG));
2853 case Intrinsic::loongarch_lsx_vslli_h:
2854 case Intrinsic::loongarch_lasx_xvslli_h:
2856 lowerVectorSplatImm<4>(
N, 2, DAG));
2857 case Intrinsic::loongarch_lsx_vslli_w:
2858 case Intrinsic::loongarch_lasx_xvslli_w:
2860 lowerVectorSplatImm<5>(
N, 2, DAG));
2861 case Intrinsic::loongarch_lsx_vslli_d:
2862 case Intrinsic::loongarch_lasx_xvslli_d:
2864 lowerVectorSplatImm<6>(
N, 2, DAG));
2865 case Intrinsic::loongarch_lsx_vsrl_b:
2866 case Intrinsic::loongarch_lsx_vsrl_h:
2867 case Intrinsic::loongarch_lsx_vsrl_w:
2868 case Intrinsic::loongarch_lsx_vsrl_d:
2869 case Intrinsic::loongarch_lasx_xvsrl_b:
2870 case Intrinsic::loongarch_lasx_xvsrl_h:
2871 case Intrinsic::loongarch_lasx_xvsrl_w:
2872 case Intrinsic::loongarch_lasx_xvsrl_d:
2875 case Intrinsic::loongarch_lsx_vsrli_b:
2876 case Intrinsic::loongarch_lasx_xvsrli_b:
2878 lowerVectorSplatImm<3>(
N, 2, DAG));
2879 case Intrinsic::loongarch_lsx_vsrli_h:
2880 case Intrinsic::loongarch_lasx_xvsrli_h:
2882 lowerVectorSplatImm<4>(
N, 2, DAG));
2883 case Intrinsic::loongarch_lsx_vsrli_w:
2884 case Intrinsic::loongarch_lasx_xvsrli_w:
2886 lowerVectorSplatImm<5>(
N, 2, DAG));
2887 case Intrinsic::loongarch_lsx_vsrli_d:
2888 case Intrinsic::loongarch_lasx_xvsrli_d:
2890 lowerVectorSplatImm<6>(
N, 2, DAG));
2891 case Intrinsic::loongarch_lsx_vsra_b:
2892 case Intrinsic::loongarch_lsx_vsra_h:
2893 case Intrinsic::loongarch_lsx_vsra_w:
2894 case Intrinsic::loongarch_lsx_vsra_d:
2895 case Intrinsic::loongarch_lasx_xvsra_b:
2896 case Intrinsic::loongarch_lasx_xvsra_h:
2897 case Intrinsic::loongarch_lasx_xvsra_w:
2898 case Intrinsic::loongarch_lasx_xvsra_d:
2901 case Intrinsic::loongarch_lsx_vsrai_b:
2902 case Intrinsic::loongarch_lasx_xvsrai_b:
2904 lowerVectorSplatImm<3>(
N, 2, DAG));
2905 case Intrinsic::loongarch_lsx_vsrai_h:
2906 case Intrinsic::loongarch_lasx_xvsrai_h:
2908 lowerVectorSplatImm<4>(
N, 2, DAG));
2909 case Intrinsic::loongarch_lsx_vsrai_w:
2910 case Intrinsic::loongarch_lasx_xvsrai_w:
2912 lowerVectorSplatImm<5>(
N, 2, DAG));
2913 case Intrinsic::loongarch_lsx_vsrai_d:
2914 case Intrinsic::loongarch_lasx_xvsrai_d:
2916 lowerVectorSplatImm<6>(
N, 2, DAG));
2917 case Intrinsic::loongarch_lsx_vclz_b:
2918 case Intrinsic::loongarch_lsx_vclz_h:
2919 case Intrinsic::loongarch_lsx_vclz_w:
2920 case Intrinsic::loongarch_lsx_vclz_d:
2921 case Intrinsic::loongarch_lasx_xvclz_b:
2922 case Intrinsic::loongarch_lasx_xvclz_h:
2923 case Intrinsic::loongarch_lasx_xvclz_w:
2924 case Intrinsic::loongarch_lasx_xvclz_d:
2926 case Intrinsic::loongarch_lsx_vpcnt_b:
2927 case Intrinsic::loongarch_lsx_vpcnt_h:
2928 case Intrinsic::loongarch_lsx_vpcnt_w:
2929 case Intrinsic::loongarch_lsx_vpcnt_d:
2930 case Intrinsic::loongarch_lasx_xvpcnt_b:
2931 case Intrinsic::loongarch_lasx_xvpcnt_h:
2932 case Intrinsic::loongarch_lasx_xvpcnt_w:
2933 case Intrinsic::loongarch_lasx_xvpcnt_d:
2935 case Intrinsic::loongarch_lsx_vbitclr_b:
2936 case Intrinsic::loongarch_lsx_vbitclr_h:
2937 case Intrinsic::loongarch_lsx_vbitclr_w:
2938 case Intrinsic::loongarch_lsx_vbitclr_d:
2939 case Intrinsic::loongarch_lasx_xvbitclr_b:
2940 case Intrinsic::loongarch_lasx_xvbitclr_h:
2941 case Intrinsic::loongarch_lasx_xvbitclr_w:
2942 case Intrinsic::loongarch_lasx_xvbitclr_d:
2944 case Intrinsic::loongarch_lsx_vbitclri_b:
2945 case Intrinsic::loongarch_lasx_xvbitclri_b:
2946 return lowerVectorBitClearImm<3>(
N, DAG);
2947 case Intrinsic::loongarch_lsx_vbitclri_h:
2948 case Intrinsic::loongarch_lasx_xvbitclri_h:
2949 return lowerVectorBitClearImm<4>(
N, DAG);
2950 case Intrinsic::loongarch_lsx_vbitclri_w:
2951 case Intrinsic::loongarch_lasx_xvbitclri_w:
2952 return lowerVectorBitClearImm<5>(
N, DAG);
2953 case Intrinsic::loongarch_lsx_vbitclri_d:
2954 case Intrinsic::loongarch_lasx_xvbitclri_d:
2955 return lowerVectorBitClearImm<6>(
N, DAG);
2956 case Intrinsic::loongarch_lsx_vbitset_b:
2957 case Intrinsic::loongarch_lsx_vbitset_h:
2958 case Intrinsic::loongarch_lsx_vbitset_w:
2959 case Intrinsic::loongarch_lsx_vbitset_d:
2960 case Intrinsic::loongarch_lasx_xvbitset_b:
2961 case Intrinsic::loongarch_lasx_xvbitset_h:
2962 case Intrinsic::loongarch_lasx_xvbitset_w:
2963 case Intrinsic::loongarch_lasx_xvbitset_d: {
2964 EVT VecTy =
N->getValueType(0);
2970 case Intrinsic::loongarch_lsx_vbitseti_b:
2971 case Intrinsic::loongarch_lasx_xvbitseti_b:
2972 return lowerVectorBitSetImm<3>(
N, DAG);
2973 case Intrinsic::loongarch_lsx_vbitseti_h:
2974 case Intrinsic::loongarch_lasx_xvbitseti_h:
2975 return lowerVectorBitSetImm<4>(
N, DAG);
2976 case Intrinsic::loongarch_lsx_vbitseti_w:
2977 case Intrinsic::loongarch_lasx_xvbitseti_w:
2978 return lowerVectorBitSetImm<5>(
N, DAG);
2979 case Intrinsic::loongarch_lsx_vbitseti_d:
2980 case Intrinsic::loongarch_lasx_xvbitseti_d:
2981 return lowerVectorBitSetImm<6>(
N, DAG);
2982 case Intrinsic::loongarch_lsx_vbitrev_b:
2983 case Intrinsic::loongarch_lsx_vbitrev_h:
2984 case Intrinsic::loongarch_lsx_vbitrev_w:
2985 case Intrinsic::loongarch_lsx_vbitrev_d:
2986 case Intrinsic::loongarch_lasx_xvbitrev_b:
2987 case Intrinsic::loongarch_lasx_xvbitrev_h:
2988 case Intrinsic::loongarch_lasx_xvbitrev_w:
2989 case Intrinsic::loongarch_lasx_xvbitrev_d: {
2990 EVT VecTy =
N->getValueType(0);
2996 case Intrinsic::loongarch_lsx_vbitrevi_b:
2997 case Intrinsic::loongarch_lasx_xvbitrevi_b:
2998 return lowerVectorBitRevImm<3>(
N, DAG);
2999 case Intrinsic::loongarch_lsx_vbitrevi_h:
3000 case Intrinsic::loongarch_lasx_xvbitrevi_h:
3001 return lowerVectorBitRevImm<4>(
N, DAG);
3002 case Intrinsic::loongarch_lsx_vbitrevi_w:
3003 case Intrinsic::loongarch_lasx_xvbitrevi_w:
3004 return lowerVectorBitRevImm<5>(
N, DAG);
3005 case Intrinsic::loongarch_lsx_vbitrevi_d:
3006 case Intrinsic::loongarch_lasx_xvbitrevi_d:
3007 return lowerVectorBitRevImm<6>(
N, DAG);
3008 case Intrinsic::loongarch_lsx_vfadd_s:
3009 case Intrinsic::loongarch_lsx_vfadd_d:
3010 case Intrinsic::loongarch_lasx_xvfadd_s:
3011 case Intrinsic::loongarch_lasx_xvfadd_d:
3014 case Intrinsic::loongarch_lsx_vfsub_s:
3015 case Intrinsic::loongarch_lsx_vfsub_d:
3016 case Intrinsic::loongarch_lasx_xvfsub_s:
3017 case Intrinsic::loongarch_lasx_xvfsub_d:
3020 case Intrinsic::loongarch_lsx_vfmul_s:
3021 case Intrinsic::loongarch_lsx_vfmul_d:
3022 case Intrinsic::loongarch_lasx_xvfmul_s:
3023 case Intrinsic::loongarch_lasx_xvfmul_d:
3026 case Intrinsic::loongarch_lsx_vfdiv_s:
3027 case Intrinsic::loongarch_lsx_vfdiv_d:
3028 case Intrinsic::loongarch_lasx_xvfdiv_s:
3029 case Intrinsic::loongarch_lasx_xvfdiv_d:
3032 case Intrinsic::loongarch_lsx_vfmadd_s:
3033 case Intrinsic::loongarch_lsx_vfmadd_d:
3034 case Intrinsic::loongarch_lasx_xvfmadd_s:
3035 case Intrinsic::loongarch_lasx_xvfmadd_d:
3037 N->getOperand(2),
N->getOperand(3));
3038 case Intrinsic::loongarch_lsx_vinsgr2vr_b:
3040 N->getOperand(1),
N->getOperand(2),
3041 legalizeIntrinsicImmArg<4>(
N, 3, DAG, Subtarget));
3042 case Intrinsic::loongarch_lsx_vinsgr2vr_h:
3043 case Intrinsic::loongarch_lasx_xvinsgr2vr_w:
3045 N->getOperand(1),
N->getOperand(2),
3046 legalizeIntrinsicImmArg<3>(
N, 3, DAG, Subtarget));
3047 case Intrinsic::loongarch_lsx_vinsgr2vr_w:
3048 case Intrinsic::loongarch_lasx_xvinsgr2vr_d:
3050 N->getOperand(1),
N->getOperand(2),
3051 legalizeIntrinsicImmArg<2>(
N, 3, DAG, Subtarget));
3052 case Intrinsic::loongarch_lsx_vinsgr2vr_d:
3054 N->getOperand(1),
N->getOperand(2),
3055 legalizeIntrinsicImmArg<1>(
N, 3, DAG, Subtarget));
3056 case Intrinsic::loongarch_lsx_vreplgr2vr_b:
3057 case Intrinsic::loongarch_lsx_vreplgr2vr_h:
3058 case Intrinsic::loongarch_lsx_vreplgr2vr_w:
3059 case Intrinsic::loongarch_lsx_vreplgr2vr_d:
3060 case Intrinsic::loongarch_lasx_xvreplgr2vr_b:
3061 case Intrinsic::loongarch_lasx_xvreplgr2vr_h:
3062 case Intrinsic::loongarch_lasx_xvreplgr2vr_w:
3063 case Intrinsic::loongarch_lasx_xvreplgr2vr_d: {
3064 EVT ResTy =
N->getValueType(0);
3068 case Intrinsic::loongarch_lsx_vreplve_b:
3069 case Intrinsic::loongarch_lsx_vreplve_h:
3070 case Intrinsic::loongarch_lsx_vreplve_w:
3071 case Intrinsic::loongarch_lsx_vreplve_d:
3072 case Intrinsic::loongarch_lasx_xvreplve_b:
3073 case Intrinsic::loongarch_lasx_xvreplve_h:
3074 case Intrinsic::loongarch_lasx_xvreplve_w:
3075 case Intrinsic::loongarch_lasx_xvreplve_d:
3087 switch (
N->getOpcode()) {
3122 MF->
insert(It, BreakMBB);
3126 SinkMBB->splice(SinkMBB->end(),
MBB, std::next(
MI.getIterator()),
MBB->
end());
3127 SinkMBB->transferSuccessorsAndUpdatePHIs(
MBB);
3145 BreakMBB->addSuccessor(SinkMBB);
3157 switch (
MI.getOpcode()) {
3160 case LoongArch::PseudoVBZ:
3161 CondOpc = LoongArch::VSETEQZ_V;
3163 case LoongArch::PseudoVBZ_B:
3164 CondOpc = LoongArch::VSETANYEQZ_B;
3166 case LoongArch::PseudoVBZ_H:
3167 CondOpc = LoongArch::VSETANYEQZ_H;
3169 case LoongArch::PseudoVBZ_W:
3170 CondOpc = LoongArch::VSETANYEQZ_W;
3172 case LoongArch::PseudoVBZ_D:
3173 CondOpc = LoongArch::VSETANYEQZ_D;
3175 case LoongArch::PseudoVBNZ:
3176 CondOpc = LoongArch::VSETNEZ_V;
3178 case LoongArch::PseudoVBNZ_B:
3179 CondOpc = LoongArch::VSETALLNEZ_B;
3181 case LoongArch::PseudoVBNZ_H:
3182 CondOpc = LoongArch::VSETALLNEZ_H;
3184 case LoongArch::PseudoVBNZ_W:
3185 CondOpc = LoongArch::VSETALLNEZ_W;
3187 case LoongArch::PseudoVBNZ_D:
3188 CondOpc = LoongArch::VSETALLNEZ_D;
3190 case LoongArch::PseudoXVBZ:
3191 CondOpc = LoongArch::XVSETEQZ_V;
3193 case LoongArch::PseudoXVBZ_B:
3194 CondOpc = LoongArch::XVSETANYEQZ_B;
3196 case LoongArch::PseudoXVBZ_H:
3197 CondOpc = LoongArch::XVSETANYEQZ_H;
3199 case LoongArch::PseudoXVBZ_W:
3200 CondOpc = LoongArch::XVSETANYEQZ_W;
3202 case LoongArch::PseudoXVBZ_D:
3203 CondOpc = LoongArch::XVSETANYEQZ_D;
3205 case LoongArch::PseudoXVBNZ:
3206 CondOpc = LoongArch::XVSETNEZ_V;
3208 case LoongArch::PseudoXVBNZ_B:
3209 CondOpc = LoongArch::XVSETALLNEZ_B;
3211 case LoongArch::PseudoXVBNZ_H:
3212 CondOpc = LoongArch::XVSETALLNEZ_H;
3214 case LoongArch::PseudoXVBNZ_W:
3215 CondOpc = LoongArch::XVSETALLNEZ_W;
3217 case LoongArch::PseudoXVBNZ_D:
3218 CondOpc = LoongArch::XVSETALLNEZ_D;
3233 F->insert(It, FalseBB);
3234 F->insert(It, TrueBB);
3235 F->insert(It, SinkBB);
3238 SinkBB->
splice(SinkBB->
end(), BB, std::next(
MI.getIterator()), BB->
end());
3242 Register FCC =
MRI.createVirtualRegister(&LoongArch::CFRRegClass);
3251 Register RD1 =
MRI.createVirtualRegister(&LoongArch::GPRRegClass);
3259 Register RD2 =
MRI.createVirtualRegister(&LoongArch::GPRRegClass);
3267 MI.getOperand(0).getReg())
3274 MI.eraseFromParent();
3283 switch (
MI.getOpcode()) {
3286 case LoongArch::PseudoXVINSGR2VR_B:
3288 InsOp = LoongArch::VINSGR2VR_B;
3290 case LoongArch::PseudoXVINSGR2VR_H:
3292 InsOp = LoongArch::VINSGR2VR_H;
3304 unsigned Idx =
MI.getOperand(3).getImm();
3307 if (
Idx >= HalfSize) {
3308 ScratchReg1 =
MRI.createVirtualRegister(RC);
3309 BuildMI(*BB,
MI,
DL,
TII->get(LoongArch::XVPERMI_Q), ScratchReg1)
3315 Register ScratchSubReg1 =
MRI.createVirtualRegister(SubRC);
3316 Register ScratchSubReg2 =
MRI.createVirtualRegister(SubRC);
3318 .
addReg(ScratchReg1, 0, LoongArch::sub_128);
3325 if (
Idx >= HalfSize)
3326 ScratchReg2 =
MRI.createVirtualRegister(RC);
3328 BuildMI(*BB,
MI,
DL,
TII->get(LoongArch::SUBREG_TO_REG), ScratchReg2)
3331 .
addImm(LoongArch::sub_128);
3333 if (
Idx >= HalfSize)
3339 MI.eraseFromParent();
3348 switch (
MI.getOpcode()) {
3351 case LoongArch::DIV_W:
3352 case LoongArch::DIV_WU:
3353 case LoongArch::MOD_W:
3354 case LoongArch::MOD_WU:
3355 case LoongArch::DIV_D:
3356 case LoongArch::DIV_DU:
3357 case LoongArch::MOD_D:
3358 case LoongArch::MOD_DU:
3361 case LoongArch::WRFCSR: {
3363 LoongArch::FCSR0 +
MI.getOperand(0).getImm())
3364 .
addReg(
MI.getOperand(1).getReg());
3365 MI.eraseFromParent();
3368 case LoongArch::RDFCSR: {
3371 MI.getOperand(0).getReg())
3372 .
addReg(LoongArch::FCSR0 +
MI.getOperand(1).getImm());
3374 MI.eraseFromParent();
3377 case LoongArch::PseudoVBZ:
3378 case LoongArch::PseudoVBZ_B:
3379 case LoongArch::PseudoVBZ_H:
3380 case LoongArch::PseudoVBZ_W:
3381 case LoongArch::PseudoVBZ_D:
3382 case LoongArch::PseudoVBNZ:
3383 case LoongArch::PseudoVBNZ_B:
3384 case LoongArch::PseudoVBNZ_H:
3385 case LoongArch::PseudoVBNZ_W:
3386 case LoongArch::PseudoVBNZ_D:
3387 case LoongArch::PseudoXVBZ:
3388 case LoongArch::PseudoXVBZ_B:
3389 case LoongArch::PseudoXVBZ_H:
3390 case LoongArch::PseudoXVBZ_W:
3391 case LoongArch::PseudoXVBZ_D:
3392 case LoongArch::PseudoXVBNZ:
3393 case LoongArch::PseudoXVBNZ_B:
3394 case LoongArch::PseudoXVBNZ_H:
3395 case LoongArch::PseudoXVBNZ_W:
3396 case LoongArch::PseudoXVBNZ_D:
3398 case LoongArch::PseudoXVINSGR2VR_B:
3399 case LoongArch::PseudoXVINSGR2VR_H:
3406 unsigned *
Fast)
const {
3407 if (!Subtarget.hasUAL())
3421#define NODE_NAME_CASE(node) \
3422 case LoongArchISD::node: \
3423 return "LoongArchISD::" #node;
3485#undef NODE_NAME_CASE
3498 LoongArch::R7, LoongArch::R8, LoongArch::R9,
3499 LoongArch::R10, LoongArch::R11};
3503 LoongArch::F3, LoongArch::F4, LoongArch::F5,
3504 LoongArch::F6, LoongArch::F7};
3507 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
3508 LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64};
3511 LoongArch::VR3, LoongArch::VR4, LoongArch::VR5,
3512 LoongArch::VR6, LoongArch::VR7};
3515 LoongArch::XR3, LoongArch::XR4, LoongArch::XR5,
3516 LoongArch::XR6, LoongArch::XR7};
3522 unsigned ValNo2,
MVT ValVT2,
MVT LocVT2,
3524 unsigned GRLenInBytes = GRLen / 8;
3557 unsigned ValNo,
MVT ValVT,
3559 CCState &State,
bool IsFixed,
bool IsRet,
3561 unsigned GRLen =
DL.getLargestLegalIntTypeSizeInBits();
3562 assert((GRLen == 32 || GRLen == 64) &&
"Unspport GRLen");
3563 MVT GRLenVT = GRLen == 32 ? MVT::i32 : MVT::i64;
3568 if (IsRet && ValNo > 1)
3572 bool UseGPRForFloat =
true;
3584 UseGPRForFloat = !IsFixed;
3592 UseGPRForFloat =
true;
3594 if (UseGPRForFloat && ValVT == MVT::f32) {
3597 }
else if (UseGPRForFloat && GRLen == 64 && ValVT == MVT::f64) {
3600 }
else if (UseGPRForFloat && GRLen == 32 && ValVT == MVT::f64) {
3611 unsigned TwoGRLenInBytes = (2 * GRLen) / 8;
3613 DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) {
3616 if (RegIdx != std::size(
ArgGPRs) && RegIdx % 2 == 1)
3625 "PendingLocs and PendingArgFlags out of sync");
3643 PendingLocs.
size() <= 2) {
3644 assert(PendingLocs.
size() == 2 &&
"Unexpected PendingLocs.size()");
3649 PendingLocs.
clear();
3650 PendingArgFlags.
clear();
3657 unsigned StoreSizeBytes = GRLen / 8;
3660 if (ValVT == MVT::f32 && !UseGPRForFloat)
3662 else if (ValVT == MVT::f64 && !UseGPRForFloat)
3676 if (!PendingLocs.
empty()) {
3678 assert(PendingLocs.
size() > 2 &&
"Unexpected PendingLocs.size()");
3679 for (
auto &It : PendingLocs) {
3681 It.convertToReg(Reg);
3686 PendingLocs.clear();
3687 PendingArgFlags.
clear();
3690 assert((!UseGPRForFloat || LocVT == GRLenVT) &&
3691 "Expected an GRLenVT at this stage");
3708void LoongArchTargetLowering::analyzeInputArgs(
3711 LoongArchCCAssignFn Fn)
const {
3713 for (
unsigned i = 0, e =
Ins.size(); i != e; ++i) {
3715 Type *ArgTy =
nullptr;
3717 ArgTy = FType->getReturnType();
3718 else if (Ins[i].isOrigArg())
3719 ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
3723 CCInfo,
true, IsRet, ArgTy)) {
3724 LLVM_DEBUG(
dbgs() <<
"InputArg #" << i <<
" has unhandled type " << ArgVT
3731void LoongArchTargetLowering::analyzeOutputArgs(
3734 CallLoweringInfo *CLI, LoongArchCCAssignFn Fn)
const {
3735 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
3736 MVT ArgVT = Outs[i].VT;
3737 Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty :
nullptr;
3741 CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
3742 LLVM_DEBUG(
dbgs() <<
"OutputArg #" << i <<
" has unhandled type " << ArgVT
3833 if (LocVT == MVT::i32 || LocVT == MVT::i64) {
3837 LoongArch::R23, LoongArch::R24, LoongArch::R25,
3838 LoongArch::R26, LoongArch::R27, LoongArch::R28,
3839 LoongArch::R29, LoongArch::R30, LoongArch::R31};
3846 if (LocVT == MVT::f32) {
3849 static const MCPhysReg FPR32List[] = {LoongArch::F24, LoongArch::F25,
3850 LoongArch::F26, LoongArch::F27};
3851 if (
unsigned Reg = State.
AllocateReg(FPR32List)) {
3857 if (LocVT == MVT::f64) {
3860 static const MCPhysReg FPR64List[] = {LoongArch::F28_64, LoongArch::F29_64,
3861 LoongArch::F30_64, LoongArch::F31_64};
3862 if (
unsigned Reg = State.
AllocateReg(FPR64List)) {
3890 "GHC calling convention requires the F and D extensions");
3895 unsigned GRLenInBytes = Subtarget.
getGRLen() / 8;
3897 std::vector<SDValue> OutChains;
3906 analyzeInputArgs(MF, CCInfo, Ins,
false,
CC_LoongArch);
3908 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
3920 unsigned ArgIndex = Ins[i].OrigArgIndex;
3921 unsigned ArgPartOffset = Ins[i].PartOffset;
3922 assert(ArgPartOffset == 0);
3923 while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
3925 unsigned PartOffset = Ins[i + 1].PartOffset - ArgPartOffset;
3948 int VaArgOffset, VarArgsSaveSize;
3954 VarArgsSaveSize = 0;
3956 VarArgsSaveSize = GRLenInBytes * (ArgRegs.
size() -
Idx);
3957 VaArgOffset = -VarArgsSaveSize;
3963 LoongArchFI->setVarArgsFrameIndex(FI);
3971 VarArgsSaveSize += GRLenInBytes;
3976 for (
unsigned I =
Idx;
I < ArgRegs.
size();
3977 ++
I, VaArgOffset += GRLenInBytes) {
3985 cast<StoreSDNode>(Store.getNode())
3987 ->setValue((
Value *)
nullptr);
3988 OutChains.push_back(Store);
3990 LoongArchFI->setVarArgsSaveSize(VarArgsSaveSize);
3995 if (!OutChains.empty()) {
3996 OutChains.push_back(Chain);
4011 if (
N->getNumValues() != 1)
4013 if (!
N->hasNUsesOfValue(1, 0))
4016 SDNode *Copy = *
N->use_begin();
4022 if (Copy->getGluedNode())
4026 bool HasRet =
false;
4027 for (
SDNode *Node : Copy->uses()) {
4036 Chain = Copy->getOperand(0);
4041bool LoongArchTargetLowering::isEligibleForTailCallOptimization(
4045 auto CalleeCC = CLI.CallConv;
4046 auto &Outs = CLI.Outs;
4048 auto CallerCC = Caller.getCallingConv();
4055 for (
auto &VA : ArgLocs)
4061 auto IsCallerStructRet = Caller.hasStructRetAttr();
4062 auto IsCalleeStructRet = Outs.
empty() ?
false : Outs[0].Flags.isSRet();
4063 if (IsCallerStructRet || IsCalleeStructRet)
4067 for (
auto &Arg : Outs)
4068 if (Arg.Flags.isByVal())
4073 const uint32_t *CallerPreserved =
TRI->getCallPreservedMask(MF, CallerCC);
4074 if (CalleeCC != CallerCC) {
4075 const uint32_t *CalleePreserved =
TRI->getCallPreservedMask(MF, CalleeCC);
4076 if (!
TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
4114 analyzeOutputArgs(MF, ArgCCInfo, Outs,
false, &CLI,
CC_LoongArch);
4118 IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
4124 "site marked musttail");
4131 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
4133 if (!Flags.isByVal())
4137 unsigned Size = Flags.getByValSize();
4138 Align Alignment = Flags.getNonZeroByValAlign();
4145 Chain = DAG.
getMemcpy(Chain,
DL, FIPtr, Arg, SizeNode, Alignment,
4159 for (
unsigned i = 0, j = 0, e = ArgLocs.
size(); i != e; ++i) {
4161 SDValue ArgValue = OutVals[i];
4174 unsigned ArgIndex = Outs[i].OrigArgIndex;
4175 unsigned ArgPartOffset = Outs[i].PartOffset;
4176 assert(ArgPartOffset == 0);
4181 while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
4182 SDValue PartValue = OutVals[i + 1];
4183 unsigned PartOffset = Outs[i + 1].PartOffset - ArgPartOffset;
4193 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
4197 for (
const auto &Part : Parts) {
4198 SDValue PartValue = Part.first;
4199 SDValue PartOffset = Part.second;
4206 ArgValue = SpillSlot;
4212 if (Flags.isByVal())
4213 ArgValue = ByValArgs[j++];
4220 assert(!IsTailCall &&
"Tail call not allowed if stack is used "
4221 "for passing parameters");
4224 if (!StackPtr.getNode())
4237 if (!MemOpChains.
empty())
4243 for (
auto &Reg : RegsToPass) {
4244 Chain = DAG.
getCopyToReg(Chain,
DL, Reg.first, Reg.second, Glue);
4271 for (
auto &Reg : RegsToPass)
4277 const uint32_t *Mask =
TRI->getCallPreservedMask(MF, CallConv);
4278 assert(Mask &&
"Missing call preserved mask for calling convention");
4296 assert(Subtarget.
is64Bit() &&
"Medium code model requires LA64");
4300 assert(Subtarget.
is64Bit() &&
"Large code model requires LA64");
4323 analyzeInputArgs(MF, RetCCInfo, Ins,
true,
CC_LoongArch);
4326 for (
auto &VA : RVLocs) {
4348 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
4352 Outs[i].Flags, CCInfo,
true,
true,
4379 for (
unsigned i = 0, e = RVLocs.
size(); i < e; ++i) {
4401bool LoongArchTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT,
4402 bool ForCodeSize)
const {
4404 if (VT == MVT::f32 && !Subtarget.hasBasicF())
4406 if (VT == MVT::f64 && !Subtarget.hasBasicD())
4408 return (Imm.isZero() || Imm.isExactlyValue(+1.0));
4419bool LoongArchTargetLowering::shouldInsertFencesForAtomic(
4422 return isa<LoadInst>(
I) || isa<StoreInst>(
I);
4424 if (isa<LoadInst>(
I))
4429 if (isa<StoreInst>(
I)) {
4430 unsigned Size =
I->getOperand(0)->getType()->getIntegerBitWidth();
4447 return Y.getValueType().isScalarInteger() && !isa<ConstantSDNode>(
Y);
4453 unsigned Intrinsic)
const {
4454 switch (Intrinsic) {
4457 case Intrinsic::loongarch_masked_atomicrmw_xchg_i32:
4458 case Intrinsic::loongarch_masked_atomicrmw_add_i32:
4459 case Intrinsic::loongarch_masked_atomicrmw_sub_i32:
4460 case Intrinsic::loongarch_masked_atomicrmw_nand_i32:
4462 Info.memVT = MVT::i32;
4463 Info.ptrVal =
I.getArgOperand(0);
4498 return Intrinsic::loongarch_masked_atomicrmw_xchg_i64;
4500 return Intrinsic::loongarch_masked_atomicrmw_add_i64;
4502 return Intrinsic::loongarch_masked_atomicrmw_sub_i64;
4504 return Intrinsic::loongarch_masked_atomicrmw_nand_i64;
4506 return Intrinsic::loongarch_masked_atomicrmw_umax_i64;
4508 return Intrinsic::loongarch_masked_atomicrmw_umin_i64;
4510 return Intrinsic::loongarch_masked_atomicrmw_max_i64;
4512 return Intrinsic::loongarch_masked_atomicrmw_min_i64;
4522 return Intrinsic::loongarch_masked_atomicrmw_xchg_i32;
4524 return Intrinsic::loongarch_masked_atomicrmw_add_i32;
4526 return Intrinsic::loongarch_masked_atomicrmw_sub_i32;
4528 return Intrinsic::loongarch_masked_atomicrmw_nand_i32;
4549 Value *FailureOrdering =
4553 Intrinsic::ID CmpXchgIntrID = Intrinsic::loongarch_masked_cmpxchg_i64;
4561 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, FailureOrdering});
4585 unsigned GRLen = Subtarget.
getGRLen();
4614 {AlignedAddr, Incr, Mask, SextShamt, Ordering});
4617 Builder.
CreateCall(LlwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
4644 const Constant *PersonalityFn)
const {
4645 return LoongArch::R4;
4649 const Constant *PersonalityFn)
const {
4650 return LoongArch::R5;
4658LoongArchTargetLowering::getConstraintType(
StringRef Constraint)
const {
4676 if (Constraint.
size() == 1) {
4677 switch (Constraint[0]) {
4692 if (Constraint ==
"ZC" || Constraint ==
"ZB")
4708std::pair<unsigned, const TargetRegisterClass *>
4709LoongArchTargetLowering::getRegForInlineAsmConstraint(
4713 if (Constraint.
size() == 1) {
4714 switch (Constraint[0]) {
4719 return std::make_pair(0U, &LoongArch::GPRRegClass);
4721 if (Subtarget.hasBasicF() && VT == MVT::f32)
4722 return std::make_pair(0U, &LoongArch::FPR32RegClass);
4723 if (Subtarget.hasBasicD() && VT == MVT::f64)
4724 return std::make_pair(0U, &LoongArch::FPR64RegClass);
4725 if (Subtarget.hasExtLSX() &&
4726 TRI->isTypeLegalForClass(LoongArch::LSX128RegClass, VT))
4727 return std::make_pair(0U, &LoongArch::LSX128RegClass);
4728 if (Subtarget.hasExtLASX() &&
4729 TRI->isTypeLegalForClass(LoongArch::LASX256RegClass, VT))
4730 return std::make_pair(0U, &LoongArch::LASX256RegClass);
4750 bool IsFP = Constraint[2] ==
'f';
4751 std::pair<StringRef, StringRef> Temp = Constraint.
split(
'$');
4752 std::pair<unsigned, const TargetRegisterClass *>
R;
4754 TRI, join_items(
"", Temp.first, Temp.second), VT);
4757 unsigned RegNo =
R.first;
4758 if (LoongArch::F0 <= RegNo && RegNo <= LoongArch::F31) {
4759 if (Subtarget.hasBasicD() && (VT == MVT::f64 || VT == MVT::Other)) {
4760 unsigned DReg = RegNo - LoongArch::F0 + LoongArch::F0_64;
4761 return std::make_pair(DReg, &LoongArch::FPR64RegClass);
4771void LoongArchTargetLowering::LowerAsmOperandForConstraint(
4775 if (Constraint.
size() == 1) {
4776 switch (Constraint[0]) {
4779 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4781 if (isInt<16>(CVal))
4788 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4790 if (isInt<12>(CVal))
4797 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
4798 if (
C->getZExtValue() == 0)
4804 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4806 if (isUInt<12>(CVal))
4818#define GET_REGISTER_MATCHER
4819#include "LoongArchGenAsmMatcher.inc"
4825 std::string NewRegName =
Name.second.str();
4827 if (Reg == LoongArch::NoRegister)
4829 if (Reg == LoongArch::NoRegister)
4833 if (!ReservedRegs.
test(Reg))
4849 if (
auto *ConstNode = dyn_cast<ConstantSDNode>(
C.getNode())) {
4850 const APInt &Imm = ConstNode->getAPIntValue();
4852 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
4853 (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())
4856 if (ConstNode->hasOneUse() &&
4857 ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() ||
4858 (Imm - 8).isPowerOf2() || (Imm - 16).isPowerOf2()))
4864 if (ConstNode->hasOneUse() && !(Imm.sge(-2048) && Imm.sle(4095))) {
4865 unsigned Shifts = Imm.countr_zero();
4871 APInt ImmPop = Imm.ashr(Shifts);
4872 if (ImmPop == 3 || ImmPop == 5 || ImmPop == 9 || ImmPop == 17)
4876 APInt ImmSmall =
APInt(Imm.getBitWidth(), 1ULL << Shifts,
true);
4877 if ((Imm - ImmSmall).isPowerOf2() || (Imm + ImmSmall).isPowerOf2() ||
4878 (ImmSmall - Imm).isPowerOf2())
4888 Type *Ty,
unsigned AS,
4904 !(isShiftedInt<14, 2>(AM.
BaseOffs) && Subtarget.hasUAL()))
4931 return isInt<12>(Imm);
4935 return isInt<12>(Imm);
4942 if (
auto *LD = dyn_cast<LoadSDNode>(Val)) {
4943 EVT MemVT = LD->getMemoryVT();
4944 if ((MemVT == MVT::i8 || MemVT == MVT::i16) &&
4955 return Subtarget.
is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
4960 if (
Y.getValueType().isVector())
4963 return !isa<ConstantSDNode>(
Y);
unsigned const MachineRegisterInfo * MRI
static MCRegister MatchRegisterName(StringRef Name)
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define NODE_NAME_CASE(node)
static MCRegister MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
Function Alias Analysis Results
static uint64_t getConstant(const Value *IndexValue)
static SDValue getTargetNode(GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
Analysis containing CSE Info
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
static SDValue performINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
const MCPhysReg ArgFPR32s[]
static SDValue emitIntrinsicErrorMessage(SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
static void emitErrorAndReplaceIntrinsicResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, StringRef ErrorMsg, bool WithChain=true)
static SDValue checkIntrinsicImmArg(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue lowerVectorBitSetImm(SDNode *Node, SelectionDAG &DAG)
#define CRC_CASE_EXT_BINARYOP(NAME, NODE)
static SDValue lowerVectorBitRevImm(SDNode *Node, SelectionDAG &DAG)
static SDValue truncateVecElts(SDNode *Node, SelectionDAG &DAG)
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
static SDValue lowerVectorBitClear(SDNode *Node, SelectionDAG &DAG)
static bool CC_LoongArch_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static void replaceVPICKVE2GRResults(SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static SDValue legalizeIntrinsicImmArg(SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, bool IsSigned=false)
static SDValue emitIntrinsicWithChainErrorMessage(SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static bool CC_LoongArchAssign2GRLen(unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
const MCPhysReg ArgFPR64s[]
#define IOCSRWR_CASE(NAME, NODE)
#define CRC_CASE_EXT_UNARYOP(NAME, NODE)
static MachineBasicBlock * emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static SDValue lowerVectorSplatImm(SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
const MCPhysReg ArgGPRs[]
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
static void replaceVecCondBranchResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
#define ASRT_LE_GT_CASE(NAME)
static bool isConstantOrUndef(const SDValue Op)
static MachineBasicBlock * emitVecCondBranchPseudo(MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
#define IOCSRRD_CASE(NAME, NODE)
static SDValue lowerVectorBitClearImm(SDNode *Node, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
static void replaceINTRINSIC_WO_CHAINResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp(unsigned GRLen, AtomicRMWInst::BinOp BinOp)
static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode)
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class for arbitrary precision integers.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
An instruction that atomically checks whether a specified value is in a memory location,...
Value * getCompareOperand()
AtomicOrdering getFailureOrdering() const
Returns the failure ordering constraint of this cmpxchg instruction.
an instruction that atomically reads a memory location, combines it with another value,...
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
BinOp
This enumeration lists the possible modifications atomicrmw can make.
@ Min
*p = old <signed v ? old : v
@ UIncWrap
Increment one up to a maximum value.
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ UMax
*p = old >unsigned v ? old : v
@ UDecWrap
Decrement one until a minimum value or zero.
bool isFloatingPointOperation() const
BinOp getOperation() const
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
LLVM Basic Block Representation.
bool test(unsigned Idx) const
A "pseudo-class" with methods for operating on BUILD_VECTORs.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
SmallVectorImpl< CCValAssign > & getPendingLocs()
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
int64_t getLocMemOffset() const
unsigned getValNo() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
bool isMinusOne() const
This function will return true iff every bit in this constant is set to true.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This is an important base class in LLVM.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Common base class shared among various IRBuilders.
Value * CreateSExt(Value *V, Type *DestTy, const Twine &Name="")
IntegerType * getInt32Ty()
Fetch the type representing a 32-bit integer.
IntegerType * getInt64Ty()
Fetch the type representing a 64-bit integer.
Value * CreateNot(Value *V, const Twine &Name="")
Value * CreateSub(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
ConstantInt * getIntN(unsigned N, uint64_t C)
Get a constant N-bit value, zero extended or truncated from a 64-bit value.
AtomicRMWInst * CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val, MaybeAlign Align, AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System)
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="", bool IsNUW=false, bool IsNSW=false)
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...
const LoongArchRegisterInfo * getRegisterInfo() const override
const LoongArchInstrInfo * getInstrInfo() const override
unsigned getMaxBytesForAlignment() const
Align getPrefFunctionAlignment() const
unsigned getGRLen() const
Align getPrefLoopAlignment() const
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
LoongArchTargetLowering(const TargetMachine &TM, const LoongArchSubtarget &STI)
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool hasFeature(unsigned Feature) const
bool is128BitVector() const
Return true if this is a 128-bit vector type.
bool isVector() const
Return true if this is a vector value type.
static auto fixedlen_vector_valuetypes()
bool is256BitVector() const
Return true if this is a 256-bit vector type.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
void setIsKill(bool Val=true)
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
size_t use_size() const
Return the number of uses of this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
uint64_t getScalarValueSizeInBits() const
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
const TargetLowering & getTargetLoweringInfo() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
void setMaxBytesForAlignment(unsigned MaxBytes)
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Primary interface to the complete machine description for the target machine.
bool useTLSDESC() const
Returns true if this target uses TLS Descriptors.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
CodeModel::Model getCodeModel() const
Returns the code model.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ UNDEF
UNDEF - An undefined node.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=std::nullopt)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
ABI getTargetABI(StringRef ABIName)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
@ SingleThread
Synchronized with respect to signal handlers executing in the same thread.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
AtomicOrdering
Atomic ordering for LLVM's memory model.
unsigned getKillRegState(bool B)
DWARFExpression::Operation Op
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool is256BitVector() const
Return true if this is a 256-bit vector type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Align getNonZeroOrigAlign() const
Register getFrameRegister(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT, bool Value=true)