28#define GET_REGINFO_TARGET_DESC
29#include "RISCVGenRegisterInfo.inc"
38 cl::desc(
"Disable two address hints for register "
41static_assert(RISCV::X1 == RISCV::X0 + 1,
"Register list not consecutive");
42static_assert(RISCV::X31 == RISCV::X0 + 31,
"Register list not consecutive");
43static_assert(RISCV::F1_H == RISCV::F0_H + 1,
"Register list not consecutive");
44static_assert(RISCV::F31_H == RISCV::F0_H + 31,
45 "Register list not consecutive");
46static_assert(RISCV::F1_F == RISCV::F0_F + 1,
"Register list not consecutive");
47static_assert(RISCV::F31_F == RISCV::F0_F + 31,
48 "Register list not consecutive");
49static_assert(RISCV::F1_D == RISCV::F0_D + 1,
"Register list not consecutive");
50static_assert(RISCV::F31_D == RISCV::F0_D + 31,
51 "Register list not consecutive");
52static_assert(RISCV::V1 == RISCV::V0 + 1,
"Register list not consecutive");
53static_assert(RISCV::V31 == RISCV::V0 + 31,
"Register list not consecutive");
63 return CSR_NoRegs_SaveList;
65 if (Subtarget.hasStdExtD())
66 return CSR_XLEN_F64_Interrupt_SaveList;
67 if (Subtarget.hasStdExtF())
68 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
69 : CSR_XLEN_F32_Interrupt_SaveList;
70 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
71 : CSR_Interrupt_SaveList;
76 Subtarget.hasVInstructions();
78 switch (Subtarget.getTargetABI()) {
83 return CSR_ILP32E_LP64E_SaveList;
87 return CSR_ILP32_LP64_V_SaveList;
88 return CSR_ILP32_LP64_SaveList;
92 return CSR_ILP32F_LP64F_V_SaveList;
93 return CSR_ILP32F_LP64F_SaveList;
97 return CSR_ILP32D_LP64D_V_SaveList;
98 return CSR_ILP32D_LP64D_SaveList;
108 for (
size_t Reg = 0; Reg < getNumRegs(); Reg++) {
109 if (Subtarget.isRegisterReservedByUser(Reg))
127 markSuperRegs(
Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);
130 if (Subtarget.hasStdExtE())
131 for (
MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
136 markSuperRegs(
Reserved, RISCV::VTYPE);
137 markSuperRegs(
Reserved, RISCV::VXSAT);
138 markSuperRegs(
Reserved, RISCV::VXRM);
139 markSuperRegs(
Reserved, RISCV::VLENB);
142 markSuperRegs(
Reserved, RISCV::FRM);
143 markSuperRegs(
Reserved, RISCV::FFLAGS);
146 markSuperRegs(
Reserved, RISCV::VCIX_STATE);
149 if (Subtarget.hasStdExtE())
151 markSuperRegs(
Reserved, RISCV::X23);
152 markSuperRegs(
Reserved, RISCV::X27);
156 markSuperRegs(
Reserved, RISCV::SSP);
168 return CSR_NoRegs_RegMask;
178 if (DestReg == SrcReg && !
Offset.getFixed() && !
Offset.getScalable())
186 bool KillSrcReg =
false;
188 if (
Offset.getScalable()) {
189 unsigned ScalableAdjOpc = RISCV::ADD;
190 int64_t ScalableValue =
Offset.getScalable();
191 if (ScalableValue < 0) {
192 ScalableValue = -ScalableValue;
193 ScalableAdjOpc = RISCV::SUB;
197 if (DestReg == SrcReg)
198 ScratchReg =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
200 assert(ScalableValue > 0 &&
"There is no need to get VLEN scaled value.");
201 assert(ScalableValue % 8 == 0 &&
202 "Reserve the stack by the multiple of one vector size.");
203 assert(isInt<32>(ScalableValue / 8) &&
204 "Expect the number of vector registers within 32-bits.");
205 uint32_t NumOfVReg = ScalableValue / 8;
209 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
210 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
211 unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD :
212 (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
217 TII->mulImm(MF,
MBB, II,
DL, ScratchReg, NumOfVReg, Flag);
226 int64_t Val =
Offset.getFixed();
227 if (DestReg == SrcReg && Val == 0)
232 if (isInt<12>(Val)) {
246 assert(
Align < 2048 &&
"Required alignment too large");
247 int64_t MaxPosAdjStep = 2048 -
Align;
248 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
249 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
267 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
269 if (isShiftedInt<12, 3>(Val)) {
272 }
else if (isShiftedInt<12, 2>(Val)) {
277 Register ScratchReg =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
278 TII->movImm(
MBB, II,
DL, ScratchReg, Val, Flag);
287 unsigned Opc = RISCV::ADD;
293 Register ScratchReg =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
294 TII->movImm(
MBB, II,
DL, ScratchReg, Val, Flag);
313 unsigned NF = ZvlssegInfo->first;
314 unsigned LMUL = ZvlssegInfo->second;
315 assert(NF * LMUL <= 8 &&
"Invalid NF/LMUL combinations.");
316 unsigned Opcode, SubRegIdx;
321 Opcode = RISCV::VS1R_V;
322 SubRegIdx = RISCV::sub_vrm1_0;
325 Opcode = RISCV::VS2R_V;
326 SubRegIdx = RISCV::sub_vrm2_0;
329 Opcode = RISCV::VS4R_V;
330 SubRegIdx = RISCV::sub_vrm4_0;
333 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
334 "Unexpected subreg numbering");
335 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
336 "Unexpected subreg numbering");
337 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
338 "Unexpected subreg numbering");
340 Register VL =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
343 const int64_t VLENB = *VLEN / 8;
344 int64_t
Offset = VLENB * LMUL;
349 if (ShiftAmount != 0)
355 Register SrcReg = II->getOperand(0).getReg();
357 bool IsBaseKill = II->getOperand(1).isKill();
358 Register NewBase =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
359 for (
unsigned I = 0;
I < NF; ++
I) {
365 .
addReg(
TRI->getSubReg(SrcReg, SubRegIdx +
I))
375 II->eraseFromParent();
390 unsigned NF = ZvlssegInfo->first;
391 unsigned LMUL = ZvlssegInfo->second;
392 assert(NF * LMUL <= 8 &&
"Invalid NF/LMUL combinations.");
393 unsigned Opcode, SubRegIdx;
398 Opcode = RISCV::VL1RE8_V;
399 SubRegIdx = RISCV::sub_vrm1_0;
402 Opcode = RISCV::VL2RE8_V;
403 SubRegIdx = RISCV::sub_vrm2_0;
406 Opcode = RISCV::VL4RE8_V;
407 SubRegIdx = RISCV::sub_vrm4_0;
410 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,
411 "Unexpected subreg numbering");
412 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,
413 "Unexpected subreg numbering");
414 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,
415 "Unexpected subreg numbering");
417 Register VL =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
420 const int64_t VLENB = *VLEN / 8;
421 int64_t
Offset = VLENB * LMUL;
426 if (ShiftAmount != 0)
432 Register DestReg = II->getOperand(0).getReg();
434 bool IsBaseKill = II->getOperand(1).isKill();
435 Register NewBase =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
436 for (
unsigned I = 0;
I < NF; ++
I) {
438 TRI->getSubReg(DestReg, SubRegIdx +
I))
447 II->eraseFromParent();
451 int SPAdj,
unsigned FIOperandNum,
453 assert(SPAdj == 0 &&
"Unexpected non-zero SPAdj value");
461 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
464 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
469 if (
Offset.getScalable() &&
470 ST.getRealMinVLen() == ST.getRealMaxVLen()) {
473 int64_t FixedValue =
Offset.getFixed();
474 int64_t ScalableValue =
Offset.getScalable();
475 assert(ScalableValue % 8 == 0 &&
476 "Scalable offset is not a multiple of a single vector size.");
477 int64_t NumOfVReg = ScalableValue / 8;
478 int64_t VLENB = ST.getRealMinVLen() / 8;
482 if (!isInt<32>(
Offset.getFixed())) {
484 "Frame offsets outside of the signed 32-bit range not supported");
488 int64_t Val =
Offset.getFixed();
489 int64_t Lo12 = SignExtend64<12>(Val);
490 unsigned Opc =
MI.getOpcode();
491 if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
497 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
498 }
else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
499 Opc == RISCV::PREFETCH_W) &&
500 (Lo12 & 0b11111) != 0) {
502 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
503 }
else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
504 Opc == RISCV::PseudoRV32ZdinxSD) &&
509 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
514 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo12);
522 if (
MI.getOpcode() == RISCV::ADDI)
523 DestReg =
MI.getOperand(0).getReg();
525 DestReg =
MRI.createVirtualRegister(&RISCV::GPRRegClass);
528 MI.getOperand(FIOperandNum).ChangeToRegister(DestReg,
false,
532 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false,
538 if (
MI.getOpcode() == RISCV::ADDI &&
539 MI.getOperand(0).getReg() ==
MI.getOperand(1).getReg() &&
540 MI.getOperand(2).getImm() == 0) {
541 MI.eraseFromParent();
549 switch (
MI.getOpcode()) {
550 case RISCV::PseudoVSPILL2_M1:
551 case RISCV::PseudoVSPILL2_M2:
552 case RISCV::PseudoVSPILL2_M4:
553 case RISCV::PseudoVSPILL3_M1:
554 case RISCV::PseudoVSPILL3_M2:
555 case RISCV::PseudoVSPILL4_M1:
556 case RISCV::PseudoVSPILL4_M2:
557 case RISCV::PseudoVSPILL5_M1:
558 case RISCV::PseudoVSPILL6_M1:
559 case RISCV::PseudoVSPILL7_M1:
560 case RISCV::PseudoVSPILL8_M1:
563 case RISCV::PseudoVRELOAD2_M1:
564 case RISCV::PseudoVRELOAD2_M2:
565 case RISCV::PseudoVRELOAD2_M4:
566 case RISCV::PseudoVRELOAD3_M1:
567 case RISCV::PseudoVRELOAD3_M2:
568 case RISCV::PseudoVRELOAD4_M1:
569 case RISCV::PseudoVRELOAD4_M2:
570 case RISCV::PseudoVRELOAD5_M1:
571 case RISCV::PseudoVRELOAD6_M1:
572 case RISCV::PseudoVRELOAD7_M1:
573 case RISCV::PseudoVRELOAD8_M1:
592 unsigned FIOperandNum = 0;
593 for (; !
MI->getOperand(FIOperandNum).isFI(); FIOperandNum++)
594 assert(FIOperandNum < MI->getNumOperands() &&
595 "Instr doesn't have FrameIndex operand");
604 if (!
MI->mayLoad() && !
MI->mayStore())
612 if (TFI->
hasFP(MF) && !shouldRealignStack(MF)) {
616 unsigned CalleeSavedSize = 0;
619 if (Subtarget.isRegisterReservedByUser(Reg))
622 if (RISCV::GPRRegClass.
contains(Reg))
623 CalleeSavedSize += getSpillSize(RISCV::GPRRegClass);
624 else if (RISCV::FPR64RegClass.
contains(Reg))
625 CalleeSavedSize += getSpillSize(RISCV::FPR64RegClass);
626 else if (RISCV::FPR32RegClass.
contains(Reg))
627 CalleeSavedSize += getSpillSize(RISCV::FPR32RegClass);
631 int64_t MaxFPOffset =
Offset - CalleeSavedSize;
639 int64_t MaxSPOffset =
Offset + 128;
649 unsigned FIOperandNum = 0;
650 while (!
MI->getOperand(FIOperandNum).isFI()) {
652 assert(FIOperandNum < MI->getNumOperands() &&
653 "Instr does not have a FrameIndex operand!");
685 unsigned FIOperandNum = 0;
686 while (!
MI.getOperand(FIOperandNum).isFI()) {
688 assert(FIOperandNum <
MI.getNumOperands() &&
689 "Instr does not have a FrameIndex operand!");
695 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg,
false);
696 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
705 "The MI must be I or S format.");
706 assert(
MI->getOperand(
Idx).isFI() &&
"The Idx'th operand of MI is not a "
707 "FrameIndex operand");
708 return MI->getOperand(
Idx + 1).getImm();
713 return TFI->
hasFP(MF) ? RISCV::X8 : RISCV::X2;
722 return CSR_NoRegs_RegMask;
723 switch (Subtarget.getTargetABI()) {
728 return CSR_ILP32E_LP64E_RegMask;
732 return CSR_ILP32_LP64_V_RegMask;
733 return CSR_ILP32_LP64_RegMask;
737 return CSR_ILP32F_LP64F_V_RegMask;
738 return CSR_ILP32F_LP64F_RegMask;
742 return CSR_ILP32D_LP64D_V_RegMask;
743 return CSR_ILP32D_LP64D_RegMask;
750 if (RC == &RISCV::VMV0RegClass)
751 return &RISCV::VRRegClass;
752 if (RC == &RISCV::VRNoV0RegClass)
753 return &RISCV::VRRegClass;
754 if (RC == &RISCV::VRM2NoV0RegClass)
755 return &RISCV::VRM2RegClass;
756 if (RC == &RISCV::VRM4NoV0RegClass)
757 return &RISCV::VRM4RegClass;
758 if (RC == &RISCV::VRM8NoV0RegClass)
759 return &RISCV::VRM8RegClass;
768 assert(
Offset.getScalable() % 8 == 0 &&
"Invalid frame offset");
774 int64_t VLENBSized =
Offset.getScalable() / 8;
775 if (VLENBSized > 0) {
778 Ops.
append({dwarf::DW_OP_bregx, VLENB, 0ULL});
781 }
else if (VLENBSized < 0) {
784 Ops.
append({dwarf::DW_OP_bregx, VLENB, 0ULL});
808 VirtReg, Order, Hints, MF, VRM,
Matrix);
811 return BaseImplRetVal;
817 bool NeedGPRC) ->
void {
823 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.
contains(PhysReg)) &&
824 !MO.getSubReg() && !VRRegMO.
getSubReg()) {
826 TwoAddrHints.
insert(PhysReg);
832 auto isCompressible = [&Subtarget](
const MachineInstr &
MI,
bool &NeedGPRC) {
834 switch (
MI.getOpcode()) {
847 if (!
MI.getOperand(2).isImm())
849 int64_t Imm =
MI.getOperand(2).getImm();
853 return Subtarget.hasStdExtZcb() && Imm == 255;
864 return MI.getOperand(2).isImm() && isInt<6>(
MI.getOperand(2).getImm());
868 case RISCV::ZEXT_H_RV32:
869 case RISCV::ZEXT_H_RV64:
872 return Subtarget.hasStdExtZcb();
876 return Subtarget.hasStdExtZcb() &&
MI.getOperand(2).isReg() &&
877 MI.getOperand(2).getReg() == RISCV::X0;
881 return Subtarget.hasStdExtZcb() &&
MI.getOperand(2).isImm() &&
882 MI.getOperand(2).getImm() == -1;
895 return PhysReg && RISCV::GPRCRegClass.contains(PhysReg);
898 for (
auto &MO :
MRI->reg_nodbg_operands(VirtReg)) {
900 unsigned OpIdx = MO.getOperandNo();
902 if (isCompressible(
MI, NeedGPRC)) {
903 if (OpIdx == 0 &&
MI.getOperand(1).isReg()) {
904 if (!NeedGPRC ||
MI.getNumExplicitOperands() < 3 ||
905 MI.getOpcode() == RISCV::ADD_UW ||
906 isCompressibleOpnd(
MI.getOperand(2)))
907 tryAddHint(MO,
MI.getOperand(1), NeedGPRC);
908 if (
MI.isCommutable() &&
MI.getOperand(2).isReg() &&
909 (!NeedGPRC || isCompressibleOpnd(
MI.getOperand(1))))
910 tryAddHint(MO,
MI.getOperand(2), NeedGPRC);
911 }
else if (OpIdx == 1 && (!NeedGPRC ||
MI.getNumExplicitOperands() < 3 ||
912 isCompressibleOpnd(
MI.getOperand(2)))) {
913 tryAddHint(MO,
MI.getOperand(0), NeedGPRC);
914 }
else if (
MI.isCommutable() && OpIdx == 2 &&
915 (!NeedGPRC || isCompressibleOpnd(
MI.getOperand(1)))) {
916 tryAddHint(MO,
MI.getOperand(0), NeedGPRC);
922 if (TwoAddrHints.
count(OrderReg))
925 return BaseImplRetVal;
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static cl::opt< bool > DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden, cl::init(false), cl::desc("Disable two address hints for register " "allocation"))
static cl::opt< bool > DisableCostPerUse("riscv-disable-cost-per-use", cl::init(false), cl::Hidden)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Wrapper class representing physical registers. Should be passed by value.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasBP(const MachineFunction &MF) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
std::optional< unsigned > getRealVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
Wrapper class representing virtual and physical registers.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
static StackOffset get(int64_t Fixed, int64_t Scalable)
Information about stack frame layout on the target.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual const TargetInstrInfo * getInstrInfo() const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ RISCV_VectorCall
Calling convention used for RISC-V V-extension.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
static unsigned getFormat(uint64_t TSFlags)
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg(unsigned Opcode)
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getKillRegState(bool B)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerVRELOAD(MachineBasicBlock::iterator II) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
RISCVRegisterInfo(unsigned HwMode)
void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
void lowerVSPILL(MachineBasicBlock::iterator II) const
Register getFrameRegister(const MachineFunction &MF) const override
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * getNoPreservedMask() const override
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override