34#include "llvm/IR/IntrinsicsWebAssembly.h"
44#define DEBUG_TYPE "wasm-lower"
49 auto MVTPtr = Subtarget->
hasAddr64() ? MVT::i64 : MVT::i32;
59 Subtarget->
hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
82 for (
auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) {
87 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
96 for (
auto T : {MVT::externref, MVT::funcref, MVT::Other}) {
116 for (
auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
147 for (
auto T : {MVT::i32, MVT::i64})
150 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
156 for (
auto T : {MVT::i32, MVT::i64})
187 for (
auto T : {MVT::v16i8, MVT::v8i16})
191 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
195 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
200 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
205 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
211 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
216 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
224 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
231 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
236 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
246 for (
auto T : {MVT::v8i16, MVT::v4i32, MVT::v2i64})
252 for (
auto T : {MVT::v4f32, MVT::v2f64})
262 for (
auto T : {MVT::v2i64, MVT::v2f64})
282 for (
auto T : {MVT::i8, MVT::i16, MVT::i32})
298 for (
auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
316 for (
auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32,
319 if (
MVT(
T) != MemT) {
357 setLibcallName(RTLIB::RETURN_ADDRESS,
"emscripten_return_address");
368 return MVT::externref;
377 return MVT::externref;
384WebAssemblyTargetLowering::shouldExpandAtomicRMWInIR(
AtomicRMWInst *AI)
const {
400bool WebAssemblyTargetLowering::shouldScalarizeBinop(
SDValue VecOp)
const {
420FastISel *WebAssemblyTargetLowering::createFastISel(
425MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(
const DataLayout & ,
436 "32-bit shift counts ought to be enough for anyone");
441 "Unable to represent scalar shift amount type");
451 bool IsUnsigned,
bool Int64,
452 bool Float64,
unsigned LoweredOpcode) {
458 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
459 unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
460 unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
461 unsigned GE = Float64 ? WebAssembly::GE_F64 : WebAssembly::GE_F32;
462 unsigned IConst =
Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
463 unsigned Eqz = WebAssembly::EQZ_I32;
464 unsigned And = WebAssembly::AND_I32;
466 int64_t Substitute = IsUnsigned ? 0 : Limit;
467 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(
double)Limit;
478 F->insert(It, FalseMBB);
479 F->insert(It, TrueMBB);
480 F->insert(It, DoneMBB);
483 DoneMBB->
splice(DoneMBB->
begin(), BB, std::next(
MI.getIterator()), BB->
end());
491 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
492 Tmp0 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
493 Tmp1 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
494 CmpReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
495 EqzReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
496 FalseReg =
MRI.createVirtualRegister(
MRI.getRegClass(OutReg));
497 TrueReg =
MRI.createVirtualRegister(
MRI.getRegClass(OutReg));
499 MI.eraseFromParent();
508 .
addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
513 Tmp1 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
515 MRI.createVirtualRegister(&WebAssembly::I32RegClass);
516 Register AndReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
518 .
addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, 0.0)));
548 CallResults.
getOpcode() == WebAssembly::RET_CALL_RESULTS);
552 bool IsRetCall = CallResults.
getOpcode() == WebAssembly::RET_CALL_RESULTS;
554 bool IsFuncrefCall =
false;
560 IsFuncrefCall = (TRC == &WebAssembly::FUNCREFRegClass);
565 if (IsIndirect && IsRetCall) {
566 CallOp = WebAssembly::RET_CALL_INDIRECT;
567 }
else if (IsIndirect) {
568 CallOp = WebAssembly::CALL_INDIRECT;
569 }
else if (IsRetCall) {
570 CallOp = WebAssembly::RET_CALL;
572 CallOp = WebAssembly::CALL;
588 TII.get(WebAssembly::I32_WRAP_I64), Reg32)
615 for (
auto Def : CallResults.
defs())
638 for (
auto Use : CallParams.
uses())
654 if (IsIndirect && IsFuncrefCall) {
666 BuildMI(MF,
DL,
TII.get(WebAssembly::REF_NULL_FUNCREF), RegFuncref);
670 BuildMI(MF,
DL,
TII.get(WebAssembly::TABLE_SET_FUNCREF))
685 switch (
MI.getOpcode()) {
688 case WebAssembly::FP_TO_SINT_I32_F32:
690 WebAssembly::I32_TRUNC_S_F32);
691 case WebAssembly::FP_TO_UINT_I32_F32:
693 WebAssembly::I32_TRUNC_U_F32);
694 case WebAssembly::FP_TO_SINT_I64_F32:
696 WebAssembly::I64_TRUNC_S_F32);
697 case WebAssembly::FP_TO_UINT_I64_F32:
699 WebAssembly::I64_TRUNC_U_F32);
700 case WebAssembly::FP_TO_SINT_I32_F64:
702 WebAssembly::I32_TRUNC_S_F64);
703 case WebAssembly::FP_TO_UINT_I32_F64:
705 WebAssembly::I32_TRUNC_U_F64);
706 case WebAssembly::FP_TO_SINT_I64_F64:
708 WebAssembly::I64_TRUNC_S_F64);
709 case WebAssembly::FP_TO_UINT_I64_F64:
711 WebAssembly::I64_TRUNC_U_F64);
712 case WebAssembly::CALL_RESULTS:
713 case WebAssembly::RET_CALL_RESULTS:
719WebAssemblyTargetLowering::getTargetNodeName(
unsigned Opcode)
const {
724#define HANDLE_NODETYPE(NODE) \
725 case WebAssemblyISD::NODE: \
726 return "WebAssemblyISD::" #NODE;
727#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE)
728#include "WebAssemblyISD.def"
729#undef HANDLE_MEM_NODETYPE
730#undef HANDLE_NODETYPE
735std::pair<unsigned, const TargetRegisterClass *>
736WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
740 if (Constraint.
size() == 1) {
741 switch (Constraint[0]) {
743 assert(VT != MVT::iPTR &&
"Pointer MVT not expected here");
746 return std::make_pair(0U, &WebAssembly::V128RegClass);
750 return std::make_pair(0U, &WebAssembly::I32RegClass);
752 return std::make_pair(0U, &WebAssembly::I64RegClass);
757 return std::make_pair(0U, &WebAssembly::F32RegClass);
759 return std::make_pair(0U, &WebAssembly::F64RegClass);
773bool WebAssemblyTargetLowering::isCheapToSpeculateCttz(
Type *Ty)
const {
778bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz(
Type *Ty)
const {
783bool WebAssemblyTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
785 Type *Ty,
unsigned AS,
801bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
815bool WebAssemblyTargetLowering::isIntDivCheap(
EVT VT,
822bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(
SDValue ExtVal)
const {
824 EVT MemT = cast<LoadSDNode>(ExtVal->
getOperand(0))->getValueType(0);
825 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
826 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
827 (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
830bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
837bool WebAssemblyTargetLowering::shouldSinkOperands(
841 if (!
I->getType()->isVectorTy() || !
I->isShift())
846 if (dyn_cast<Constant>(V))
852 Ops.
push_back(&cast<Instruction>(V)->getOperandUse(0));
874bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
877 unsigned Intrinsic)
const {
879 case Intrinsic::wasm_memory_atomic_notify:
881 Info.memVT = MVT::i32;
882 Info.ptrVal =
I.getArgOperand(0);
893 case Intrinsic::wasm_memory_atomic_wait32:
895 Info.memVT = MVT::i32;
896 Info.ptrVal =
I.getArgOperand(0);
901 case Intrinsic::wasm_memory_atomic_wait64:
903 Info.memVT = MVT::i64;
904 Info.ptrVal =
I.getArgOperand(0);
909 case Intrinsic::wasm_loadf16_f32:
911 Info.memVT = MVT::f16;
912 Info.ptrVal =
I.getArgOperand(0);
917 case Intrinsic::wasm_storef16_f32:
919 Info.memVT = MVT::f16;
920 Info.ptrVal =
I.getArgOperand(1);
930void WebAssemblyTargetLowering::computeKnownBitsForTargetNode(
933 switch (
Op.getOpcode()) {
937 unsigned IntNo =
Op.getConstantOperandVal(0);
941 case Intrinsic::wasm_bitmask: {
943 EVT VT =
Op.getOperand(1).getSimpleValueType();
946 Known.
Zero |= ZeroMask;
955WebAssemblyTargetLowering::getPreferredVectorAction(
MVT VT)
const {
961 if (EltVT == MVT::i8 || EltVT == MVT::i16 || EltVT == MVT::i32 ||
962 EltVT == MVT::i64 || EltVT == MVT::f32 || EltVT == MVT::f64)
969bool WebAssemblyTargetLowering::shouldSimplifyDemandedVectorElts(
970 SDValue Op,
const TargetLoweringOpt &TLO)
const {
1023WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
1035 "WebAssembly doesn't support language-specific or target-specific "
1036 "calling conventions yet");
1037 if (CLI.IsPatchPoint)
1038 fail(
DL, DAG,
"WebAssembly doesn't support patch point yet");
1040 if (CLI.IsTailCall) {
1041 auto NoTail = [&](
const char *Msg) {
1042 if (CLI.CB && CLI.CB->isMustTailCall())
1044 CLI.IsTailCall =
false;
1048 NoTail(
"WebAssembly 'tail-call' feature not enabled");
1052 NoTail(
"WebAssembly does not support varargs tail calls");
1062 bool TypesMatch = CallerRetTys.
size() == CalleeRetTys.
size() &&
1063 std::equal(CallerRetTys.
begin(), CallerRetTys.
end(),
1064 CalleeRetTys.
begin());
1066 NoTail(
"WebAssembly tail call requires caller and callee return types to "
1071 for (
auto &Arg : CLI.CB->args()) {
1072 Value *Val = Arg.get();
1076 if (
auto *
GEP = dyn_cast<GetElementPtrInst>(Src))
1077 Src =
GEP->getPointerOperand();
1082 if (isa<AllocaInst>(Val)) {
1084 "WebAssembly does not support tail calling with stack arguments");
1099 Outs[0].Flags.isSRet()) {
1104 bool HasSwiftSelfArg =
false;
1105 bool HasSwiftErrorArg =
false;
1107 for (
unsigned I = 0;
I < Outs.
size(); ++
I) {
1113 fail(
DL, DAG,
"WebAssembly hasn't implemented nest arguments");
1115 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca arguments");
1117 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs arguments");
1119 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last arguments");
1138 bool IsVarArg = CLI.IsVarArg;
1146 if (!HasSwiftSelfArg) {
1150 CLI.Outs.push_back(Arg);
1152 CLI.OutVals.push_back(ArgVal);
1154 if (!HasSwiftErrorArg) {
1158 CLI.Outs.push_back(Arg);
1160 CLI.OutVals.push_back(ArgVal);
1175 assert(VT != MVT::iPTR &&
"Legalized args should be concrete");
1180 CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty), Alignment);
1187 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
1190 if (IsVarArg && NumBytes) {
1194 Layout.getStackAlignment(),
1199 assert(ArgLocs[ValNo].getValNo() == ValNo &&
1200 "ArgLocs should remain in order and only hold varargs args");
1201 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
1209 if (!Chains.
empty())
1211 }
else if (IsVarArg) {
1241 for (
const auto &In : Ins) {
1242 assert(!
In.Flags.isByVal() &&
"byval is not valid for return values");
1243 assert(!
In.Flags.isNest() &&
"nest is not valid for return values");
1244 if (
In.Flags.isInAlloca())
1245 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca return values");
1246 if (
In.Flags.isInConsecutiveRegs())
1247 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs return values");
1248 if (
In.Flags.isInConsecutiveRegsLast())
1250 "WebAssembly hasn't implemented cons regs last return values");
1259 CLI.CB->getCalledOperand()->getType())) {
1274 WebAssemblyISD::TABLE_SET,
DL, DAG.
getVTList(MVT::Other), TableSetOps,
1279 CLI.CB->getCalledOperand()->getPointerAlignment(DAG.
getDataLayout()),
1285 if (CLI.IsTailCall) {
1288 return DAG.
getNode(WebAssemblyISD::RET_CALL,
DL, NodeTys, Ops);
1295 for (
size_t I = 0;
I <
Ins.size(); ++
I)
1302bool WebAssemblyTargetLowering::CanLowerReturn(
1310SDValue WebAssemblyTargetLowering::LowerReturn(
1316 "MVP WebAssembly can only return up to one value");
1318 fail(
DL, DAG,
"WebAssembly doesn't support non-C calling conventions");
1321 RetOps.append(OutVals.
begin(), OutVals.
end());
1322 Chain = DAG.
getNode(WebAssemblyISD::RETURN,
DL, MVT::Other, RetOps);
1328 assert(Out.
IsFixed &&
"non-fixed return value is not valid");
1330 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca results");
1332 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs results");
1334 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last results");
1340SDValue WebAssemblyTargetLowering::LowerFormalArguments(
1345 fail(
DL, DAG,
"WebAssembly doesn't support non-C calling conventions");
1354 bool HasSwiftErrorArg =
false;
1355 bool HasSwiftSelfArg =
false;
1357 HasSwiftSelfArg |=
In.Flags.isSwiftSelf();
1358 HasSwiftErrorArg |=
In.Flags.isSwiftError();
1359 if (
In.Flags.isInAlloca())
1360 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca arguments");
1361 if (
In.Flags.isNest())
1362 fail(
DL, DAG,
"WebAssembly hasn't implemented nest arguments");
1363 if (
In.Flags.isInConsecutiveRegs())
1364 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs arguments");
1365 if (
In.Flags.isInConsecutiveRegsLast())
1366 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last arguments");
1375 MFI->addParam(
In.VT);
1384 if (!HasSwiftSelfArg) {
1385 MFI->addParam(PtrVT);
1387 if (!HasSwiftErrorArg) {
1388 MFI->addParam(PtrVT);
1397 MFI->setVarargBufferVreg(VarargVreg);
1399 Chain,
DL, VarargVreg,
1400 DAG.
getNode(WebAssemblyISD::ARGUMENT,
DL, PtrVT,
1402 MFI->addParam(PtrVT);
1414 assert(MFI->getParams().size() == Params.
size() &&
1415 std::equal(MFI->getParams().begin(), MFI->getParams().end(),
1421void WebAssemblyTargetLowering::ReplaceNodeResults(
1423 switch (
N->getOpcode()) {
1437 "ReplaceNodeResults not implemented for this op for WebAssembly!");
1448 switch (
Op.getOpcode()) {
1453 return LowerFrameIndex(
Op, DAG);
1455 return LowerGlobalAddress(
Op, DAG);
1457 return LowerGlobalTLSAddress(
Op, DAG);
1459 return LowerExternalSymbol(
Op, DAG);
1461 return LowerJumpTable(
Op, DAG);
1463 return LowerBR_JT(
Op, DAG);
1465 return LowerVASTART(
Op, DAG);
1468 fail(
DL, DAG,
"WebAssembly hasn't implemented computed gotos");
1471 return LowerRETURNADDR(
Op, DAG);
1473 return LowerFRAMEADDR(
Op, DAG);
1475 return LowerCopyToReg(
Op, DAG);
1478 return LowerAccessVectorElement(
Op, DAG);
1482 return LowerIntrinsic(
Op, DAG);
1484 return LowerSIGN_EXTEND_INREG(
Op, DAG);
1487 return LowerEXTEND_VECTOR_INREG(
Op, DAG);
1489 return LowerBUILD_VECTOR(
Op, DAG);
1491 return LowerVECTOR_SHUFFLE(
Op, DAG);
1493 return LowerSETCC(
Op, DAG);
1497 return LowerShift(
Op, DAG);
1500 return LowerFP_TO_INT_SAT(
Op, DAG);
1502 return LowerLoad(
Op, DAG);
1504 return LowerStore(
Op, DAG);
1523 return std::nullopt;
1556 return DAG.
getNode(WebAssemblyISD::LOCAL_SET,
DL, Tys, Ops);
1561 "Encountered an unlowerable store to the wasm_var address space",
1577 "unexpected offset when loading from webassembly global",
false);
1588 "unexpected offset when loading from webassembly local",
false);
1595 assert(
Result->getNumValues() == 2 &&
"Loads must carry a chain!");
1601 "Encountered an unlowerable load from the wasm_var address space",
1610 if (isa<FrameIndexSDNode>(Src.getNode())) {
1618 Register Reg = cast<RegisterSDNode>(
Op.getOperand(1))->getReg();
1619 EVT VT = Src.getValueType();
1621 : WebAssembly::COPY_I64,
1624 return Op.getNode()->getNumValues() == 1
1635 int FI = cast<FrameIndexSDNode>(
Op)->getIndex();
1645 "Non-Emscripten WebAssembly hasn't implemented "
1646 "__builtin_return_address");
1653 unsigned Depth =
Op.getConstantOperandVal(0);
1654 MakeLibCallOptions CallOptions;
1655 return makeLibCall(DAG, RTLIB::RETURN_ADDRESS,
Op.getValueType(),
1656 {DAG.getConstant(Depth, DL, MVT::i32)}, CallOptions,
DL)
1665 if (
Op.getConstantOperandVal(0) > 0)
1669 EVT VT =
Op.getValueType();
1676WebAssemblyTargetLowering::LowerGlobalTLSAddress(
SDValue Op,
1679 const auto *GA = cast<GlobalAddressSDNode>(
Op);
1706 auto GlobalGet = PtrVT == MVT::i64 ? WebAssembly::GLOBAL_GET_I64
1707 : WebAssembly::GLOBAL_GET_I32;
1718 DAG.
getNode(WebAssemblyISD::WrapperREL,
DL, PtrVT, TLSOffset);
1725 EVT VT =
Op.getValueType();
1726 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1735 const auto *GA = cast<GlobalAddressSDNode>(
Op);
1736 EVT VT =
Op.getValueType();
1738 "Unexpected target flags on generic GlobalAddressSDNode");
1740 fail(
DL, DAG,
"Invalid address space for WebAssembly target");
1751 const char *BaseName;
1760 DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
1764 WebAssemblyISD::WrapperREL,
DL, VT,
1773 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1779WebAssemblyTargetLowering::LowerExternalSymbol(
SDValue Op,
1782 const auto *ES = cast<ExternalSymbolSDNode>(
Op);
1783 EVT VT =
Op.getValueType();
1784 assert(ES->getTargetFlags() == 0 &&
1785 "Unexpected target flags on generic ExternalSymbolSDNode");
1786 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1797 JT->getTargetFlags());
1804 const auto *
JT = cast<JumpTableSDNode>(
Op.getOperand(1));
1806 assert(
JT->getTargetFlags() == 0 &&
"WebAssembly doesn't set target flags");
1816 for (
auto *
MBB : MBBs)
1823 return DAG.
getNode(WebAssemblyISD::BR_TABLE,
DL, MVT::Other, Ops);
1832 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1835 MFI->getVarargBufferVreg(), PtrVT);
1836 return DAG.
getStore(
Op.getOperand(0),
DL, ArgN,
Op.getOperand(1),
1844 switch (
Op.getOpcode()) {
1847 IntNo =
Op.getConstantOperandVal(1);
1850 IntNo =
Op.getConstantOperandVal(0);
1861 case Intrinsic::wasm_lsda: {
1870 DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
1877 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
Node);
1880 case Intrinsic::wasm_shuffle: {
1884 Ops[OpIdx++] =
Op.getOperand(1);
1885 Ops[OpIdx++] =
Op.getOperand(2);
1886 while (OpIdx < 18) {
1887 const SDValue &MaskIdx =
Op.getOperand(OpIdx + 1);
1892 Ops[OpIdx++] = MaskIdx;
1895 return DAG.
getNode(WebAssemblyISD::SHUFFLE,
DL,
Op.getValueType(), Ops);
1901WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(
SDValue Op,
1915 const SDValue &Extract =
Op.getOperand(0);
1919 MVT ExtractedLaneT =
1920 cast<VTSDNode>(
Op.getOperand(1).getNode())->
getVT().getSimpleVT();
1923 if (ExtractedVecT == VecT)
1928 if (!isa<ConstantSDNode>(
Index))
1930 unsigned IndexVal =
Index->getAsZExtVal();
1944WebAssemblyTargetLowering::LowerEXTEND_VECTOR_INREG(
SDValue Op,
1947 EVT VT =
Op.getValueType();
1949 EVT SrcVT = Src.getValueType();
1956 "Unexpected extension factor.");
1959 if (Scale != 2 && Scale != 4 && Scale != 8)
1963 switch (
Op.getOpcode()) {
1965 Ext = WebAssemblyISD::EXTEND_LOW_U;
1968 Ext = WebAssemblyISD::EXTEND_LOW_S;
1973 while (Scale != 1) {
1976 .widenIntegerVectorElementType(*DAG.
getContext())
1977 .getHalfNumVectorElementsVT(*DAG.
getContext()),
1987 if (
Op.getValueType() != MVT::v2f64)
1991 unsigned &
Index) ->
bool {
1992 switch (
Op.getOpcode()) {
1994 Opcode = WebAssemblyISD::CONVERT_LOW_S;
1997 Opcode = WebAssemblyISD::CONVERT_LOW_U;
2000 Opcode = WebAssemblyISD::PROMOTE_LOW;
2006 auto ExtractVector =
Op.getOperand(0);
2010 if (!isa<ConstantSDNode>(ExtractVector.getOperand(1).getNode()))
2013 SrcVec = ExtractVector.getOperand(0);
2014 Index = ExtractVector.getConstantOperandVal(1);
2018 unsigned LHSOpcode, RHSOpcode, LHSIndex, RHSIndex;
2020 if (!GetConvertedLane(
Op.getOperand(0), LHSOpcode, LHSSrcVec, LHSIndex) ||
2021 !GetConvertedLane(
Op.getOperand(1), RHSOpcode, RHSSrcVec, RHSIndex))
2024 if (LHSOpcode != RHSOpcode)
2028 switch (LHSOpcode) {
2029 case WebAssemblyISD::CONVERT_LOW_S:
2030 case WebAssemblyISD::CONVERT_LOW_U:
2031 ExpectedSrcVT = MVT::v4i32;
2033 case WebAssemblyISD::PROMOTE_LOW:
2034 ExpectedSrcVT = MVT::v4f32;
2040 auto Src = LHSSrcVec;
2041 if (LHSIndex != 0 || RHSIndex != 1 || LHSSrcVec != RHSSrcVec) {
2044 ExpectedSrcVT,
DL, LHSSrcVec, RHSSrcVec,
2045 {
static_cast<int>(LHSIndex),
static_cast<int>(RHSIndex) + 4, -1, -1});
2047 return DAG.
getNode(LHSOpcode,
DL, MVT::v2f64, Src);
2056 const EVT VecT =
Op.getValueType();
2057 const EVT LaneT =
Op.getOperand(0).getValueType();
2059 bool CanSwizzle = VecT == MVT::v16i8;
2080 auto GetSwizzleSrcs = [](
size_t I,
const SDValue &Lane) {
2095 Index->getConstantOperandVal(1) !=
I)
2097 return std::make_pair(SwizzleSrc, SwizzleIndices);
2104 auto GetShuffleSrc = [&](
const SDValue &Lane) {
2107 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode()))
2109 if (Lane->getOperand(0).getValueType().getVectorNumElements() >
2115 using ValueEntry = std::pair<SDValue, size_t>;
2118 using SwizzleEntry = std::pair<std::pair<SDValue, SDValue>,
size_t>;
2121 using ShuffleEntry = std::pair<SDValue, size_t>;
2124 auto AddCount = [](
auto &Counts,
const auto &Val) {
2126 llvm::find_if(Counts, [&Val](
auto E) {
return E.first == Val; });
2127 if (CountIt == Counts.end()) {
2128 Counts.emplace_back(Val, 1);
2134 auto GetMostCommon = [](
auto &Counts) {
2137 assert(CommonIt != Counts.end() &&
"Unexpected all-undef build_vector");
2141 size_t NumConstantLanes = 0;
2144 for (
size_t I = 0;
I < Lanes; ++
I) {
2149 AddCount(SplatValueCounts, Lane);
2153 if (
auto ShuffleSrc = GetShuffleSrc(Lane))
2154 AddCount(ShuffleCounts, ShuffleSrc);
2156 auto SwizzleSrcs = GetSwizzleSrcs(
I, Lane);
2157 if (SwizzleSrcs.first)
2158 AddCount(SwizzleCounts, SwizzleSrcs);
2163 size_t NumSplatLanes;
2164 std::tie(SplatValue, NumSplatLanes) = GetMostCommon(SplatValueCounts);
2168 size_t NumSwizzleLanes = 0;
2169 if (SwizzleCounts.
size())
2170 std::forward_as_tuple(std::tie(SwizzleSrc, SwizzleIndices),
2171 NumSwizzleLanes) = GetMostCommon(SwizzleCounts);
2175 SDValue ShuffleSrc1, ShuffleSrc2;
2176 size_t NumShuffleLanes = 0;
2177 if (ShuffleCounts.
size()) {
2178 std::tie(ShuffleSrc1, NumShuffleLanes) = GetMostCommon(ShuffleCounts);
2180 [&](
const auto &Pair) {
return Pair.first == ShuffleSrc1; });
2182 if (ShuffleCounts.
size()) {
2183 size_t AdditionalShuffleLanes;
2184 std::tie(ShuffleSrc2, AdditionalShuffleLanes) =
2185 GetMostCommon(ShuffleCounts);
2186 NumShuffleLanes += AdditionalShuffleLanes;
2191 std::function<
bool(
size_t,
const SDValue &)> IsLaneConstructed;
2194 if (NumSwizzleLanes >= NumShuffleLanes &&
2195 NumSwizzleLanes >= NumConstantLanes && NumSwizzleLanes >= NumSplatLanes) {
2198 auto Swizzled = std::make_pair(SwizzleSrc, SwizzleIndices);
2199 IsLaneConstructed = [&, Swizzled](
size_t I,
const SDValue &Lane) {
2200 return Swizzled == GetSwizzleSrcs(
I, Lane);
2202 }
else if (NumShuffleLanes >= NumConstantLanes &&
2203 NumShuffleLanes >= NumSplatLanes) {
2213 assert(LaneSize > DestLaneSize);
2214 Scale1 = LaneSize / DestLaneSize;
2220 assert(LaneSize > DestLaneSize);
2221 Scale2 = LaneSize / DestLaneSize;
2226 assert(DestLaneCount <= 16);
2227 for (
size_t I = 0;
I < DestLaneCount; ++
I) {
2229 SDValue Src = GetShuffleSrc(Lane);
2230 if (Src == ShuffleSrc1) {
2232 }
else if (Src && Src == ShuffleSrc2) {
2240 IsLaneConstructed = [&](size_t,
const SDValue &Lane) {
2241 auto Src = GetShuffleSrc(Lane);
2242 return Src == ShuffleSrc1 || (Src && Src == ShuffleSrc2);
2244 }
else if (NumConstantLanes >= NumSplatLanes) {
2246 for (
const SDValue &Lane :
Op->op_values()) {
2254 auto *
Const = dyn_cast<ConstantSDNode>(Lane.
getNode());
2255 int64_t Val =
Const ?
Const->getSExtValue() : 0;
2257 assert((LaneBits == 64 || Val >= -(1ll << (LaneBits - 1))) &&
2258 "Unexpected out of bounds negative value");
2259 if (Const && LaneBits != 64 && Val > (1ll << (LaneBits - 1)) - 1) {
2261 auto NewVal = (((
uint64_t)Val & Mask) - (1ll << LaneBits)) &
Mask;
2279 IsLaneConstructed = [&SplatValue](
size_t _,
const SDValue &Lane) {
2280 return Lane == SplatValue;
2285 assert(IsLaneConstructed);
2288 for (
size_t I = 0;
I < Lanes; ++
I) {
2290 if (!Lane.
isUndef() && !IsLaneConstructed(
I, Lane))
2299WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(
SDValue Op,
2304 assert(
VecType.is128BitVector() &&
"Unexpected shuffle vector type");
2305 size_t LaneBytes =
VecType.getVectorElementType().getSizeInBits() / 8;
2310 Ops[OpIdx++] =
Op.getOperand(0);
2311 Ops[OpIdx++] =
Op.getOperand(1);
2314 for (
int M : Mask) {
2315 for (
size_t J = 0; J < LaneBytes; ++J) {
2324 return DAG.
getNode(WebAssemblyISD::SHUFFLE,
DL,
Op.getValueType(), Ops);
2332 assert(
Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
2337 auto MakeLane = [&](
unsigned I) {
2343 {MakeLane(0), MakeLane(1)});
2347WebAssemblyTargetLowering::LowerAccessVectorElement(
SDValue Op,
2351 if (isa<ConstantSDNode>(IdxNode)) {
2364 EVT LaneT =
Op.getSimpleValueType().getVectorElementType();
2366 if (LaneT.
bitsGE(MVT::i32))
2370 size_t NumLanes =
Op.getSimpleValueType().getVectorNumElements();
2372 unsigned ShiftOpcode =
Op.getOpcode();
2378 for (
size_t i = 0; i < NumLanes; ++i) {
2381 SDValue ShiftedValue = ShiftedElements[i];
2386 DAG.
getNode(ShiftOpcode,
DL, MVT::i32, ShiftedValue, MaskedShiftValue));
2396 assert(
Op.getSimpleValueType().isVector());
2398 uint64_t LaneBits =
Op.getValueType().getScalarSizeInBits();
2399 auto ShiftVal =
Op.getOperand(1);
2413 MaskVal == MaskBits)
2416 if (!isa<ConstantSDNode>(
RHS.getNode()))
2419 auto ConstantRHS = dyn_cast<ConstantSDNode>(
RHS.getNode());
2420 if (ConstantRHS && ConstantRHS->getAPIntValue() == MaskBits)
2428 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2434 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2439 switch (
Op.getOpcode()) {
2441 Opcode = WebAssemblyISD::VEC_SHL;
2444 Opcode = WebAssemblyISD::VEC_SHR_S;
2447 Opcode = WebAssemblyISD::VEC_SHR_U;
2453 return DAG.
getNode(Opcode,
DL,
Op.getValueType(),
Op.getOperand(0), ShiftVal);
2459 EVT ResT =
Op.getValueType();
2460 EVT SatVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
2462 if ((ResT == MVT::i32 || ResT == MVT::i64) &&
2463 (SatVT == MVT::i32 || SatVT == MVT::i64))
2466 if (ResT == MVT::v4i32 && SatVT == MVT::i32)
2477 auto &DAG = DCI.
DAG;
2478 auto Shuffle = cast<ShuffleVectorSDNode>(
N);
2484 SDValue Bitcast =
N->getOperand(0);
2487 if (!
N->getOperand(1).isUndef())
2489 SDValue CastOp = Bitcast.getOperand(0);
2491 EVT DstType = Bitcast.getValueType();
2496 SrcType,
SDLoc(
N), CastOp, DAG.
getUNDEF(SrcType), Shuffle->getMask());
2506 auto &DAG = DCI.
DAG;
2510 EVT InVT =
N->getOperand(0)->getValueType(0);
2511 EVT ResVT =
N->getValueType(0);
2513 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8))
2515 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8))
2528 auto &DAG = DCI.
DAG;
2534 auto Extract =
N->getOperand(0);
2538 auto *IndexNode = dyn_cast<ConstantSDNode>(Extract.
getOperand(1));
2539 if (IndexNode ==
nullptr)
2541 auto Index = IndexNode->getZExtValue();
2545 EVT ResVT =
N->getValueType(0);
2546 if (ResVT == MVT::v8i16) {
2548 Source.getValueType() != MVT::v16i8 || (
Index != 0 &&
Index != 8))
2550 }
else if (ResVT == MVT::v4i32) {
2552 Source.getValueType() != MVT::v8i16 || (
Index != 0 &&
Index != 4))
2554 }
else if (ResVT == MVT::v2i64) {
2556 Source.getValueType() != MVT::v4i32 || (
Index != 0 &&
Index != 2))
2563 bool IsLow =
Index == 0;
2565 unsigned Op = IsSext ? (IsLow ? WebAssemblyISD::EXTEND_LOW_S
2566 : WebAssemblyISD::EXTEND_HIGH_S)
2567 : (IsLow ? WebAssemblyISD::EXTEND_LOW_U
2568 : WebAssemblyISD::EXTEND_HIGH_U);
2575 auto &DAG = DCI.
DAG;
2577 auto GetWasmConversionOp = [](
unsigned Op) {
2580 return WebAssemblyISD::TRUNC_SAT_ZERO_S;
2582 return WebAssemblyISD::TRUNC_SAT_ZERO_U;
2584 return WebAssemblyISD::DEMOTE_ZERO;
2589 auto IsZeroSplat = [](
SDValue SplatVal) {
2590 auto *
Splat = dyn_cast<BuildVectorSDNode>(SplatVal.getNode());
2591 APInt SplatValue, SplatUndef;
2592 unsigned SplatBitSize;
2597 Splat->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2615 EVT ExpectedConversionType;
2618 switch (ConversionOp) {
2622 ExpectedConversionType = MVT::v2i32;
2626 ExpectedConversionType = MVT::v2f32;
2632 if (
N->getValueType(0) != ResVT)
2635 if (
Conversion.getValueType() != ExpectedConversionType)
2639 if (Source.getValueType() != MVT::v2f64)
2642 if (!IsZeroSplat(
N->getOperand(1)) ||
2643 N->getOperand(1).getValueType() != ExpectedConversionType)
2646 unsigned Op = GetWasmConversionOp(ConversionOp);
2662 auto ConversionOp =
N->getOpcode();
2663 switch (ConversionOp) {
2675 if (
N->getValueType(0) != ResVT)
2678 auto Concat =
N->getOperand(0);
2679 if (
Concat.getValueType() != MVT::v4f64)
2682 auto Source =
Concat.getOperand(0);
2683 if (Source.getValueType() != MVT::v2f64)
2686 if (!IsZeroSplat(
Concat.getOperand(1)) ||
2687 Concat.getOperand(1).getValueType() != MVT::v2f64)
2690 unsigned Op = GetWasmConversionOp(ConversionOp);
2696 const SDLoc &
DL,
unsigned VectorWidth) {
2704 unsigned ElemsPerChunk = VectorWidth / ElVT.
getSizeInBits();
2709 IdxVal &= ~(ElemsPerChunk - 1);
2714 Vec->
ops().slice(IdxVal, ElemsPerChunk));
2726 EVT SrcVT = In.getValueType();
2744 EVT InVT = MVT::i16, OutVT = MVT::i8;
2749 unsigned SubSizeInBits = SrcSizeInBits / 2;
2751 OutVT =
EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits());
2777 auto &DAG = DCI.
DAG;
2780 EVT InVT = In.getValueType();
2784 EVT OutVT =
N->getValueType(0);
2791 if (!((InSVT == MVT::i16 || InSVT == MVT::i32 || InSVT == MVT::i64) &&
2792 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.
is128BitVector()))
2804 auto &DAG = DCI.
DAG;
2807 EVT VT =
N->getValueType(0);
2808 EVT SrcVT = Src.getValueType();
2815 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2820 {DAG.getConstant(Intrinsic::wasm_bitmask, DL, MVT::i32),
2821 DAG.getSExtOrTrunc(N->getOperand(0), DL,
2822 SrcVT.changeVectorElementType(Width))}),
2831 auto &DAG = DCI.
DAG;
2837 EVT VT =
N->getValueType(0);
2851 EVT FromVT =
LHS->getOperand(0).getValueType();
2855 : Intrinsic::wasm_alltrue;
2857 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2863 {DAG.getConstant(Intrin, DL, MVT::i32),
2864 DAG.getSExtOrTrunc(LHS->getOperand(0), DL,
2865 FromVT.changeVectorElementType(Width))}),
2869 Ret = DAG.
getNOT(
DL, Ret, MVT::i1);
2879WebAssemblyTargetLowering::PerformDAGCombine(
SDNode *
N,
2880 DAGCombinerInfo &DCI)
const {
2881 switch (
N->getOpcode()) {
unsigned const MachineRegisterInfo * MRI
static SDValue performTruncateCombine(SDNode *N, SelectionDAG &DAG)
static SDValue performSETCCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg, SDValue Val={})
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
static unsigned NumFixedArgs
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachineBasicBlock * LowerFPToInt(MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode)
static bool callingConvSupported(CallingConv::ID CallConv)
static std::optional< unsigned > IsWebAssemblyLocal(SDValue Op, SelectionDAG &DAG)
static SDValue performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue unrollVectorShift(SDValue Op, SelectionDAG &DAG)
static MachineBasicBlock * LowerCallResults(MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB, const WebAssemblySubtarget *Subtarget, const TargetInstrInfo &TII)
static SDValue performVECTOR_SHUFFLECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue performVectorTruncZeroCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool IsWebAssemblyGlobal(SDValue Op)
static SDValue performVectorExtendToFPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instr...
static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG)
static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &DL, unsigned VectorWidth)
static SDValue performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG)
This file defines the interfaces that WebAssembly uses to lower LLVM code into a selection DAG.
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file declares the WebAssembly-specific subclass of TargetMachine.
This file contains the declaration of the WebAssembly-specific type parsing utility functions.
This file contains the declaration of the WebAssembly-specific utility functions.
static constexpr int Concat[]
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
Diagnostic information for unsupported feature in backend.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
FunctionType * getFunctionType() const
Returns the FunctionType for me.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
ThreadLocalMode getThreadLocalMode() const
Type * getValueType() const
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
Describe properties that are true of each instruction in the target description file.
static auto integer_fixedlen_vector_valuetypes()
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
bool isFixedLengthVector() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isOSEmscripten() const
Tests whether the OS is Emscripten.
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getDoubleTy(LLVMContext &C)
bool isFunctionTy() const
True if this is an instance of FunctionType.
static Type * getFloatTy(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
const Value * stripPointerCastsAndAliases() const
Strip off pointer casts, all-zero GEPs, address space casts, and aliases.
static std::optional< unsigned > getLocalForStackObject(MachineFunction &MF, int FrameIndex)
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Register getFrameRegister(const MachineFunction &MF) const override
const Triple & getTargetTriple() const
const WebAssemblyInstrInfo * getInstrInfo() const override
bool hasBulkMemory() const
const WebAssemblyRegisterInfo * getRegisterInfo() const override
bool hasReferenceTypes() const
bool hasNontrappingFPToInt() const
WebAssemblyTargetLowering(const TargetMachine &TM, const WebAssemblySubtarget &STI)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const override
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Swift
Calling convention for Swift.
@ PreserveMost
Used for runtime calls that preserves most registers.
@ CXX_FAST_TLS
Used for access functions.
@ WASM_EmscriptenInvoke
For emscripten __invoke_* functions.
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
bool match(Val *V, const Pattern &P)
cst_pred_ty< is_zero_int > m_ZeroInt()
Match an integer 0 or a vector with all elements equal to 0.
TwoOps_match< V1_t, V2_t, Instruction::ShuffleVector > m_Shuffle(const V1_t &v1, const V2_t &v2)
Matches ShuffleVectorInst independently of mask value.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
ThreeOps_match< Val_t, Elt_t, Idx_t, Instruction::InsertElement > m_InsertElt(const Val_t &Val, const Elt_t &Elt, const Idx_t &Idx)
Matches InsertElementInst.
MCSymbolWasm * getOrCreateFunctionTableSymbol(MCContext &Ctx, const WebAssemblySubtarget *Subtarget)
Returns the __indirect_function_table, for use in call_indirect and in function bitcasts.
@ WASM_ADDRESS_SPACE_EXTERNREF
@ WASM_ADDRESS_SPACE_FUNCREF
bool isWebAssemblyFuncrefType(const Type *Ty)
Return true if this is a WebAssembly Funcref Type.
bool isWebAssemblyTableType(const Type *Ty)
Return true if the table represents a WebAssembly table type.
MCSymbolWasm * getOrCreateFuncrefCallTableSymbol(MCContext &Ctx, const WebAssemblySubtarget *Subtarget)
Returns the __funcref_call_table, for use in funcref calls when lowered to table.set + call_indirect.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isValidAddressSpace(unsigned AS)
bool canLowerReturn(size_t ResultSize, const WebAssemblySubtarget *Subtarget)
Returns true if the function's return value(s) can be lowered directly, i.e., not indirectly via a po...
bool isWasmVarAddressSpace(unsigned AS)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
void computeSignatureVTs(const FunctionType *Ty, const Function *TargetFunc, const Function &ContextFunc, const TargetMachine &TM, SmallVectorImpl< MVT > &Params, SmallVectorImpl< MVT > &Results)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ And
Bitwise or logical AND of integers.
DWARFExpression::Operation Op
constexpr unsigned BitWidth
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
void computeLegalValueVTs(const WebAssemblyTargetLowering &TLI, LLVMContext &Ctx, const DataLayout &DL, Type *Ty, SmallVectorImpl< MVT > &ValueVTs)
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool is256BitVector() const
Return true if this is a 256-bit vector type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInConsecutiveRegs() const
Align getNonZeroOrigAlign() const
bool isSwiftError() const
unsigned getByValSize() const
bool isInConsecutiveRegsLast() const
Align getNonZeroByValAlign() const
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
bool IsFixed
IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
unsigned getBitWidth() const
Get the bit width of this value.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
bool isBeforeLegalize() const
Function object to check whether the second component of a container supported by std::get (like std:...