LLVM 18.0.0git
ARMFixupKinds.h
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1//===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
10#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
11
12#include "llvm/MC/MCFixup.h"
13
14namespace llvm {
15namespace ARM {
16enum Fixups {
17 // 12-bit PC relative relocation for symbol addresses
19
20 // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
22
23 // 10-bit PC relative relocation for symbol addresses used in
24 // LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
26 // 10-bit PC relative relocation for symbol addresses used in VFP instructions
27 // where the lower 2 bits are not encoded (so it's encoded as an 8-bit
28 // immediate).
30 // Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding
31 // of Thumb2 instructions.
33 // 9-bit PC relative relocation for symbol addresses used in VFP instructions
34 // where bit 0 not encoded (so it's encoded as an 8-bit immediate).
36 // Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
37 // of Thumb2 instructions.
39 // 12-bit immediate value.
41 // 10-bit PC relative relocation for symbol addresses where the lower 2 bits
42 // are not encoded (so it's encoded as an 8-bit immediate).
44 // 12-bit PC relative relocation for the ADR instruction.
46 // 12-bit PC relative relocation for the ADR instruction.
48 // 24-bit PC relative relocation for conditional branch instructions.
50 // 24-bit PC relative relocation for branch instructions. (unconditional)
52 // 20-bit PC relative relocation for Thumb2 direct uconditional branch
53 // instructions.
55 // 20-bit PC relative relocation for Thumb2 direct branch unconditional branch
56 // instructions.
58
59 // 12-bit fixup for Thumb B instructions.
61
62 // The following fixups handle the ARM BL instructions. These can be
63 // conditionalised; however, the ARM ELF ABI requires a different relocation
64 // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
65 // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
66 // no conditional version; R_ARM_JUMP24 would have to insert a veneer.
67 //
68 // MachO does not draw a distinction between the two cases, so it will treat
69 // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
70
71 // Fixup for unconditional ARM BL instructions.
73
74 // Fixup for ARM BL instructions with nontrivial conditionalisation.
76
77 // Fixup for ARM BLX instructions.
79
80 // Fixup for Thumb BL instructions.
82
83 // Fixup for Thumb BLX instructions.
85
86 // Fixup for Thumb branch instructions.
88
89 // Fixup for Thumb load/store from constant pool instrs.
91
92 // Fixup for Thumb conditional branching instructions.
94
95 // The next two are for the movt/movw pair
96 // the 16bit imm field are split into imm{15-12} and imm{11-0}
97 fixup_arm_movt_hi16, // :upper16:
98 fixup_arm_movw_lo16, // :lower16:
99 fixup_t2_movt_hi16, // :upper16:
100 fixup_t2_movw_lo16, // :lower16:
101
102 // Fixup for Thumb movs (enc T1) and adds (enc T2) 8-bit immediate field (7-0)
107
108 // Fixup for mod_imm
110
111 // Fixup for Thumb2 8-bit rotated operand
113
114 // Fixups for Branch Future.
122
123 // Marker
127}
128} // namespace llvm
129
130#endif
@ fixup_arm_thumb_br
Definition: ARMFixupKinds.h:60
@ fixup_thumb_adr_pcrel_10
Definition: ARMFixupKinds.h:43
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_adr_pcrel_12
Definition: ARMFixupKinds.h:45
@ fixup_arm_pcrel_10
Definition: ARMFixupKinds.h:29
@ fixup_arm_uncondbranch
Definition: ARMFixupKinds.h:51
@ fixup_arm_thumb_cb
Definition: ARMFixupKinds.h:87
@ fixup_arm_movw_lo16
Definition: ARMFixupKinds.h:98
@ fixup_t2_movt_hi16
Definition: ARMFixupKinds.h:99
@ fixup_t2_ldst_pcrel_12
Definition: ARMFixupKinds.h:21
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_ldst_abs_12
Definition: ARMFixupKinds.h:40
@ fixup_arm_pcrel_9
Definition: ARMFixupKinds.h:35
@ fixup_arm_movt_hi16
Definition: ARMFixupKinds.h:97
@ fixup_t2_pcrel_9
Definition: ARMFixupKinds.h:38
@ fixup_t2_pcrel_10
Definition: ARMFixupKinds.h:32
@ fixup_arm_thumb_blx
Definition: ARMFixupKinds.h:84
@ fixup_arm_thumb_cp
Definition: ARMFixupKinds.h:90
@ fixup_t2_uncondbranch
Definition: ARMFixupKinds.h:57
@ NumTargetFixupKinds
@ fixup_arm_uncondbl
Definition: ARMFixupKinds.h:72
@ fixup_arm_pcrel_10_unscaled
Definition: ARMFixupKinds.h:25
@ fixup_arm_thumb_bcc
Definition: ARMFixupKinds.h:93
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_t2_adr_pcrel_12
Definition: ARMFixupKinds.h:47
@ fixup_t2_condbranch
Definition: ARMFixupKinds.h:54
@ fixup_arm_condbl
Definition: ARMFixupKinds.h:75
@ fixup_arm_ldst_pcrel_12
Definition: ARMFixupKinds.h:18
@ fixup_arm_thumb_lower_8_15
@ LastTargetFixupKind
@ fixup_arm_thumb_bl
Definition: ARMFixupKinds.h:81
@ fixup_t2_movw_lo16
@ fixup_arm_condbranch
Definition: ARMFixupKinds.h:49
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ FirstTargetFixupKind
Definition: MCFixup.h:44