llvm::ARM Namespace Reference

Define some predicates that are used for node matching. More...

Namespaces
	EHABI
	WinEH

Classes
struct	ArchNames
struct	CpuNames
struct	ExtName
struct	FPUName

Enumerations
enum	ArchExtKind : uint64_t {   AEK_INVALID = 0, AEK_NONE = 1, AEK_CRC = 1 << 1, AEK_CRYPTO = 1 << 2,   AEK_FP = 1 << 3, AEK_HWDIVTHUMB = 1 << 4, AEK_HWDIVARM = 1 << 5, AEK_MP = 1 << 6,   AEK_SIMD = 1 << 7, AEK_SEC = 1 << 8, AEK_VIRT = 1 << 9, AEK_DSP = 1 << 10,   AEK_FP16 = 1 << 11, AEK_RAS = 1 << 12, AEK_DOTPROD = 1 << 13, AEK_SHA2 = 1 << 14,   AEK_AES = 1 << 15, AEK_FP16FML = 1 << 16, AEK_SB = 1 << 17, AEK_FP_DP = 1 << 18,   AEK_LOB = 1 << 19, AEK_BF16 = 1 << 20, AEK_I8MM = 1 << 21, AEK_CDECP0 = 1 << 22,   AEK_CDECP1 = 1 << 23, AEK_CDECP2 = 1 << 24, AEK_CDECP3 = 1 << 25, AEK_CDECP4 = 1 << 26,   AEK_CDECP5 = 1 << 27, AEK_CDECP6 = 1 << 28, AEK_CDECP7 = 1 << 29, AEK_OS = 1ULL << 59,   AEK_IWMMXT = 1ULL << 60, AEK_IWMMXT2 = 1ULL << 61, AEK_MAVERICK = 1ULL << 62, AEK_XSCALE = 1ULL << 63 }
enum	ArchKind { ArchKind::ARM_ARCH }
enum	FPUKind { FK_LAST }
enum	FPUVersion {   FPUVersion::NONE, FPUVersion::VFPV2, FPUVersion::VFPV3, FPUVersion::VFPV3_FP16,   FPUVersion::VFPV4, FPUVersion::VFPV5, FPUVersion::VFPV5_FULLFP16 }
enum	FPURestriction { FPURestriction::None = 0, FPURestriction::D16, FPURestriction::SP_D16 }
enum	NeonSupportLevel { NeonSupportLevel::None = 0, NeonSupportLevel::Neon, NeonSupportLevel::Crypto }
enum	ISAKind { ISAKind::INVALID = 0, ISAKind::ARM, ISAKind::THUMB, ISAKind::AARCH64 }
enum	EndianKind { EndianKind::INVALID = 0, EndianKind::LITTLE, EndianKind::BIG }
enum	ProfileKind { ProfileKind::INVALID = 0, ProfileKind::A, ProfileKind::R, ProfileKind::M }
enum	DW_ISA { DW_ISA_ARM_thumb = 1, DW_ISA_ARM_arm = 2 }
enum	Rounding {   RN = 0, RP = 1, RM = 2, RZ = 3,   rmMask = 3 }
	Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR. More...
enum	PartialMappingIdx { PMI_GPR, PMI_SPR, PMI_DPR, PMI_Min = PMI_GPR }
enum	ValueMappingIdx { InvalidIdx = 0, GPR3OpsIdx = 1, SPR3OpsIdx = 4, DPR3OpsIdx = 7 }
enum	Fixups {   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind, fixup_t2_ldst_pcrel_12, fixup_arm_pcrel_10_unscaled, fixup_arm_pcrel_10,   fixup_t2_pcrel_10, fixup_arm_pcrel_9, fixup_t2_pcrel_9, fixup_arm_ldst_abs_12,   fixup_thumb_adr_pcrel_10, fixup_arm_adr_pcrel_12, fixup_t2_adr_pcrel_12, fixup_arm_condbranch,   fixup_arm_uncondbranch, fixup_t2_condbranch, fixup_t2_uncondbranch, fixup_arm_thumb_br,   fixup_arm_uncondbl, fixup_arm_condbl, fixup_arm_blx, fixup_arm_thumb_bl,   fixup_arm_thumb_blx, fixup_arm_thumb_cb, fixup_arm_thumb_cp, fixup_arm_thumb_bcc,   fixup_arm_movt_hi16, fixup_arm_movw_lo16, fixup_t2_movt_hi16, fixup_t2_movw_lo16,   fixup_arm_mod_imm, fixup_t2_so_imm, fixup_bf_branch, fixup_bf_target,   fixup_bfl_target, fixup_bfc_target, fixup_bfcsel_else_target, fixup_wls,   fixup_le, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	OperandType { OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET, OPERAND_VPRED_N }
enum	PredBlockMask {   PredBlockMask::T = 0b1000, PredBlockMask::TT = 0b0100, PredBlockMask::TE = 0b1100, PredBlockMask::TTT = 0b0010,   PredBlockMask::TTE = 0b0110, PredBlockMask::TEE = 0b1110, PredBlockMask::TET = 0b1010, PredBlockMask::TTTT = 0b0001,   PredBlockMask::TTTE = 0b0011, PredBlockMask::TTEE = 0b0111, PredBlockMask::TTET = 0b0101, PredBlockMask::TEEE = 0b1111,   PredBlockMask::TEET = 0b1101, PredBlockMask::TETT = 0b1001, PredBlockMask::TETE = 0b1011 }
	Mask values for IT and VPT Blocks, to be used by MCOperands. More...

Functions
StringRef	getFPUName (unsigned FPUKind)
FPUVersion	getFPUVersion (unsigned FPUKind)
NeonSupportLevel	getFPUNeonSupportLevel (unsigned FPUKind)
FPURestriction	getFPURestriction (unsigned FPUKind)
bool	getFPUFeatures (unsigned FPUKind, std::vector< StringRef > &Features)
bool	getHWDivFeatures (uint64_t HWDivKind, std::vector< StringRef > &Features)
bool	getExtensionFeatures (uint64_t Extensions, std::vector< StringRef > &Features)
StringRef	getArchName (ArchKind AK)
unsigned	getArchAttr (ArchKind AK)
StringRef	getCPUAttr (ArchKind AK)
StringRef	getSubArch (ArchKind AK)
StringRef	getArchExtName (uint64_t ArchExtKind)
StringRef	getArchExtFeature (StringRef ArchExt)
bool	appendArchExtFeatures (StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, unsigned &ArgFPUKind)
unsigned	getDefaultFPU (StringRef CPU, ArchKind AK)
uint64_t	getDefaultExtensions (StringRef CPU, ArchKind AK)
StringRef	getDefaultCPU (StringRef Arch)
StringRef	getCanonicalArchName (StringRef Arch)
StringRef	getFPUSynonym (StringRef FPU)
StringRef	getArchSynonym (StringRef Arch)
uint64_t	parseHWDiv (StringRef HWDiv)
unsigned	parseFPU (StringRef FPU)
ArchKind	parseArch (StringRef Arch)
uint64_t	parseArchExt (StringRef ArchExt)
ArchKind	parseCPUArch (StringRef CPU)
ISAKind	parseArchISA (StringRef Arch)
EndianKind	parseArchEndian (StringRef Arch)
ProfileKind	parseArchProfile (StringRef Arch)
unsigned	parseArchVersion (StringRef Arch)
void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values)
StringRef	computeDefaultTargetABI (const Triple &TT, StringRef CPU)
bool	isBitFieldInvertedMask (unsigned v)
FastISel *	createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
static bool	checkPartMapping (const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)
static void	checkPartialMappings ()
static bool	checkValueMapping (const RegisterBankInfo::ValueMapping &VM, RegisterBankInfo::PartialMapping *BreakDown)
static void	checkValueMappings ()
bool	isVpred (OperandType op)
bool	isVpred (uint8_t op)
bool	isCDECoproc (size_t Coproc, const MCSubtargetInfo &STI)

Variables
const ExtName	ARCHExtNames []
struct {
const char *   llvm::ARM::NameCStr
size_t   llvm::ARM::NameLength
uint64_t   llvm::ARM::ID
}	HWDivNames []
const CpuNames< ArchKind >	CPUNames []
static const FPUName	FPUNames []
static const ArchNames< ArchKind >	ARCHNames []
const unsigned	RoundingBitsPos = 22
RegisterBankInfo::PartialMapping	PartMappings []
RegisterBankInfo::ValueMapping	ValueMappings []

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

ArchExtKind

enum llvm::ARM::ArchExtKind : uint64_t

Enumerator
AEK_INVALID
AEK_NONE
AEK_CRC
AEK_CRYPTO
AEK_FP
AEK_HWDIVTHUMB
AEK_HWDIVARM
AEK_MP
AEK_SIMD
AEK_SEC
AEK_VIRT
AEK_DSP
AEK_FP16
AEK_RAS
AEK_DOTPROD
AEK_SHA2
AEK_AES
AEK_FP16FML
AEK_SB
AEK_FP_DP
AEK_LOB
AEK_BF16
AEK_I8MM
AEK_CDECP0
AEK_CDECP1
AEK_CDECP2
AEK_CDECP3
AEK_CDECP4
AEK_CDECP5
AEK_CDECP6
AEK_CDECP7
AEK_OS
AEK_IWMMXT
AEK_IWMMXT2
AEK_MAVERICK
AEK_XSCALE

Definition at line 30 of file ARMTargetParser.h.

ArchKind

enum llvm::ARM::ArchKind

strong

Enumerator
ARM_ARCH

Definition at line 104 of file ARMTargetParser.h.

DW_ISA

enum llvm::ARM::DW_ISA

Enumerator
DW_ISA_ARM_thumb
DW_ISA_ARM_arm

Definition at line 25 of file ARMAsmPrinter.h.

EndianKind

enum llvm::ARM::EndianKind

strong

Enumerator
INVALID
LITTLE
BIG

Definition at line 167 of file ARMTargetParser.h.

Fixups

enum llvm::ARM::Fixups

Enumerator
fixup_arm_ldst_pcrel_12
fixup_t2_ldst_pcrel_12
fixup_arm_pcrel_10_unscaled
fixup_arm_pcrel_10
fixup_t2_pcrel_10
fixup_arm_pcrel_9
fixup_t2_pcrel_9
fixup_arm_ldst_abs_12
fixup_thumb_adr_pcrel_10
fixup_arm_adr_pcrel_12
fixup_t2_adr_pcrel_12
fixup_arm_condbranch
fixup_arm_uncondbranch
fixup_t2_condbranch
fixup_t2_uncondbranch
fixup_arm_thumb_br
fixup_arm_uncondbl
fixup_arm_condbl
fixup_arm_blx
fixup_arm_thumb_bl
fixup_arm_thumb_blx
fixup_arm_thumb_cb
fixup_arm_thumb_cp
fixup_arm_thumb_bcc
fixup_arm_movt_hi16
fixup_arm_movw_lo16
fixup_t2_movt_hi16
fixup_t2_movw_lo16
fixup_arm_mod_imm
fixup_t2_so_imm
fixup_bf_branch
fixup_bf_target
fixup_bfl_target
fixup_bfc_target
fixup_bfcsel_else_target
fixup_wls
fixup_le
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file ARMFixupKinds.h.

FPUKind

enum llvm::ARM::FPUKind

Enumerator
FK_LAST

Definition at line 131 of file ARMTargetParser.h.

FPURestriction

enum llvm::ARM::FPURestriction

strong

Enumerator
None	No restriction.
D16	Only 16 D registers.
SP_D16	Only single-precision instructions, with 16 D registers.

Definition at line 149 of file ARMTargetParser.h.

FPUVersion

enum llvm::ARM::FPUVersion

strong

Enumerator
NONE
VFPV2
VFPV3
VFPV3_FP16
VFPV4
VFPV5
VFPV5_FULLFP16

Definition at line 138 of file ARMTargetParser.h.

ISAKind

enum llvm::ARM::ISAKind

strong

Enumerator
INVALID
ARM
THUMB
AARCH64

Definition at line 163 of file ARMTargetParser.h.

NeonSupportLevel

enum llvm::ARM::NeonSupportLevel

strong

Enumerator
None	No Neon.
Neon	Neon.
Crypto	Neon with Crypto.

Definition at line 156 of file ARMTargetParser.h.

OperandType

enum llvm::ARM::OperandType

Enumerator
OPERAND_VPRED_R
OPERAND_VPRED_N

Definition at line 118 of file ARMMCTargetDesc.h.

PartialMappingIdx

enum llvm::ARM::PartialMappingIdx

Enumerator
PMI_GPR
PMI_SPR
PMI_DPR
PMI_Min

Definition at line 31 of file ARMRegisterBankInfo.cpp.

PredBlockMask

enum llvm::ARM::PredBlockMask

strong

Mask values for IT and VPT Blocks, to be used by MCOperands.

Note that this is different from the "real" encoding used by the instructions. In this encoding, the lowest set bit indicates the end of the encoding, and above that, "1" indicates an else, while "0" indicates a then. Tx = x100 Txy = xy10 Txyz = xyz1

Enumerator
T
TT
TE
TTT
TTE
TEE
TET
TTTT
TTTE
TTEE
TTET
TEEE
TEET
TETT
TETE

Definition at line 105 of file ARMBaseInfo.h.

ProfileKind

enum llvm::ARM::ProfileKind

strong

Enumerator
INVALID
A
R
M

Definition at line 170 of file ARMTargetParser.h.

Rounding

enum llvm::ARM::Rounding

Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.

Enumerator
RN
RP
RM
RZ
rmMask

Definition at line 367 of file ARMISelLowering.h.

ValueMappingIdx

enum llvm::ARM::ValueMappingIdx

Enumerator
InvalidIdx
GPR3OpsIdx
SPR3OpsIdx
DPR3OpsIdx

Definition at line 68 of file ARMRegisterBankInfo.cpp.

Function Documentation

appendArchExtFeatures()

bool llvm::ARM::appendArchExtFeatures	(	StringRef	CPU,
		ARM::ArchKind	AK,
		StringRef	ArchExt,
		std::vector< StringRef > &	Features,
		unsigned &	ArgFPUKind
	)

Definition at line 499 of file ARMTargetParser.cpp.

References llvm::AArch64::AEK_INVALID, ARCHExtNames, findDoublePrecisionFPU(), llvm::FK_NONE, llvm::AArch64::getDefaultFPU(), getFPUFeatures(), llvm::AArch64::parseArchExt(), and stripNegationPrefix().

checkPartialMappings()

static void llvm::ARM::checkPartialMappings ( )

static

Definition at line 55 of file ARMRegisterBankInfo.cpp.

References assert(), checkPartMapping(), PartMappings, PMI_DPR, PMI_GPR, PMI_Min, and PMI_SPR.

Referenced by llvm::ARMRegisterBankInfo::ARMRegisterBankInfo().

checkPartMapping()

static bool llvm::ARM::checkPartMapping ( const RegisterBankInfo::PartialMapping &  PM, unsigned  Start, unsigned  Length, unsigned  RegBankID  )

static

Definition at line 48 of file ARMRegisterBankInfo.cpp.

Referenced by checkPartialMappings().

checkValueMapping()

static bool llvm::ARM::checkValueMapping ( const RegisterBankInfo::ValueMapping &  VM, RegisterBankInfo::PartialMapping *  BreakDown  )

static

Definition at line 92 of file ARMRegisterBankInfo.cpp.

References llvm::RegisterBankInfo::ValueMapping::BreakDown, and llvm::RegisterBankInfo::ValueMapping::NumBreakDowns.

Referenced by checkValueMappings().

checkValueMappings()

static void llvm::ARM::checkValueMappings ( )

static

Definition at line 97 of file ARMRegisterBankInfo.cpp.

References assert(), checkValueMapping(), DPR3OpsIdx, GPR3OpsIdx, PartMappings, PMI_DPR, PMI_GPR, PMI_Min, PMI_SPR, SPR3OpsIdx, and ValueMappings.

Referenced by llvm::ARMRegisterBankInfo::ARMRegisterBankInfo().

computeDefaultTargetABI()

StringRef llvm::ARM::computeDefaultTargetABI	(	const Triple &	TT,
		StringRef	CPU
	)

Definition at line 590 of file ARMTargetParser.cpp.

References llvm::Triple::Android, llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::StringRef::empty(), llvm::AArch64::getArchName(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, M, llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, parseArchProfile(), llvm::AArch64::parseCPUArch(), TT, and llvm::Triple::UnknownOS.

Referenced by computeTargetABI().

createFastISel()

FastISel * llvm::ARM::createFastISel	(	FunctionLoweringInfo &	funcInfo,
		const TargetLibraryInfo *	libInfo
	)

Definition at line 3076 of file ARMFastISel.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::FunctionLoweringInfo::MF, and llvm::ARMSubtarget::useFastISel().

Referenced by llvm::ARMTargetLowering::createFastISel().

fillValidCPUArchList()

void llvm::ARM::fillValidCPUArchList

(

SmallVectorImpl< StringRef > &

Values

)

Definition at line 583 of file ARMTargetParser.cpp.

References CPUNames.

getArchAttr()

unsigned llvm::ARM::getArchAttr

(

ARM::ArchKind

AK

)

Definition at line 440 of file ARMTargetParser.cpp.

References ARCHNames.

getArchExtFeature()

StringRef llvm::ARM::getArchExtFeature

(

StringRef

ArchExt

)

Definition at line 460 of file ARMTargetParser.cpp.

References ARCHExtNames, and stripNegationPrefix().

getArchExtName()

StringRef llvm::ARM::getArchExtName

(

uint64_t

ArchExtKind

)

Definition at line 444 of file ARMTargetParser.cpp.

References ARCHExtNames.

getArchName()

StringRef llvm::ARM::getArchName

(

ARM::ArchKind

AK

)

Definition at line 428 of file ARMTargetParser.cpp.

References ARCHNames, and getName().

Referenced by llvm::ARM_MC::ParseARMTriple().

getArchSynonym()

StringRef llvm::ARM::getArchSynonym

(

StringRef

Arch

)

Definition at line 140 of file ARMTargetParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Cases(), and llvm::StringSwitch< T, R >::Default().

Referenced by llvm::AArch64::parseArch(), and parseArch().

getCanonicalArchName()

StringRef llvm::ARM::getCanonicalArchName

(

StringRef

Arch

)

Definition at line 279 of file ARMTargetParser.cpp.

References llvm::StringRef::npos.

Referenced by llvm::Triple::getARMCPUForArch(), llvm::AArch64::parseArch(), parseArch(), parseArchProfile(), parseArchVersion(), parseARMArch(), and parseSubArch().

getCPUAttr()

StringRef llvm::ARM::getCPUAttr

(

ARM::ArchKind

AK

)

Definition at line 432 of file ARMTargetParser.cpp.

References ARCHNames, and llvm::AArch64::getCPUAttr().

getDefaultCPU()

StringRef llvm::ARM::getDefaultCPU

(

StringRef

Arch

)

Definition at line 543 of file ARMTargetParser.cpp.

References CPUNames, and parseArch().

Referenced by llvm::Triple::getARMCPUForArch().

getDefaultExtensions()

uint64_t llvm::ARM::getDefaultExtensions	(	StringRef	CPU,
		ARM::ArchKind	AK
	)

Definition at line 380 of file ARMTargetParser.cpp.

References AEK_INVALID, ARCHNames, and llvm::StringSwitch< T, R >::Default().

getDefaultFPU()

unsigned llvm::ARM::getDefaultFPU	(	StringRef	CPU,
		ARM::ArchKind	AK
	)

Definition at line 369 of file ARMTargetParser.cpp.

References ARCHNames, llvm::StringSwitch< T, R >::Default(), and llvm::RISCV::FK_INVALID.

getExtensionFeatures()

bool llvm::ARM::getExtensionFeatures	(	uint64_t	Extensions,
		std::vector< StringRef > &	Features
	)

Definition at line 412 of file ARMTargetParser.cpp.

References llvm::AArch64::AEK_INVALID, ARCHExtNames, and getHWDivFeatures().

getFPUFeatures()

bool llvm::ARM::getFPUFeatures	(	unsigned	FPUKind,
		std::vector< StringRef > &	Features
	)

Definition at line 167 of file ARMTargetParser.cpp.

References llvm::RISCV::FK_INVALID, FK_LAST, FPUNames, Info, llvm::None, and llvm::ARM::FPUName::Restriction.

Referenced by appendArchExtFeatures().

getFPUName()

StringRef llvm::ARM::getFPUName

(

unsigned

FPUKind

)

Definition at line 351 of file ARMTargetParser.cpp.

References FK_LAST, FPUNames, and llvm::ARM::FPUName::getName().

getFPUNeonSupportLevel()

ARM::NeonSupportLevel llvm::ARM::getFPUNeonSupportLevel

(

unsigned

FPUKind

)

Definition at line 269 of file ARMTargetParser.cpp.

References FK_LAST, FPUNames, llvm::ARM::FPUName::NeonSupport, and llvm::None.

getFPURestriction()

ARM::FPURestriction llvm::ARM::getFPURestriction

(

unsigned

FPUKind

)

Definition at line 363 of file ARMTargetParser.cpp.

References FK_LAST, FPUNames, llvm::None, and llvm::ARM::FPUName::Restriction.

getFPUSynonym()

StringRef llvm::ARM::getFPUSynonym

(

StringRef

FPU

)

Definition at line 334 of file ARMTargetParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Cases(), and llvm::StringSwitch< T, R >::Default().

Referenced by parseFPU().

getFPUVersion()

ARM::FPUVersion llvm::ARM::getFPUVersion

(

unsigned

FPUKind

)

Definition at line 357 of file ARMTargetParser.cpp.

References FK_LAST, FPUNames, llvm::ARM::FPUName::FPUVer, and llvm::NONE.

getHWDivFeatures()

bool llvm::ARM::getHWDivFeatures	(	uint64_t	HWDivKind,
		std::vector< StringRef > &	Features
	)

Definition at line 393 of file ARMTargetParser.cpp.

References AEK_HWDIVARM, AEK_HWDIVTHUMB, and llvm::AArch64::AEK_INVALID.

Referenced by getExtensionFeatures().

getSubArch()

StringRef llvm::ARM::getSubArch

(

ARM::ArchKind

AK

)

Definition at line 436 of file ARMTargetParser.cpp.

References ARCHNames, and llvm::AArch64::getSubArch().

isBitFieldInvertedMask()

bool llvm::ARM::isBitFieldInvertedMask

(

unsigned

v

)

Definition at line 19871 of file ARMISelLowering.cpp.

References llvm::isShiftedMask_32().

Referenced by PerformORCombineToBFI().

isCDECoproc()

bool llvm::ARM::isCDECoproc	(	size_t	Coproc,
		const MCSubtargetInfo &	STI
	)

Definition at line 452 of file ARMMCTargetDesc.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

isVpred() [1/2]

bool llvm::ARM::isVpred ( OperandType  op )

inline

Definition at line 122 of file ARMMCTargetDesc.h.

References op, OPERAND_VPRED_N, and OPERAND_VPRED_R.

Referenced by findFirstVectorPredOperandIdx(), llvm::findFirstVPTPredOperandIdx(), isVectorPredicable(), and isVpred().

isVpred() [2/2]

bool llvm::ARM::isVpred ( uint8_t  op )

inline

Definition at line 125 of file ARMMCTargetDesc.h.

References isVpred(), and op.

parseArch()

ARM::ArchKind llvm::ARM::parseArch

(

StringRef

Arch

)

Definition at line 28 of file ARMTargetParser.cpp.

References A, ARCHNames, getArchSynonym(), and getCanonicalArchName().

Referenced by getARMSubType(), llvm::ARM_MC::ParseARMTriple(), and parseSubArch().

parseArchEndian()

ARM::EndianKind llvm::ARM::parseArchEndian

(

StringRef

Arch

)

Definition at line 232 of file ARMTargetParser.cpp.

References llvm::StringRef::endswith(), and llvm::StringRef::startswith().

Referenced by parseARMArch().

parseArchExt()

uint64_t llvm::ARM::parseArchExt

(

StringRef

ArchExt

)

Definition at line 567 of file ARMTargetParser.cpp.

References llvm::AArch64::AEK_INVALID, and ARCHExtNames.

parseArchISA()

ARM::ISAKind llvm::ARM::parseArchISA

(

StringRef

Arch

)

Definition at line 251 of file ARMTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default(), and llvm::StringSwitch< T, R >::StartsWith().

Referenced by parseARMArch().

parseArchProfile()

ARM::ProfileKind llvm::ARM::parseArchProfile

(

StringRef

Arch

)

Definition at line 92 of file ARMTargetParser.cpp.

References A, getCanonicalArchName(), llvm_unreachable, M, parseArch(), and llvm::RISCVFenceField::R.

Referenced by computeDefaultTargetABI(), and parseARMArch().

parseArchVersion()

unsigned llvm::ARM::parseArchVersion

(

StringRef

Arch

)

Definition at line 39 of file ARMTargetParser.cpp.

References getCanonicalArchName(), llvm_unreachable, and parseArch().

Referenced by llvm::Triple::getARMCPUForArch(), and parseARMArch().

parseCPUArch()

ARM::ArchKind llvm::ARM::parseCPUArch

(

StringRef

CPU

)

Definition at line 575 of file ARMTargetParser.cpp.

References CPUNames.

parseFPU()

unsigned llvm::ARM::parseFPU

(

StringRef

FPU

)

Definition at line 260 of file ARMTargetParser.cpp.

References F, llvm::RISCV::FK_INVALID, FPUNames, and getFPUSynonym().

parseHWDiv()

uint64_t llvm::ARM::parseHWDiv

(

StringRef

HWDiv

)

Definition at line 558 of file ARMTargetParser.cpp.

References llvm::AArch64::AEK_INVALID, D, getHWDivSynonym(), and HWDivNames.

Variable Documentation

ARCHExtNames

const ExtName llvm::ARM::ARCHExtNames[]

Initial value:

= {
#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       
 
}

Definition at line 83 of file ARMTargetParser.h.

Referenced by appendArchExtFeatures(), getArchExtFeature(), getArchExtName(), getExtensionFeatures(), and parseArchExt().

ARCHNames

const ArchNames<ArchKind> llvm::ARM::ARCHNames[]

static

Initial value:

= {
                 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,            ARCH_BASE_EXT)                                                
 
 
 
 
 
 
 
}

Definition at line 223 of file ARMTargetParser.h.

Referenced by getArchAttr(), getArchName(), getCPUAttr(), getDefaultExtensions(), getDefaultFPU(), getSubArch(), and parseArch().

CPUNames

const CpuNames<ArchKind> llvm::ARM::CPUNames[]

Initial value:

= {
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           
 
}

Definition at line 124 of file ARMTargetParser.h.

Referenced by fillValidCPUArchList(), getDefaultCPU(), and parseCPUArch().

FPUNames

const FPUName llvm::ARM::FPUNames[]

static

Initial value:

= {
#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                
 
 
}

Definition at line 188 of file ARMTargetParser.h.

Referenced by findDoublePrecisionFPU(), getFPUFeatures(), getFPUName(), getFPUNeonSupportLevel(), getFPURestriction(), getFPUVersion(), and parseFPU().

HWDivNames

const { ... } llvm::ARM::HWDivNames[]

Initial value:

= {
#define ARM_HW_DIV_NAME(NAME, ID) 
}

Referenced by parseHWDiv().

ID

uint64_t llvm::ARM::ID

Definition at line 95 of file ARMTargetParser.h.

NameCStr

const char* llvm::ARM::NameCStr

Definition at line 93 of file ARMTargetParser.h.

NameLength

size_t llvm::ARM::NameLength

Definition at line 94 of file ARMTargetParser.h.

Referenced by LLVMIntrinsicCopyOverloadedName(), LLVMIntrinsicCopyOverloadedName2(), and LLVMIntrinsicGetName().

PartMappings

RegisterBankInfo::PartialMapping llvm::ARM::PartMappings[]

Initial value:

{
    
    {0, 32, GPRRegBank},
    
    {0, 32, FPRRegBank},
    
    {0, 64, FPRRegBank},
}

Definition at line 38 of file ARMRegisterBankInfo.cpp.

Referenced by checkPartialMappings(), and checkValueMappings().

RoundingBitsPos

const unsigned llvm::ARM::RoundingBitsPos = 22

Definition at line 376 of file ARMISelLowering.h.

ValueMappings

RegisterBankInfo::ValueMapping llvm::ARM::ValueMappings[]

Initial value:

= {
    
    {nullptr, 0},
    
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    {&PartMappings[PMI_GPR - PMI_Min], 1},
    
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    {&PartMappings[PMI_SPR - PMI_Min], 1},
    
    {&PartMappings[PMI_DPR - PMI_Min], 1},
    {&PartMappings[PMI_DPR - PMI_Min], 1},
    {&PartMappings[PMI_DPR - PMI_Min], 1}}

Definition at line 75 of file ARMRegisterBankInfo.cpp.

Referenced by checkValueMappings(), and llvm::ARMRegisterBankInfo::getInstrMapping().