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15 #ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
16 #define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
22 namespace X86Disassembler {
25 #define modFromModRM(modRM) (((modRM) & 0xc0) >> 6)
26 #define regFromModRM(modRM) (((modRM) & 0x38) >> 3)
27 #define rmFromModRM(modRM) ((modRM) & 0x7)
28 #define scaleFromSIB(sib) (((sib) & 0xc0) >> 6)
29 #define indexFromSIB(sib) (((sib) & 0x38) >> 3)
30 #define baseFromSIB(sib) ((sib) & 0x7)
31 #define wFromREX(rex) (((rex) & 0x8) >> 3)
32 #define rFromREX(rex) (((rex) & 0x4) >> 2)
33 #define xFromREX(rex) (((rex) & 0x2) >> 1)
34 #define bFromREX(rex) ((rex) & 0x1)
36 #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
37 #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
38 #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
39 #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
40 #define mmmFromEVEX2of4(evex) ((evex) & 0x7)
41 #define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
42 #define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
43 #define ppFromEVEX3of4(evex) ((evex) & 0x3)
44 #define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
45 #define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
46 #define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
47 #define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
48 #define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
49 #define aaaFromEVEX4of4(evex) ((evex) & 0x7)
51 #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
52 #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
53 #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
54 #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
55 #define wFromVEX3of3(vex) (((vex) & 0x80) >> 7)
56 #define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3)
57 #define lFromVEX3of3(vex) (((vex) & 0x4) >> 2)
58 #define ppFromVEX3of3(vex) ((vex) & 0x3)
60 #define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7)
61 #define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3)
62 #define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
63 #define ppFromVEX2of2(vex) ((vex) & 0x3)
65 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
66 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
67 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
68 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
69 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
70 #define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
71 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
72 #define ppFromXOP3of3(xop) ((xop) & 0x3)
97 #define EA_BASES_16BIT \
133 #define EA_BASES_32BIT \
169 #define EA_BASES_64BIT \
327 #define REGS_MASK_PAIRS \
333 #define REGS_SEGMENT \
359 #define REGS_CONTROL \
388 #define ALL_EA_BASES \
393 #define ALL_SIB_BASES \
420 #define ENTRY(x) EA_BASE_##x,
423 #define ENTRY(x) EA_REG_##x,
435 #define ENTRY(x) SIB_INDEX_##x,
447 #define ENTRY(x) SIB_BASE_##x,
463 #define ENTRY(x) MODRM_REG_##x,
VectorExtensionType vectorExtensionType
EADisplacement
Possible displacement types for effective-address computations.
This is an optimization pass for GlobalISel generic memory operations.
Reg
All possible values of the reg field in the ModR/M byte.
SegmentOverride segmentOverride
VEXLeadingOpcodeByte
Possible values for the VEX.m-mmmm field.
uint8_t numImmediatesTranslated
The x86 internal instruction, which is produced by the decoder.
SIBIndex
All possible values of the SIB index field.
SIBBase
All possible values of the SIB base field.
llvm::ArrayRef< uint8_t > bytes
EABase
All possible values of the base field for effective-address computations, a.k.a.
const InstructionSpecifier * spec
uint8_t numImmediatesConsumed
ArrayRef< OperandSpecifier > operands
uint8_t displacementOffset
EADisplacement eaDisplacement
VEXPrefixCode
Possible values for the VEX.pp/EVEX.pp field.
DisassemblerMode
Decoding mode for the Intel disassembler.
SegmentOverride
All possible segment overrides.
The specification for how to extract and interpret a full instruction and its operands.
uint8_t vectorExtensionPrefix[4]