LLVM 19.0.0git
llvm::AArch64TargetLowering Member List

This is the complete list of members for llvm::AArch64TargetLowering, including all inherited members.

AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)llvm::AArch64TargetLoweringexplicit
ABS enum valuellvm::TargetLoweringBase
AddAnd enum valuellvm::TargetLoweringBase
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
aggressivelyPreferBuildVectorSources(EVT VecVT) constllvm::TargetLoweringBaseinlinevirtual
alignLoopsWithOptSize() constllvm::TargetLoweringBaseinlinevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) constllvm::TargetLoweringBasevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const overridellvm::AArch64TargetLoweringvirtual
allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast=nullptr) const overridellvm::AArch64TargetLoweringvirtual
allowTruncateForTailCall(Type *FromTy, Type *ToTy) constllvm::TargetLoweringBaseinlinevirtual
AndOrSETCCFoldKind enum namellvm::TargetLoweringBase
areJTsAllowed(const Function *Fn) constllvm::TargetLoweringBaseinlinevirtual
areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) constllvm::TargetLoweringBaseinlinevirtual
ArgListTy typedefllvm::TargetLoweringBase
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) constllvm::TargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
C_Address enum valuellvm::TargetLowering
C_Immediate enum valuellvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) constllvm::TargetLoweringBaseinlinevirtual
canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) constllvm::TargetLoweringBaseinlinevirtual
canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) constllvm::TargetLoweringvirtual
canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const overridellvm::AArch64TargetLoweringinlinevirtual
canOpTrap(unsigned Op, EVT VT) constllvm::TargetLoweringBasevirtual
CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) constllvm::AArch64TargetLowering
CCAssignFnForReturn(CallingConv::ID CC) constllvm::AArch64TargetLowering
changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, SDValue Chain, SDValue InGlue, unsigned Condition, SDValue PStateSM=SDValue()) constllvm::AArch64TargetLowering
checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) constllvm::TargetLoweringinlinevirtual
CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) constllvm::TargetLoweringvirtual
computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AArch64TargetLoweringvirtual
computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const overridellvm::AArch64TargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintGroup typedefllvm::TargetLowering
ConstraintPair typedefllvm::TargetLowering
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
convertSelectOfConstantsToMath(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
convertSetCCLogicToBitwiseLogic(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const overridellvm::AArch64TargetLoweringvirtual
createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const overridellvm::AArch64TargetLoweringvirtual
createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) constllvm::TargetLowering
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) constllvm::TargetLoweringBaseinlinevirtual
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const overridellvm::AArch64TargetLoweringvirtual
emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) constllvm::TargetLoweringBaseinlinevirtual
emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) constllvm::TargetLoweringBaseinlinevirtual
EmitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::AArch64TargetLowering
emitExpandAtomicRMW(AtomicRMWInst *AI) constllvm::TargetLoweringBaseinlinevirtual
EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) constllvm::AArch64TargetLowering
EmitFill(MachineInstr &MI, MachineBasicBlock *BB) constllvm::AArch64TargetLowering
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const overridellvm::AArch64TargetLoweringvirtual
EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const overridellvm::AArch64TargetLoweringvirtual
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const overridellvm::AArch64TargetLoweringvirtual
EmitLoweredCatchRet(MachineInstr &MI, MachineBasicBlock *BB) constllvm::AArch64TargetLowering
emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) constllvm::TargetLoweringinlinevirtual
emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const overridellvm::AArch64TargetLoweringvirtual
EmitTileLoad(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB) constllvm::AArch64TargetLowering
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
EmitZAInstr(unsigned Opc, unsigned BaseReg, MachineInstr &MI, MachineBasicBlock *BB, bool HasTile) constllvm::AArch64TargetLowering
EmitZero(MachineInstr &MI, MachineBasicBlock *BB) constllvm::AArch64TargetLowering
EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, bool Op0IsDef) constllvm::AArch64TargetLowering
enableAggressiveFMAFusion(EVT VT) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::enableAggressiveFMAFusion(LLT Ty) constllvm::TargetLoweringBaseinlinevirtual
Enabled enum valuellvm::TargetLoweringBase
enableExtLdPromotion() constllvm::TargetLoweringBaseinline
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
Expand enum valuellvm::TargetLoweringBase
expandABD(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) constllvm::TargetLowering
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandBITREVERSE(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandBSWAP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTLZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTPOP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTTZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandDIVREMByConstant(SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) constllvm::TargetLowering
expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandFunnelShift(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
ExpandInlineAsm(CallInst *) constllvm::TargetLoweringinlinevirtual
expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLowering
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) constllvm::TargetLowering
expandRoundInexactToOdd(EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLowering
expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) constllvm::TargetLowering
expandShlSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduce(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVectorSplice(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPBSWAP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTLZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTPOP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTTZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
fallBackToDAGISel(const Instruction &Inst) const overridellvm::AArch64TargetLoweringvirtual
findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) constllvm::TargetLoweringvirtual
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) constllvm::TargetLoweringBaseprotectedvirtual
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) constllvm::TargetLowering
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) constllvm::TargetLowering
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const overridellvm::AArch64TargetLoweringvirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const overridellvm::AArch64TargetLoweringvirtual
getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) constllvm::TargetLoweringBaseinlinevirtual
getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const overridellvm::AArch64TargetLoweringvirtual
getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) constllvm::TargetLoweringBase
getBooleanContents(bool isVec, bool isFloat) constllvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) constllvm::TargetLoweringBaseinline
getBypassSlowDivWidths() constllvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) constllvm::TargetLoweringBasevirtual
getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) constllvm::TargetLoweringinline
getClearCacheBuiltinName() constllvm::TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getCmpLibcallReturnType() constllvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
getConstraintPreferences(AsmOperandInfo &OpInfo) constllvm::TargetLowering
getCustomCtpopCost(EVT VT, ISD::CondCode Cond) constllvm::TargetLoweringBaseinlinevirtual
getCustomOperationAction(SDNode &Op) constllvm::TargetLoweringBaseinlinevirtual
getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) constllvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getExceptionPointerRegister(const Constant *PersonalityFn) const overridellvm::AArch64TargetLoweringinlinevirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) const overridellvm::AArch64TargetLoweringinlinevirtual
getExtendForAtomicCmpSwapArg() constllvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicOps() constllvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getFenceOperandTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinline
getFrameIndexTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getGatherAllAliasesMaxDepth() constllvm::TargetLoweringBaseinline
getIndexedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIRStackGuard(IRBuilderBase &IRB) const overridellvm::AArch64TargetLoweringvirtual
getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) constllvm::TargetLoweringBaseinlinevirtual
getJumpTableEncoding() constllvm::TargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) constllvm::TargetLoweringBase
getMaxAtomicSizeInBitsSupported() constllvm::TargetLoweringBaseinline
getMaxDivRemBitWidthSupported() constllvm::TargetLoweringBaseinline
getMaxExpandSizeMemcmp(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxGluedStoresPerMemcpy() constllvm::TargetLoweringBaseinlinevirtual
getMaximumJumpTableSize() constllvm::TargetLoweringBase
getMaxLargeFPConvertBitWidthSupported() constllvm::TargetLoweringBaseinline
getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) constllvm::TargetLoweringBasevirtual
getMaxStoresPerMemcpy(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() const overridellvm::AArch64TargetLoweringinlinevirtual
getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getMinCmpXchgSizeInBits() constllvm::TargetLoweringBaseinline
getMinFunctionAlignment() constllvm::TargetLoweringBaseinline
getMinimumJumpTableDensity(bool OptForSize) constllvm::TargetLoweringBase
getMinStackArgumentAlignment() constllvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) constllvm::TargetLoweringvirtual
getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) constllvm::TargetLoweringvirtual
getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, bool UseScalable) constllvm::AArch64TargetLowering
getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) constllvm::TargetLoweringBaseinlinevirtual
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
getOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getOptimalMemOpLLT(const MemOp &Op, const AttributeList &FuncAttributes) const overridellvm::AArch64TargetLoweringvirtual
getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const overridellvm::AArch64TargetLoweringvirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) constllvm::TargetLoweringvirtual
getPointerMemTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPointerTy(const DataLayout &DL, uint32_t AS=0) const overridellvm::AArch64TargetLoweringinlinevirtual
getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const overridellvm::AArch64TargetLoweringvirtual
getPreferredShiftAmountTy(LLT ShiftValueTy) constllvm::TargetLoweringBaseinlinevirtual
getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) constllvm::TargetLoweringBasevirtual
getPreferredVectorAction(MVT VT) const overridellvm::AArch64TargetLoweringvirtual
getPrefFunctionAlignment() constllvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML=nullptr) constllvm::TargetLoweringBasevirtual
getProgramPointerTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getPromotedVTForPredicate(EVT VT) constllvm::AArch64TargetLowering
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRedZoneSize(const Function &F) constllvm::AArch64TargetLoweringinline
getRegClassFor(MVT VT, bool isDivergent=false) constllvm::TargetLoweringBaseinlinevirtual
getRegisterType(MVT VT) constllvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
getRepRegClassCostFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRoundingControlRegisters() const overridellvm::AArch64TargetLoweringvirtual
getSafeStackPointerLocation(IRBuilderBase &IRB) const overridellvm::AArch64TargetLoweringvirtual
getScalarShiftAmountTy(const DataLayout &DL, EVT) const overridellvm::AArch64TargetLoweringvirtual
getSchedulingPreference() constllvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) constllvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) const overridellvm::AArch64TargetLoweringvirtual
getSDagStackGuard(const Module &M) const overridellvm::AArch64TargetLoweringvirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) constllvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getSSPStackGuardCheck(const Module &M) const overridellvm::AArch64TargetLoweringvirtual
getStackPointerRegisterToSaveRestore() constllvm::TargetLoweringBaseinline
getStackProbeSymbolName(const MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) constllvm::TargetLoweringBase
getStrictFPOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getTargetConstantFromLoad(LoadSDNode *LD) constllvm::TargetLoweringvirtual
getTargetMachine() constllvm::TargetLoweringBaseinline
getTargetMMOFlags(const Instruction &I) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::getTargetMMOFlags(const MemSDNode &Node) constllvm::TargetLoweringBaseinlinevirtual
getTargetNodeName(unsigned Opcode) const overridellvm::AArch64TargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const overridellvm::AArch64TargetLoweringvirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeAction(MVT VT) constllvm::TargetLoweringBaseinline
getTypeConversion(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBase
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) constllvm::TargetLoweringinlinevirtual
getTypeToExpandTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) constllvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getVaListSizeInBits(const DataLayout &DL) const overridellvm::AArch64TargetLoweringvirtual
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getValueTypeActions() constllvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) constllvm::TargetLowering
getVectorIdxTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) constllvm::TargetLowering
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBase
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const overridellvm::AArch64TargetLoweringvirtual
getVPExplicitVectorLengthTy() constllvm::TargetLoweringBaseinlinevirtual
HandleByVal(CCState *, unsigned &, Align) constllvm::TargetLoweringinlinevirtual
hasAndNot(SDValue Y) const overridellvm::AArch64TargetLoweringinlinevirtual
hasAndNotCompare(SDValue V) const overridellvm::AArch64TargetLoweringinlinevirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) constllvm::TargetLoweringBaseinline
hasBitTest(SDValue X, SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasExtractBitsInsn() constllvm::TargetLoweringBaseinline
hasFastEqualityCompare(unsigned NumBits) constllvm::TargetLoweringBaseinlinevirtual
hasInlineStackProbe(const MachineFunction &MF) const overridellvm::AArch64TargetLoweringvirtual
hasMultipleConditionRegisters() constllvm::TargetLoweringBaseinline
hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const overridellvm::AArch64TargetLoweringvirtual
hasStackProbeSymbol(const MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
hasStandaloneRem(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) constllvm::TargetLoweringBaseinline
hasVectorBlend() constllvm::TargetLoweringBaseinlinevirtual
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) constllvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
initializeSplitCSR(MachineBasicBlock *Entry) const overridellvm::AArch64TargetLoweringvirtual
insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const overridellvm::AArch64TargetLoweringvirtual
insertSSPDeclarations(Module &M) const overridellvm::AArch64TargetLoweringvirtual
InstructionOpcodeToISD(unsigned Opcode) constllvm::TargetLoweringBase
isAllActivePredicate(SelectionDAG &DAG, SDValue N) constllvm::AArch64TargetLowering
isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) constllvm::TargetLoweringBaseinline
isBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isCheapToSpeculateCtlz(Type *) const overridellvm::AArch64TargetLoweringinlinevirtual
isCheapToSpeculateCttz(Type *) const overridellvm::AArch64TargetLoweringinlinevirtual
isCommutativeBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const overridellvm::AArch64TargetLoweringvirtual
isComplexDeinterleavingSupported() const overridellvm::AArch64TargetLoweringvirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isConstFalseVal(SDValue N) constllvm::TargetLowering
isConstTrueVal(SDValue N) constllvm::TargetLowering
isCtlzFast() constllvm::TargetLoweringBaseinlinevirtual
isCtpopFast(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteXorWithShift(const SDNode *N) const overridellvm::AArch64TargetLoweringvirtual
IsDesirableToPromoteOp(SDValue, EVT &) constllvm::TargetLoweringinlinevirtual
isDesirableToPullExtFromShl(const MachineInstr &MI) const overridellvm::AArch64TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) constllvm::TargetLoweringinlinevirtual
isEqualityCmpFoldedWithSignedCmp() constllvm::TargetLoweringBaseinlinevirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) constllvm::TargetLowering
isExtFree(const Instruction *I) constllvm::TargetLoweringBaseinline
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const overridellvm::AArch64TargetLoweringvirtual
isExtractVecEltCheap(EVT VT, unsigned Index) constllvm::TargetLoweringBaseinlinevirtual
isFAbsFree(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isFMADLegal(const MachineInstr &MI, LLT Ty) constllvm::TargetLoweringBaseinlinevirtual
isFMADLegal(const SelectionDAG &DAG, const SDNode *N) constllvm::TargetLoweringBaseinlinevirtual
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) constllvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const overridellvm::AArch64TargetLoweringvirtual
isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) constllvm::TargetLoweringBasevirtual
isFsqrtCheap(SDValue X, SelectionDAG &DAG) constllvm::TargetLoweringBaseinlinevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) constllvm::TargetLoweringvirtual
isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) constllvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) constllvm::TargetLoweringinlinevirtual
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) constllvm::TargetLowering
isIntDivCheap(EVT VT, AttributeList Attr) const overridellvm::AArch64TargetLoweringvirtual
isJumpExpensive() constllvm::TargetLoweringBaseinline
isJumpTableRelative() constllvm::TargetLoweringBasevirtual
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) constllvm::TargetLoweringvirtual
isLegalAddImmediate(int64_t) const overridellvm::AArch64TargetLoweringvirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const overridellvm::AArch64TargetLoweringvirtual
isLegalAddScalableImmediate(int64_t) const overridellvm::AArch64TargetLoweringvirtual
isLegalICmpImmediate(int64_t) const overridellvm::AArch64TargetLoweringvirtual
isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, bool &UseScalable) constllvm::AArch64TargetLowering
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) constllvm::TargetLoweringBaseprotected
isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) constllvm::TargetLoweringBaseinlinevirtual
isLegalStoreImmediate(int64_t Value) constllvm::TargetLoweringBaseinlinevirtual
isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) constllvm::TargetLoweringBasevirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const overridellvm::AArch64TargetLoweringvirtual
isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const overridellvm::AArch64TargetLoweringvirtual
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) constllvm::TargetLoweringBaseinlinevirtual
isNarrowingProfitable(EVT SrcVT, EVT DestVT) constllvm::TargetLoweringBaseinlinevirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const overridellvm::AArch64TargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOpSuitableForLDPSTP(const Instruction *I) constllvm::AArch64TargetLowering
isOpSuitableForLSE128(const Instruction *I) constllvm::AArch64TargetLowering
isOpSuitableForRCPC3(const Instruction *I) constllvm::AArch64TargetLowering
isPositionIndependent() constllvm::TargetLowering
isPredictableSelectExpensive() constllvm::TargetLoweringBaseinline
isProfitableToCombineMinNumMaxNum(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isProfitableToHoist(Instruction *I) const overridellvm::AArch64TargetLoweringvirtual
isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) constllvm::TargetLoweringinlinevirtual
isSafeMemOpType(MVT) constllvm::TargetLoweringBaseinlinevirtual
isSDNodeAlwaysUniform(const SDNode *N) constllvm::TargetLoweringinlinevirtual
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) constllvm::TargetLoweringinlinevirtual
isSelectSupported(SelectSupportKind) constllvm::TargetLoweringBaseinlinevirtual
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
isSlowDivBypassed() constllvm::TargetLoweringBaseinline
isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLoweringvirtual
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) constllvm::TargetLoweringBaseinlinevirtual
IsStrictFPEnabledllvm::TargetLoweringBaseprotected
isStrictFPEnabled() constllvm::TargetLoweringBaseinline
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) constllvm::TargetLoweringBasevirtual
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinlinevirtual
isTruncateFree(Type *Ty1, Type *Ty2) const overridellvm::AArch64TargetLoweringvirtual
isTruncateFree(EVT VT1, EVT VT2) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::isTruncateFree(LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
llvm::TargetLowering::isTruncateFree(SDValue Val, EVT VT2) constllvm::TargetLoweringBaseinlinevirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) constllvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) constllvm::TargetLoweringBaseinline
isVectorClearMaskLegal(ArrayRef< int > M, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
isVectorShiftByScalarCheap(Type *Ty) constllvm::TargetLoweringBaseinlinevirtual
isVScaleKnownToBeAPowerOfTwo() const overridellvm::AArch64TargetLoweringinlinevirtual
isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) constllvm::TargetLoweringinlinevirtual
isZExtFree(Type *Ty1, Type *Ty2) const overridellvm::AArch64TargetLoweringvirtual
isZExtFree(EVT VT1, EVT VT2) const overridellvm::AArch64TargetLoweringvirtual
isZExtFree(SDValue Val, EVT VT2) const overridellvm::AArch64TargetLoweringvirtual
llvm::TargetLowering::isZExtFree(LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
LowerCallTo(CallLoweringInfo &CLI) constllvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) constllvm::TargetLoweringinlinevirtual
lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI) const overridellvm::AArch64TargetLoweringvirtual
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) constllvm::TargetLoweringBaseinlinevirtual
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const overridellvm::AArch64TargetLoweringvirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const overridellvm::AArch64TargetLoweringvirtual
lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI) const overridellvm::AArch64TargetLoweringvirtual
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::AArch64TargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) constllvm::TargetLowering
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) constllvm::TargetLoweringBaseinlinevirtual
MaxGluedStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mergeStoresAfterLegalization(EVT VT) const overridellvm::AArch64TargetLoweringvirtual
MulExpansionKind enum namellvm::TargetLoweringBase
needsFixedCatchObjects() const overridellvm::AArch64TargetLoweringvirtual
NegatibleCost enum namellvm::TargetLoweringBase
None enum valuellvm::TargetLoweringBase
NotAnd enum valuellvm::TargetLoweringBase
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const overridellvm::AArch64TargetLoweringvirtual
optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) constllvm::TargetLoweringBaseinlinevirtual
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) constllvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) constllvm::TargetLoweringvirtual
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::AArch64TargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
preferABDSToABSWithNSW(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) constllvm::TargetLoweringBaseinlinevirtual
preferIncOfAddToSubOfNot(EVT VT) const overridellvm::AArch64TargetLoweringvirtual
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const overridellvm::AArch64TargetLoweringvirtual
preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) constllvm::TargetLoweringBaseinlinevirtual
preferZeroCompareBranch() constllvm::TargetLoweringBaseinlinevirtual
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) constllvm::TargetLoweringBaseinline
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
ReciprocalEstimate enum namellvm::TargetLoweringBase
ReconstructShuffle(SDValue Op, SelectionDAG &DAG) constllvm::AArch64TargetLowering
reduceSelectOfFPConstantLoads(EVT CmpOpVT) constllvm::TargetLoweringBaseinlinevirtual
requiresUniformRegister(MachineFunction &MF, const Value *) constllvm::TargetLoweringBaseinlinevirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaxBytesForAlignment(unsigned MaxBytes)llvm::TargetLoweringBaseinlineprotected
setMaxDivRemBitWidthSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(Register R)llvm::TargetLoweringBaseinlineprotected
setSupportsUnalignedAtomics(bool UnalignedSupported)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) constllvm::TargetLoweringBaseinlinevirtual
ShiftLegalizationStrategy enum namellvm::TargetLoweringBase
shouldAlignPointerArgs(CallInst *, unsigned &, Align &) constllvm::TargetLoweringBaseinlinevirtual
shouldAvoidTransformToShift(EVT VT, unsigned Amount) constllvm::TargetLoweringBaseinlinevirtual
shouldCastAtomicLoadInIR(LoadInst *LI) constllvm::TargetLoweringBaseinlinevirtual
shouldCastAtomicRMWIInIR(AtomicRMWInst *RMWI) constllvm::TargetLoweringBaseinlinevirtual
shouldCastAtomicStoreInIR(StoreInst *SI) constllvm::TargetLoweringBaseinlinevirtual
shouldConsiderGEPOffsetSplit() const overridellvm::AArch64TargetLoweringvirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const overridellvm::AArch64TargetLoweringvirtual
shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
shouldConvertPhiType(Type *From, Type *To) constllvm::TargetLoweringBaseinlinevirtual
shouldConvertSplatType(ShuffleVectorInst *SVI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandCttzElements(EVT VT) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const overridellvm::AArch64TargetLoweringvirtual
shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) constllvm::TargetLoweringBaseinlinevirtual
shouldExtendTypeInLibCall(EVT Type) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const overridellvm::AArch64TargetLoweringvirtual
shouldFoldMaskToVariableShiftPair(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const overridellvm::AArch64TargetLoweringvirtual
shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) constllvm::TargetLoweringBaseinlinevirtual
shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const overridellvm::AArch64TargetLoweringinlinevirtual
shouldInsertFencesForAtomic(const Instruction *I) const overridellvm::AArch64TargetLoweringvirtual
shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const overridellvm::AArch64TargetLoweringvirtual
shouldKeepZExtForFP16Conv() constllvm::TargetLoweringBaseinlinevirtual
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const overridellvm::AArch64TargetLoweringvirtual
shouldReassociateReduction(unsigned RedOpc, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const overridellvm::AArch64TargetLoweringvirtual
shouldRemoveRedundantExtend(SDValue Op) const overridellvm::AArch64TargetLoweringvirtual
shouldScalarizeBinop(SDValue VecOp) constllvm::TargetLoweringBaseinlinevirtual
ShouldShrinkFPConstant(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) constllvm::TargetLoweringinlinevirtual
shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const overridellvm::AArch64TargetLoweringvirtual
shouldSplatInsEltVarIndex(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const overridellvm::AArch64TargetLoweringinlinevirtual
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) constllvm::TargetLowering
signExtendConstant(const ConstantInt *C) constllvm::TargetLoweringBaseinlinevirtual
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) constllvm::TargetLoweringvirtual
SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) constllvm::TargetLoweringBaseinlinevirtual
supportKCFIBundles() const overridellvm::AArch64TargetLoweringinlinevirtual
supportSplitCSR(MachineFunction *MF) const overridellvm::AArch64TargetLoweringinlinevirtual
supportsUnalignedAtomics() constllvm::TargetLoweringBaseinline
supportSwiftError() const overridellvm::AArch64TargetLoweringinlinevirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const overridellvm::AArch64TargetLoweringvirtual
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeScalableVector enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSoftPromoteHalf enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
unwrapAddress(SDValue N) constllvm::TargetLoweringinlinevirtual
useFPRegsForHalfType() constllvm::TargetLoweringBaseinlinevirtual
useLoadStackGuardNode() const overridellvm::AArch64TargetLoweringvirtual
useSoftFloat() constllvm::TargetLoweringBaseinlinevirtual
useStackGuardXorFP() constllvm::TargetLoweringBaseinlinevirtual
useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON=false) constllvm::AArch64TargetLowering
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual