LLVM 19.0.0git
Classes | Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::TargetLoweringBase Class Reference

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen. More...

#include "llvm/CodeGen/TargetLowering.h"

Inheritance diagram for llvm::TargetLoweringBase:
Inheritance graph
[legend]

Classes

struct  AddrMode
 This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null, there is no BaseGV. More...
 
class  ArgListEntry
 
struct  CondMergingParams
 
struct  IntrinsicInfo
 
class  ValueTypeActionImpl
 

Public Types

enum  LegalizeAction : uint8_t {
  Legal , Promote , Expand , LibCall ,
  Custom
}
 This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...
 
enum  LegalizeTypeAction : uint8_t {
  TypeLegal , TypePromoteInteger , TypeExpandInteger , TypeSoftenFloat ,
  TypeExpandFloat , TypeScalarizeVector , TypeSplitVector , TypeWidenVector ,
  TypePromoteFloat , TypeSoftPromoteHalf , TypeScalarizeScalableVector
}
 This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...
 
enum  BooleanContent { UndefinedBooleanContent , ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect , ScalarCondVectorVal , VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
enum class  AtomicExpansionKind {
  None , CastToInteger , LLSC , LLOnly ,
  CmpXChg , MaskedIntrinsic , BitTestIntrinsic , CmpArithIntrinsic ,
  Expand , NotAtomic
}
 Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...
 
enum class  MulExpansionKind { Always , OnlyLegalOrCustom }
 Enum that specifies when a multiplication should be expanded. More...
 
enum class  NegatibleCost { Cheaper = 0 , Neutral = 1 , Expensive = 2 }
 Enum that specifies when a float negation is beneficial. More...
 
enum  AndOrSETCCFoldKind : uint8_t { None = 0 , AddAnd = 1 , NotAnd = 2 , ABS = 4 }
 Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)). More...
 
enum  ReciprocalEstimate : int { Unspecified = -1 , Disabled = 0 , Enabled = 1 }
 Reciprocal estimate status values used by the functions below. More...
 
enum class  ShiftLegalizationStrategy { ExpandToParts , ExpandThroughStack , LowerToLibcall }
 Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recursion depth - how many expansion needed. More...
 
using LegalizeKind = std::pair< LegalizeTypeAction, EVT >
 LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
 
using ArgListTy = std::vector< ArgListEntry >
 

Public Member Functions

virtual void markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const
 
 TargetLoweringBase (const TargetMachine &TM)
 NOTE: The TargetMachine owns TLOF.
 
 TargetLoweringBase (const TargetLoweringBase &)=delete
 
TargetLoweringBaseoperator= (const TargetLoweringBase &)=delete
 
virtual ~TargetLoweringBase ()=default
 
bool isStrictFPEnabled () const
 Return true if the target support strict float operation.
 
const TargetMachinegetTargetMachine () const
 
virtual bool useSoftFloat () const
 
virtual MVT getPointerTy (const DataLayout &DL, uint32_t AS=0) const
 Return the pointer type for the given address space, defaults to the pointer type from the data layout.
 
virtual MVT getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const
 Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.
 
MVT getFrameIndexTy (const DataLayout &DL) const
 Return the type for frame index, which is determined by the alloca address space specified through the data layout.
 
MVT getProgramPointerTy (const DataLayout &DL) const
 Return the type for code pointers, which is determined by the program address space specified through the data layout.
 
virtual MVT getFenceOperandTy (const DataLayout &DL) const
 Return the type for operands of fence.
 
virtual MVT getScalarShiftAmountTy (const DataLayout &, EVT) const
 Return the type to use for a scalar shift opcode, given the shifted amount type.
 
EVT getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
 Returns the type for the shift amount of a shift opcode.
 
virtual LLVM_READONLY LLT getPreferredShiftAmountTy (LLT ShiftValueTy) const
 Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
 
virtual MVT getVectorIdxTy (const DataLayout &DL) const
 Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.
 
virtual MVT getVPExplicitVectorLengthTy () const
 Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.
 
virtual MachineMemOperand::Flags getTargetMMOFlags (const Instruction &I) const
 This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.
 
virtual MachineMemOperand::Flags getTargetMMOFlags (const MemSDNode &Node) const
 This callback is used to inspect load/store SDNode.
 
MachineMemOperand::Flags getLoadMemOperandFlags (const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
 
MachineMemOperand::Flags getStoreMemOperandFlags (const StoreInst &SI, const DataLayout &DL) const
 
MachineMemOperand::Flags getAtomicMemOperandFlags (const Instruction &AI, const DataLayout &DL) const
 
virtual bool isSelectSupported (SelectSupportKind) const
 
virtual bool shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const
 Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.
 
virtual bool shouldExpandGetVectorLength (EVT CountVT, unsigned VF, bool IsScalable) const
 
virtual bool shouldExpandCttzElements (EVT VT) const
 Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder.
 
virtual bool shouldReassociateReduction (unsigned RedOpc, EVT VT) const
 
virtual bool reduceSelectOfFPConstantLoads (EVT CmpOpVT) const
 Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available.
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions.
 
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction (MVT VT) const
 Return the preferred vector type legalization action.
 
virtual bool softPromoteHalfType () const
 
virtual bool useFPRegsForHalfType () const
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
virtual bool isIntDivCheap (EVT VT, AttributeList Attr) const
 Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
 
virtual bool hasStandaloneRem (EVT VT) const
 Return true if the target can handle a standalone remainder operation.
 
virtual bool isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
 Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
 
int getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.
 
int getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
 Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.
 
int getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a square root of the given type based on the function's attributes.
 
int getDivRefinementSteps (EVT VT, MachineFunction &MF) const
 Return the refinement step count for a division of the given type based on the function's attributes.
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed.
 
const DenseMap< unsigned int, unsigned int > & getBypassSlowDivWidths () const
 Returns map of slow types for division or remainder with corresponding fast types.
 
virtual bool isVScaleKnownToBeAPowerOfTwo () const
 Return true only if vscale must be a power of two.
 
bool isJumpExpensive () const
 Return true if Flow Control is an expensive operation that should be avoided.
 
virtual CondMergingParams getJumpConditionMergingParams (Instruction::BinaryOps, const Value *, const Value *) const
 
bool isPredictableSelectExpensive () const
 Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
 
virtual bool fallBackToDAGISel (const Instruction &Inst) const
 
virtual bool isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
 Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
 
virtual bool isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
 Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
 
virtual bool storeOfVectorConstantIsCheap (bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
 Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants.
 
virtual bool mergeStoresAfterLegalization (EVT MemVT) const
 Allow store merging for the specified type after legalization in addition to before legalization.
 
virtual bool canMergeStoresTo (unsigned AS, EVT MemVT, const MachineFunction &MF) const
 Returns if it's reasonable to merge stores to MemVT size.
 
virtual bool isCheapToSpeculateCttz (Type *Ty) const
 Return true if it is cheap to speculate a call to intrinsic cttz.
 
virtual bool isCheapToSpeculateCtlz (Type *Ty) const
 Return true if it is cheap to speculate a call to intrinsic ctlz.
 
virtual bool isCtlzFast () const
 Return true if ctlz instruction is fast.
 
virtual bool isCtpopFast (EVT VT) const
 Return true if ctpop instruction is fast.
 
virtual unsigned getCustomCtpopCost (EVT VT, ISD::CondCode Cond) const
 Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.
 
virtual bool isEqualityCmpFoldedWithSignedCmp () const
 Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.
 
virtual bool preferZeroCompareBranch () const
 Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
 
virtual bool isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
 Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
 
virtual bool isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
 Return if the target supports combining a chain like:
 
virtual bool areTwoSDNodeTargetMMOFlagsMergeable (const MemSDNode &NodeX, const MemSDNode &NodeY) const
 Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
 
virtual bool convertSetCCLogicToBitwiseLogic (EVT VT) const
 Use bitwise logic to make pairs of compares more efficient.
 
virtual MVT hasFastEqualityCompare (unsigned NumBits) const
 Return the preferred operand type if the target has a quick way to compare integer values of the given size.
 
virtual bool hasAndNotCompare (SDValue Y) const
 Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
 
virtual bool hasAndNot (SDValue X) const
 Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
 
virtual bool hasBitTest (SDValue X, SDValue Y) const
 Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.
 
virtual bool shouldFoldMaskToVariableShiftPair (SDValue X) const
 There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.
 
virtual bool shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const
 Return true if it is profitable to fold a pair of shifts into a mask.
 
virtual bool shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const
 Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.
 
virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const
 Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.
 
virtual bool optimizeFMulOrFDivAsShiftAddBitcast (SDNode *N, SDValue FPConst, SDValue IntPow2) const
 
virtual unsigned preferedOpcodeForCmpEqPiecesOfOperand (EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const
 
virtual bool preferIncOfAddToSubOfNot (EVT VT) const
 These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.
 
virtual bool preferABDSToABSWithNSW (EVT VT) const
 
virtual bool preferScalarizeSplat (SDNode *N) const
 
virtual bool preferSextInRegOfTruncate (EVT TruncVT, EVT VT, EVT ExtVT) const
 
bool enableExtLdPromotion () const
 Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
 
virtual bool canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const
 Return true if the target can combine store(extractelement VectorTy, Idx).
 
virtual bool shallExtractConstSplatVectorElementToStore (Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
 Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant.
 
virtual bool shouldSplatInsEltVarIndex (EVT) const
 Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
 
virtual bool enableAggressiveFMAFusion (EVT VT) const
 Return true if target always benefits from combining into FMA for a given value type.
 
virtual bool enableAggressiveFMAFusion (LLT Ty) const
 Return true if target always benefits from combining into FMA for a given value type.
 
virtual EVT getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
 Return the ValueType of the result of SETCC operations.
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 Return the ValueType for comparison libcalls.
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.
 
BooleanContent getBooleanContents (EVT Type) const
 
SDValue promoteTargetBoolean (SelectionDAG &DAG, SDValue Bool, EVT ValVT) const
 Promote the given target boolean to a target boolean of the given type.
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference.
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 Some scheduler, e.g.
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT, bool isDivergent=false) const
 Return the register class that should be used for the specified value type.
 
virtual bool requiresUniformRegister (MachineFunction &MF, const Value *) const
 Allows target to decide about the register class of the specific value that is live outside the defining block.
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 Return the 'representative' register class for the specified value type.
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 Return the cost of the 'representative' register class for the specified value type.
 
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy (SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
 
bool isTypeLegal (EVT VT) const
 Return true if the target has native support for the specified value type.
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
virtual EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function.
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 For types supported by the target, this is an identity function.
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Vector types are broken down into some number of legal first class types.
 
virtual unsigned getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
 Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
 
virtual bool isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const
 Returns true if the target can instruction select the specified FP immediate natively.
 
virtual bool isShuffleMaskLegal (ArrayRef< int >, EVT) const
 Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 Returns true if the operation can trap for the value type.
 
virtual bool isVectorClearMaskLegal (ArrayRef< int >, EVT) const
 Similar to isShuffleMaskLegal.
 
virtual LegalizeAction getCustomOperationAction (SDNode &Op) const
 How to legalize this custom operation?
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
virtual bool isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const
 Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.
 
LegalizeAction getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const
 Some fixed point operations may be natively supported by the target but only for specific scales.
 
LegalizeAction getStrictFPOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT, bool LegalOnly=false) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering.
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
 Return true if the specified operation is legal on this target or can be made legal using promotion.
 
bool isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
 Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.
 
bool isOperationCustom (unsigned Op, EVT VT) const
 Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
 
virtual bool areJTsAllowed (const Function *Fn) const
 Return true if lowering to a jump table is allowed.
 
bool rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
 Check whether the range [Low,High] fits in a machine word.
 
virtual bool isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
 Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.
 
virtual MVT getPreferredSwitchConditionType (LLVMContext &Context, EVT ConditionVT) const
 Returns preferred type for switch condition.
 
bool isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
 Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.
 
bool isOperationExpand (unsigned Op, EVT VT) const
 Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target.
 
LegalizeAction getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal on this target.
 
bool isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
 Return true if the specified load with extension is legal or custom on this target.
 
LegalizeAction getTruncStoreAction (EVT ValVT, EVT MemVT) const
 Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation is legal on this target.
 
bool isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
 Return true if the specified store with truncation has solution on this target.
 
virtual bool canCombineTruncStore (EVT ValVT, EVT MemVT, bool LegalOnly) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target.
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target.
 
LegalizeAction getIndexedMaskedLoadAction (unsigned IdxMode, MVT VT) const
 Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isIndexedMaskedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target.
 
LegalizeAction getIndexedMaskedStoreAction (unsigned IdxMode, MVT VT) const
 Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isIndexedMaskedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target.
 
virtual bool shouldExtendGSIndex (EVT VT, EVT &EltTy) const
 Returns true if the index type for a masked gather/scatter requires extending.
 
virtual bool shouldRemoveExtendFromGSIndex (SDValue Extend, EVT DataVT) const
 
virtual bool isLegalScaleForGatherScatter (uint64_t Scale, uint64_t ElemSize) const
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target.
 
bool isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal or custom on this target.
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 If the action for this operation is to promote, this method returns the ValueType to promote to.
 
virtual EVT getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 
EVT getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the EVT corresponding to this LLVM type.
 
EVT getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType.
 
virtual uint64_t getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
 Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require.
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require.
 
virtual unsigned getNumRegisters (LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
 Return the number of registers that this ValueType will eventually require.
 
virtual MVT getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
 Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
 
virtual unsigned getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
 Certain targets require unusual breakdowns of certain types.
 
virtual Align getABIAlignmentForCallingConv (Type *ArgTy, const DataLayout &DL) const
 Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.
 
virtual bool ShouldShrinkFPConstant (EVT) const
 If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
 
virtual bool shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
 Return true if it is profitable to reduce a load to a smaller type.
 
virtual bool shouldRemoveRedundantExtend (SDValue Op) const
 Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.
 
bool hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
 When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 If true, the target has custom DAG combine transformations that it can perform for the specified node.
 
unsigned getGatherAllAliasesMaxDepth () const
 
virtual unsigned getVaListSizeInBits (const DataLayout &DL) const
 Returns the size of the platform's va_list object.
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset.
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy.
 
virtual unsigned getMaxGluedStoresPerMemcpy () const
 Get maximum # of store operations to be glued together.
 
unsigned getMaxExpandSizeMemcmp (bool OptSize) const
 Get maximum # of load operations permitted for memcmp.
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove.
 
virtual bool allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
 Determine if the target supports unaligned memory accesses.
 
virtual bool allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
 LLT handling variant.
 
bool allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
 This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.
 
bool allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
 Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.
 
virtual bool allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
 Return true if the target supports a memory access of this type for the given address space and alignment.
 
bool allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
 Return true if the target supports a memory access of this type for the given MachineMemOperand.
 
bool allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
 LLT handling variant.
 
virtual EVT getOptimalMemOpType (const MemOp &Op, const AttributeList &) const
 Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
 
virtual LLT getOptimalMemOpLLT (const MemOp &Op, const AttributeList &) const
 LLT returning variant.
 
virtual bool isSafeMemOpType (MVT) const
 Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
 
virtual unsigned getMinimumJumpTableEntries () const
 Return lower limit for number of blocks in a jump table.
 
unsigned getMinimumJumpTableDensity (bool OptForSize) const
 Return lower limit of the density in a jump table.
 
unsigned getMaximumJumpTableSize () const
 Return upper limit for number of entries in a jump table.
 
virtual bool isJumpTableRelative () const
 
Register getStackPointerRegisterToSaveRestore () const
 If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
 
virtual Register getExceptionPointerRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception address on entry to an EH pad.
 
virtual Register getExceptionSelectorRegister (const Constant *PersonalityFn) const
 If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
 
virtual bool needsFixedCatchObjects () const
 
Align getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument.
 
Align getMinFunctionAlignment () const
 Return the minimum function alignment.
 
Align getPrefFunctionAlignment () const
 Return the preferred function alignment.
 
virtual Align getPrefLoopAlignment (MachineLoop *ML=nullptr) const
 Return the preferred loop alignment.
 
virtual unsigned getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB) const
 Return the maximum amount of bytes allowed to be emitted when padding for alignment.
 
virtual bool alignLoopsWithOptSize () const
 Should loops be aligned even when the function is marked OptSize (but not MinSize).
 
virtual ValuegetIRStackGuard (IRBuilderBase &IRB) const
 If the target has a standard location for the stack protector guard, returns the address of that location.
 
virtual void insertSSPDeclarations (Module &M) const
 Inserts necessary declarations for SSP (stack protection) purpose.
 
virtual ValuegetSDagStackGuard (const Module &M) const
 Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
 
virtual bool useStackGuardXorFP () const
 If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.
 
virtual FunctiongetSSPStackGuardCheck (const Module &M) const
 If the target has a standard stack protection check function that performs validation and error handling, returns the function.
 
virtual ValuegetSafeStackPointerLocation (IRBuilderBase &IRB) const
 Returns the target-specific address of the unsafe stack pointer.
 
virtual bool hasStackProbeSymbol (const MachineFunction &MF) const
 Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
 
virtual bool hasInlineStackProbe (const MachineFunction &MF) const
 
virtual StringRef getStackProbeSymbolName (const MachineFunction &MF) const
 
virtual bool isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
 
virtual bool shouldAlignPointerArgs (CallInst *, unsigned &, Align &) const
 Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.
 
virtual void emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const
 
virtual bool shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
 Returns true if arguments should be sign-extended in lib calls.
 
virtual bool shouldExtendTypeInLibCall (EVT Type) const
 Returns true if arguments should be extended in lib calls.
 
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR (LoadInst *LI) const
 Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
 
virtual AtomicExpansionKind shouldCastAtomicLoadInIR (LoadInst *LI) const
 Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
 
virtual AtomicExpansionKind shouldExpandAtomicStoreInIR (StoreInst *SI) const
 Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
 
virtual AtomicExpansionKind shouldCastAtomicStoreInIR (StoreInst *SI) const
 Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
 
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
 Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
 
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const
 Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
 
virtual AtomicExpansionKind shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI) const
 Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
 
virtual LoadInstlowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
 On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.
 
virtual ISD::NodeType getExtendForAtomicOps () const
 Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
 
virtual ISD::NodeType getExtendForAtomicCmpSwapArg () const
 Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
 
virtual bool shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
 Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
 
virtual bool isProfitableToCombineMinNumMaxNum (EVT VT) const
 
virtual bool convertSelectOfConstantsToMath (EVT VT) const
 Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.
 
virtual bool decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const
 Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.
 
virtual bool isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const
 Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
 
virtual bool shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const
 Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.
 
bool isBeneficialToExpandPowI (int64_t Exponent, bool OptForSize) const
 Return true if it is beneficial to expand an @llvm.powi.
 
virtual bool getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.
 
virtual bool isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
 Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
 
virtual int64_t getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset) const
 Return the prefered common base offset.
 
virtual bool isLegalICmpImmediate (int64_t) const
 Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
 
virtual bool isLegalAddImmediate (int64_t) const
 Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
 
virtual bool isLegalStoreImmediate (int64_t Value) const
 Return true if the specified immediate is legal for the value input of a store instruction.
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.
 
virtual TypeshouldConvertSplatType (ShuffleVectorInst *SVI) const
 Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable.
 
virtual bool shouldConvertPhiType (Type *From, Type *To) const
 Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.
 
virtual bool isCommutativeBinOp (unsigned Opcode) const
 Returns true if the opcode is a commutative binary operation.
 
virtual bool isBinOp (unsigned Opcode) const
 Return true if the node is a math/logic binary operator.
 
virtual bool isTruncateFree (Type *FromTy, Type *ToTy) const
 Return true if it's free to truncate a value of type FromTy to type ToTy.
 
virtual bool allowTruncateForTailCall (Type *FromTy, Type *ToTy) const
 Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.
 
virtual bool isTruncateFree (EVT FromVT, EVT ToVT) const
 
virtual bool isTruncateFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const
 
virtual bool isTruncateFree (SDValue Val, EVT VT2) const
 Return true if truncating the specific node Val to type VT2 is free.
 
virtual bool isProfitableToHoist (Instruction *I) const
 
bool isExtFree (const Instruction *I) const
 Return true if the extension represented by I is free.
 
bool isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const
 Return true if Load and Ext can form an ExtLoad.
 
virtual bool isZExtFree (Type *FromTy, Type *ToTy) const
 Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.
 
virtual bool isZExtFree (EVT FromTy, EVT ToTy) const
 
virtual bool isZExtFree (LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) const
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
 
virtual bool isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const
 Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
 
virtual bool signExtendConstant (const ConstantInt *C) const
 Return true if this constant should be sign extended when promoting to a larger type.
 
virtual bool shouldSinkOperands (Instruction *I, SmallVectorImpl< Use * > &Ops) const
 Return true if sinking I's operands to the same basic block as I is profitable, e.g.
 
virtual bool optimizeExtendOrTruncateConversion (Instruction *I, Loop *L, const TargetTransformInfo &TTI) const
 Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.
 
virtual bool hasPairedLoad (EVT, Align &) const
 Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
 
virtual bool hasVectorBlend () const
 Return true if the target has a vector blend instruction.
 
virtual unsigned getMaxSupportedInterleaveFactor () const
 Get the maximum supported factor for interleaved memory accesses.
 
virtual bool lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
 Lower an interleaved load to target specific intrinsics.
 
virtual bool lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
 Lower an interleaved store to target specific intrinsics.
 
virtual bool lowerDeinterleaveIntrinsicToLoad (IntrinsicInst *DI, LoadInst *LI) const
 Lower a deinterleave intrinsic to a target specific load intrinsic.
 
virtual bool lowerInterleaveIntrinsicToStore (IntrinsicInst *II, StoreInst *SI) const
 Lower an interleave intrinsic to a target specific store intrinsic.
 
virtual bool isFPExtFree (EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).
 
virtual bool isFPExtFoldable (const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const
 Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
 
virtual bool isFPExtFoldable (const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const
 Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
 
virtual bool isVectorLoadExtDesirable (SDValue ExtVal) const
 Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
 
virtual bool isFNegFree (EVT VT) const
 Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
 
virtual bool isFAbsFree (EVT VT) const
 Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
 
virtual bool isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT) const
 Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
 
virtual bool isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, LLT) const
 Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
 
virtual bool isFMAFasterThanFMulAndFAdd (const Function &F, Type *) const
 IR version.
 
virtual bool isFMADLegal (const MachineInstr &MI, LLT Ty) const
 Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.
 
virtual bool isFMADLegal (const SelectionDAG &DAG, const SDNode *N) const
 Returns true if be combined with to form an ISD::FMAD.
 
virtual bool generateFMAsInMachineCombiner (EVT VT, CodeGenOptLevel OptLevel) const
 
virtual bool isNarrowingProfitable (EVT SrcVT, EVT DestVT) const
 Return true if it's profitable to narrow operations of type SrcVT to DestVT.
 
virtual bool shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const
 Return true if pulling a binary operation into a select with an identity constant is profitable.
 
virtual bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
 Return true if it is beneficial to convert a load of a constant to just the constant itself.
 
virtual bool isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
 Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.
 
virtual bool shouldScalarizeBinop (SDValue VecOp) const
 Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.
 
virtual bool isExtractVecEltCheap (EVT VT, unsigned Index) const
 Return true if extraction of a scalar element from the given vector type at the given index is cheap.
 
virtual bool shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const
 Try to convert math with an overflow comparison into the corresponding DAG node operation.
 
virtual bool aggressivelyPreferBuildVectorSources (EVT VecVT) const
 
virtual bool shouldConsiderGEPOffsetSplit () const
 
virtual bool shouldAvoidTransformToShift (EVT VT, unsigned Amount) const
 Return true if creating a shift of the type by the given amount is not profitable.
 
virtual bool shouldFoldSelectWithSingleBitTest (EVT VT, const APInt &AndMask) const
 
virtual bool shouldKeepZExtForFP16Conv () const
 Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.
 
virtual bool shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const
 Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.
 
virtual bool isComplexDeinterleavingSupported () const
 Does this target support complex deinterleaving.
 
virtual bool isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperation Operation, Type *Ty) const
 Does this target support complex deinterleaving with the given operation and type.
 
virtual ValuecreateComplexDeinterleavingIR (IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const
 Create the IR node for the given complex deinterleaving operation.
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall.
 
void setLibcallName (ArrayRef< RTLIB::Libcall > Calls, const char *Name)
 
const chargetLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall.
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 Override the default CondCode to be used to test the result of the comparison libcall against zero.
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 Get the CondCode that's to be used to test the result of the comparison libcall against zero.
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall.
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall.
 
virtual void finalizeLowering (MachineFunction &MF) const
 Execute target specific actions to finalize target lowering.
 
virtual bool shouldLocalize (const MachineInstr &MI, const TargetTransformInfo *TTI) const
 Check whether or not MI needs to be moved close to its uses.
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode.
 
Helpers for atomic expansion.
unsigned getMaxAtomicSizeInBitsSupported () const
 Returns the maximum atomic operation size (in bits) supported by the backend.
 
unsigned getMaxDivRemBitWidthSupported () const
 Returns the size in bits of the maximum div/rem the backend supports.
 
unsigned getMaxLargeFPConvertBitWidthSupported () const
 Returns the size in bits of the maximum larget fp convert the backend supports.
 
unsigned getMinCmpXchgSizeInBits () const
 Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
 
bool supportsUnalignedAtomics () const
 Whether the target supports unaligned atomic operations.
 
virtual bool shouldInsertFencesForAtomic (const Instruction *I) const
 Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
 
virtual bool shouldInsertTrailingFenceForAtomicStore (const Instruction *I) const
 Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.
 
virtual ValueemitLoadLinked (IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const
 Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
 
virtual ValueemitStoreConditional (IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 Perform a store-conditional operation to Addr.
 
virtual ValueemitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
 Perform a masked atomicrmw using a target-specific intrinsic.
 
virtual void emitExpandAtomicRMW (AtomicRMWInst *AI) const
 Perform a atomicrmw expansion using a target-specific way.
 
virtual void emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI) const
 Perform a bit test atomicrmw using a target-specific intrinsic.
 
virtual void emitCmpArithAtomicRMWIntrinsic (AtomicRMWInst *AI) const
 Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.
 
virtual ValueemitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
 Perform a masked cmpxchg using a target-specific intrinsic.
 
KCFI check lowering.
virtual MachineInstrEmitKCFICheck (MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const
 
virtual InstructionemitLeadingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
 Inserts in the IR a target-specific intrinsic specifying a fence.
 
virtual InstructionemitTrailingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

void initActions ()
 Initialize all of the actions to default values.
 
ValuegetDefaultSafeStackPointerLocation (IRBuilderBase &IRB, bool UseTLS) const
 
void setBooleanContents (BooleanContent Ty)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
 
void setBooleanVectorContents (BooleanContent Ty)
 Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference.
 
void setMinimumJumpTableEntries (unsigned Val)
 Indicate the minimum number of blocks to generate jump tables.
 
void setMaximumJumpTableSize (unsigned)
 Indicate the maximum number of entries in jump tables.
 
void setStackPointerRegisterToSaveRestore (Register R)
 If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 Tells the code generator that the target has BitExtract instructions.
 
void setJumpIsExpensive (bool isExpensive=true)
 Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass.
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 Add the specified register class as an available regclass for the specified value type.
 
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
 Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
 
void computeRegisterProperties (const TargetRegisterInfo *TRI)
 Once all of the register classes are added, this allows us to compute derived properties we expose.
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 Indicate that the specified operation does not work with the specified type and indicate what to do about it.
 
void setOperationAction (ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
 
void setOperationAction (ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.
 
void setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.
 
void setIndexedLoadAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.
 
void setIndexedLoadAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
 
void setIndexedStoreAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.
 
void setIndexedStoreAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)
 
void setIndexedMaskedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.
 
void setIndexedMaskedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.
 
void setCondCodeAction (ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
 Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.
 
void setCondCodeAction (ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.
 
void setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 Convenience method to set an operation to Promote and specify the type in a single call.
 
void setOperationPromotedToType (ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ArrayRef< ISD::NodeType > NTs)
 Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.
 
void setMinFunctionAlignment (Align Alignment)
 Set the target's minimum function alignment.
 
void setPrefFunctionAlignment (Align Alignment)
 Set the target's preferred function alignment.
 
void setPrefLoopAlignment (Align Alignment)
 Set the target's preferred loop alignment.
 
void setMaxBytesForAlignment (unsigned MaxBytes)
 
void setMinStackArgumentAlignment (Align Alignment)
 Set the minimum stack alignment of an argument.
 
void setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
 Set the maximum atomic operation size supported by the backend.
 
void setMaxDivRemBitWidthSupported (unsigned SizeInBits)
 Set the size in bits of the maximum div/rem the backend supports.
 
void setMaxLargeFPConvertBitWidthSupported (unsigned SizeInBits)
 Set the size in bits of the maximum fp convert the backend supports.
 
void setMinCmpXchgSizeInBits (unsigned SizeInBits)
 Sets the minimum cmpxchg or ll/sc size supported by the backend.
 
void setSupportsUnalignedAtomics (bool UnalignedSupported)
 Sets whether unaligned atomic operations are supported.
 
virtual bool isExtFreeImpl (const Instruction *I) const
 Return true if the extension represented by I is free.
 
bool isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
 Return true if the value types that can be represented by the specified register class are all legal.
 
MachineBasicBlockemitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
 Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
 

Protected Attributes

unsigned GatherAllAliasesMaxDepth
 Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain.
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call.
 
unsigned MaxStoresPerMemsetOptSize
 Likewise for functions with the OptSize attribute.
 
unsigned MaxStoresPerMemcpy
 Specify maximum number of store instructions per memcpy call.
 
unsigned MaxStoresPerMemcpyOptSize
 Likewise for functions with the OptSize attribute.
 
unsigned MaxGluedStoresPerMemcpy = 0
 Specify max number of store instructions to glue in inlined memcpy.
 
unsigned MaxLoadsPerMemcmp
 Specify maximum number of load instructions per memcmp call.
 
unsigned MaxLoadsPerMemcmpOptSize
 Likewise for functions with the OptSize attribute.
 
unsigned MaxStoresPerMemmove
 Specify maximum number of store instructions per memmove call.
 
unsigned MaxStoresPerMemmoveOptSize
 Likewise for functions with the OptSize attribute.
 
bool PredictableSelectIsExpensive
 Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.
 
bool EnableExtLdPromotion
 
bool IsStrictFPEnabled
 

Detailed Description

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.

Definition at line 193 of file TargetLowering.h.

Member Typedef Documentation

◆ ArgListTy

Definition at line 325 of file TargetLowering.h.

◆ LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 229 of file TargetLowering.h.

Member Enumeration Documentation

◆ AndOrSETCCFoldKind

Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)).

Enumerator
None 
AddAnd 
NotAnd 
ABS 

Definition at line 288 of file TargetLowering.h.

◆ AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.

Enumerator
None 
CastToInteger 
LLSC 
LLOnly 
CmpXChg 
MaskedIntrinsic 
BitTestIntrinsic 
CmpArithIntrinsic 
Expand 
NotAtomic 

Definition at line 251 of file TargetLowering.h.

◆ BooleanContent

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 232 of file TargetLowering.h.

◆ LegalizeAction

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
LibCall 
Custom 

Definition at line 197 of file TargetLowering.h.

◆ LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 
TypePromoteFloat 
TypeSoftPromoteHalf 
TypeScalarizeScalableVector 

Definition at line 207 of file TargetLowering.h.

◆ MulExpansionKind

Enum that specifies when a multiplication should be expanded.

Enumerator
Always 
OnlyLegalOrCustom 

Definition at line 273 of file TargetLowering.h.

◆ NegatibleCost

Enum that specifies when a float negation is beneficial.

Enumerator
Cheaper 
Neutral 
Expensive 

Definition at line 280 of file TargetLowering.h.

◆ ReciprocalEstimate

Reciprocal estimate status values used by the functions below.

Enumerator
Unspecified 
Disabled 
Enabled 

Definition at line 553 of file TargetLowering.h.

◆ SelectSupportKind

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 239 of file TargetLowering.h.

◆ ShiftLegalizationStrategy

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recursion depth - how many expansion needed.

Enumerator
ExpandToParts 
ExpandThroughStack 
LowerToLibcall 

Definition at line 1057 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ TargetLoweringBase() [1/2]

TargetLoweringBase::TargetLoweringBase ( const TargetMachine TM)
explicit

◆ TargetLoweringBase() [2/2]

llvm::TargetLoweringBase::TargetLoweringBase ( const TargetLoweringBase )
delete

◆ ~TargetLoweringBase()

virtual llvm::TargetLoweringBase::~TargetLoweringBase ( )
virtualdefault

Member Function Documentation

◆ addBypassSlowDiv()

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotected

◆ AddPromotedToType()

void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

If that default is insufficient, this method can be used by the target to override the default.

Definition at line 2626 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), setOperationPromotedToType(), and llvm::SITargetLowering::SITargetLowering().

◆ addRegisterClass()

void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotected

Add the specified register class as an available regclass for the specified value type.

This indicates the selector can handle values of that class natively.

Definition at line 2485 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), llvm::XCoreTargetLowering::XCoreTargetLowering(), and llvm::XtensaTargetLowering::XtensaTargetLowering().

◆ aggressivelyPreferBuildVectorSources()

virtual bool llvm::TargetLoweringBase::aggressivelyPreferBuildVectorSources ( EVT  VecVT) const
inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::NVPTXTargetLowering.

Definition at line 3289 of file TargetLowering.h.

◆ alignLoopsWithOptSize()

virtual bool llvm::TargetLoweringBase::alignLoopsWithOptSize ( ) const
inlinevirtual

Should loops be aligned even when the function is marked OptSize (but not MinSize).

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2007 of file TargetLowering.h.

◆ allowsMemoryAccess() [1/3]

bool TargetLoweringBase::allowsMemoryAccess ( LLVMContext Context,
const DataLayout DL,
EVT  VT,
const MachineMemOperand MMO,
unsigned Fast = nullptr 
) const

Return true if the target supports a memory access of this type for the given MachineMemOperand.

If the access is allowed, the optional final parameter returns the relative access speed (as defined by the target).

Definition at line 1855 of file TargetLoweringBase.cpp.

References allowsMemoryAccess(), Context, DL, llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().

◆ allowsMemoryAccess() [2/3]

bool TargetLoweringBase::allowsMemoryAccess ( LLVMContext Context,
const DataLayout DL,
EVT  VT,
unsigned  AddrSpace = 0,
Align  Alignment = Align(1),
MachineMemOperand::Flags  Flags = MachineMemOperand::MONone,
unsigned Fast = nullptr 
) const
virtual

Return true if the target supports a memory access of this type for the given address space and alignment.

If the access is allowed, the optional final parameter returns the relative speed of the access (as defined by the target).

Reimplemented in llvm::HexagonTargetLowering, and llvm::X86TargetLowering.

Definition at line 1846 of file TargetLoweringBase.cpp.

References allowsMemoryAccessForAlignment(), Context, DL, and llvm::CallingConv::Fast.

Referenced by allowsMemoryAccess(), llvm::HexagonTargetLowering::allowsMemoryAccess(), combineLoad(), combineStore(), isLoadBitCastBeneficial(), llvm::LegalizerHelper::lowerLoad(), llvm::LegalizerHelper::lowerStore(), and ShrinkLoadReplaceStoreWithStore().

◆ allowsMemoryAccess() [3/3]

bool TargetLoweringBase::allowsMemoryAccess ( LLVMContext Context,
const DataLayout DL,
LLT  Ty,
const MachineMemOperand MMO,
unsigned Fast = nullptr 
) const

◆ allowsMemoryAccessForAlignment() [1/2]

bool TargetLoweringBase::allowsMemoryAccessForAlignment ( LLVMContext Context,
const DataLayout DL,
EVT  VT,
const MachineMemOperand MMO,
unsigned Fast = nullptr 
) const

Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.

If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).

Definition at line 1839 of file TargetLoweringBase.cpp.

References allowsMemoryAccessForAlignment(), Context, DL, llvm::CallingConv::Fast, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), and llvm::MachineMemOperand::getFlags().

◆ allowsMemoryAccessForAlignment() [2/2]

bool TargetLoweringBase::allowsMemoryAccessForAlignment ( LLVMContext Context,
const DataLayout DL,
EVT  VT,
unsigned  AddrSpace = 0,
Align  Alignment = Align(1),
MachineMemOperand::Flags  Flags = MachineMemOperand::MONone,
unsigned Fast = nullptr 
) const

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.

If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).

Definition at line 1819 of file TargetLoweringBase.cpp.

References allowsMisalignedMemoryAccesses(), Context, DL, llvm::CallingConv::Fast, llvm::EVT::getTypeForEVT(), and llvm::EVT::isZeroSized().

Referenced by allowsMemoryAccess(), allowsMemoryAccessForAlignment(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ allowsMisalignedMemoryAccesses() [1/2]

virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses ( EVT  ,
unsigned  AddrSpace = 0,
Align  Alignment = Align(1),
MachineMemOperand::Flags  Flags = MachineMemOperand::MONone,
unsigned = nullptr 
) const
inlinevirtual

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns a relative speed of the unaligned memory access in the last argument by reference. The higher the speed number the faster the operation comparing to a number returned by another such call. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Reimplemented in llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::Mips16TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, llvm::VETargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::R600TargetLowering, llvm::SITargetLowering, and llvm::MipsSETargetLowering.

Definition at line 1867 of file TargetLowering.h.

Referenced by allowsMemoryAccessForAlignment(), llvm::BasicTTIImplBase< T >::allowsMisalignedMemoryAccesses(), findGISelOptimalMemOpLowering(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::AMDGPUTargetLowering::performLoadCombine(), and llvm::AMDGPUTargetLowering::performStoreCombine().

◆ allowsMisalignedMemoryAccesses() [2/2]

virtual bool llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses ( LLT  ,
unsigned  AddrSpace = 0,
Align  Alignment = Align(1),
MachineMemOperand::Flags  Flags = MachineMemOperand::MONone,
unsigned = nullptr 
) const
inlinevirtual

LLT handling variant.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 1875 of file TargetLowering.h.

◆ allowTruncateForTailCall()

virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall ( Type FromTy,
Type ToTy 
) const
inlinevirtual

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.

Reimplemented in llvm::SystemZTargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, and llvm::X86TargetLowering.

Definition at line 2890 of file TargetLowering.h.

Referenced by getNoopInput().

◆ areJTsAllowed()

virtual bool llvm::TargetLoweringBase::areJTsAllowed ( const Function Fn) const
inlinevirtual

◆ areTwoSDNodeTargetMMOFlagsMergeable()

virtual bool llvm::TargetLoweringBase::areTwoSDNodeTargetMMOFlagsMergeable ( const MemSDNode NodeX,
const MemSDNode NodeY 
) const
inlinevirtual

Return true if it is valid to merge the TargetMMOFlags in two SDNodes.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 742 of file TargetLowering.h.

◆ canCombineStoreAndExtract()

virtual bool llvm::TargetLoweringBase::canCombineStoreAndExtract ( Type VectorTy,
Value Idx,
unsigned Cost 
) const
inlinevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 931 of file TargetLowering.h.

◆ canCombineTruncStore()

virtual bool llvm::TargetLoweringBase::canCombineTruncStore ( EVT  ValVT,
EVT  MemVT,
bool  LegalOnly 
) const
inlinevirtual

Reimplemented in llvm::R600TargetLowering.

Definition at line 1483 of file TargetLowering.h.

References isTruncStoreLegal(), and isTruncStoreLegalOrCustom().

◆ canMergeStoresTo()

virtual bool llvm::TargetLoweringBase::canMergeStoresTo ( unsigned  AS,
EVT  MemVT,
const MachineFunction MF 
) const
inlinevirtual

Returns if it's reasonable to merge stores to MemVT size.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::X86TargetLowering, llvm::R600TargetLowering, and llvm::SITargetLowering.

Definition at line 681 of file TargetLowering.h.

◆ canOpTrap()

bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtual

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.

Definition at line 1027 of file TargetLoweringBase.cpp.

References assert(), isTypeLegal(), llvm::ISD::SDIV, llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.

◆ computeRegisterProperties()

void TargetLoweringBase::computeRegisterProperties ( const TargetRegisterInfo TRI)
protected

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1379 of file TargetLoweringBase.cpp.

References assert(), findRepresentativeClass(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::MVT::getPow2VectorType(), getPreferredVectorAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), getVectorTypeBreakdownMVT(), llvm::isPowerOf2_32(), llvm::MVT::isScalableVector(), isTypeLegal(), llvm_unreachable, llvm::MVT::MAX_ALLOWED_VALUETYPE, llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), softPromoteHalfType(), TRI, TypeExpandFloat, TypeExpandInteger, TypePromoteFloat, TypePromoteInteger, TypeScalarizeScalableVector, TypeScalarizeVector, TypeSoftenFloat, TypeSoftPromoteHalf, TypeSplitVector, TypeWidenVector, useFPRegsForHalfType(), and llvm::MVT::VALUETYPE_SIZE.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::VETargetLowering::VETargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), llvm::XCoreTargetLowering::XCoreTargetLowering(), and llvm::XtensaTargetLowering::XtensaTargetLowering().

◆ convertSelectOfConstantsToMath()

virtual bool llvm::TargetLoweringBase::convertSelectOfConstantsToMath ( EVT  VT) const
inlinevirtual

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.

For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 2362 of file TargetLowering.h.

Referenced by shouldConvertSelectOfConstantsToMath().

◆ convertSetCCLogicToBitwiseLogic()

virtual bool llvm::TargetLoweringBase::convertSetCCLogicToBitwiseLogic ( EVT  VT) const
inlinevirtual

Use bitwise logic to make pairs of compares more efficient.

For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 752 of file TargetLowering.h.

◆ createComplexDeinterleavingIR()

virtual Value * llvm::TargetLoweringBase::createComplexDeinterleavingIR ( IRBuilderBase B,
ComplexDeinterleavingOperation  OperationType,
ComplexDeinterleavingRotation  Rotation,
Value InputA,
Value InputB,
Value Accumulator = nullptr 
) const
inlinevirtual

Create the IR node for the given complex deinterleaving operation.

If one cannot be created using all the given inputs, nullptr should be returned.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3335 of file TargetLowering.h.

◆ decomposeMulByConstant()

virtual bool llvm::TargetLoweringBase::decomposeMulByConstant ( LLVMContext Context,
EVT  VT,
SDValue  C 
) const
inlinevirtual

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.

This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 2371 of file TargetLowering.h.

◆ emitAtomicCmpXchgNoStoreLLBalance()

virtual void llvm::TargetLoweringBase::emitAtomicCmpXchgNoStoreLLBalance ( IRBuilderBase Builder) const
inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2235 of file TargetLowering.h.

◆ emitBitTestAtomicRMWIntrinsic()

virtual void llvm::TargetLoweringBase::emitBitTestAtomicRMWIntrinsic ( AtomicRMWInst AI) const
inlinevirtual

Perform a bit test atomicrmw using a target-specific intrinsic.

This represents the combined bit test intrinsic which will be lowered at a late stage by the backend.

Definition at line 2166 of file TargetLowering.h.

References llvm_unreachable.

◆ emitCmpArithAtomicRMWIntrinsic()

virtual void llvm::TargetLoweringBase::emitCmpArithAtomicRMWIntrinsic ( AtomicRMWInst AI) const
inlinevirtual

Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.

This represents the combined atomic and compare intrinsic which will be lowered at a late stage by the backend.

Definition at line 2174 of file TargetLowering.h.

References llvm_unreachable.

◆ emitExpandAtomicRMW()

virtual void llvm::TargetLoweringBase::emitExpandAtomicRMW ( AtomicRMWInst AI) const
inlinevirtual

Perform a atomicrmw expansion using a target-specific way.

This is expected to be called when masked atomicrmw and bit test atomicrmw don't work, and the target supports another way to lower atomicrmw.

Reimplemented in llvm::SITargetLowering.

Definition at line 2158 of file TargetLowering.h.

References llvm_unreachable.

◆ EmitKCFICheck()

virtual MachineInstr * llvm::TargetLoweringBase::EmitKCFICheck ( MachineBasicBlock MBB,
MachineBasicBlock::instr_iterator MBBI,
const TargetInstrInfo TII 
) const
inlinevirtual

◆ emitLeadingFence()

Instruction * TargetLoweringBase::emitLeadingFence ( IRBuilderBase Builder,
Instruction Inst,
AtomicOrdering  Ord 
) const
virtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.

Inst is the original atomic instruction, prior to other expansions that may be performed.

This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later.

The default implementation emits an IR fence before any release (or stronger) operation that stores, and after any acquire (or stronger) operation. This is generally a correct implementation, but backends may override if they wish to use alternative schemes (e.g. the PowerPC standard ABI uses a fence before a seq_cst load instead of after a seq_cst store).

Reimplemented in llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::VETargetLowering.

Definition at line 2399 of file TargetLoweringBase.cpp.

References llvm::IRBuilderBase::CreateFence(), llvm::Instruction::hasAtomicStore(), and llvm::isReleaseOrStronger().

◆ emitLoadLinked()

virtual Value * llvm::TargetLoweringBase::emitLoadLinked ( IRBuilderBase Builder,
Type ValueTy,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2131 of file TargetLowering.h.

References llvm_unreachable.

◆ emitMaskedAtomicCmpXchgIntrinsic()

virtual Value * llvm::TargetLoweringBase::emitMaskedAtomicCmpXchgIntrinsic ( IRBuilderBase Builder,
AtomicCmpXchgInst CI,
Value AlignedAddr,
Value CmpVal,
Value NewVal,
Value Mask,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a masked cmpxchg using a target-specific intrinsic.

This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2183 of file TargetLowering.h.

References llvm_unreachable.

◆ emitMaskedAtomicRMWIntrinsic()

virtual Value * llvm::TargetLoweringBase::emitMaskedAtomicRMWIntrinsic ( IRBuilderBase Builder,
AtomicRMWInst AI,
Value AlignedAddr,
Value Incr,
Value Mask,
Value ShiftAmt,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a masked atomicrmw using a target-specific intrinsic.

This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.

Reimplemented in llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2147 of file TargetLowering.h.

References llvm_unreachable.

◆ emitPatchPoint()

MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr MI,
MachineBasicBlock MBB 
) const
protected

◆ emitStoreConditional()

virtual Value * llvm::TargetLoweringBase::emitStoreConditional ( IRBuilderBase Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtual

Perform a store-conditional operation to Addr.

Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2138 of file TargetLowering.h.

References llvm_unreachable.

◆ emitTrailingFence()

Instruction * TargetLoweringBase::emitTrailingFence ( IRBuilderBase Builder,
Instruction Inst,
AtomicOrdering  Ord 
) const
virtual

◆ enableAggressiveFMAFusion() [1/2]

virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( EVT  VT) const
inlinevirtual

Return true if target always benefits from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::NVPTXTargetLowering, and llvm::PPCTargetLowering.

Definition at line 954 of file TargetLowering.h.

◆ enableAggressiveFMAFusion() [2/2]

virtual bool llvm::TargetLoweringBase::enableAggressiveFMAFusion ( LLT  Ty) const
inlinevirtual

Return true if target always benefits from combining into FMA for a given value type.

This must typically return false on targets where FMA takes more cycles to execute than FADD.

Reimplemented in llvm::SITargetLowering.

Definition at line 959 of file TargetLowering.h.

◆ enableExtLdPromotion()

bool llvm::TargetLoweringBase::enableExtLdPromotion ( ) const
inline

Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

Definition at line 926 of file TargetLowering.h.

References EnableExtLdPromotion.

◆ fallBackToDAGISel()

virtual bool llvm::TargetLoweringBase::fallBackToDAGISel ( const Instruction Inst) const
inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.

Definition at line 641 of file TargetLowering.h.

◆ finalizeLowering()

void TargetLoweringBase::finalizeLowering ( MachineFunction MF) const
virtual

Execute target specific actions to finalize target lowering.

This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.

Reimplemented in llvm::SITargetLowering, llvm::ARMTargetLowering, and llvm::SPIRVTargetLowering.

Definition at line 2338 of file TargetLoweringBase.cpp.

References llvm::MachineRegisterInfo::freezeReservedRegs(), and llvm::MachineFunction::getRegInfo().

Referenced by llvm::SITargetLowering::finalizeLowering(), llvm::ARMTargetLowering::finalizeLowering(), llvm::SPIRVTargetLowering::finalizeLowering(), INITIALIZE_PASS(), and llvm::InstructionSelect::runOnMachineFunction().

◆ findRepresentativeClass()

std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass ( const TargetRegisterInfo TRI,
MVT  VT 
) const
protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 1352 of file TargetLoweringBase.cpp.

References isLegalRC(), llvm::SuperRegClassIterator::isValid(), llvm::BitVector::set_bits(), llvm::BitVector::setBitsInMask(), llvm::MVT::SimpleTy, and TRI.

Referenced by computeRegisterProperties(), llvm::ARMTargetLowering::findRepresentativeClass(), and llvm::X86TargetLowering::findRepresentativeClass().

◆ generateFMAsInMachineCombiner()

virtual bool llvm::TargetLoweringBase::generateFMAsInMachineCombiner ( EVT  VT,
CodeGenOptLevel  OptLevel 
) const
inlinevirtual

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 3213 of file TargetLowering.h.

◆ getABIAlignmentForCallingConv()

virtual Align llvm::TargetLoweringBase::getABIAlignmentForCallingConv ( Type ArgTy,
const DataLayout DL 
) const
inlinevirtual

Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.

Reimplemented in llvm::ARMTargetLowering, and llvm::MipsTargetLowering.

Definition at line 1759 of file TargetLowering.h.

References DL.

Referenced by llvm::TargetLowering::LowerCallTo().

◆ getAddrModeArguments()

virtual bool llvm::TargetLoweringBase::getAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value * > &  ,
Type *&   
) const
inlinevirtual

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Reimplemented in llvm::SITargetLowering.

Definition at line 2718 of file TargetLowering.h.

◆ getAsmOperandValueType()

virtual EVT llvm::TargetLoweringBase::getAsmOperandValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inlinevirtual

◆ getAtomicMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getAtomicMemOperandFlags ( const Instruction AI,
const DataLayout DL 
) const

◆ getBooleanContents() [1/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inline

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 984 of file TargetLowering.h.

Referenced by combineSelectAsExtAnd(), llvm::SelectionDAG::computeKnownBits(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::GISelKnownBits::computeNumSignBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandIntMINMAX(), extractBooleanFlip(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldSetCC(), getAsCarry(), llvm::SelectionDAG::getBoolConstant(), getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::getICmpTrueVal(), llvm::isConstFalseVal(), llvm::TargetLowering::isConstFalseVal(), llvm::isConstTrueVal(), llvm::TargetLowering::isConstTrueVal(), llvm::TargetLowering::isExtendedTrueVal(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SDPatternMatch::m_False(), llvm::SDPatternMatch::m_True(), promoteTargetBoolean(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::TargetLowering::SimplifySetCC().

◆ getBooleanContents() [2/2]

BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inline

Definition at line 990 of file TargetLowering.h.

References getBooleanContents().

◆ getBypassSlowDivWidths()

const DenseMap< unsigned int, unsigned int > & llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inline

Returns map of slow types for division or remainder with corresponding fast types.

Definition at line 588 of file TargetLowering.h.

◆ getByValTypeAlignment()

uint64_t TargetLoweringBase::getByValTypeAlignment ( Type Ty,
const DataLayout DL 
) const
virtual

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

This is the actual alignment, not its logarithm.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 1814 of file TargetLoweringBase.cpp.

References DL.

Referenced by llvm::FastISel::lowerCallTo(), and llvm::TargetLowering::LowerCallTo().

◆ getCmpLibcallCC()

ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inline

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 3368 of file TargetLowering.h.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCmpLibcallReturnType()

MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtual

Return the ValueType for comparison libcalls.

Comparison libcalls include floating point comparison calls, and Ordered/Unordered check calls on floating point numbers.

Reimplemented in llvm::AVRTargetLowering, and llvm::MSP430TargetLowering.

Definition at line 1636 of file TargetLoweringBase.cpp.

Referenced by llvm::TargetLowering::softenSetCCOperands().

◆ getCondCodeAction()

LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1573 of file TargetLowering.h.

References assert(), CC, Promote, and llvm::MVT::SimpleTy.

Referenced by isCondCodeLegal(), isCondCodeLegalOrCustom(), and llvm::TargetLowering::LegalizeSetCCCondCode().

◆ getCustomCtpopCost()

virtual unsigned llvm::TargetLoweringBase::getCustomCtpopCost ( EVT  VT,
ISD::CondCode  Cond 
) const
inlinevirtual

Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 708 of file TargetLowering.h.

Referenced by simplifySetCCWithCTPOP().

◆ getCustomOperationAction()

virtual LegalizeAction llvm::TargetLoweringBase::getCustomOperationAction ( SDNode Op) const
inlinevirtual

How to legalize this custom operation?

Reimplemented in llvm::VETargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1243 of file TargetLowering.h.

References Legal.

◆ getDefaultSafeStackPointerLocation()

Value * TargetLoweringBase::getDefaultSafeStackPointerLocation ( IRBuilderBase IRB,
bool  UseTLS 
) const
protected

◆ getDivRefinementSteps()

int TargetLoweringBase::getDivRefinementSteps ( EVT  VT,
MachineFunction MF 
) const

Return the refinement step count for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2305 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

◆ getExceptionPointerRegister()

virtual Register llvm::TargetLoweringBase::getExceptionPointerRegister ( const Constant PersonalityFn) const
inlinevirtual

◆ getExceptionSelectorRegister()

virtual Register llvm::TargetLoweringBase::getExceptionSelectorRegister ( const Constant PersonalityFn) const
inlinevirtual

◆ getExtendForAtomicCmpSwapArg()

virtual ISD::NodeType llvm::TargetLoweringBase::getExtendForAtomicCmpSwapArg ( ) const
inlinevirtual

Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

This is separate from getExtendForAtomicOps, which is concerned with the sign-extension of the instruction's output, whereas here we are concerned with the sign-extension of the input. For targets with compare-and-swap instructions (or sub-word comparisons in their LL/SC loop expansions), the input can be ANY_EXTEND, but the output will still have a specific extension.

Reimplemented in llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 2333 of file TargetLowering.h.

References llvm::ISD::ANY_EXTEND.

◆ getExtendForAtomicOps()

virtual ISD::NodeType llvm::TargetLoweringBase::getExtendForAtomicOps ( ) const
inlinevirtual

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

Reimplemented in llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::VETargetLowering.

Definition at line 2321 of file TargetLowering.h.

References llvm::ISD::ZERO_EXTEND.

Referenced by llvm::SelectionDAG::computeKnownBits(), and llvm::SelectionDAG::ComputeNumSignBits().

◆ getExtendForContent()

static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestatic

◆ getFenceOperandTy()

virtual MVT llvm::TargetLoweringBase::getFenceOperandTy ( const DataLayout DL) const
inlinevirtual

Return the type for operands of fence.

TODO: Let fence operands be of i32 type and remove this.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 392 of file TargetLowering.h.

References DL, and getPointerTy().

◆ getFixedPointOperationAction()

LegalizeAction llvm::TargetLoweringBase::getFixedPointOperationAction ( unsigned  Op,
EVT  VT,
unsigned  Scale 
) const
inline

Some fixed point operations may be natively supported by the target but only for specific scales.

This method allows for checking if the width is supported by the target for a given operation that may depend on scale.

Definition at line 1271 of file TargetLowering.h.

References Expand, getOperationAction(), isSupportedFixedPointOperation(), Legal, llvm_unreachable, llvm::ISD::SDIVFIX, llvm::ISD::SDIVFIXSAT, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::UDIVFIX, llvm::ISD::UDIVFIXSAT, llvm::ISD::UMULFIX, and llvm::ISD::UMULFIXSAT.

Referenced by expandDivFix().

◆ getFrameIndexTy()

MVT llvm::TargetLoweringBase::getFrameIndexTy ( const DataLayout DL) const
inline

Return the type for frame index, which is determined by the alloca address space specified through the data layout.

Definition at line 380 of file TargetLowering.h.

References DL, and getPointerTy().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), getAddressForMemoryInput(), llvm::SelectionDAGBuilder::getFrameIndexTy(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), and llvm::TargetLowering::LowerCallTo().

◆ getGatherAllAliasesMaxDepth()

unsigned llvm::TargetLoweringBase::getGatherAllAliasesMaxDepth ( ) const
inline

Definition at line 1799 of file TargetLowering.h.

References GatherAllAliasesMaxDepth.

◆ getIndexedLoadAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1494 of file TargetLowering.h.

Referenced by isIndexedLoadLegal().

◆ getIndexedMaskedLoadAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedMaskedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1522 of file TargetLowering.h.

Referenced by isIndexedMaskedLoadLegal().

◆ getIndexedMaskedStoreAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedMaskedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1536 of file TargetLowering.h.

Referenced by isIndexedMaskedStoreLegal().

◆ getIndexedStoreAction()

LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inline

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1508 of file TargetLowering.h.

Referenced by isIndexedStoreLegal().

◆ getIRStackGuard()

Value * TargetLoweringBase::getIRStackGuard ( IRBuilderBase IRB) const
virtual

If the target has a standard location for the stack protector guard, returns the address of that location.

Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize @llvm.stackguard().

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 2049 of file TargetLoweringBase.cpp.

References llvm::CallingConv::C, G, llvm::IRBuilderBase::GetInsertBlock(), llvm::GlobalValue::getParent(), llvm::BasicBlock::getParent(), getTargetMachine(), llvm::PointerType::getUnqual(), and llvm::GlobalValue::HiddenVisibility.

Referenced by llvm::AArch64TargetLowering::getIRStackGuard(), llvm::RISCVTargetLowering::getIRStackGuard(), llvm::X86TargetLowering::getIRStackGuard(), and getStackGuard().

◆ getJumpConditionMergingParams()

virtual CondMergingParams llvm::TargetLoweringBase::getJumpConditionMergingParams ( Instruction::BinaryOps  ,
const Value ,
const Value  
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 629 of file TargetLowering.h.

◆ getLibcallCallingConv()

CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inline

◆ getLibcallName()

const char * llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inline

◆ getLoadExtAction()

LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1434 of file TargetLowering.h.

References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::ISD::LAST_LOADEXT_TYPE, llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.

Referenced by isLoadExtLegal(), and isLoadExtLegalOrCustom().

◆ getLoadMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags ( const LoadInst LI,
const DataLayout DL,
AssumptionCache AC = nullptr,
const TargetLibraryInfo LibInfo = nullptr 
) const

◆ getMaxAtomicSizeInBitsSupported()

unsigned llvm::TargetLoweringBase::getMaxAtomicSizeInBitsSupported ( ) const
inline

Returns the maximum atomic operation size (in bits) supported by the backend.

Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Definition at line 2085 of file TargetLowering.h.

Referenced by atomicSizeSupported().

◆ getMaxDivRemBitWidthSupported()

unsigned llvm::TargetLoweringBase::getMaxDivRemBitWidthSupported ( ) const
inline

Returns the size in bits of the maximum div/rem the backend supports.

Larger operations will be expanded by ExpandLargeDivRem.

Definition at line 2091 of file TargetLowering.h.

Referenced by runImpl().

◆ getMaxExpandSizeMemcmp()

unsigned llvm::TargetLoweringBase::getMaxExpandSizeMemcmp ( bool  OptSize) const
inline

Get maximum # of load operations permitted for memcmp.

This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1843 of file TargetLowering.h.

References MaxLoadsPerMemcmp, and MaxLoadsPerMemcmpOptSize.

Referenced by llvm::AArch64TTIImpl::enableMemCmpExpansion(), llvm::BPFTTIImpl::enableMemCmpExpansion(), llvm::PPCTTIImpl::enableMemCmpExpansion(), and llvm::X86TTIImpl::enableMemCmpExpansion().

◆ getMaxGluedStoresPerMemcpy()

virtual unsigned llvm::TargetLoweringBase::getMaxGluedStoresPerMemcpy ( ) const
inlinevirtual

Get maximum # of store operations to be glued together.

This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by

Definition at line 1833 of file TargetLowering.h.

References MaxGluedStoresPerMemcpy.

Referenced by getMemcpyLoadsAndStores().

◆ getMaximumJumpTableSize()

unsigned TargetLoweringBase::getMaximumJumpTableSize ( ) const

Return upper limit for number of entries in a jump table.

Zero if no limit.

Definition at line 2101 of file TargetLoweringBase.cpp.

References MaximumJumpTableSize.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), and isSuitableForJumpTable().

◆ getMaxLargeFPConvertBitWidthSupported()

unsigned llvm::TargetLoweringBase::getMaxLargeFPConvertBitWidthSupported ( ) const
inline

Returns the size in bits of the maximum larget fp convert the backend supports.

Larger operations will be expanded by ExpandLargeFPConvert.

Definition at line 2097 of file TargetLowering.h.

Referenced by runImpl().

◆ getMaxPermittedBytesForAlignment()

unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment ( MachineBasicBlock MBB) const
virtual

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

Definition at line 2119 of file TargetLoweringBase.cpp.

◆ getMaxStoresPerMemcpy()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1824 of file TargetLowering.h.

References MaxStoresPerMemcpy, and MaxStoresPerMemcpyOptSize.

Referenced by getMemcpyLoadsAndStores(), llvm::ARMTTIImpl::getNumMemOps(), and llvm::LegalizerHelper::lowerMemCpyFamily().

◆ getMaxStoresPerMemmove()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1853 of file TargetLowering.h.

References MaxStoresPerMemmove, and MaxStoresPerMemmoveOptSize.

Referenced by getMemmoveLoadsAndStores(), and llvm::ARMTTIImpl::getNumMemOps().

◆ getMaxStoresPerMemset()

unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inline

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 1814 of file TargetLowering.h.

References MaxStoresPerMemset, and MaxStoresPerMemsetOptSize.

Referenced by getMemsetStores(), and llvm::ARMTTIImpl::getNumMemOps().

◆ getMaxSupportedInterleaveFactor()

virtual unsigned llvm::TargetLoweringBase::getMaxSupportedInterleaveFactor ( ) const
inlinevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3053 of file TargetLowering.h.

Referenced by llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().

◆ getMemValueType()

EVT llvm::TargetLoweringBase::getMemValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

◆ getMinCmpXchgSizeInBits()

unsigned llvm::TargetLoweringBase::getMinCmpXchgSizeInBits ( ) const
inline

Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.

Any smaller operations are widened in AtomicExpandPass.

Note that unlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.

Definition at line 2108 of file TargetLowering.h.

Referenced by llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode().

◆ getMinFunctionAlignment()

Align llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inline

Return the minimum function alignment.

Definition at line 1992 of file TargetLowering.h.

◆ getMinimumJumpTableDensity()

unsigned TargetLoweringBase::getMinimumJumpTableDensity ( bool  OptForSize) const

Return lower limit of the density in a jump table.

Definition at line 2097 of file TargetLoweringBase.cpp.

References JumpTableDensity, and OptsizeJumpTableDensity.

Referenced by isSuitableForJumpTable().

◆ getMinimumJumpTableEntries()

unsigned TargetLoweringBase::getMinimumJumpTableEntries ( ) const
virtual

Return lower limit for number of blocks in a jump table.

Reimplemented in llvm::VETargetLowering.

Definition at line 2089 of file TargetLoweringBase.cpp.

References MinimumJumpTableEntries.

Referenced by llvm::SwitchCG::SwitchLowering::findJumpTables(), and llvm::VETargetLowering::getMinimumJumpTableEntries().

◆ getMinStackArgumentAlignment()

Align llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inline

Return the minimum stack alignment of an argument.

Definition at line 1987 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::expandVAArg(), and llvm::LegalizerHelper::lowerVAArg().

◆ getNumRegisters()

virtual unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT,
std::optional< MVT RegisterVT = std::nullopt 
) const
inlinevirtual

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

RegisterVT may be passed as a way to override the default settings, for instance with i128 inline assembly operands on SystemZ.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 1719 of file TargetLowering.h.

References assert(), llvm::BitWidth, Context, getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::computeLegalValueVTs(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FunctionLoweringInfo::CreateRegs(), llvm::SystemZTargetLowering::getNumRegisters(), getNumRegistersForCallingConv(), llvm::MipsTargetLowering::getNumRegistersForCallingConv(), llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(), getRegistersForValue(), llvm::BasicTTIImplBase< T >::getRegUsageForType(), llvm::FunctionLoweringInfo::getValueFromVirtualReg(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::FastISel::lowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RegsForValue::RegsForValue(), llvm::FastISel::selectExtractValue(), and llvm::FunctionLoweringInfo::set().

◆ getNumRegistersForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getNumRegistersForCallingConv ( LLVMContext Context,
CallingConv::ID  CC,
EVT  VT 
) const
inlinevirtual

◆ getOperationAction()

LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inline

◆ getOptimalMemOpLLT()

virtual LLT llvm::TargetLoweringBase::getOptimalMemOpLLT ( const MemOp Op,
const AttributeList  
) const
inlinevirtual

LLT returning variant.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1936 of file TargetLowering.h.

Referenced by findGISelOptimalMemOpLowering().

◆ getOptimalMemOpType()

virtual EVT llvm::TargetLoweringBase::getOptimalMemOpType ( const MemOp Op,
const AttributeList  
) const
inlinevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 1929 of file TargetLowering.h.

Referenced by llvm::TargetLowering::findOptimalMemOpLowering().

◆ getPointerMemTy()

virtual MVT llvm::TargetLoweringBase::getPointerMemTy ( const DataLayout DL,
uint32_t  AS = 0 
) const
inlinevirtual

Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Reimplemented in llvm::WebAssemblyTargetLowering.

Definition at line 374 of file TargetLowering.h.

References DL, and llvm::MVT::getIntegerVT().

Referenced by getLoadStackGuard(), getMemValueType(), llvm::WebAssemblyTargetLowering::getPointerMemTy(), llvm::SITargetLowering::getPointerMemTy(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getPointerTy()

virtual MVT llvm::TargetLoweringBase::getPointerTy ( const DataLayout DL,
uint32_t  AS = 0 
) const
inlinevirtual

Return the pointer type for the given address space, defaults to the pointer type from the data layout.

FIXME: The default needs to be removed once all the code is updated.

Reimplemented in llvm::AArch64TargetLowering, and llvm::WebAssemblyTargetLowering.

Definition at line 367 of file TargetLowering.h.

References DL, and llvm::MVT::getIntegerVT().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::X86TargetLowering::BuildFILD(), CheckType(), CheckValueType(), combineConcatVectorOps(), combineGatherScatter(), combineLoad(), combineStore(), combineTargetShuffle(), llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), createMMXBuildVector(), createSetFPEnvNodes(), llvm::TargetLowering::CTTZTableLookup(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), llvm::TargetLowering::forceExpandWideMUL(), getADAEntry(), getAddressForMemoryInput(), llvm::SelectionDAG::getAtomicMemcpy(), llvm::SelectionDAG::getAtomicMemmove(), llvm::SelectionDAG::getAtomicMemset(), getAVX2GatherNode(), getCopyFromParts(), getFenceOperandTy(), getFrameIndexTy(), getGatherNode(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getJumpTableDebugInfo(), getLoadStackGuard(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), llvm::SwiftErrorValueTracking::getOrCreateVReg(), llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::WebAssemblyTargetLowering::getPointerTy(), llvm::SITargetLowering::getPointerTy(), getPrefetchNode(), getProgramPointerTy(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForGEPIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getScatterNode(), getSetCCResultType(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::LoongArchTargetLowering::getSetCCResultType(), llvm::RISCVTargetLowering::getSetCCResultType(), getShiftAmountTy(), llvm::SelectionDAG::getSymbolFunctionGlobalAddress(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), getUniformBase(), getVaListSizeInBits(), llvm::SelectionDAGBuilder::getValueImpl(), getValueType(), getVectorIdxTy(), getzOSCalleeAndADA(), isBLACompatibleAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::TargetLowering::LowerCallTo(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCTPOP(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFRAMEADDR(), LowerFSINCOS(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::R600TargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::SparcTargetLowering::makeAddress(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), llvm::SelectionDAG::makeStateFunctionCall(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformTruncatingStoreCombine(), llvm::SwiftErrorValueTracking::propagateVRegs(), recoverFramePointer(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FastISel::selectGetElementPtr(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), transformCallee(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getPreferredLargeGEPBaseOffset()

virtual int64_t llvm::TargetLoweringBase::getPreferredLargeGEPBaseOffset ( int64_t  MinOffset,
int64_t  MaxOffset 
) const
inlinevirtual

Return the prefered common base offset.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2754 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::getPreferredLargeGEPBaseOffset().

◆ getPreferredShiftAmountTy()

virtual LLVM_READONLY LLT llvm::TargetLoweringBase::getPreferredShiftAmountTy ( LLT  ShiftValueTy) const
inlinevirtual

◆ getPreferredSwitchConditionType()

MVT TargetLoweringBase::getPreferredSwitchConditionType ( LLVMContext Context,
EVT  ConditionVT 
) const
virtual

Returns preferred type for switch condition.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1760 of file TargetLoweringBase.cpp.

References Context, and getRegisterType().

Referenced by llvm::X86TargetLowering::getPreferredSwitchConditionType().

◆ getPreferredVectorAction()

virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( MVT  VT) const
inlinevirtual

◆ getPrefFunctionAlignment()

Align llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inline

Return the preferred function alignment.

Definition at line 1995 of file TargetLowering.h.

◆ getPrefLoopAlignment()

Align TargetLoweringBase::getPrefLoopAlignment ( MachineLoop ML = nullptr) const
virtual

◆ getProgramPointerTy()

MVT llvm::TargetLoweringBase::getProgramPointerTy ( const DataLayout DL) const
inline

Return the type for code pointers, which is determined by the program address space specified through the data layout.

Definition at line 386 of file TargetLowering.h.

References DL, and getPointerTy().

◆ getRecipEstimateDivEnabled()

int TargetLoweringBase::getRecipEstimateDivEnabled ( EVT  VT,
MachineFunction MF 
) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2295 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

◆ getRecipEstimateSqrtEnabled()

int TargetLoweringBase::getRecipEstimateSqrtEnabled ( EVT  VT,
MachineFunction MF 
) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2290 of file TargetLoweringBase.cpp.

References getOpEnabled(), and getRecipEstimateForFunc().

◆ getRegClassFor()

virtual const TargetRegisterClass * llvm::TargetLoweringBase::getRegClassFor ( MVT  VT,
bool  isDivergent = false 
) const
inlinevirtual

◆ getRegisterType() [1/2]

MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inline

Return the type of registers that this ValueType will eventually require.

Definition at line 1690 of file TargetLowering.h.

References Context, getRegisterType(), llvm::EVT::getSimpleVT(), getTypeToTransformTo(), getVectorTypeBreakdown(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), and llvm_unreachable.

◆ getRegisterType() [2/2]

MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inline

◆ getRegisterTypeForCallingConv()

virtual MVT llvm::TargetLoweringBase::getRegisterTypeForCallingConv ( LLVMContext Context,
CallingConv::ID  CC,
EVT  VT 
) const
inlinevirtual

◆ getRepRegClassCostFor()

virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtual

Return the cost of the 'representative' register class for the specified value type.

Definition at line 1051 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef().

◆ getRepRegClassFor()

virtual const TargetRegisterClass * llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtual

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 1044 of file TargetLowering.h.

References llvm::MVT::SimpleTy.

Referenced by GetCostForDef(), and llvm::MipsSETargetLowering::getRepRegClassFor().

◆ getSafeStackPointerLocation()

Value * TargetLoweringBase::getSafeStackPointerLocation ( IRBuilderBase IRB) const
virtual

◆ getScalarShiftAmountTy()

MVT TargetLoweringBase::getScalarShiftAmountTy ( const DataLayout DL,
EVT   
) const
virtual

Return the type to use for a scalar shift opcode, given the shifted amount type.

Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.

Reimplemented in llvm::AVRTargetLowering, llvm::X86TargetLowering, llvm::SITargetLowering, llvm::BPFTargetLowering, llvm::M68kTargetLowering, llvm::MipsTargetLowering, llvm::MSP430TargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::AArch64TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1006 of file TargetLoweringBase.cpp.

References DL, and llvm::MVT::getIntegerVT().

Referenced by getShiftAmountTy().

◆ getSchedulingPreference() [1/2]

Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inline

Return target scheduling preference.

Definition at line 1009 of file TargetLowering.h.

Referenced by llvm::createDefaultScheduler(), llvm::PPCTargetLowering::getSchedulingPreference(), and llvm::ScheduleDAGSDNodes::newSUnit().

◆ getSchedulingPreference() [2/2]

virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode ) const
inlinevirtual

Some scheduler, e.g.

hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::ARMTargetLowering, and llvm::PPCTargetLowering.

Definition at line 1016 of file TargetLowering.h.

References llvm::Sched::None.

◆ getSDagStackGuard()

Value * TargetLoweringBase::getSDagStackGuard ( const Module M) const
virtual

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.

Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2081 of file TargetLoweringBase.cpp.

Referenced by getLoadStackGuard(), llvm::AArch64TargetLowering::getSDagStackGuard(), llvm::ARMTargetLowering::getSDagStackGuard(), llvm::PPCTargetLowering::getSDagStackGuard(), llvm::X86TargetLowering::getSDagStackGuard(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getSetCCResultType()

EVT TargetLoweringBase::getSetCCResultType ( const DataLayout DL,
LLVMContext Context,
EVT  VT 
) const
virtual

Return the ValueType of the result of SETCC operations.

Reimplemented in llvm::HexagonTargetLowering, llvm::R600TargetLowering, llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, llvm::CSKYTargetLowering, llvm::LoongArchTargetLowering, llvm::M68kTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::NVPTXTargetLowering.

Definition at line 1630 of file TargetLoweringBase.cpp.

References assert(), DL, getPointerTy(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.

Referenced by llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), combineFMinNumFMaxNum(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineVSelectWithAllOnesOrZeros(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), foldXorTruncShiftIntoCmp(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), llvm::AMDGPUTargetLowering::getScaledLogInput(), llvm::TargetLowering::getSqrtInputTest(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerMULO(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), promoteTargetBoolean(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), llvm::SelectionDAG::UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getShiftAmountTy()

EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy,
const DataLayout DL,
bool  LegalTypes = true 
) const

Returns the type for the shift amount of a shift opcode.

For vectors, returns the input type. For scalars, behavior depends on LegalTypes. If LegalTypes is true, calls getScalarShiftAmountTy, otherwise uses pointer type. If getScalarShiftAmountTy or pointer type cannot represent all possible shift amounts, returns MVT::i32. In general, LegalTypes should be set to true for calls during type legalization and after type legalization has been completed.

Definition at line 1011 of file TargetLoweringBase.cpp.

References assert(), DL, getPointerTy(), getScalarShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::isInteger(), llvm::EVT::isVector(), and llvm::Log2_32_Ceil().

Referenced by BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), expandDivFix(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), getCopyFromParts(), GetExponent(), getLimitedPrecisionExp2(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getShiftAmountOperand(), and llvm::AMDGPUTargetLowering::performTruncateCombine().

◆ getSimpleValueType()

MVT llvm::TargetLoweringBase::getSimpleValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 1673 of file TargetLowering.h.

References DL, llvm::EVT::getSimpleVT(), and getValueType().

Referenced by llvm::InlineAsmLowering::lowerInlineAsm(), and llvm::TargetLowering::ParseConstraints().

◆ getSqrtRefinementSteps()

int TargetLoweringBase::getSqrtRefinementSteps ( EVT  VT,
MachineFunction MF 
) const

Return the refinement step count for a square root of the given type based on the function's attributes.

If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Definition at line 2300 of file TargetLoweringBase.cpp.

References getOpRefinementSteps(), and getRecipEstimateForFunc().

◆ getSSPStackGuardCheck()

Function * TargetLoweringBase::getSSPStackGuardCheck ( const Module M) const
virtual

If the target has a standard stack protection check function that performs validation and error handling, returns the function.

Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 2085 of file TargetLoweringBase.cpp.

Referenced by llvm::AArch64TargetLowering::getSSPStackGuardCheck(), llvm::ARMTargetLowering::getSSPStackGuardCheck(), llvm::X86TargetLowering::getSSPStackGuardCheck(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getStackPointerRegisterToSaveRestore()

Register llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inline

◆ getStackProbeSymbolName()

virtual StringRef llvm::TargetLoweringBase::getStackProbeSymbolName ( const MachineFunction MF) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 2050 of file TargetLowering.h.

◆ getStoreMemOperandFlags()

MachineMemOperand::Flags TargetLoweringBase::getStoreMemOperandFlags ( const StoreInst SI,
const DataLayout DL 
) const

◆ getStrictFPOperationAction()

LegalizeAction llvm::TargetLoweringBase::getStrictFPOperationAction ( unsigned  Op,
EVT  VT 
) const
inline

Definition at line 1300 of file TargetLowering.h.

References getOperationAction(), and llvm_unreachable.

◆ getTargetMachine()

const TargetMachine & llvm::TargetLoweringBase::getTargetMachine ( ) const
inline

Definition at line 360 of file TargetLowering.h.

Referenced by llvm::AArch64TTIImpl::areInlineCompatible(), llvm::GCNTTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::WebAssemblyTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areTypesABICompatible(), llvm::ARMTargetLowering::ARMTargetLowering(), checkAddrSpaceIsValidForLibcall(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::finalizeLowering(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::BasicTTIImplBase< T >::getAssumedAddrSpace(), llvm::NVPTXTargetLowering::getDivF32Level(), getIRStackGuard(), llvm::TargetLowering::getJumpTableEncoding(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::X86TargetLowering::getJumpTableEncoding(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getOptimalMemOpType(), llvm::NVPTXTargetLowering::getParamName(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr(), llvm::BasicTTIImplBase< T >::getPredicatedAddrSpace(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getTgtMemIntrinsic(), getTM(), llvm::PPCTargetLowering::isAccessedAsGotIndirect(), llvm::SystemZSubtarget::isAddressedViaADA(), llvm::SITargetLowering::isFreeAddrSpaceCast(), isJumpTableRelative(), llvm::MipsTargetLowering::isJumpTableRelative(), llvm::X86TargetLowering::isLegalAddressingMode(), llvm::BasicTTIImplBase< T >::isNoopAddrSpaceCast(), llvm::TargetLowering::isOffsetFoldingLegal(), llvm::SystemZSubtarget::isPC32DBLSymbol(), llvm::TargetLowering::isPositionIndependent(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), llvm::BasicTTIImplBase< T >::isSingleThreaded(), IsSmallObject(), llvm::M68kCallLowering::lowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), llvm::BasicTTIImplBase< T >::shouldBuildRelLookupTables(), llvm::SITargetLowering::shouldEmitFixup(), llvm::SITargetLowering::shouldEmitGOTReloc(), llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR(), llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(), llvm::HexagonTargetLowering::shouldReduceLoadWidth(), llvm::SITargetLowering::shouldUseLDSConstAddress(), llvm::CSKYSubtarget::useHardFloatABI(), llvm::NVPTXTargetLowering::usePrecSqrtF32(), and llvm::AArch64Subtarget::useSmallAddressing().

◆ getTargetMMOFlags() [1/2]

virtual MachineMemOperand::Flags llvm::TargetLoweringBase::getTargetMMOFlags ( const Instruction I) const
inlinevirtual

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.

The default implementation does nothing.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, and llvm::RISCVTargetLowering.

Definition at line 434 of file TargetLowering.h.

References llvm::MachineMemOperand::MONone.

Referenced by getAtomicMemOperandFlags(), getLoadMemOperandFlags(), and getStoreMemOperandFlags().

◆ getTargetMMOFlags() [2/2]

virtual MachineMemOperand::Flags llvm::TargetLoweringBase::getTargetMMOFlags ( const MemSDNode Node) const
inlinevirtual

This callback is used to inspect load/store SDNode.

The default implementation does nothing.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 441 of file TargetLowering.h.

References llvm::MachineMemOperand::MONone.

◆ getTgtMemIntrinsic()

virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic ( IntrinsicInfo ,
const CallInst ,
MachineFunction ,
unsigned   
) const
inlinevirtual

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::SITargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SPIRVTargetLowering, and llvm::X86TargetLowering.

Definition at line 1206 of file TargetLowering.h.

◆ getTruncStoreAction()

LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 1460 of file TargetLowering.h.

References assert(), Expand, llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::MVT::SimpleTy, and llvm::MVT::VALUETYPE_SIZE.

Referenced by isTruncStoreLegal(), and isTruncStoreLegalOrCustom().

◆ getTypeAction() [1/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inline

◆ getTypeAction() [2/2]

LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inline

◆ getTypeConversion()

TargetLoweringBase::LegalizeKind TargetLoweringBase::getTypeConversion ( LLVMContext Context,
EVT  VT 
) const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.

First: how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Second: for types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 1052 of file TargetLoweringBase.cpp.

References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(), Context, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::EVT::getIntegerVT(), llvm::EVT::getPow2VectorType(), llvm::EVT::getRoundIntegerType(), llvm::ElementCount::getScalable(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), getTypeConversion(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::EVT::isInteger(), llvm::EVT::isPow2VectorType(), llvm::isPowerOf2_32(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::ElementCount::isScalar(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm::MVT::SimpleTy, TypeExpandInteger, TypeLegal, TypePromoteInteger, TypeScalarizeScalableVector, TypeScalarizeVector, TypeSoftenFloat, TypeSoftPromoteHalf, TypeSplitVector, and TypeWidenVector.

Referenced by llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getTypeAction(), getTypeConversion(), llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(), getTypeToTransformTo(), and getVectorTypeBreakdown().

◆ getTypeToExpandTo()

EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inline

For types supported by the target, this is an identity function.

For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 1144 of file TargetLowering.h.

References assert(), Context, getTypeAction(), getTypeToTransformTo(), llvm::EVT::isVector(), llvm_unreachable, TypeExpandInteger, and TypeLegal.

◆ getTypeToPromoteTo()

MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inline

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 1599 of file TargetLowering.h.

References assert(), getOperationAction(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), Promote, and llvm::MVT::SimpleTy.

Referenced by isLoadBitCastBeneficial().

◆ getTypeToTransformTo()

virtual EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

For types supported by the target, this is an identity function.

For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1136 of file TargetLowering.h.

References Context, and getTypeConversion().

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineMinNumMaxNumImpl(), combineShiftToMULH(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getConstant(), getMemcpyLoadsAndStores(), getPTest(), llvm::FastISel::getRegForValue(), getRegisterType(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::BasicTTIImplBase< T >::getStoreMinimumVF(), getTypeToExpandTo(), llvm::X86TargetLowering::getTypeToTransformTo(), getVectorTypeBreakdown(), LowerMSCATTER(), LowerStore(), llvm::VETargetLowering::lowerToVVP(), OptimizeNoopCopyExpression(), llvm::FastISel::selectBinaryOp(), and widenAbs().

◆ getVaListSizeInBits()

virtual unsigned llvm::TargetLoweringBase::getVaListSizeInBits ( const DataLayout DL) const
inlinevirtual

Returns the size of the platform's va_list object.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1804 of file TargetLowering.h.

References DL, getPointerTy(), and llvm::MVT::getSizeInBits().

◆ getValueType()

EVT llvm::TargetLoweringBase::getValueType ( const DataLayout DL,
Type Ty,
bool  AllowUnknown = false 
) const
inline

Return the EVT corresponding to this LLVM type.

This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 1632 of file TargetLowering.h.

References DL, llvm::Type::getContext(), llvm::EVT::getEVT(), getPointerTy(), and llvm::EVT::getVectorVT().

Referenced by analyzeCallOperands(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ComputeValueVTs(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), getAsmOperandValueType(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), llvm::BasicTTIImplBase< T >::getFPOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::ARMTTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::RISCVTTIImpl::getMemoryOpCost(), llvm::AArch64TTIImpl::getMemoryOpCost(), llvm::ARMTTIImpl::getMemoryOpCost(), llvm::PPCTTIImpl::getMemoryOpCost(), llvm::SystemZTTIImpl::getMemoryOpCost(), llvm::X86TTIImpl::getMemoryOpCost(), getMemValueType(), llvm::GCNTTIImpl::getMinMaxReductionCost(), llvm::ARMTTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::ARMTTIImpl::getMulAccReductionCost(), llvm::NVPTXTargetLowering::getPrototype(), llvm::FastISel::getRegForValue(), llvm::BasicTTIImplBase< T >::getRegUsageForType(), llvm::X86TTIImpl::getShuffleCost(), getSimpleValueType(), llvm::BasicTTIImplBase< T >::getStoreMinimumVF(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), llvm::RISCVTargetLowering::getTgtMemIntrinsic(), llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::X86TTIImpl::getVectorInstrCost(), llvm::PPCTTIImpl::getVPMemoryOpCost(), llvm::MipsTTIImpl::hasDivRemOp(), llvm::SystemZTTIImpl::hasDivRemOp(), llvm::X86TTIImpl::hasDivRemOp(), llvm::BasicTTIImplBase< T >::haveFastSqrt(), llvm::RISCVTTIImpl::isElementTypeLegalForScalableVector(), isExtLoad(), llvm::AArch64TTIImpl::isExtPartOfAvgExpr(), llvm::BasicTTIImplBase< T >::isIndexedLoadLegal(), llvm::BasicTTIImplBase< T >::isIndexedStoreLegal(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(), llvm::RISCVTTIImpl::isLegalMaskedLoadStore(), llvm::RISCVTTIImpl::isLegalStridedLoadStore(), llvm::RISCVTTIImpl::isLegalToVectorizeReduction(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), isSupportedType(), llvm::BasicTTIImplBase< T >::isTypeLegal(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::ARMTTIImpl::maybeLoweredToCall(), OptimizeExtractBits(), OptimizeNoopCopyExpression(), llvm::BasicTTIImplBase< T >::preferToKeepConstantsAttached(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectFreeze(), llvm::FastISel::selectOperator(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and SinkShiftAndTruncate().

◆ getValueTypeActions()

const ValueTypeActionImpl & llvm::TargetLoweringBase::getValueTypeActions ( ) const
inline

Definition at line 1099 of file TargetLowering.h.

◆ getVectorIdxTy()

virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( const DataLayout DL) const
inlinevirtual

◆ getVectorTypeBreakdown()

unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned NumIntermediates,
MVT RegisterVT 
) const

Vector types are broken down into some number of legal first class types.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.

For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1648 of file TargetLoweringBase.cpp.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(), Context, llvm::divideCeil(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::ElementCount::getFixed(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getRegisterType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeConversion(), getTypeToTransformTo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::ElementCount::isScalar(), isTypeLegal(), llvm::EVT::isVector(), llvm::report_fatal_error(), TypeLegal, TypePromoteInteger, and TypeWidenVector.

Referenced by getCopyFromPartsVector(), getCopyToPartsVector(), getNumRegisters(), llvm::SelectionDAG::getReducedAlign(), getRegisterType(), and getVectorTypeBreakdownForCallingConv().

◆ getVectorTypeBreakdownForCallingConv()

virtual unsigned llvm::TargetLoweringBase::getVectorTypeBreakdownForCallingConv ( LLVMContext Context,
CallingConv::ID  CC,
EVT  VT,
EVT IntermediateVT,
unsigned NumIntermediates,
MVT RegisterVT 
) const
inlinevirtual

◆ getVPExplicitVectorLengthTy()

virtual MVT llvm::TargetLoweringBase::getVPExplicitVectorLengthTy ( ) const
inlinevirtual

Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.

It must be a legal scalar integer type, and must be at least as large as i32. The EVL is implicitly zero-extended to any larger type.

Definition at line 429 of file TargetLowering.h.

◆ hasAndNot()

virtual bool llvm::TargetLoweringBase::hasAndNot ( SDValue  X) const
inlinevirtual

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

Reimplemented in llvm::AArch64TargetLowering, llvm::LoongArchTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 784 of file TargetLowering.h.

References hasAndNotCompare(), and X.

Referenced by foldVSelectToSignBitSplatMask().

◆ hasAndNotCompare()

virtual bool llvm::TargetLoweringBase::hasAndNotCompare ( SDValue  Y) const
inlinevirtual

Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.

This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.

Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0

Reimplemented in llvm::AArch64TargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 777 of file TargetLowering.h.

Referenced by hasAndNot().

◆ hasBigEndianPartOrdering()

bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT,
const DataLayout DL 
) const
inline

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 1788 of file TargetLowering.h.

References DL.

Referenced by getCopyFromParts(), and llvm::CallLowering::handleAssignments().

◆ hasBitTest()

virtual bool llvm::TargetLoweringBase::hasBitTest ( SDValue  X,
SDValue  Y 
) const
inlinevirtual

Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.

Reimplemented in llvm::HexagonTargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 794 of file TargetLowering.h.

Referenced by combineShiftAnd1ToBitTest(), and shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().

◆ hasExtractBitsInsn()

bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inline

Return true if the target has BitExtract instructions.

Definition at line 493 of file TargetLowering.h.

◆ hasFastEqualityCompare()

virtual MVT llvm::TargetLoweringBase::hasFastEqualityCompare ( unsigned  NumBits) const
inlinevirtual

Return the preferred operand type if the target has a quick way to compare integer values of the given size.

Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.

Reimplemented in llvm::X86TargetLowering.

Definition at line 760 of file TargetLowering.h.

References llvm::MVT::getIntegerVT(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, and isTypeLegal().

◆ hasInlineStackProbe()

virtual bool llvm::TargetLoweringBase::hasInlineStackProbe ( const MachineFunction MF) const
inlinevirtual

◆ hasMultipleConditionRegisters()

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inline

Return true if multiple condition registers are available.

Definition at line 488 of file TargetLowering.h.

Referenced by shouldNormalizeToSelectSequence(), and sinkCmpExpression().

◆ hasPairedLoad()

virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
Align  
) const
inlinevirtual

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 3043 of file TargetLowering.h.

◆ hasStackProbeSymbol()

virtual bool llvm::TargetLoweringBase::hasStackProbeSymbol ( const MachineFunction MF) const
inlinevirtual

Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2046 of file TargetLowering.h.

◆ hasStandaloneRem()

virtual bool llvm::TargetLoweringBase::hasStandaloneRem ( EVT  VT) const
inlinevirtual

Return true if the target can handle a standalone remainder operation.

Reimplemented in llvm::ARMTargetLowering, and llvm::VETargetLowering.

Definition at line 542 of file TargetLowering.h.

◆ hasTargetDAGCombine()

bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inline

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 1794 of file TargetLowering.h.

References assert().

◆ hasVectorBlend()

virtual bool llvm::TargetLoweringBase::hasVectorBlend ( ) const
inlinevirtual

Return true if the target has a vector blend instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3049 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getVectorShuffle().

◆ initActions()

void TargetLoweringBase::initActions ( )
protected

Initialize all of the actions to default values.

Definition at line 815 of file TargetLoweringBase.cpp.

References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ABS, llvm::ISD::ADDC, llvm::ISD::ADDE, AddPromotedToType(), llvm::MVT::all_valuetypes(), llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::BITREVERSE, llvm::ISD::BUILTIN_OP_END, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DEBUGTRAP, llvm::ISD::DELETED_NODE, llvm::enum_seq(), Expand, llvm::ISD::EXTLOAD, llvm::ISD::FCBRT, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FEXP, llvm::ISD::FEXP10, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FFREXP, llvm::ISD::FGETSIGN, llvm::ISD::FLDEXP, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMAD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FNEARBYINT, llvm::force_iteration_on_noniterable_enum, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::MVT::fp_valuetypes(), llvm::ISD::FPOWI, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FTRUNC, llvm::ISD::GET_DYNAMIC_AREA_OFFSET, llvm::ISD::GET_FPENV, llvm::ISD::GET_FPENV_MEM, llvm::ISD::GET_FPMODE, llvm::MVT::getIntegerVT(), llvm::ISD::IS_FPCLASS, llvm::MVT::isValid(), llvm::ISD::LAST_INDEXED_MODE, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LRINT, llvm::ISD::LROUND, llvm::ISD::PARITY, llvm::ISD::PRE_INC, llvm::ISD::PREFETCH, Promote, llvm::ISD::READCYCLECOUNTER, llvm::ISD::READSTEADYCOUNTER, llvm::ISD::RESET_FPENV, llvm::ISD::RESET_FPMODE, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SADDSAT, llvm::ISD::SDIVFIX, llvm::ISD::SDIVFIXSAT, llvm::ISD::SET_FPENV, llvm::ISD::SET_FPENV_MEM, llvm::ISD::SET_FPMODE, llvm::ISD::SETCCCARRY, setIndexedLoadAction(), setIndexedMaskedLoadAction(), setIndexedMaskedStoreAction(), setIndexedStoreAction(), setLoadExtAction(), setOperationAction(), setTruncStoreAction(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULFIX, llvm::ISD::SMULFIXSAT, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SSHLSAT, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::SSUBSAT, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UADDSAT, llvm::ISD::UBSANTRAP, llvm::ISD::UDIVFIX, llvm::ISD::UDIVFIXSAT, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULFIX, llvm::ISD::UMULFIXSAT, llvm::ISD::UMULO, llvm::ISD::USHLSAT, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SEQ_FADD, llvm::ISD::VECREDUCE_SEQ_FMUL, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, llvm::ISD::VECTOR_SPLICE, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::ISD::ZEXTLOAD.

Referenced by TargetLoweringBase().

◆ insertSSPDeclarations()

void TargetLoweringBase::insertSSPDeclarations ( Module M) const
virtual

◆ InstructionOpcodeToISD()

int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1876 of file TargetLoweringBase.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::FAdd, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::FMul, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREEZE, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::ISD::INSERT_VECTOR_ELT, llvm_unreachable, llvm::ISD::LOAD, llvm::ISD::MERGE_VALUES, llvm::Mul, llvm::ISD::MUL, llvm::Or, llvm::ISD::OR, PHI, llvm::ISD::SDIV, llvm::ISD::SELECT, Select, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::VECTOR_SHUFFLE, llvm::Xor, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TTIImpl::getArithmeticInstrCost(), llvm::GCNTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::NVPTXTTIImpl::getArithmeticInstrCost(), llvm::PPCTTIImpl::getArithmeticInstrCost(), llvm::RISCVTTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::RISCVTTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::ARMTTIImpl::getArithmeticReductionCost(), llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::PPCTTIImpl::getCastInstrCost(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::BasicTTIImplBase< T >::getCmpSelInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::ARMTTIImpl::getExtendedReductionCost(), llvm::PPCTTIImpl::getVectorInstrCost(), llvm::X86TTIImpl::getVectorInstrCost(), isPromotedInstructionLegal(), llvm::ARMTTIImpl::maybeLoweredToCall(), SinkShiftAndTruncate(), and llvm::PPCTTIImpl::vectorCostAdjustmentFactor().

◆ isBeneficialToExpandPowI()

bool llvm::TargetLoweringBase::isBeneficialToExpandPowI ( int64_t  Exponent,
bool  OptForSize 
) const
inline

Return true if it is beneficial to expand an @llvm.powi.

  • intrinsic. If not optimizing for size, expanding @llvm.powi.* intrinsics is always considered beneficial. If optimizing for size, expansion is only considered beneficial for upto 5 multiplies and a divide (if the exponent is negative).

Definition at line 2405 of file TargetLowering.h.

References E, llvm::Exponent, llvm::Log2_64(), and llvm::popcount().

Referenced by ExpandPowI(), and llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().

◆ isBinOp()

virtual bool llvm::TargetLoweringBase::isBinOp ( unsigned  Opcode) const
inlinevirtual

◆ isCheapToSpeculateCtlz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCtlz ( Type Ty) const
inlinevirtual

◆ isCheapToSpeculateCttz()

virtual bool llvm::TargetLoweringBase::isCheapToSpeculateCttz ( Type Ty) const
inlinevirtual

◆ isCommutativeBinOp()

virtual bool llvm::TargetLoweringBase::isCommutativeBinOp ( unsigned  Opcode) const
inlinevirtual

◆ isComplexDeinterleavingOperationSupported()

virtual bool llvm::TargetLoweringBase::isComplexDeinterleavingOperationSupported ( ComplexDeinterleavingOperation  Operation,
Type Ty 
) const
inlinevirtual

Does this target support complex deinterleaving with the given operation and type.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3327 of file TargetLowering.h.

◆ isComplexDeinterleavingSupported()

virtual bool llvm::TargetLoweringBase::isComplexDeinterleavingSupported ( ) const
inlinevirtual

Does this target support complex deinterleaving.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3323 of file TargetLowering.h.

◆ isCondCodeLegal()

bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return true if the specified condition code is legal on this target.

Definition at line 1586 of file TargetLowering.h.

References CC, getCondCodeAction(), and Legal.

Referenced by llvm::SelectionDAG::FoldSetCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), llvm::R600TargetLowering::PerformDAGCombine(), and llvm::TargetLowering::SimplifySetCC().

◆ isCondCodeLegalOrCustom()

bool llvm::TargetLoweringBase::isCondCodeLegalOrCustom ( ISD::CondCode  CC,
MVT  VT 
) const
inline

Return true if the specified condition code is legal or custom on this target.

Definition at line 1592 of file TargetLowering.h.

References CC, Custom, getCondCodeAction(), and Legal.

Referenced by llvm::TargetLowering::expandIS_FPCLASS(), and llvm::TargetLowering::LegalizeSetCCCondCode().

◆ isCtlzFast()

virtual bool llvm::TargetLoweringBase::isCtlzFast ( ) const
inlinevirtual

Return true if ctlz instruction is fast.

Reimplemented in llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 697 of file TargetLowering.h.

Referenced by llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().

◆ isCtpopFast()

virtual bool llvm::TargetLoweringBase::isCtpopFast ( EVT  VT) const
inlinevirtual

Return true if ctpop instruction is fast.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 702 of file TargetLowering.h.

References llvm::ISD::CTPOP, and isOperationLegal().

Referenced by simplifySetCCWithCTPOP().

◆ isEqualityCmpFoldedWithSignedCmp()

virtual bool llvm::TargetLoweringBase::isEqualityCmpFoldedWithSignedCmp ( ) const
inlinevirtual

Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 714 of file TargetLowering.h.

Referenced by foldICmpWithDominatingICmp().

◆ isExtFree()

bool llvm::TargetLoweringBase::isExtFree ( const Instruction I) const
inline

Return true if the extension represented by I is free.

Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by I to decide whether or not I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.

Precondition
I must be a sign, zero, or fp extension.

Definition at line 2918 of file TargetLowering.h.

References llvm::EVT::getEVT(), I, isExtFreeImpl(), isFPExtFree(), isZExtFree(), and llvm_unreachable.

◆ isExtFreeImpl()

virtual bool llvm::TargetLoweringBase::isExtFreeImpl ( const Instruction I) const
inlineprotectedvirtual

Return true if the extension represented by I is free.

Precondition
I is a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.

Definition at line 3597 of file TargetLowering.h.

Referenced by isExtFree().

◆ isExtLoad()

bool llvm::TargetLoweringBase::isExtLoad ( const LoadInst Load,
const Instruction Ext,
const DataLayout DL 
) const
inline

Return true if Load and Ext can form an ExtLoad.

For example, in AArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]

Definition at line 2943 of file TargetLowering.h.

References assert(), DL, getValueType(), isLoadExtLegal(), isTruncateFree(), isTypeLegal(), llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.

◆ isExtractSubvectorCheap()

virtual bool llvm::TargetLoweringBase::isExtractSubvectorCheap ( EVT  ResVT,
EVT  SrcVT,
unsigned  Index 
) const
inlinevirtual

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.

This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3247 of file TargetLowering.h.

Referenced by foldExtractSubvectorFromShuffleVector(), llvm::SelectionDAG::matchBinOpReduction(), and narrowExtractedVectorBinOp().

◆ isExtractVecEltCheap()

virtual bool llvm::TargetLoweringBase::isExtractVecEltCheap ( EVT  VT,
unsigned  Index 
) const
inlinevirtual

Return true if extraction of a scalar element from the given vector type at the given index is cheap.

For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3262 of file TargetLowering.h.

Referenced by scalarizeBinOpOfSplats().

◆ isFAbsFree()

virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 3142 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost().

◆ isFMADLegal() [1/2]

virtual bool llvm::TargetLoweringBase::isFMADLegal ( const MachineInstr MI,
LLT  Ty 
) const
inlinevirtual

Returns true if MI can be combined with another instruction to form TargetOpcode::G_FMAD.

N may be an TargetOpcode::G_FADD, TargetOpcode::G_FSUB, or an TargetOpcode::G_FMUL which will be distributed into an fadd/fsub.

Reimplemented in llvm::SITargetLowering.

Definition at line 3182 of file TargetLowering.h.

References assert(), llvm::LLT::getScalarSizeInBits(), isOperationLegal(), and MI.

◆ isFMADLegal() [2/2]

virtual bool llvm::TargetLoweringBase::isFMADLegal ( const SelectionDAG DAG,
const SDNode N 
) const
inlinevirtual

Returns true if be combined with to form an ISD::FMAD.

N may be an ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an fadd/fsub.

Reimplemented in llvm::SITargetLowering.

Definition at line 3204 of file TargetLowering.h.

References assert(), llvm::ISD::FADD, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FSUB, isOperationLegal(), and N.

◆ isFMAFasterThanFMulAndFAdd() [1/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd ( const Function F,
Type  
) const
inlinevirtual

IR version.

Reimplemented in llvm::AArch64TargetLowering, and llvm::PPCTargetLowering.

Definition at line 3174 of file TargetLowering.h.

◆ isFMAFasterThanFMulAndFAdd() [2/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd ( const MachineFunction MF,
EVT   
) const
inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::HexagonTargetLowering, llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::NVPTXTargetLowering, and llvm::SPIRVTargetLowering.

Definition at line 3155 of file TargetLowering.h.

◆ isFMAFasterThanFMulAndFAdd() [3/3]

virtual bool llvm::TargetLoweringBase::isFMAFasterThanFMulAndFAdd ( const MachineFunction MF,
LLT   
) const
inlinevirtual

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented in llvm::SITargetLowering.

Definition at line 3168 of file TargetLowering.h.

◆ isFNegFree()

virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::ARMTargetLowering.

Definition at line 3135 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

◆ isFPExtFoldable() [1/2]

virtual bool llvm::TargetLoweringBase::isFPExtFoldable ( const MachineInstr MI,
unsigned  Opcode,
LLT  DestTy,
LLT  SrcTy 
) const
inlinevirtual

Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Reimplemented in llvm::SITargetLowering.

Definition at line 3114 of file TargetLowering.h.

◆ isFPExtFoldable() [2/2]

virtual bool llvm::TargetLoweringBase::isFPExtFoldable ( const SelectionDAG DAG,
unsigned  Opcode,
EVT  DestVT,
EVT  SrcVT 
) const
inlinevirtual

Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Reimplemented in llvm::SITargetLowering.

Definition at line 3122 of file TargetLowering.h.

References assert(), llvm::EVT::isFloatingPoint(), and isFPExtFree().

◆ isFPExtFree()

virtual bool llvm::TargetLoweringBase::isFPExtFree ( EVT  DestVT,
EVT  SrcVT 
) const
inlinevirtual

Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

Reimplemented in llvm::PPCTargetLowering.

Definition at line 3105 of file TargetLowering.h.

References assert(), and llvm::EVT::isFloatingPoint().

Referenced by llvm::TargetLowering::getNegatedExpression(), isExtFree(), and isFPExtFoldable().

◆ isFPImmLegal()

virtual bool llvm::TargetLoweringBase::isFPImmLegal ( const APFloat ,
EVT  ,
bool  ForCodeSize = false 
) const
inlinevirtual

Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 1215 of file TargetLowering.h.

Referenced by llvm::TargetLowering::getNegatedExpression(), and llvm::TargetLowering::SimplifySetCC().

◆ isFreeAddrSpaceCast()

bool TargetLoweringBase::isFreeAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
virtual

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.

Reimplemented in llvm::SITargetLowering.

Definition at line 1040 of file TargetLoweringBase.cpp.

References llvm::TargetMachine::isNoopAddrSpaceCast().

Referenced by llvm::BasicTTIImplBase< T >::getCastInstrCost(), and OptimizeNoopCopyExpression().

◆ isFsqrtCheap()

virtual bool llvm::TargetLoweringBase::isFsqrtCheap ( SDValue  X,
SelectionDAG DAG 
) const
inlinevirtual

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 547 of file TargetLowering.h.

◆ isIndexedLoadLegal()

bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 1499 of file TargetLowering.h.

References Custom, getIndexedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< T >::isIndexedLoadLegal().

◆ isIndexedMaskedLoadLegal()

bool llvm::TargetLoweringBase::isIndexedMaskedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 1527 of file TargetLowering.h.

References Custom, getIndexedMaskedLoadAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts().

◆ isIndexedMaskedStoreLegal()

bool llvm::TargetLoweringBase::isIndexedMaskedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 1541 of file TargetLowering.h.

References Custom, getIndexedMaskedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts().

◆ isIndexedStoreLegal()

bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inline

Return true if the specified indexed load is legal on this target.

Definition at line 1513 of file TargetLowering.h.

References Custom, getIndexedStoreAction(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and Legal.

Referenced by getCombineLoadStoreParts(), and llvm::BasicTTIImplBase< T >::isIndexedStoreLegal().

◆ isIntDivCheap()

virtual bool llvm::TargetLoweringBase::isIntDivCheap ( EVT  VT,
AttributeList  Attr 
) const
inlinevirtual

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

The definition of "cheaper" may depend on whether we're optimizing for speed or for size.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::VETargetLowering.

Definition at line 539 of file TargetLowering.h.

Referenced by llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), llvm::BasicTTIImplBase< T >::preferToKeepConstantsAttached(), and llvm::TargetLowering::SimplifySetCC().

◆ isJumpExpensive()

bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inline

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 597 of file TargetLowering.h.

◆ isJumpTableRelative()

bool TargetLoweringBase::isJumpTableRelative ( ) const
virtual

◆ isLegalAddImmediate()

virtual bool llvm::TargetLoweringBase::isLegalAddImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::ARMTargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2769 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::isLegalAddImmediate(), and performAddCSelIntoCSinc().

◆ isLegalAddressingMode()

bool TargetLoweringBase::isLegalAddressingMode ( const DataLayout DL,
const AddrMode AM,
Type Ty,
unsigned  AddrSpace,
Instruction I = nullptr 
) const
virtual

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

If the address space cannot be determined, it will be -1.

TODO: Remove default argument

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARCTargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 2008 of file TargetLoweringBase.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.

Referenced by canFoldInAddressingMode(), and llvm::BasicTTIImplBase< T >::isLegalAddressingMode().

◆ isLegalICmpImmediate()

virtual bool llvm::TargetLoweringBase::isLegalICmpImmediate ( int64_t  ) const
inlinevirtual

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented in llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::MSP430TargetLowering.

Definition at line 2762 of file TargetLowering.h.

Referenced by llvm::BasicTTIImplBase< T >::isLegalICmpImmediate(), llvm::MSP430TargetLowering::isLegalICmpImmediate(), and llvm::TargetLowering::SimplifySetCC().

◆ isLegalRC()

bool TargetLoweringBase::isLegalRC ( const TargetRegisterInfo TRI,
const TargetRegisterClass RC 
) const
protected

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 1248 of file TargetLoweringBase.cpp.

References I, isTypeLegal(), and TRI.

Referenced by findRepresentativeClass(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

◆ isLegalScaleForGatherScatter()

virtual bool llvm::TargetLoweringBase::isLegalScaleForGatherScatter ( uint64_t  Scale,
uint64_t  ElemSize 
) const
inlinevirtual

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 1560 of file TargetLowering.h.

Referenced by getUniformBase().

◆ isLegalStoreImmediate()

virtual bool llvm::TargetLoweringBase::isLegalStoreImmediate ( int64_t  Value) const
inlinevirtual

Return true if the specified immediate is legal for the value input of a store instruction.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2775 of file TargetLowering.h.

Referenced by getMemsetValue().

◆ isLoadBitCastBeneficial()

bool TargetLoweringBase::isLoadBitCastBeneficial ( EVT  LoadVT,
EVT  BitcastVT,
const SelectionDAG DAG,
const MachineMemOperand MMO 
) const
virtual

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 2310 of file TargetLoweringBase.cpp.

References allowsMemoryAccess(), llvm::CallingConv::Fast, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getOperationAction(), llvm::EVT::getSimpleVT(), getTypeToPromoteTo(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and Promote.

Referenced by llvm::X86TargetLowering::isLoadBitCastBeneficial(), and isStoreBitCastBeneficial().

◆ isLoadExtLegal()

bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal on this target.

Definition at line 1446 of file TargetLowering.h.

References getLoadExtAction(), and Legal.

Referenced by combineEXTEND_VECTOR_INREG(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), isExtLoad(), tryToFoldExtendSelectLoad(), tryToFoldExtOfExtload(), and tryToFoldExtOfLoad().

◆ isLoadExtLegalOrCustom()

bool llvm::TargetLoweringBase::isLoadExtLegalOrCustom ( unsigned  ExtType,
EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified load with extension is legal or custom on this target.

Definition at line 1452 of file TargetLowering.h.

References Custom, getLoadExtAction(), and Legal.

Referenced by tryToFoldExtOfMaskedLoad().

◆ isMaskAndCmp0FoldingBeneficial()

virtual bool llvm::TargetLoweringBase::isMaskAndCmp0FoldingBeneficial ( const Instruction AndI) const
inlinevirtual

Return if the target supports combining a chain like:

%andResult = and %val1, #mask
%icmpResult = icmp %andResult, 0

into a single machine instruction of a form like:

cc = test %register, #mask
modulo schedule test

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 736 of file TargetLowering.h.

Referenced by sinkAndCmp0Expression().

◆ isMulAddWithConstProfitable()

virtual bool llvm::TargetLoweringBase::isMulAddWithConstProfitable ( SDValue  AddNode,
SDValue  ConstNode 
) const
inlinevirtual

Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).

This may not be true if c1 and c2 can be represented as immediates but c1*c2 cannot, for example. The target should check if c1, c2 and c1*c2 can be represented as immediates, or have to be materialized into registers. If it is not sure about some cases, a default true can be returned to let the DAGCombiner decide. AddNode is (add x, c1), and ConstNode is c2.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2385 of file TargetLowering.h.

◆ isMultiStoresCheaperThanBitsMerge()

virtual bool llvm::TargetLoweringBase::isMultiStoresCheaperThanBitsMerge ( EVT  LTy,
EVT  HTy 
) const
inlinevirtual

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 722 of file TargetLowering.h.

Referenced by splitMergedValStore().

◆ isNarrowingProfitable()

virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  SrcVT,
EVT  DestVT 
) const
inlinevirtual

Return true if it's profitable to narrow operations of type SrcVT to DestVT.

e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::X86TargetLowering.

Definition at line 3221 of file TargetLowering.h.

Referenced by llvm::TargetLowering::SimplifyDemandedBits().

◆ isOperationCustom()

bool llvm::TargetLoweringBase::isOperationCustom ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

Definition at line 1359 of file TargetLowering.h.

References Custom, and getOperationAction().

Referenced by llvm::RISCVTTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::shouldScalarizeBinop(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isOperationExpand()

bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inline

◆ isOperationLegal()

bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inline

Return true if the specified operation is legal on this target.

Definition at line 1426 of file TargetLowering.h.

References getOperationAction(), isTypeLegal(), and Legal.

Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineLogicBlendIntoConditionalNegate(), combineSetCC(), combineTruncatedArithmetic(), llvm::X86TargetLowering::decomposeMulByConstant(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandSADDSUBO(), foldAndOrOfSETCC(), foldExtendVectorInregToExtendOfSubvector(), foldFPToIntToFP(), llvm::SelectionDAG::getConstant(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), llvm::X86TTIImpl::hasDivRemOp(), isCtpopFast(), llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(), isFMADLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), LowerADDSAT_SUBSAT(), LowerVSETCC(), llvm::SDPatternMatch::m_LegalOp(), PerformABSCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performXORCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), stripModuloOnShift(), and tryFoldToZero().

◆ isOperationLegalOrCustom()

bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT,
bool  LegalOnly = false 
) const
inline

Return true if the specified operation is legal on this target or can be made legal with custom lowering.

This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.

Definition at line 1318 of file TargetLowering.h.

References Custom, getOperationAction(), isOperationLegal(), isTypeLegal(), and Legal.

Referenced by areJTsAllowed(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canExpandVectorCTPOP(), combineCarryDiamond(), combineConcatVectorOfCasts(), combineConcatVectorOfShuffleAndItsOperands(), combineMinNumMaxNumImpl(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleOfBitcast(), combineVSelectToBLENDV(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandREM(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::findOptimalMemOpLowering(), foldAndOrOfSETCC(), foldExtractSubvectorFromShuffleVector(), llvm::AArch64TTIImpl::getArithmeticInstrCost(), getAsCarry(), llvm::TargetLowering::getNegatedExpression(), llvm::MipsTTIImpl::hasDivRemOp(), llvm::BasicTTIImplBase< T >::haveFastSqrt(), llvm::AArch64TargetLowering::isExtractSubvectorCheap(), llvm::SITargetLowering::isExtractSubvectorCheap(), llvm::ARMTargetLowering::isExtractSubvectorCheap(), llvm::RISCVTargetLowering::isExtractSubvectorCheap(), llvm::X86TargetLowering::isExtractSubvectorCheap(), llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::AArch64TargetLowering::isProfitableToHoist(), llvm::PPCTargetLowering::isProfitableToHoist(), isPromotedInstructionLegal(), lowerBitreverseShuffle(), matchBSwapHWordOrAndAnd(), narrowInsertExtractVectorBinOp(), performBUILD_VECTORCombine(), scalarizeBinOpOfSplats(), llvm::BasicTTIImplBase< T >::shouldBuildLookupTables(), shouldConvertFpToSat(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86TargetLowering::shouldConvertFpToSat(), shouldConvertSelectOfConstantsToMath(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SinkShiftAndTruncate(), and widenCtPop().

◆ isOperationLegalOrCustomOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote ( unsigned  Op,
EVT  VT,
bool  LegalOnly = false 
) const
inline

◆ isOperationLegalOrPromote()

bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT,
bool  LegalOnly = false 
) const
inline

Return true if the specified operation is legal on this target or can be made legal using promotion.

This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.

Definition at line 1332 of file TargetLowering.h.

References getOperationAction(), isOperationLegal(), isTypeLegal(), Legal, and Promote.

Referenced by llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(), lowerBuildVectorToBitOp(), and PromoteMaskArithmetic().

◆ isPredictableSelectExpensive()

bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inline

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 637 of file TargetLowering.h.

References PredictableSelectIsExpensive.

Referenced by isFormingBranchFromSelectProfitable().

◆ isProfitableToCombineMinNumMaxNum()

virtual bool llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum ( EVT  VT) const
inlinevirtual

Definition at line 2357 of file TargetLowering.h.

Referenced by isLegalToCombineMinNumMaxNum().

◆ isProfitableToHoist()

virtual bool llvm::TargetLoweringBase::isProfitableToHoist ( Instruction I) const
inlinevirtual

◆ isSafeMemOpType()

virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtual

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1948 of file TargetLowering.h.

Referenced by llvm::TargetLowering::findOptimalMemOpLowering().

◆ isSelectSupported()

virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtual

◆ isSExtCheaperThanZExt()

virtual bool llvm::TargetLoweringBase::isSExtCheaperThanZExt ( EVT  FromTy,
EVT  ToTy 
) const
inlinevirtual

Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

Reimplemented in llvm::LoongArchTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2996 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::getConstant(), and llvm::TargetLowering::SimplifySetCC().

◆ isShuffleMaskLegal()

virtual bool llvm::TargetLoweringBase::isShuffleMaskLegal ( ArrayRef< int >  ,
EVT   
) const
inlinevirtual

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsSETargetLowering, llvm::X86TargetLowering, and llvm::SITargetLowering.

Definition at line 1224 of file TargetLowering.h.

Referenced by llvm::TargetLowering::buildLegalVectorShuffle(), combineConcatVectorOfShuffleAndItsOperands(), combineShuffleOfBitcast(), ExpandBVWithShuffles(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), and formSplatFromShuffles().

◆ isSlowDivBypassed()

bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inline

Returns true if target has indicated at least one type should be bypassed.

Definition at line 584 of file TargetLowering.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty().

◆ isStoreBitCastBeneficial()

virtual bool llvm::TargetLoweringBase::isStoreBitCastBeneficial ( EVT  StoreVT,
EVT  BitcastVT,
const SelectionDAG DAG,
const MachineMemOperand MMO 
) const
inlinevirtual

Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))

Definition at line 657 of file TargetLowering.h.

References isLoadBitCastBeneficial().

◆ isStrictFPEnabled()

bool llvm::TargetLoweringBase::isStrictFPEnabled ( ) const
inline

Return true if the target support strict float operation.

Definition at line 351 of file TargetLowering.h.

References IsStrictFPEnabled.

◆ isSuitableForBitTests()

bool llvm::TargetLoweringBase::isSuitableForBitTests ( unsigned  NumDests,
unsigned  NumCmps,
const APInt Low,
const APInt High,
const DataLayout DL 
) const
inline

Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons.

Check if the number of destinations, comparison metric, and range are all suitable.

Definition at line 1396 of file TargetLowering.h.

References DL, High, llvm::Low, and rangeFitsInWord().

Referenced by llvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().

◆ isSuitableForJumpTable()

bool TargetLoweringBase::isSuitableForJumpTable ( const SwitchInst SI,
uint64_t  NumCases,
uint64_t  Range,
ProfileSummaryInfo PSI,
BlockFrequencyInfo BFI 
) const
virtual

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.

Definition at line 1738 of file TargetLoweringBase.cpp.

References getMaximumJumpTableSize(), getMinimumJumpTableDensity(), and llvm::shouldOptimizeForSize().

Referenced by llvm::SwitchCG::SwitchLowering::findJumpTables(), and llvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().

◆ isSupportedFixedPointOperation()

virtual bool llvm::TargetLoweringBase::isSupportedFixedPointOperation ( unsigned  Op,
EVT  VT,
unsigned  Scale 
) const
inlinevirtual

Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.

If not, the operation is illegal.

Definition at line 1262 of file TargetLowering.h.

Referenced by getFixedPointOperationAction().

◆ isTruncateFree() [1/4]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( EVT  FromVT,
EVT  ToVT 
) const
inlinevirtual

◆ isTruncateFree() [2/4]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( LLT  FromTy,
LLT  ToTy,
const DataLayout DL,
LLVMContext Ctx 
) const
inlinevirtual

Definition at line 2895 of file TargetLowering.h.

References DL, llvm::getApproximateEVTForLLT(), and isTruncateFree().

◆ isTruncateFree() [3/4]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( SDValue  Val,
EVT  VT2 
) const
inlinevirtual

Return true if truncating the specific node Val to type VT2 is free.

Definition at line 2902 of file TargetLowering.h.

References llvm::SDValue::getValueType(), and isTruncateFree().

◆ isTruncateFree() [4/4]

virtual bool llvm::TargetLoweringBase::isTruncateFree ( Type FromTy,
Type ToTy 
) const
inlinevirtual

◆ isTruncStoreLegal()

bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inline

◆ isTruncStoreLegalOrCustom()

bool llvm::TargetLoweringBase::isTruncStoreLegalOrCustom ( EVT  ValVT,
EVT  MemVT 
) const
inline

Return true if the specified store with truncation has solution on this target.

Definition at line 1477 of file TargetLowering.h.

References Custom, getTruncStoreAction(), isTypeLegal(), and Legal.

Referenced by canCombineTruncStore().

◆ isTypeLegal()

bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inline

Return true if the target has native support for the specified value type.

This means that it has a register that directly holds it without promotions or expansions.

Definition at line 1073 of file TargetLowering.h.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::allowTruncateForTailCall(), llvm::X86TargetLowering::allowTruncateForTailCall(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canOpTrap(), CollectOpsToWiden(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndShuffleNot(), combineBitcast(), combineBitcastToBoolVector(), combineBITREVERSE(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfScalars(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineFMA(), combineFMinNumFMaxNum(), combineFneg(), combineLoad(), combineOr(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShuffle(), combineShuffleToFMAddSub(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combineTargetShuffle(), combineTruncateWithSat(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineXor(), computeRegisterProperties(), EltsFromConsecutiveLoads(), expandDivFix(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::findOptimalMemOpLowering(), getAVX512Node(), getAVX512TruncNode(), getBT(), llvm::AArch64TTIImpl::getCastInstrCost(), llvm::AArch64TTIImpl::getCmpSelInstrCost(), getConstVector(), getContainerForFixedLengthVector(), getCopyFromPartsVector(), getCopyToParts(), llvm::AArch64TTIImpl::getExtractWithExtendCost(), getMemsetStores(), llvm::X86TargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), getPredicateForFixedLengthVector(), getPredicateForScalableVector(), getPromotedVectorElementType(), getPTest(), llvm::SelectionDAG::getReducedAlign(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::FastISel::getRegForValue(), llvm::SelectionDAG::getSplatValue(), getSVEPredicateBitCast(), getTypeToPromoteTo(), getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVectorTypeBreakdownMVT(), getZeroVector(), llvm::SystemZTTIImpl::hasDivRemOp(), hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::BasicTTIImplBase< T >::haveFastSqrt(), llvm::GenericScheduler::initPolicy(), isAddSubOrSubAdd(), llvm::RISCVTargetLowering::isCtpopFast(), isExtLoad(), llvm::AArch64TTIImpl::isExtPartOfAvgExpr(), isLegalBitRotate(), llvm::RISCVTargetLowering::isLegalInterleavedAccessType(), isLegalRC(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), isNoopBitcast(), isOperationExpand(), isOperationLegal(), isOperationLegalOrCustom(), isOperationLegalOrCustomOrPromote(), isOperationLegalOrPromote(), isPackedVectorType(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), isTruncStoreLegal(), isTruncStoreLegalOrCustom(), llvm::X86TargetLowering::isTypeDesirableForOp(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::BasicTTIImplBase< T >::isTypeLegal(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), LowerABD(), LowerADDSUBO_CARRY(), LowerATOMIC_STORE(), lowerBitreverseShuffle(), LowerCTPOP(), LowerFABSorFNEG(), lowerFCMPIntrinsic(), LowerFCOPYSIGN(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), lowerGR128ToI128(), lowerI128ToGR128(), lowerICMPIntrinsic(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleAsElementInsertion(), lowerShuffleAsShift(), LowerSINT_TO_FP(), lowerStatepointMetaArgs(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerXALUO(), llvm::SDPatternMatch::m_LegalType(), narrowShuffle(), OptimizeExtractBits(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), performBUILD_VECTORCombine(), performBuildVectorCombine(), performCONCAT_VECTORSSplitCombine(), performCONCAT_VECTORSStridedLoadCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltToVMOVRRD(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performORCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSUBCombine(), PerformTruncatingStoreCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::FastISel::selectBinaryOp(), llvm::FastISel::selectBitCast(), llvm::FastISel::selectCast(), llvm::FastISel::selectExtractValue(), llvm::FastISel::selectFNeg(), llvm::FastISel::selectFreeze(), llvm::AMDGPUTargetLowering::shouldCombineMemoryType(), llvm::AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::ARMTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(), llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(), llvm::X86TargetLowering::shouldSplatInsEltVarIndex(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::SITargetLowering::SITargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), tryToFoldExtendOfConstant(), tryWidenMaskForShuffle(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestHeader(), widenVectorToPartType(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isVectorClearMaskLegal()

virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( ArrayRef< int >  ,
EVT   
) const
inlinevirtual

Similar to isShuffleMaskLegal.

Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::AArch64TargetLowering, and llvm::X86TargetLowering.

Definition at line 1237 of file TargetLowering.h.

◆ isVectorLoadExtDesirable()

virtual bool llvm::TargetLoweringBase::isVectorLoadExtDesirable ( SDValue  ExtVal) const
inlinevirtual

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 3131 of file TargetLowering.h.

Referenced by tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().

◆ isVectorShiftByScalarCheap()

virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtual

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.

On x86 before AVX2 for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors. This should also apply to lowering for vector funnel shifts (rotates).

Reimplemented in llvm::X86TargetLowering.

Definition at line 2786 of file TargetLowering.h.

◆ isVScaleKnownToBeAPowerOfTwo()

virtual bool llvm::TargetLoweringBase::isVScaleKnownToBeAPowerOfTwo ( ) const
inlinevirtual

Return true only if vscale must be a power of two.

Reimplemented in llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.

Definition at line 593 of file TargetLowering.h.

◆ isZExtFree() [1/4]

virtual bool llvm::TargetLoweringBase::isZExtFree ( EVT  FromTy,
EVT  ToTy 
) const
inlinevirtual

◆ isZExtFree() [2/4]

virtual bool llvm::TargetLoweringBase::isZExtFree ( LLT  FromTy,
LLT  ToTy,
const DataLayout DL,
LLVMContext Ctx 
) const
inlinevirtual

Definition at line 2981 of file TargetLowering.h.

References DL, llvm::getApproximateEVTForLLT(), and isZExtFree().

◆ isZExtFree() [3/4]

virtual bool llvm::TargetLoweringBase::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
inlinevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 2990 of file TargetLowering.h.

References llvm::SDValue::getValueType(), and isZExtFree().

◆ isZExtFree() [4/4]

virtual bool llvm::TargetLoweringBase::isZExtFree ( Type FromTy,
Type ToTy 
) const
inlinevirtual

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::X86TargetLowering.

Definition at line 2976 of file TargetLowering.h.

Referenced by combineShuffleOfScalars(), foldCONCAT_VECTORS(), llvm::BasicTTIImplBase< T >::getCastInstrCost(), llvm::RegsForValue::getCopyToRegs(), hasSameExtUse(), isExtFree(), isZExtFree(), llvm::LoongArchTargetLowering::isZExtFree(), llvm::PPCTargetLowering::isZExtFree(), llvm::RISCVTargetLowering::isZExtFree(), llvm::TargetLowering::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), and tryToFoldExtendOfConstant().

◆ lowerDeinterleaveIntrinsicToLoad()

virtual bool llvm::TargetLoweringBase::lowerDeinterleaveIntrinsicToLoad ( IntrinsicInst DI,
LoadInst LI 
) const
inlinevirtual

Lower a deinterleave intrinsic to a target specific load intrinsic.

Return true on success. Currently only supports llvm.experimental.vector.deinterleave2

DI is the deinterleave intrinsic. LI is the accompanying load instruction

Reimplemented in llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.

Definition at line 3086 of file TargetLowering.h.

◆ lowerIdempotentRMWIntoFencedLoad()

virtual LoadInst * llvm::TargetLoweringBase::lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst RMWI) const
inlinevirtual

On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.

Reimplemented in llvm::SITargetLowering.

Definition at line 2315 of file TargetLowering.h.

◆ lowerInterleavedLoad()

virtual bool llvm::TargetLoweringBase::lowerInterleavedLoad ( LoadInst LI,
ArrayRef< ShuffleVectorInst * >  Shuffles,
ArrayRef< unsigned Indices,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved load to target specific intrinsics.

Return true on success.

LI is the vector load instruction. Shuffles is the shufflevector list to DE-interleave the loaded vector. Indices is the corresponding indices for each shufflevector. Factor is the interleave factor.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3062 of file TargetLowering.h.

◆ lowerInterleavedStore()

virtual bool llvm::TargetLoweringBase::lowerInterleavedStore ( StoreInst SI,
ShuffleVectorInst SVI,
unsigned  Factor 
) const
inlinevirtual

Lower an interleaved store to target specific intrinsics.

Return true on success.

SI is the vector store instruction. SVI is the shufflevector to RE-interleave the stored vector. Factor is the interleave factor.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3075 of file TargetLowering.h.

◆ lowerInterleaveIntrinsicToStore()

virtual bool llvm::TargetLoweringBase::lowerInterleaveIntrinsicToStore ( IntrinsicInst II,
StoreInst SI 
) const
inlinevirtual

Lower an interleave intrinsic to a target specific store intrinsic.

Return true on success. Currently only supports llvm.experimental.vector.interleave2

II is the interleave intrinsic. SI is the accompanying store instruction

Reimplemented in llvm::AArch64TargetLowering, and llvm::RISCVTargetLowering.

Definition at line 3097 of file TargetLowering.h.

◆ markLibCallAttributes()

virtual void llvm::TargetLoweringBase::markLibCallAttributes ( MachineFunction MF,
unsigned  CC,
ArgListTy Args 
) const
inlinevirtual

◆ mergeStoresAfterLegalization()

virtual bool llvm::TargetLoweringBase::mergeStoresAfterLegalization ( EVT  MemVT) const
inlinevirtual

Allow store merging for the specified type after legalization in addition to before legalization.

This may transform stores that do not exist earlier (for example, stores created from intrinsics).

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 676 of file TargetLowering.h.

◆ needsFixedCatchObjects()

virtual bool llvm::TargetLoweringBase::needsFixedCatchObjects ( ) const
inlinevirtual

◆ operator=()

TargetLoweringBase & llvm::TargetLoweringBase::operator= ( const TargetLoweringBase )
delete

◆ optimizeExtendOrTruncateConversion()

virtual bool llvm::TargetLoweringBase::optimizeExtendOrTruncateConversion ( Instruction I,
Loop L,
const TargetTransformInfo TTI 
) const
inlinevirtual

Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 3017 of file TargetLowering.h.

◆ optimizeFMulOrFDivAsShiftAddBitcast()

virtual bool llvm::TargetLoweringBase::optimizeFMulOrFDivAsShiftAddBitcast ( SDNode N,
SDValue  FPConst,
SDValue  IntPow2 
) const
inlinevirtual

Definition at line 872 of file TargetLowering.h.

References llvm::ISD::FDIV, and N.

◆ preferABDSToABSWithNSW()

virtual bool llvm::TargetLoweringBase::preferABDSToABSWithNSW ( EVT  VT) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 908 of file TargetLowering.h.

◆ preferedOpcodeForCmpEqPiecesOfOperand()

virtual unsigned llvm::TargetLoweringBase::preferedOpcodeForCmpEqPiecesOfOperand ( EVT  VT,
unsigned  ShiftOpc,
bool  MayTransformRotate,
const APInt ShiftOrRotateAmt,
const std::optional< APInt > &  AndMask 
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 889 of file TargetLowering.h.

◆ preferIncOfAddToSubOfNot()

virtual bool llvm::TargetLoweringBase::preferIncOfAddToSubOfNot ( EVT  VT) const
inlinevirtual

These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.

Some targets may prefer one to the other.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::PPCTargetLowering.

Definition at line 901 of file TargetLowering.h.

◆ preferredShiftLegalizationStrategy()

virtual ShiftLegalizationStrategy llvm::TargetLoweringBase::preferredShiftLegalizationStrategy ( SelectionDAG DAG,
SDNode N,
unsigned  ExpansionFactor 
) const
inlinevirtual

◆ preferScalarizeSplat()

virtual bool llvm::TargetLoweringBase::preferScalarizeSplat ( SDNode N) const
inlinevirtual

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 913 of file TargetLowering.h.

◆ preferSextInRegOfTruncate()

virtual bool llvm::TargetLoweringBase::preferSextInRegOfTruncate ( EVT  TruncVT,
EVT  VT,
EVT  ExtVT 
) const
inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 919 of file TargetLowering.h.

◆ preferZeroCompareBranch()

virtual bool llvm::TargetLoweringBase::preferZeroCompareBranch ( ) const
inlinevirtual

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

Reimplemented in llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 718 of file TargetLowering.h.

Referenced by optimizeBranch().

◆ promoteTargetBoolean()

SDValue llvm::TargetLoweringBase::promoteTargetBoolean ( SelectionDAG DAG,
SDValue  Bool,
EVT  ValVT 
) const
inline

Promote the given target boolean to a target boolean of the given type.

A target boolean is an integer value, not necessarily of type i1, the bits of which conform to getBooleanContents.

ValVT is the type of values that produced the boolean.

Definition at line 999 of file TargetLowering.h.

References Bool, getBooleanContents(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), getExtendForContent(), llvm::SelectionDAG::getNode(), and getSetCCResultType().

◆ rangeFitsInWord()

bool llvm::TargetLoweringBase::rangeFitsInWord ( const APInt Low,
const APInt High,
const DataLayout DL 
) const
inline

Check whether the range [Low,High] fits in a machine word.

Definition at line 1373 of file TargetLowering.h.

References DL, High, llvm::Low, and UINT64_MAX.

Referenced by isSuitableForBitTests().

◆ reduceSelectOfFPConstantLoads()

virtual bool llvm::TargetLoweringBase::reduceSelectOfFPConstantLoads ( EVT  CmpOpVT) const
inlinevirtual

Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.

The parameter may be used to differentiate a select with FP compare from integer compare.

Reimplemented in llvm::X86TargetLowering.

Definition at line 483 of file TargetLowering.h.

◆ requiresUniformRegister()

virtual bool llvm::TargetLoweringBase::requiresUniformRegister ( MachineFunction MF,
const Value  
) const
inlinevirtual

Allows target to decide about the register class of the specific value that is live outside the defining block.

Returns true if the value needs uniform register class.

Reimplemented in llvm::SITargetLowering.

Definition at line 1032 of file TargetLowering.h.

Referenced by llvm::FunctionLoweringInfo::CreateRegs().

◆ setBooleanContents() [1/2]

void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotected

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

See getBooleanContents.

Definition at line 2426 of file TargetLowering.h.

◆ setBooleanContents() [2/2]

void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotected

◆ setBooleanVectorContents()

void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotected

◆ setCmpLibcallCC()

void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inline

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 3362 of file TargetLowering.h.

References CC.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::MSP430TargetLowering::MSP430TargetLowering().

◆ setCondCodeAction() [1/2]

void llvm::TargetLoweringBase::setCondCodeAction ( ArrayRef< ISD::CondCode CCs,
ArrayRef< MVT VTs,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2616 of file TargetLowering.h.

References setCondCodeAction().

◆ setCondCodeAction() [2/2]

void llvm::TargetLoweringBase::setCondCodeAction ( ArrayRef< ISD::CondCode CCs,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

◆ setHasExtractBitsInsn()

void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotected

Tells the code generator that the target has BitExtract instructions.

The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 2468 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), and llvm::SITargetLowering::SITargetLowering().

◆ setHasMultipleConditionRegisters()

void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotected

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.

With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 2460 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ setIndexedLoadAction() [1/2]

void llvm::TargetLoweringBase::setIndexedLoadAction ( ArrayRef< unsigned IdxModes,
ArrayRef< MVT VTs,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2557 of file TargetLowering.h.

References setIndexedLoadAction().

◆ setIndexedLoadAction() [2/2]

void llvm::TargetLoweringBase::setIndexedLoadAction ( ArrayRef< unsigned IdxModes,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

◆ setIndexedMaskedLoadAction()

void llvm::TargetLoweringBase::setIndexedMaskedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode masked loads are initialized to Expand in TargetLowering.cpp

Definition at line 2585 of file TargetLowering.h.

Referenced by initActions().

◆ setIndexedMaskedStoreAction()

void llvm::TargetLoweringBase::setIndexedMaskedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode masked stores are initialized to Expand in TargetLowering.cpp

Definition at line 2595 of file TargetLowering.h.

Referenced by initActions().

◆ setIndexedStoreAction() [1/2]

void llvm::TargetLoweringBase::setIndexedStoreAction ( ArrayRef< unsigned IdxModes,
ArrayRef< MVT VTs,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2574 of file TargetLowering.h.

References setIndexedStoreAction().

◆ setIndexedStoreAction() [2/2]

void llvm::TargetLoweringBase::setIndexedStoreAction ( ArrayRef< unsigned IdxModes,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 2568 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and setIndexedStoreAction().

◆ setJumpIsExpensive()

void TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
protected

Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.

Definition at line 1045 of file TargetLoweringBase.cpp.

References JumpIsExpensiveOverride.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ setLibcallCallingConv()

void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inline

◆ setLibcallName() [1/2]

void llvm::TargetLoweringBase::setLibcallName ( ArrayRef< RTLIB::Libcall Calls,
const char Name 
)
inline

Definition at line 3350 of file TargetLowering.h.

References Name, and setLibcallName().

◆ setLibcallName() [2/2]

void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char Name 
)
inline

◆ setLoadExtAction() [1/3]

void llvm::TargetLoweringBase::setLoadExtAction ( ArrayRef< unsigned ExtTypes,
MVT  ValVT,
ArrayRef< MVT MemVTs,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2533 of file TargetLowering.h.

References setLoadExtAction().

◆ setLoadExtAction() [2/3]

void llvm::TargetLoweringBase::setLoadExtAction ( ArrayRef< unsigned ExtTypes,
MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2528 of file TargetLowering.h.

References setLoadExtAction().

◆ setLoadExtAction() [3/3]

void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected

◆ setMaxAtomicSizeInBitsSupported()

void llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported ( unsigned  SizeInBits)
inlineprotected

◆ setMaxBytesForAlignment()

void llvm::TargetLoweringBase::setMaxBytesForAlignment ( unsigned  MaxBytes)
inlineprotected

◆ setMaxDivRemBitWidthSupported()

void llvm::TargetLoweringBase::setMaxDivRemBitWidthSupported ( unsigned  SizeInBits)
inlineprotected

Set the size in bits of the maximum div/rem the backend supports.

Larger operations will be expanded by ExpandLargeDivRem.

Definition at line 2688 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setMaximumJumpTableSize()

void TargetLoweringBase::setMaximumJumpTableSize ( unsigned  Val)
protected

Indicate the maximum number of entries in jump tables.

Set to zero to generate unlimited jump tables.

Definition at line 2105 of file TargetLoweringBase.cpp.

References MaximumJumpTableSize.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().

◆ setMaxLargeFPConvertBitWidthSupported()

void llvm::TargetLoweringBase::setMaxLargeFPConvertBitWidthSupported ( unsigned  SizeInBits)
inlineprotected

Set the size in bits of the maximum fp convert the backend supports.

Larger operations will be expanded by ExpandLargeFPConvert.

Definition at line 2694 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setMinCmpXchgSizeInBits()

void llvm::TargetLoweringBase::setMinCmpXchgSizeInBits ( unsigned  SizeInBits)
inlineprotected

◆ setMinFunctionAlignment()

void llvm::TargetLoweringBase::setMinFunctionAlignment ( Align  Alignment)
inlineprotected

◆ setMinimumJumpTableEntries()

void TargetLoweringBase::setMinimumJumpTableEntries ( unsigned  Val)
protected

◆ setMinStackArgumentAlignment()

void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( Align  Alignment)
inlineprotected

◆ setOperationAction() [1/3]

void llvm::TargetLoweringBase::setOperationAction ( ArrayRef< unsigned Ops,
ArrayRef< MVT VTs,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2511 of file TargetLowering.h.

References setOperationAction().

◆ setOperationAction() [2/3]

void llvm::TargetLoweringBase::setOperationAction ( ArrayRef< unsigned Ops,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Definition at line 2506 of file TargetLowering.h.

References setOperationAction().

◆ setOperationAction() [3/3]

void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotected

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Note that VT may refer to either the type of a result or that of an operand of Op.

Definition at line 2502 of file TargetLowering.h.

References assert(), and llvm::MVT::SimpleTy.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsSETargetLowering::addMSAFloatType(), llvm::MipsSETargetLowering::addMSAIntType(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARCTargetLowering::ARCTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), llvm::CSKYTargetLowering::CSKYTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), initActions(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::Mips16TargetLowering::Mips16TargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), setOperationAction(), setOperationPromotedToType(), llvm::SITargetLowering::SITargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ setOperationPromotedToType() [1/2]

void llvm::TargetLoweringBase::setOperationPromotedToType ( ArrayRef< unsigned Ops,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

Definition at line 2636 of file TargetLowering.h.

References AddPromotedToType(), Promote, and setOperationAction().

◆ setOperationPromotedToType() [2/2]

void llvm::TargetLoweringBase::setOperationPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotected

Convenience method to set an operation to Promote and specify the type in a single call.

Definition at line 2632 of file TargetLowering.h.

References AddPromotedToType(), Promote, and setOperationAction().

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setPrefFunctionAlignment()

void llvm::TargetLoweringBase::setPrefFunctionAlignment ( Align  Alignment)
inlineprotected

◆ setPrefLoopAlignment()

void llvm::TargetLoweringBase::setPrefLoopAlignment ( Align  Alignment)
inlineprotected

Set the target's preferred loop alignment.

Default alignment is one, it means the target does not care about loop alignment. The target may also override getPrefLoopAlignment to provide per-loop values.

Definition at line 2668 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

◆ setSchedulingPreference()

void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotected

◆ setStackPointerRegisterToSaveRestore()

void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( Register  R)
inlineprotected

◆ setSupportsUnalignedAtomics()

void llvm::TargetLoweringBase::setSupportsUnalignedAtomics ( bool  UnalignedSupported)
inlineprotected

Sets whether unaligned atomic operations are supported.

Definition at line 2704 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), and llvm::AVRTargetLowering::AVRTargetLowering().

◆ setTargetDAGCombine()

void llvm::TargetLoweringBase::setTargetDAGCombine ( ArrayRef< ISD::NodeType NTs)
inlineprotected

◆ setTruncStoreAction()

void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotected

◆ shallExtractConstSplatVectorElementToStore()

virtual bool llvm::TargetLoweringBase::shallExtractConstSplatVectorElementToStore ( Type VectorTy,
unsigned  ElemSizeInBits,
unsigned Index 
) const
inlinevirtual

Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant.

Index[out] gives the index of the vector element to be extracted when this is true.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 940 of file TargetLowering.h.

Referenced by getMemsetStores().

◆ shouldAlignPointerArgs()

virtual bool llvm::TargetLoweringBase::shouldAlignPointerArgs ( CallInst ,
unsigned ,
Align  
) const
inlinevirtual

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2063 of file TargetLowering.h.

◆ shouldAvoidTransformToShift()

virtual bool llvm::TargetLoweringBase::shouldAvoidTransformToShift ( EVT  VT,
unsigned  Amount 
) const
inlinevirtual

Return true if creating a shift of the type by the given amount is not profitable.

Reimplemented in llvm::MSP430TargetLowering.

Definition at line 3300 of file TargetLowering.h.

Referenced by foldExtendedSignBitTest(), shouldFoldSelectWithSingleBitTest(), and llvm::TargetLowering::SimplifySetCC().

◆ shouldCastAtomicLoadInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldCastAtomicLoadInIR ( LoadInst LI) const
inlinevirtual

Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

Reimplemented in llvm::NVPTXTargetLowering.

Definition at line 2255 of file TargetLowering.h.

References CastToInteger, llvm::Value::getType(), llvm::Type::isFloatingPointTy(), and None.

◆ shouldCastAtomicRMWIInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldCastAtomicRMWIInIR ( AtomicRMWInst RMWI) const
inlinevirtual

Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.

Definition at line 2294 of file TargetLowering.h.

References CastToInteger, llvm::AtomicRMWInst::getOperation(), llvm::Value::getType(), llvm::AtomicRMWInst::getValOperand(), llvm::Type::isFloatingPointTy(), llvm::Type::isPointerTy(), None, and llvm::AtomicRMWInst::Xchg.

◆ shouldCastAtomicStoreInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldCastAtomicStoreInIR ( StoreInst SI) const
inlinevirtual

Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

For instance AtomicExpansionKind::CastToInteger will try to cast the operands to integer values.

Reimplemented in llvm::NVPTXTargetLowering.

Definition at line 2271 of file TargetLowering.h.

References CastToInteger, and None.

◆ shouldConsiderGEPOffsetSplit()

virtual bool llvm::TargetLoweringBase::shouldConsiderGEPOffsetSplit ( ) const
inlinevirtual

◆ shouldConvertConstantLoadToIntImm()

virtual bool llvm::TargetLoweringBase::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
inlinevirtual

Return true if it is beneficial to convert a load of a constant to just the constant itself.

On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3238 of file TargetLowering.h.

Referenced by getMemsetStringVal().

◆ shouldConvertFpToSat()

virtual bool llvm::TargetLoweringBase::shouldConvertFpToSat ( unsigned  Op,
EVT  FPVT,
EVT  VT 
) const
inlinevirtual

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3318 of file TargetLowering.h.

References isOperationLegalOrCustom().

Referenced by PerformMinMaxFpToSatCombine(), PerformUMinFpToSatCombine(), and llvm::AArch64TargetLowering::shouldConvertFpToSat().

◆ shouldConvertPhiType()

virtual bool llvm::TargetLoweringBase::shouldConvertPhiType ( Type From,
Type To 
) const
inlinevirtual

Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2802 of file TargetLowering.h.

References From, llvm::Type::isFloatingPointTy(), and llvm::Type::isIntegerTy().

Referenced by llvm::X86TargetLowering::shouldConvertPhiType().

◆ shouldConvertSplatType()

virtual Type * llvm::TargetLoweringBase::shouldConvertSplatType ( ShuffleVectorInst SVI) const
inlinevirtual

Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable.

Returns nullptr otherwise. For example under MVE float splats are converted to integer to prevent the need to move from SPR to GPR registers.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2795 of file TargetLowering.h.

◆ shouldExpandAtomicCmpXchgInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst AI) const
inlinevirtual

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::PPCTargetLowering, llvm::LoongArchTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 2280 of file TargetLowering.h.

References None.

Referenced by llvm::PPCTargetLowering::shouldExpandAtomicCmpXchgInIR().

◆ shouldExpandAtomicLoadInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicLoadInIR ( LoadInst LI) const
inlinevirtual

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2249 of file TargetLowering.h.

References None.

◆ shouldExpandAtomicRMWInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicRMWInIR ( AtomicRMWInst RMW) const
inlinevirtual

◆ shouldExpandAtomicStoreInIR()

virtual AtomicExpansionKind llvm::TargetLoweringBase::shouldExpandAtomicStoreInIR ( StoreInst SI) const
inlinevirtual

Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

For instance AtomicExpansionKind::Expand will try to use an atomicrmw xchg.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 2264 of file TargetLowering.h.

References None.

◆ shouldExpandBuildVectorWithShuffles()

virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtual

◆ shouldExpandCttzElements()

virtual bool llvm::TargetLoweringBase::shouldExpandCttzElements ( EVT  VT) const
inlinevirtual

Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 471 of file TargetLowering.h.

◆ shouldExpandGetActiveLaneMask()

virtual bool llvm::TargetLoweringBase::shouldExpandGetActiveLaneMask ( EVT  VT,
EVT  OpVT 
) const
inlinevirtual

Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 460 of file TargetLowering.h.

◆ shouldExpandGetVectorLength()

virtual bool llvm::TargetLoweringBase::shouldExpandGetVectorLength ( EVT  CountVT,
unsigned  VF,
bool  IsScalable 
) const
inlinevirtual

Definition at line 464 of file TargetLowering.h.

◆ shouldExtendGSIndex()

virtual bool llvm::TargetLoweringBase::shouldExtendGSIndex ( EVT  VT,
EVT EltTy 
) const
inlinevirtual

Returns true if the index type for a masked gather/scatter requires extending.

Definition at line 1549 of file TargetLowering.h.

◆ shouldExtendTypeInLibCall()

virtual bool llvm::TargetLoweringBase::shouldExtendTypeInLibCall ( EVT  Type) const
inlinevirtual

Returns true if arguments should be extended in lib calls.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 2243 of file TargetLowering.h.

Referenced by llvm::TargetLowering::makeLibCall().

◆ shouldFoldConstantShiftPairToMask()

virtual bool llvm::TargetLoweringBase::shouldFoldConstantShiftPairToMask ( const SDNode N,
CombineLevel  Level 
) const
inlinevirtual

Return true if it is profitable to fold a pair of shifts into a mask.

This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, and llvm::X86TargetLowering.

Definition at line 810 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask().

◆ shouldFoldMaskToVariableShiftPair()

virtual bool llvm::TargetLoweringBase::shouldFoldMaskToVariableShiftPair ( SDValue  X) const
inlinevirtual

There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.

Return false if there is no preference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 801 of file TargetLowering.h.

◆ shouldFoldSelectWithIdentityConstant()

virtual bool llvm::TargetLoweringBase::shouldFoldSelectWithIdentityConstant ( unsigned  BinOpcode,
EVT  VT 
) const
inlinevirtual

Return true if pulling a binary operation into a select with an identity constant is profitable.

This is the inverse of an IR transform. Example: X + (Cond ? Y : 0) --> Cond ? (X + Y) : X

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3228 of file TargetLowering.h.

◆ shouldFoldSelectWithSingleBitTest()

virtual bool llvm::TargetLoweringBase::shouldFoldSelectWithSingleBitTest ( EVT  VT,
const APInt AndMask 
) const
inlinevirtual

Definition at line 3306 of file TargetLowering.h.

References llvm::APInt::getBitWidth(), and shouldAvoidTransformToShift().

◆ shouldFormOverflowOp()

virtual bool llvm::TargetLoweringBase::shouldFormOverflowOp ( unsigned  Opcode,
EVT  VT,
bool  MathUsed 
) const
inlinevirtual

Try to convert math with an overflow comparison into the corresponding DAG node operation.

Targets may want to override this independently of whether the operation is legal/custom for the given type because it may obscure matching of other patterns.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 3270 of file TargetLowering.h.

References isOperationExpand(), llvm::EVT::isSimple(), llvm::EVT::isVector(), and llvm::ISD::UADDO.

Referenced by llvm::AArch64TargetLowering::shouldFormOverflowOp(), llvm::ARMTargetLowering::shouldFormOverflowOp(), and llvm::RISCVTargetLowering::shouldFormOverflowOp().

◆ shouldInsertFencesForAtomic()

virtual bool llvm::TargetLoweringBase::shouldInsertFencesForAtomic ( const Instruction I) const
inlinevirtual

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

This should be true for most architectures with weak memory ordering. Defaults to false.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, and llvm::VETargetLowering.

Definition at line 2116 of file TargetLowering.h.

◆ shouldInsertTrailingFenceForAtomicStore()

virtual bool llvm::TargetLoweringBase::shouldInsertTrailingFenceForAtomicStore ( const Instruction I) const
inlinevirtual

Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.

Defaults to false.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2123 of file TargetLowering.h.

◆ shouldKeepZExtForFP16Conv()

virtual bool llvm::TargetLoweringBase::shouldKeepZExtForFP16Conv ( ) const
inlinevirtual

Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 3314 of file TargetLowering.h.

◆ shouldLocalize()

bool TargetLoweringBase::shouldLocalize ( const MachineInstr MI,
const TargetTransformInfo TTI 
) const
virtual

Check whether or not MI needs to be moved close to its uses.

Definition at line 2421 of file TargetLoweringBase.cpp.

References llvm::TargetTransformInfo::getGISelRematGlobalCost(), llvm_unreachable, MI, and MRI.

◆ shouldNormalizeToSelectSequence()

virtual bool llvm::TargetLoweringBase::shouldNormalizeToSelectSequence ( LLVMContext Context,
EVT  VT 
) const
inlinevirtual

Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.

Targets that are able to perform and/or on flags should return false here.

Definition at line 2344 of file TargetLowering.h.

References Context, getTypeAction(), hasMultipleConditionRegisters(), TypeExpandFloat, TypeExpandInteger, and TypeSplitVector.

◆ shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()

virtual bool llvm::TargetLoweringBase::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd ( SDValue  X,
ConstantSDNode XC,
ConstantSDNode CC,
SDValue  Y,
unsigned  OldShiftOpcode,
unsigned  NewShiftOpcode,
SelectionDAG DAG 
) const
inlinevirtual

Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 835 of file TargetLowering.h.

References CC, hasBitTest(), llvm::ISD::SHL, X, and Y.

Referenced by llvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), and llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().

◆ shouldReassociateReduction()

virtual bool llvm::TargetLoweringBase::shouldReassociateReduction ( unsigned  RedOpc,
EVT  VT 
) const
inlinevirtual

Reimplemented in llvm::ARMTargetLowering.

Definition at line 475 of file TargetLowering.h.

◆ shouldReduceLoadWidth()

virtual bool llvm::TargetLoweringBase::shouldReduceLoadWidth ( SDNode Load,
ISD::LoadExtType  ExtTy,
EVT  NewVT 
) const
inlinevirtual

◆ shouldRemoveExtendFromGSIndex()

virtual bool llvm::TargetLoweringBase::shouldRemoveExtendFromGSIndex ( SDValue  Extend,
EVT  DataVT 
) const
inlinevirtual

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 1553 of file TargetLowering.h.

Referenced by refineIndexType().

◆ shouldRemoveRedundantExtend()

virtual bool llvm::TargetLoweringBase::shouldRemoveRedundantExtend ( SDValue  Op) const
inlinevirtual

Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1783 of file TargetLowering.h.

Referenced by llvm::TargetLowering::SimplifyMultipleUseDemandedBits().

◆ shouldScalarizeBinop()

virtual bool llvm::TargetLoweringBase::shouldScalarizeBinop ( SDValue  VecOp) const
inlinevirtual

Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3254 of file TargetLowering.h.

Referenced by scalarizeExtractedBinop().

◆ ShouldShrinkFPConstant()

virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtual

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 1767 of file TargetLowering.h.

◆ shouldSignExtendTypeInLibCall()

virtual bool llvm::TargetLoweringBase::shouldSignExtendTypeInLibCall ( EVT  Type,
bool  IsSigned 
) const
inlinevirtual

Returns true if arguments should be sign-extended in lib calls.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 2238 of file TargetLowering.h.

Referenced by llvm::SystemZTargetLowering::makeExternalCall(), and llvm::TargetLowering::makeLibCall().

◆ shouldSinkOperands()

virtual bool llvm::TargetLoweringBase::shouldSinkOperands ( Instruction I,
SmallVectorImpl< Use * > &  Ops 
) const
inlinevirtual

Return true if sinking I's operands to the same basic block as I is profitable, e.g.

because the operands can be folded into a target instruction during instruction selection. After calling the function Ops contains the Uses to sink ordered by dominance (dominating users come first).

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3009 of file TargetLowering.h.

◆ shouldSplatInsEltVarIndex()

virtual bool llvm::TargetLoweringBase::shouldSplatInsEltVarIndex ( EVT  ) const
inlinevirtual

Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.

Reimplemented in llvm::X86TargetLowering.

Definition at line 947 of file TargetLowering.h.

◆ shouldTransformSignedTruncationCheck()

virtual bool llvm::TargetLoweringBase::shouldTransformSignedTruncationCheck ( EVT  XVT,
unsigned  KeptBits 
) const
inlinevirtual

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.

Return false if there is no preference.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 822 of file TargetLowering.h.

◆ shouldUseStrictFP_TO_INT()

virtual bool llvm::TargetLoweringBase::shouldUseStrictFP_TO_INT ( EVT  FpVT,
EVT  IntVT,
bool  IsSigned 
) const
inlinevirtual

Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.

This may be true if the target throws exceptions for out of bounds conversions or has fast FP CMOV.

Definition at line 2395 of file TargetLowering.h.

Referenced by llvm::TargetLowering::expandFP_TO_UINT().

◆ signExtendConstant()

virtual bool llvm::TargetLoweringBase::signExtendConstant ( const ConstantInt C) const
inlinevirtual

Return true if this constant should be sign extended when promoting to a larger type.

Reimplemented in llvm::RISCVTargetLowering.

Definition at line 3002 of file TargetLowering.h.

Referenced by llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo().

◆ softPromoteHalfType()

virtual bool llvm::TargetLoweringBase::softPromoteHalfType ( ) const
inlinevirtual

◆ storeOfVectorConstantIsCheap()

virtual bool llvm::TargetLoweringBase::storeOfVectorConstantIsCheap ( bool  IsZero,
EVT  MemVT,
unsigned  NumElem,
unsigned  AddrSpace 
) const
inlinevirtual

Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants.

Reimplemented in llvm::RISCVTargetLowering, llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 667 of file TargetLowering.h.

◆ supportsUnalignedAtomics()

bool llvm::TargetLoweringBase::supportsUnalignedAtomics ( ) const
inline

Whether the target supports unaligned atomic operations.

Definition at line 2111 of file TargetLowering.h.

◆ useFPRegsForHalfType()

virtual bool llvm::TargetLoweringBase::useFPRegsForHalfType ( ) const
inlinevirtual

Reimplemented in llvm::ARMTargetLowering.

Definition at line 518 of file TargetLowering.h.

Referenced by computeRegisterProperties().

◆ useSoftFloat()

virtual bool llvm::TargetLoweringBase::useSoftFloat ( ) const
inlinevirtual

◆ useStackGuardXorFP()

virtual bool llvm::TargetLoweringBase::useStackGuardXorFP ( ) const
inlinevirtual

If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.

getIRStackGuard must return nullptr if this returns true.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2028 of file TargetLowering.h.

Referenced by llvm::SelectionDAGBuilder::visitSPDescriptorParent().

Member Data Documentation

◆ EnableExtLdPromotion

bool llvm::TargetLoweringBase::EnableExtLdPromotion
protected

◆ GatherAllAliasesMaxDepth

unsigned llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
protected

Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain.

As an approximation, this should be more than the number of consecutive stores expected to be merged.

Definition at line 3603 of file TargetLowering.h.

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), getGatherAllAliasesMaxDepth(), and TargetLoweringBase().

◆ IsStrictFPEnabled

bool llvm::TargetLoweringBase::IsStrictFPEnabled
protected

◆ MaxGluedStoresPerMemcpy

unsigned llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy = 0
protected

Specify max number of store instructions to glue in inlined memcpy.

When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number of store instructions to keep together. This helps in pairing and

Definition at line 3638 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), getMaxGluedStoresPerMemcpy(), and TargetLoweringBase().

◆ MaxLoadsPerMemcmp

unsigned llvm::TargetLoweringBase::MaxLoadsPerMemcmp
protected

Specify maximum number of load instructions per memcmp call.

When lowering @llvm.memcmp this field specifies the maximum number of pairs of load operations that may be substituted for a call to memcmp. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcmp will be done using as many of the largest load operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, loading 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte load, a one 2-byte load and one 1-byte load. This only applies to copying a constant array of constant size.

Definition at line 3651 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxExpandSizeMemcmp(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), and llvm::X86TargetLowering::X86TargetLowering().

◆ MaxLoadsPerMemcmpOptSize

unsigned llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
protected

◆ MaxStoresPerMemcpy

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protected

Specify maximum number of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 3630 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemcpy(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemcpyOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protected

◆ MaxStoresPerMemmove

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protected

Specify maximum number of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 3665 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemmove(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemmoveOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protected

◆ MaxStoresPerMemset

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protected

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 3615 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), getMaxStoresPerMemset(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TargetLoweringBase(), llvm::X86TargetLowering::X86TargetLowering(), and llvm::XCoreTargetLowering::XCoreTargetLowering().

◆ MaxStoresPerMemsetOptSize

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protected

◆ PredictableSelectIsExpensive

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protected

The documentation for this class was generated from the following files: