| AddressableLocalMemorySize | llvm::AMDGPUSubtarget | protected |
| adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override | llvm::GCNSubtarget | |
| AMDGPUSubtarget(Triple TT) | llvm::AMDGPUSubtarget | inline |
| checkSubtargetFeatures(const Function &F) const | llvm::GCNSubtarget | |
| computeOccupancy(const Function &F, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const | llvm::GCNSubtarget | |
| d16PreservesUnusedBits() const | llvm::GCNSubtarget | inline |
| DynamicVGPR | llvm::GCNSubtarget | protected |
| DynamicVGPRBlockSize32 | llvm::GCNSubtarget | protected |
| enableEarlyIfConversion() const override | llvm::GCNSubtarget | inline |
| enableMachineScheduler() const override | llvm::GCNSubtarget | inline |
| enableSubRegLiveness() const override | llvm::GCNSubtarget | inline |
| EUsPerCU | llvm::AMDGPUSubtarget | protected |
| EVERGREEN enum value | llvm::AMDGPUSubtarget | |
| flatScratchIsPointer() const | llvm::GCNSubtarget | inline |
| GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM) | llvm::GCNSubtarget | |
| Gen | llvm::GCNSubtarget | protected |
| Generation enum name | llvm::AMDGPUSubtarget | |
| get(const MachineFunction &MF) | llvm::AMDGPUSubtarget | static |
| get(const TargetMachine &TM, const Function &F) | llvm::AMDGPUSubtarget | static |
| getAddressableLocalMemorySize() const | llvm::AMDGPUSubtarget | inline |
| getAddressableNumArchVGPRs() const | llvm::GCNSubtarget | inline |
| getAddressableNumSGPRs() const | llvm::GCNSubtarget | inline |
| getAddressableNumVGPRs(unsigned DynamicVGPRBlockSize) const | llvm::GCNSubtarget | inline |
| getAlignmentForImplicitArgPtr() const | llvm::AMDGPUSubtarget | inline |
| getAMDGPUDwarfFlavour() const | llvm::AMDGPUSubtarget | |
| getBaseMaxNumSGPRs(const Function &F, std::pair< unsigned, unsigned > WavesPerEU, unsigned PreloadedSGPRs, unsigned ReservedNumSGPRs) const | llvm::GCNSubtarget | |
| getBaseMaxNumVGPRs(const Function &F, std::pair< unsigned, unsigned > NumVGPRBounds) const | llvm::GCNSubtarget | |
| getBaseReservedNumSGPRs(const bool HasFlatScratch) const | llvm::GCNSubtarget | |
| getBoolRC() const | llvm::GCNSubtarget | inline |
| getCallLowering() const override | llvm::GCNSubtarget | inline |
| getConstantBusLimit(unsigned Opcode) const | llvm::GCNSubtarget | |
| getDefaultFlatWorkGroupSize(CallingConv::ID CC) const | llvm::AMDGPUSubtarget | |
| getDynamicVGPRBlockSize() const | llvm::GCNSubtarget | inline |
| getEffectiveWavesPerEU(std::pair< unsigned, unsigned > RequestedWavesPerEU, std::pair< unsigned, unsigned > FlatWorkGroupSizes, unsigned LDSBytes) const | llvm::AMDGPUSubtarget | |
| getEUsPerCU() const | llvm::AMDGPUSubtarget | inline |
| getExplicitKernArgSize(const Function &F, Align &MaxAlign) const | llvm::AMDGPUSubtarget | |
| getExplicitKernelArgOffset() const | llvm::AMDGPUSubtarget | inline |
| getFlatWorkGroupSizes(const Function &F) const | llvm::AMDGPUSubtarget | |
| getFrameLowering() const override | llvm::GCNSubtarget | inline |
| getGeneration() const | llvm::GCNSubtarget | inline |
| getImplicitArgNumBytes(const Function &F) const | llvm::AMDGPUSubtarget | |
| getInlineAsmLowering() const override | llvm::GCNSubtarget | inline |
| getInstrInfo() const override | llvm::GCNSubtarget | inline |
| getInstrItineraryData() const override | llvm::GCNSubtarget | inline |
| getInstructionSelector() const override | llvm::GCNSubtarget | inline |
| getKernArgSegmentSize(const Function &F, Align &MaxAlign) const | llvm::AMDGPUSubtarget | |
| getKnownHighZeroBitsForFrameIndex() const | llvm::GCNSubtarget | inline |
| getLDSBankCount() const | llvm::GCNSubtarget | inline |
| getLegalizerInfo() const override | llvm::GCNSubtarget | inline |
| getLocalMemorySize() const | llvm::AMDGPUSubtarget | inline |
| getMaxFlatWorkGroupSize() const override | llvm::GCNSubtarget | inlinevirtual |
| getMaxLocalMemSizeWithWaveCount(unsigned WaveCount, const Function &) const | llvm::GCNSubtarget | |
| getMaxNumAGPRs(const Function &F) const | llvm::GCNSubtarget | inline |
| getMaxNumPreloadedSGPRs() const | llvm::GCNSubtarget | |
| getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const | llvm::GCNSubtarget | inline |
| getMaxNumSGPRs(const MachineFunction &MF) const | llvm::GCNSubtarget | |
| getMaxNumSGPRs(const Function &F) const | llvm::GCNSubtarget | |
| getMaxNumUserSGPRs() const | llvm::GCNSubtarget | inline |
| getMaxNumVectorRegs(const Function &F) const | llvm::GCNSubtarget | |
| getMaxNumVGPRs(unsigned WavesPerEU, unsigned DynamicVGPRBlockSize) const | llvm::GCNSubtarget | inline |
| getMaxNumVGPRs(const Function &F) const | llvm::GCNSubtarget | |
| getMaxNumVGPRs(const MachineFunction &MF) const | llvm::GCNSubtarget | |
| getMaxNumWorkGroups(const Function &F) const | llvm::AMDGPUSubtarget | |
| getMaxPrivateElementSize(bool ForBufferRSrc=false) const | llvm::GCNSubtarget | inline |
| getMaxWaveScratchSize() const | llvm::GCNSubtarget | inline |
| getMaxWavesPerEU() const | llvm::GCNSubtarget | inline |
| getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override | llvm::GCNSubtarget | inlinevirtual |
| getMaxWorkitemID(const Function &Kernel, unsigned Dimension) const | llvm::AMDGPUSubtarget | |
| getMinFlatWorkGroupSize() const override | llvm::GCNSubtarget | inlinevirtual |
| getMinNumSGPRs(unsigned WavesPerEU) const | llvm::GCNSubtarget | inline |
| getMinNumVGPRs(unsigned WavesPerEU, unsigned DynamicVGPRBlockSize) const | llvm::GCNSubtarget | inline |
| getMinWavesPerEU() const override | llvm::GCNSubtarget | inlinevirtual |
| getNSAMaxSize(bool HasSampler=false) const | llvm::GCNSubtarget | inline |
| getNSAThreshold(const MachineFunction &MF) const | llvm::GCNSubtarget | |
| getOccupancyWithNumSGPRs(unsigned SGPRs) const | llvm::GCNSubtarget | |
| getOccupancyWithNumVGPRs(unsigned VGPRs, unsigned DynamicVGPRBlockSize) const | llvm::GCNSubtarget | |
| getOccupancyWithWorkGroupSizes(uint32_t LDSBytes, const Function &F) const | llvm::AMDGPUSubtarget | inline |
| getOccupancyWithWorkGroupSizes(uint32_t LDSBytes, std::pair< unsigned, unsigned > FlatWorkGroupSizes) const | llvm::AMDGPUSubtarget | |
| getOccupancyWithWorkGroupSizes(const MachineFunction &MF) const | llvm::AMDGPUSubtarget | |
| getRegBankInfo() const override | llvm::GCNSubtarget | inline |
| getRegisterInfo() const override | llvm::GCNSubtarget | inline |
| getReqdWorkGroupSize(const Function &F, unsigned Dim) const | llvm::AMDGPUSubtarget | |
| getReservedNumSGPRs(const MachineFunction &MF) const | llvm::GCNSubtarget | |
| getReservedNumSGPRs(const Function &F) const | llvm::GCNSubtarget | |
| getScalarizeGlobalBehavior() const | llvm::GCNSubtarget | inline |
| getSelectionDAGInfo() const override | llvm::GCNSubtarget | |
| getSetRegWaitStates() const | llvm::GCNSubtarget | inline |
| getSGPRAllocGranule() const | llvm::GCNSubtarget | inline |
| getSGPREncodingGranule() const | llvm::GCNSubtarget | inline |
| getSNopBits() const | llvm::GCNSubtarget | inline |
| getStackAlignment() const | llvm::GCNSubtarget | inline |
| getTargetID() const | llvm::GCNSubtarget | inline |
| getTargetLowering() const override | llvm::GCNSubtarget | inline |
| getTotalNumSGPRs() const | llvm::GCNSubtarget | inline |
| getTotalNumVGPRs() const | llvm::GCNSubtarget | inline |
| getTrapHandlerAbi() const | llvm::GCNSubtarget | inline |
| getVGPRAllocGranule(unsigned DynamicVGPRBlockSize) const | llvm::GCNSubtarget | inline |
| getVGPREncodingGranule() const | llvm::GCNSubtarget | inline |
| getWavefrontSize() const | llvm::AMDGPUSubtarget | inline |
| getWavefrontSizeLog2() const | llvm::AMDGPUSubtarget | inline |
| getWavesPerEU(const Function &F) const | llvm::AMDGPUSubtarget | |
| getWavesPerEU(const Function &F, std::pair< unsigned, unsigned > FlatWorkGroupSizes) const | llvm::AMDGPUSubtarget | |
| getWavesPerEU(std::pair< unsigned, unsigned > FlatWorkGroupSizes, unsigned LDSBytes, const Function &F) const | llvm::AMDGPUSubtarget | |
| getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override | llvm::GCNSubtarget | inlinevirtual |
| GFX10 enum value | llvm::AMDGPUSubtarget | |
| GFX11 enum value | llvm::AMDGPUSubtarget | |
| GFX12 enum value | llvm::AMDGPUSubtarget | |
| GFX13 enum value | llvm::AMDGPUSubtarget | |
| GFX9 enum value | llvm::AMDGPUSubtarget | |
| has12DWordStoreHazard() const | llvm::GCNSubtarget | inline |
| hasAddPC64Inst() const | llvm::GCNSubtarget | inline |
| hasAddr64() const | llvm::GCNSubtarget | inline |
| hasAtomicCSub() const | llvm::GCNSubtarget | inline |
| hasAtomicFaddInsts() const | llvm::GCNSubtarget | inline |
| hasCompressedExport() const | llvm::GCNSubtarget | inline |
| hasCondSubInsts() const | llvm::GCNSubtarget | inline |
| hasCvtScaleForwardingHazard() const | llvm::GCNSubtarget | inline |
| hasD16Images() const | llvm::GCNSubtarget | inline |
| hasD16LoadStore() const | llvm::GCNSubtarget | inline |
| hasDelayAlu() const | llvm::GCNSubtarget | inline |
| hasDenormModeInst() const | llvm::GCNSubtarget | inline |
| hasDOTOpSelHazard() const | llvm::GCNSubtarget | inline |
| hasDPPBroadcasts() const | llvm::GCNSubtarget | inline |
| hasDPPWavefrontShifts() const | llvm::GCNSubtarget | inline |
| hasDS96AndDS128() const | llvm::GCNSubtarget | inline |
| hasDsAtomicAsyncBarrierArriveB64PipeBug() const | llvm::GCNSubtarget | inline |
| hasDstSelForwardingHazard() const | llvm::GCNSubtarget | inline |
| hasDwordx3LoadStores() const | llvm::GCNSubtarget | inline |
| hasDX10ClampMode() const | llvm::GCNSubtarget | inline |
| hasExpertSchedulingMode() const | llvm::GCNSubtarget | inline |
| hasExportInsts() const | llvm::GCNSubtarget | inline |
| hasExtendedWaitCounts() const | llvm::GCNSubtarget | inline |
| hasFlat() const | llvm::GCNSubtarget | inline |
| hasFlatLgkmVMemCountInOrder() const | llvm::GCNSubtarget | inline |
| hasFlatScratchEnabled() const | llvm::GCNSubtarget | inline |
| hasFlatScratchHiInB64InstHazard() const | llvm::GCNSubtarget | inline |
| hasFlatScratchSTMode() const | llvm::GCNSubtarget | inline |
| hasFlatScratchSVSMode() const | llvm::GCNSubtarget | inline |
| hasFlatScratchSVSSwizzleBug() const | llvm::GCNSubtarget | inline |
| hasFlatScrRegister() const | llvm::GCNSubtarget | inline |
| hasFmaakFmamkF32Insts() const | llvm::GCNSubtarget | inline |
| hasFmaakFmamkF64Insts() const | llvm::GCNSubtarget | inline |
| HasFminFmaxLegacy | llvm::AMDGPUSubtarget | protected |
| hasFminFmaxLegacy() const | llvm::AMDGPUSubtarget | inline |
| hasFormattedMUBUFInsts() const | llvm::GCNSubtarget | inline |
| hasFPAtomicToDenormModeHazard() const | llvm::GCNSubtarget | inline |
| hasFractBug() const | llvm::GCNSubtarget | inline |
| hasGetPCZeroExtension() const | llvm::GCNSubtarget | inline |
| hasGlobalAddTidInsts() const | llvm::GCNSubtarget | inline |
| hasGWSAutoReplay() const | llvm::GCNSubtarget | inline |
| hasGWSSemaReleaseAll() const | llvm::GCNSubtarget | inline |
| hasHalfRate64Ops(const TargetSubtargetInfo &STI) | llvm::GCNSubtarget | static |
| hasHardClauses() const | llvm::GCNSubtarget | inline |
| hasHWFP64() const | llvm::GCNSubtarget | inline |
| hasIEEEMode() const | llvm::GCNSubtarget | inline |
| hasInstPrefetch() const | llvm::GCNSubtarget | inline |
| hasIntMinMax64() const | llvm::GCNSubtarget | inline |
| hasINVWBL2WaitCntRequirement() const | llvm::GCNSubtarget | inline |
| hasLdsAtomicAddF64() const | llvm::GCNSubtarget | inline |
| hasLdsDirect() const | llvm::GCNSubtarget | inline |
| hasLDSFPAtomicAddF32() const | llvm::GCNSubtarget | inline |
| hasLDSFPAtomicAddF64() const | llvm::GCNSubtarget | inline |
| hasLDSLoadB96_B128() const | llvm::GCNSubtarget | inline |
| hasLDSMisalignedBugInWGPMode() const | llvm::GCNSubtarget | inline |
| hasLdsWaitVMSRC() const | llvm::GCNSubtarget | inline |
| hasLegacyGeometry() const | llvm::GCNSubtarget | inline |
| hasMad64_32() const | llvm::GCNSubtarget | inline |
| hasMadF16() const | llvm::GCNSubtarget | |
| hasMadU64U32NoCarry() const | llvm::GCNSubtarget | inline |
| hasMed3_16() const | llvm::GCNSubtarget | inline |
| hasMergedShaders() const | llvm::GCNSubtarget | inline |
| hasMin3Max3_16() const | llvm::GCNSubtarget | inline |
| hasMovB64() const | llvm::GCNSubtarget | inline |
| hasMTBUFInsts() const | llvm::GCNSubtarget | inline |
| HasMulI24 | llvm::AMDGPUSubtarget | protected |
| hasMulI24() const | llvm::AMDGPUSubtarget | inline |
| hasMultiDwordFlatScratchAddressing() const | llvm::GCNSubtarget | inline |
| HasMulU24 | llvm::AMDGPUSubtarget | protected |
| hasMulU24() const | llvm::AMDGPUSubtarget | inline |
| hasNoF16PseudoScalarTransInlineConstants() const | llvm::GCNSubtarget | inline |
| hasNonNSAEncoding() const | llvm::GCNSubtarget | inline |
| hasNullExportTarget() const | llvm::GCNSubtarget | inline |
| hasOnlyRevVALUShifts() const | llvm::GCNSubtarget | inline |
| hasPermLane64() const | llvm::GCNSubtarget | inline |
| hasPermLaneX16() const | llvm::GCNSubtarget | inline |
| hasPKF32InstsReplicatingLower32BitsOfScalarInput() const | llvm::GCNSubtarget | inline |
| hasPkMinMax3Insts() const | llvm::GCNSubtarget | inline |
| hasPkMovB32() const | llvm::GCNSubtarget | inline |
| hasPrefetch() const | llvm::GCNSubtarget | inline |
| hasReadM0LdsDirectHazard() const | llvm::GCNSubtarget | inline |
| hasReadM0LdsDmaHazard() const | llvm::GCNSubtarget | inline |
| hasReadM0MovRelInterpHazard() const | llvm::GCNSubtarget | inline |
| hasReadM0SendMsgHazard() const | llvm::GCNSubtarget | inline |
| hasReadVCCZBug() const | llvm::GCNSubtarget | inline |
| hasRFEHazards() const | llvm::GCNSubtarget | inline |
| hasRrWGMode() const | llvm::GCNSubtarget | inline |
| hasScalarAddSub64() const | llvm::GCNSubtarget | inline |
| hasScalarCompareEq64() const | llvm::GCNSubtarget | inline |
| hasScalarMulHiInsts() const | llvm::GCNSubtarget | inline |
| hasScalarPackInsts() const | llvm::GCNSubtarget | inline |
| hasScalarSMulU64() const | llvm::GCNSubtarget | inline |
| hasScalarSubwordLoads() const | llvm::GCNSubtarget | inline |
| hasScaleOffset() const | llvm::GCNSubtarget | inline |
| hasSCmpK() const | llvm::GCNSubtarget | inline |
| hasScratchBaseForwardingHazard() const | llvm::GCNSubtarget | inline |
| hasSGetShaderCyclesInst() const | llvm::GCNSubtarget | inline |
| hasShift64HighRegBug() const | llvm::GCNSubtarget | inline |
| hasSignedGVSOffset() const | llvm::GCNSubtarget | inline |
| hasSignedScratchOffsets() const | llvm::GCNSubtarget | inline |
| hasSMRDReadVALUDefHazard() const | llvm::GCNSubtarget | inline |
| HasSMulHi | llvm::AMDGPUSubtarget | protected |
| hasSMulHi() const | llvm::AMDGPUSubtarget | inline |
| hasSPackHL() const | llvm::GCNSubtarget | inline |
| hasSplitBarriers() const | llvm::GCNSubtarget | inline |
| hasSubClampInsts() const | llvm::GCNSubtarget | inline |
| hasSwap() const | llvm::GCNSubtarget | inline |
| hasTransForwardingHazard() const | llvm::GCNSubtarget | inline |
| hasUnalignedBufferAccessEnabled() const | llvm::GCNSubtarget | inline |
| hasUnalignedDSAccessEnabled() const | llvm::GCNSubtarget | inline |
| hasUnalignedScratchAccessEnabled() const | llvm::GCNSubtarget | inline |
| hasUsableDivScaleConditionOutput() const | llvm::GCNSubtarget | inline |
| hasUsableDSOffset() const | llvm::GCNSubtarget | inline |
| hasUserSGPRInit16BugInWave32() const | llvm::GCNSubtarget | inline |
| hasVALUMaskWriteHazard() const | llvm::GCNSubtarget | inline |
| hasVALUPartialForwardingHazard() const | llvm::GCNSubtarget | inline |
| hasVALUReadSGPRHazard() const | llvm::GCNSubtarget | inline |
| hasVDecCoExecHazard() const | llvm::GCNSubtarget | inline |
| hasVectorMulU64() const | llvm::GCNSubtarget | inline |
| hasVINTERPEncoding() const | llvm::GCNSubtarget | inline |
| hasVMEMReadSGPRVALUDefHazard() const | llvm::GCNSubtarget | inline |
| hasVOP3DPP() const | llvm::GCNSubtarget | inline |
| hasVOPD3() const | llvm::GCNSubtarget | inline |
| hasWavefrontsEvenlySplittingXDim(const Function &F, bool REquiresUniformYZ=false) const | llvm::AMDGPUSubtarget | |
| haveRoundOpsF64() const | llvm::GCNSubtarget | inline |
| initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS) | llvm::GCNSubtarget | |
| InstrItins | llvm::GCNSubtarget | protected |
| INVALID enum value | llvm::AMDGPUSubtarget | |
| isAmdHsaOrMesa(const Function &F) const | llvm::AMDGPUSubtarget | inline |
| isAmdHsaOS() const | llvm::AMDGPUSubtarget | inline |
| isAmdPalOS() const | llvm::AMDGPUSubtarget | inline |
| isCuModeEnabled() const | llvm::GCNSubtarget | inline |
| isDynamicVGPREnabled() const | llvm::GCNSubtarget | inline |
| isGCN() const | llvm::AMDGPUSubtarget | inline |
| isGFX11Plus() const | llvm::GCNSubtarget | inline |
| isMesa3DOS() const | llvm::AMDGPUSubtarget | inline |
| isMesaGfxShader(const Function &F) const | llvm::GCNSubtarget | inline |
| isMesaKernel(const Function &F) const | llvm::AMDGPUSubtarget | |
| isPreciseMemoryEnabled() const | llvm::GCNSubtarget | inline |
| isSingleLaneExecution(const Function &Kernel) const | llvm::AMDGPUSubtarget | |
| isTgSplitEnabled() const | llvm::GCNSubtarget | inline |
| isWave32() const | llvm::GCNSubtarget | inline |
| isWave64() const | llvm::GCNSubtarget | inline |
| isWaveSizeKnown() const | llvm::GCNSubtarget | inline |
| isXNACKEnabled() const | llvm::GCNSubtarget | inline |
| LDSBankCount | llvm::GCNSubtarget | protected |
| ldsRequiresM0Init() const | llvm::GCNSubtarget | inline |
| loadStoreOptEnabled() const | llvm::GCNSubtarget | inline |
| LocalMemorySize | llvm::AMDGPUSubtarget | protected |
| makeLIDRangeMetadata(Instruction *I) const | llvm::AMDGPUSubtarget | |
| MaxHardClauseLength | llvm::GCNSubtarget | protected |
| maxHardClauseLength() const | llvm::GCNSubtarget | inline |
| MaxPrivateElementSize | llvm::GCNSubtarget | protected |
| MaxWavesPerEU | llvm::AMDGPUSubtarget | protected |
| mirFileLoaded(MachineFunction &MF) const override | llvm::GCNSubtarget | |
| needsAlignedVGPRs() const | llvm::GCNSubtarget | inline |
| needsKernArgPreloadProlog() const | llvm::GCNSubtarget | inline |
| NORTHERN_ISLANDS enum value | llvm::AMDGPUSubtarget | |
| overridePostRASchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override | llvm::GCNSubtarget | |
| overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override | llvm::GCNSubtarget | |
| ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::GCNSubtarget | |
| partialVCCWritesUpdateVCCZ() const | llvm::GCNSubtarget | inline |
| privateMemoryResourceIsRangeChecked() const | llvm::GCNSubtarget | inline |
| R600 enum value | llvm::AMDGPUSubtarget | |
| R700 enum value | llvm::AMDGPUSubtarget | |
| requiresCodeObjectV6() const | llvm::GCNSubtarget | inline |
| requiresDisjointEarlyClobberAndUndef() const override | llvm::GCNSubtarget | inline |
| requiresNopBeforeDeallocVGPRs() const | llvm::GCNSubtarget | inline |
| requiresWaitIdleBeforeGetReg() const | llvm::GCNSubtarget | inline |
| requiresWaitOnWorkgroupReleaseFence() const | llvm::GCNSubtarget | inline |
| requiresWaitXCntForSingleAccessInstructions() const | llvm::GCNSubtarget | inline |
| ScalarizeGlobal | llvm::GCNSubtarget | protected |
| SEA_ISLANDS enum value | llvm::AMDGPUSubtarget | |
| setRegModeNeedsVNOPs() const | llvm::GCNSubtarget | inline |
| setScalarizeGlobalBehavior(bool b) | llvm::GCNSubtarget | inline |
| shouldClusterStores() const | llvm::GCNSubtarget | inline |
| SOUTHERN_ISLANDS enum value | llvm::AMDGPUSubtarget | |
| supportsBPermute() const | llvm::GCNSubtarget | inline |
| supportsGetDoorbellID() const | llvm::GCNSubtarget | inline |
| supportsMinMaxDenormModes() const | llvm::GCNSubtarget | inline |
| supportsWave32() const | llvm::GCNSubtarget | inline |
| supportsWave64() const | llvm::GCNSubtarget | inline |
| supportsWaveWideBPermute() const | llvm::GCNSubtarget | inline |
| supportsWGP() const | llvm::GCNSubtarget | inline |
| TargetID | llvm::GCNSubtarget | protected |
| TrapHandlerAbi enum name | llvm::GCNSubtarget | |
| TrapID enum name | llvm::GCNSubtarget | |
| unsafeDSOffsetFoldingEnabled() const | llvm::GCNSubtarget | inline |
| useAA() const override | llvm::GCNSubtarget | |
| useDS128() const | llvm::GCNSubtarget | inline |
| usePRTStrictNull() const | llvm::GCNSubtarget | inline |
| useRealTrue16Insts() const | llvm::GCNSubtarget | inline |
| useVGPRBlockOpsForCSR() const | llvm::GCNSubtarget | inline |
| useVGPRIndexMode() const | llvm::GCNSubtarget | |
| vmemWriteNeedsExpWaitcnt() const | llvm::GCNSubtarget | inline |
| VOLCANIC_ISLANDS enum value | llvm::AMDGPUSubtarget | |
| WavefrontSizeLog2 | llvm::AMDGPUSubtarget | protected |
| zeroesHigh16BitsOfDest(unsigned Opcode) const | llvm::GCNSubtarget | |
| ~AMDGPUSubtarget()=default | llvm::AMDGPUSubtarget | virtual |
| ~GCNSubtarget() override | llvm::GCNSubtarget | |
1.14.0