LLVM  14.0.0git
llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::PPCInstrInfo
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const overridellvm::PPCInstrInfo
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const overridellvm::PPCInstrInfo
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const overridellvm::PPCInstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const overridellvm::PPCInstrInfo
ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const overridellvm::PPCInstrInfo
combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) constllvm::PPCInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const overridellvm::PPCInstrInfoprotected
convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) constllvm::PPCInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const overridellvm::PPCInstrInfo
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const overridellvm::PPCInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::PPCInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::PPCInstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::PPCInstrInfo
expandVSXMemPseudo(MachineInstr &MI) constllvm::PPCInstrInfo
finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const overridellvm::PPCInstrInfo
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::PPCInstrInfo
findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) constllvm::PPCInstrInfo
fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) constllvm::PPCInstrInfo
foldFrameOffset(MachineInstr &MI) constllvm::PPCInstrInfo
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const overridellvm::PPCInstrInfo
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const overridellvm::PPCInstrInfo
getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) constllvm::PPCInstrInfo
getExtendResourceLenLimit() const overridellvm::PPCInstrInfoinline
getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) constllvm::PPCInstrInfo
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const overridellvm::PPCInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::PPCInstrInfo
getLoadOpcodeForSpill(const TargetRegisterClass *RC) constllvm::PPCInstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const overridellvm::PPCInstrInfo
getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const overridellvm::PPCInstrInfo
getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) constllvm::PPCInstrInfo
getNop() const overridellvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const overridellvm::PPCInstrInfoinline
getRecordFormOpcode(unsigned Opcode)llvm::PPCInstrInfostatic
getRegisterInfo() constllvm::PPCInstrInfoinline
getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)llvm::PPCInstrInfoinlinestatic
getSerializableBitmaskMachineOperandTargetFlags() const overridellvm::PPCInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::PPCInstrInfo
getStoreOpcodeForSpill(const TargetRegisterClass *RC) constllvm::PPCInstrInfo
hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const overridellvm::PPCInstrInfoinline
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::PPCInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::PPCInstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const overridellvm::PPCInstrInfo
instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) constllvm::PPCInstrInfo
isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) constllvm::PPCInstrInfo
isADDInstrEligibleForFolding(MachineInstr &ADDMI) constllvm::PPCInstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst) const overridellvm::PPCInstrInfo
isBDNZ(unsigned Opcode) constllvm::PPCInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const overridellvm::PPCInstrInfo
isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) constllvm::PPCInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::PPCInstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::PPCInstrInfo
isPrefixed(unsigned Opcode) constllvm::PPCInstrInfoinline
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::PPCInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::PPCInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const overridellvm::PPCInstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const overridellvm::PPCInstrInfoinline
isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const overridellvm::PPCInstrInfo
isSameClassPhysRegCopy(unsigned Opcode)llvm::PPCInstrInfoinlinestatic
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::PPCInstrInfo
isSignExtended(const MachineInstr &MI, const unsigned depth=0) constllvm::PPCInstrInfoinline
isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) constllvm::PPCInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::PPCInstrInfo
isTOCSaveMI(const MachineInstr &MI) constllvm::PPCInstrInfo
isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) constllvm::PPCInstrInfo
isVFRegister(unsigned Reg)llvm::PPCInstrInfoinlinestatic
isVRRegister(unsigned Reg)llvm::PPCInstrInfoinlinestatic
isXFormMemOp(unsigned Opcode) constllvm::PPCInstrInfoinline
isZeroExtended(const MachineInstr &MI, const unsigned depth=0) constllvm::PPCInstrInfoinline
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::PPCInstrInfo
loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) constllvm::PPCInstrInfo
onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) constllvm::PPCInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const overridellvm::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)llvm::PPCInstrInfoexplicit
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::PPCInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::PPCInstrInfo
replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) constllvm::PPCInstrInfo
replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) constllvm::PPCInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::PPCInstrInfo
setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const overridellvm::PPCInstrInfo
setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const overridellvm::PPCInstrInfo
shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const overridellvm::PPCInstrInfo
shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const overridellvm::PPCInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::PPCInstrInfo
storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) constllvm::PPCInstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::PPCInstrInfo
updatedRC(const TargetRegisterClass *RC) constllvm::PPCInstrInfo
useMachineCombiner() const overridellvm::PPCInstrInfoinline