LLVM
15.0.0git
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#include "Target/PowerPC/PPCInstrInfo.h"
Public Member Functions | |
PPCInstrInfo (PPCSubtarget &STI) | |
const PPCRegisterInfo & | getRegisterInfo () const |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More... | |
bool | isXFormMemOp (unsigned Opcode) const |
bool | isPrefixed (unsigned Opcode) const |
bool | isNoTOCCallInstr (unsigned Opcode) const |
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation. More... | |
ScheduleHazardRecognizer * | CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override |
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG. More... | |
ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override |
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG. More... | |
unsigned | getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override |
int | getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override |
int | getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override |
bool | hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override |
bool | useMachineCombiner () const override |
void | genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override |
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More... | |
bool | getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const |
Return true when there is potentially a faster code sequence for a fma chain ending in Root . More... | |
bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override |
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More... | |
bool | shouldReduceRegisterPressure (MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override |
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB. More... | |
void | finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override |
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner. More... | |
bool | isAssociativeAndCommutative (const MachineInstr &Inst) const override |
int | getExtendResourceLenLimit () const override |
On PowerPC, we try to reassociate FMA chain which will increase instruction size. More... | |
void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override |
This is an architecture-specific helper function of reassociateOps. More... | |
void | setSpecialOperandAttr (MachineInstr &MI, uint16_t Flags) const |
bool | isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override |
unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
bool | isReallyTriviallyReMaterializable (const MachineInstr &MI, AAResults *AA) const override |
unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
bool | findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override |
void | insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override |
bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
bool | canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override |
void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override |
void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override |
void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
void | storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const |
void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
void | loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const |
unsigned | getStoreOpcodeForSpill (const TargetRegisterClass *RC) const |
unsigned | getLoadOpcodeForSpill (const TargetRegisterClass *RC) const |
bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
bool | FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override |
bool | onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const |
bool | isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override |
bool | isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override |
bool | isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override |
bool | isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override |
bool | isPredicated (const MachineInstr &MI) const override |
bool | isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override |
bool | PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override |
bool | SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override |
bool | ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override |
bool | analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override |
bool | optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override |
bool | getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const |
Return true if get the base operand, byte offset of an instruction and the memory width. More... | |
bool | getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override |
Get the base operand and byte offset of an instruction that reads/writes memory. More... | |
bool | shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override |
Returns true if the two given memory operations should be scheduled adjacent. More... | |
bool | areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override |
Return true if two MIs access different memory addresses and false otherwise. More... | |
unsigned | getInstSizeInBytes (const MachineInstr &MI) const override |
GetInstSize - Return the number of bytes of code the specified instruction may be. More... | |
MCInst | getNop () const override |
Return the noop instruction to use for a noop. More... | |
std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned TF) const override |
ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const override |
ArrayRef< std::pair< unsigned, const char * > > | getSerializableBitmaskMachineOperandTargetFlags () const override |
bool | expandVSXMemPseudo (MachineInstr &MI) const |
bool | expandPostRAPseudo (MachineInstr &MI) const override |
const TargetRegisterClass * | updatedRC (const TargetRegisterClass *RC) const |
bool | isTOCSaveMI (const MachineInstr &MI) const |
bool | isSignOrZeroExtended (const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const |
bool | isSignExtended (const MachineInstr &MI, const unsigned depth=0) const |
Return true if the output of the instruction is always a sign-extended, i.e. More... | |
bool | isZeroExtended (const MachineInstr &MI, const unsigned depth=0) const |
Return true if the output of the instruction is always zero-extended, i.e. More... | |
bool | convertToImmediateForm (MachineInstr &MI, MachineInstr **KilledDef=nullptr) const |
bool | foldFrameOffset (MachineInstr &MI) const |
bool | combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const |
bool | isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const |
bool | isADDInstrEligibleForFolding (MachineInstr &ADDMI) const |
bool | isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const |
bool | isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const |
void | fixupIsDeadOrKill (MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const |
Fixup killed/dead flag for register RegNo between instructions [StartMI , EndMI ]. More... | |
void | replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const |
void | replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const |
bool | instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const |
MachineInstr * | getDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const |
void | materializeImmPostRA (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const |
bool | isBDNZ (unsigned Opcode) const |
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). More... | |
MachineInstr * | findLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const |
Find the hardware loop instruction used to set-up the specified loop. More... | |
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > | analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override |
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More... | |
Static Public Member Functions | |
static bool | isSameClassPhysRegCopy (unsigned Opcode) |
static bool | isVFRegister (unsigned Reg) |
static bool | isVRRegister (unsigned Reg) |
static int | getRecordFormOpcode (unsigned Opcode) |
static unsigned | getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo) |
getRegNumForOperand - some operands use different numbering schemes for the same registers. More... | |
Protected Member Functions | |
MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override |
Commutes the operands in the given instruction. More... | |
Definition at line 191 of file PPCInstrInfo.h.
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Definition at line 90 of file PPCInstrInfo.cpp.
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Definition at line 1273 of file PPCInstrInfo.cpp.
References B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DisableCTRLoopAnal, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), llvm::PPCSubtarget::isPPC64(), MBB, llvm::PPC::PRED_BIT_SET, and llvm::PPC::PRED_BIT_UNSET.
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Definition at line 2354 of file PPCInstrInfo.cpp.
References llvm::BitmaskEnumDetail::Mask(), and MI.
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Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Definition at line 5482 of file PPCInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().
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Return true if two MIs access different memory addresses and false otherwise.
Definition at line 5540 of file PPCInstrInfo.cpp.
References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::max(), llvm::MachineInstr::mayLoadOrStore(), llvm::min(), and TRI.
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Definition at line 1533 of file PPCInstrInfo.cpp.
References Cond, llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::Register::isPhysicalRegister(), MBB, and MRI.
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Definition at line 2319 of file PPCInstrInfo.cpp.
References llvm::array_lengthof(), c, llvm::TargetRegisterClass::contains(), and MI.
bool PPCInstrInfo::combineRLWINM | ( | MachineInstr & | MI, |
MachineInstr ** | ToErase = nullptr |
||
) | const |
Definition at line 3760 of file PPCInstrInfo.cpp.
References assert(), llvm::dbgs(), llvm::Pass::dump(), llvm::MachineInstr::dump(), get, llvm::APInt::getBitsSetWithWrap(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::APInt::getZExtValue(), llvm::MachineInstr::hasImplicitDef(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::isRunOfOnes(), llvm::Register::isVirtualRegister(), llvm::APInt::isZero(), LLVM_DEBUG, MI, MRI, llvm::APInt::rotl(), llvm::MachineOperand::setIsKill(), llvm::JumpTable::Simplified, and llvm::MachineRegisterInfo::use_nodbg_empty().
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Commutes the operands in the given instruction.
The commutable operands are specified by their indices OpIdx1 and OpIdx2.
Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.
Definition at line 1144 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.
bool PPCInstrInfo::convertToImmediateForm | ( | MachineInstr & | MI, |
MachineInstr ** | KilledDef = nullptr |
||
) | const |
Definition at line 3708 of file PPCInstrInfo.cpp.
References assert(), DefMI, llvm::PPCRegisterInfo::getMappedIdxOpcForImmOpc(), llvm::MachineFunction::getRegInfo(), instrHasImmForm(), llvm::MachineRegisterInfo::isSSA(), isVFRegister(), MI, and MRI.
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Definition at line 1688 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, llvm::PPCRegisterInfo::emitAccCopyInfo(), get, getCRBitValue(), llvm::getCRFromCRBit(), llvm::MCRegisterInfo::getEncodingValue(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MCInstrDesc::getNumOperands(), getRegisterInfo(), llvm::PPCSubtarget::hasDirectMove(), llvm::PPCSubtarget::hasP9Vector(), I, llvm::RegState::Kill, llvm_unreachable, MBB, llvm::PPCISD::MFOCRF, llvm::ISD::OR, llvm::PPCSubtarget::pairedVectorMemops(), TRI, VSXSelfCopyCrash, and llvm::PPCISD::XXMFACC.
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CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.
Definition at line 99 of file PPCInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.
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CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.
Definition at line 116 of file PPCInstrInfo.cpp.
References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.
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Definition at line 2892 of file PPCInstrInfo.cpp.
References llvm::BitmaskEnumDetail::Mask(), and llvm::PPCII::MO_ACCESS_MASK.
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Definition at line 3003 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, expandVSXMemPseudo(), get, llvm::PPCSubtarget::hasP8Vector(), llvm::PPCSubtarget::hasP9Vector(), llvm::PPCSubtarget::hasVSX(), isAnImmediateOperand(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isTargetLinux(), llvm::ARM_MB::LD, LLVM_FALLTHROUGH, MBB, MI, llvm::PPC::PRED_NE_MINUS, and R2.
bool PPCInstrInfo::expandVSXMemPseudo | ( | MachineInstr & | MI | ) | const |
Definition at line 2937 of file PPCInstrInfo.cpp.
References get, llvm::PPCISD::LFIWAX, llvm::PPCISD::LFIWZX, llvm_unreachable, MI, and llvm::PPCISD::STFIWX.
Referenced by expandPostRAPseudo().
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Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Definition at line 543 of file PPCInstrInfo.cpp.
References assert(), llvm::APFloat::changeSign(), FMAOpIdxInfo, llvm::ConstantFP::get(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPrefTypeAlign(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), InfoArrayIdxMULOpIdx, llvm::TargetRegisterInfo::lookThruCopyLike(), MRI, P, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, and TRI.
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Definition at line 1228 of file PPCInstrInfo.cpp.
References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::PPC::getAltVSXFMAOpcode(), and MI.
MachineInstr * PPCInstrInfo::findLoopInstr | ( | MachineBasicBlock & | PreHeader, |
SmallPtrSet< MachineBasicBlock *, 8 > & | Visited | ||
) | const |
Find the hardware loop instruction used to set-up the specified loop.
On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.
Definition at line 5502 of file PPCInstrInfo.cpp.
References I, llvm::MachineBasicBlock::instrs(), and llvm::PPCSubtarget::isPPC64().
Referenced by analyzeLoopForPipelining().
void PPCInstrInfo::fixupIsDeadOrKill | ( | MachineInstr * | StartMI, |
MachineInstr * | EndMI, | ||
unsigned | RegNo | ||
) | const |
Fixup killed/dead flag for register RegNo
between instructions [StartMI
, EndMI
].
Some pre-RA or post-RA transformations may violate register killed/dead flags semantics, this function can be called to fix up. Before calling this function,
RegNo
liveness is killed after instruction EndMI
.StartMI
, EndMI
) and possible definition for RegNo
is StartMI
or EndMI
. For pre-RA cases, definition may be StartMI
through COPY, StartMI
will be adjust to true definition.StartMI
, EndMI
] are in same basic block.StartMI
and EndMI
are not in same basic block, we conservatively clear kill flag for all uses of RegNo
for pre-RA and for post-RA, we give an assertion as without reaching definition analysis post-RA, StartMI
and EndMI
are hard to keep right. Definition at line 3380 of file PPCInstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::numbers::e, E, llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), i, llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::MachineOperand::isUse(), llvm::Register::isVirtualRegister(), MI, MRI, llvm::MachineInstr::readsWritesVirtualRegister(), llvm::MachineBasicBlock::rend(), llvm::MachineOperand::setIsDead(), and llvm::MachineOperand::setIsKill().
bool PPCInstrInfo::foldFrameOffset | ( | MachineInstr & | MI | ) | const |
Definition at line 3499 of file PPCInstrInfo.cpp.
References assert(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), isADDInstrEligibleForFolding(), isImmInstrEligibleForFolding(), llvm::MachineRegisterInfo::isSSA(), isValidToBeChangedReg(), MI, and MRI.
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Definition at line 2132 of file PPCInstrInfo.cpp.
References DefMI, MRI, onlyFoldImmediate(), llvm::MachineRegisterInfo::use_nodbg_empty(), and UseMI.
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When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 774 of file PPCInstrInfo.cpp.
References llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.
MachineInstr * PPCInstrInfo::getDefMIPostRA | ( | unsigned | Reg, |
MachineInstr & | MI, | ||
bool & | SeenIntermediateUse | ||
) | const |
Definition at line 3220 of file PPCInstrInfo.cpp.
References assert(), E, getRegisterInfo(), MI, and TRI.
Referenced by foldFrameOffset(), and isValidToBeChangedReg().
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On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.
Definition at line 483 of file PPCInstrInfo.h.
bool PPCInstrInfo::getFMAPatterns | ( | MachineInstr & | Root, |
SmallVectorImpl< MachineCombinerPattern > & | P, | ||
bool | DoRegPressureReduce | ||
) | const |
Return true when there is potentially a faster code sequence for a fma chain ending in Root
.
All potential patterns are output in the P
array.
Definition at line 367 of file PPCInstrInfo.cpp.
References assert(), llvm::dbgs(), FMAOpIdxInfo, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), InfoArrayIdxAddOpIdx, InfoArrayIdxFAddInst, InfoArrayIdxFSubInst, InfoArrayIdxMULOpIdx, llvm::Register::isVirtualRegister(), LLVM_DEBUG, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), MBB, MRI, llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, TRI, and true.
Referenced by getMachineCombinerPatterns().
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Definition at line 136 of file PPCInstrInfo.cpp.
References llvm::numbers::e, llvm::InstrItineraryData::getOperandCycle(), i, llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::Latency, llvm::max(), MI, and UseOldLatencyCalc.
Referenced by getOperandLatency().
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GetInstSize - Return the number of bytes of code the specified instruction may be.
This returns the maximum number of bytes.
Definition at line 2873 of file PPCInstrInfo.cpp.
References get, llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, and MI.
unsigned PPCInstrInfo::getLoadOpcodeForSpill | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 1927 of file PPCInstrInfo.cpp.
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Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
All potential patterns are output in the <Pattern> array.
Definition at line 759 of file PPCInstrInfo.cpp.
References llvm::CodeGenOpt::Aggressive, getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), and llvm::PPCSubtarget::getTargetMachine().
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Get the base operand and byte offset of an instruction that reads/writes memory.
Definition at line 2764 of file PPCInstrInfo.cpp.
References getMemOperandWithOffsetWidth(), and TRI.
bool PPCInstrInfo::getMemOperandWithOffsetWidth | ( | const MachineInstr & | LdSt, |
const MachineOperand *& | BaseOp, | ||
int64_t & | Offset, | ||
unsigned & | Width, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Return true if get the base operand, byte offset of an instruction and the memory width.
Width is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).
Definition at line 5517 of file PPCInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), and llvm::MachineInstr::memoperands_begin().
Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), and shouldClusterMemOps().
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Return the noop instruction to use for a noop.
Definition at line 1264 of file PPCInstrInfo.cpp.
References llvm::WebAssembly::Nop.
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Definition at line 166 of file PPCInstrInfo.cpp.
References DefMI, llvm::PPC::DIR_7400, llvm::PPC::DIR_750, llvm::PPC::DIR_970, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR4, llvm::PPC::DIR_PWR5, llvm::PPC::DIR_PWR5X, llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR6X, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPCSubtarget::getCPUDirective(), getInstrLatency(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtualRegister(), llvm::Latency, MRI, and UseMI.
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Definition at line 417 of file PPCInstrInfo.h.
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Definition at line 5127 of file PPCInstrInfo.cpp.
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 289 of file PPCInstrInfo.h.
Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), finalizeInsInstrs(), fixupIsDeadOrKill(), getDefMIPostRA(), getFMAPatterns(), llvm::PPCSubtarget::getRegisterInfo(), optimizeCompareInstr(), replaceInstrOperandWithImm(), shouldClusterMemOps(), and shouldReduceRegisterPressure().
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getRegNumForOperand - some operands use different numbering schemes for the same registers.
For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).
Definition at line 763 of file PPCInstrInfo.h.
References isVFRegister(), isVRRegister(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().
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Definition at line 2913 of file PPCInstrInfo.cpp.
References llvm::makeArrayRef(), llvm::PPCII::MO_GOT_FLAG, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG, llvm::PPCII::MO_PCREL_FLAG, llvm::PPCII::MO_PCREL_OPT_FLAG, llvm::PPCII::MO_PIC_FLAG, llvm::M68kII::MO_PLT, llvm::PPCII::MO_TLSGD_FLAG, llvm::PPCII::MO_TLSGDM_FLAG, llvm::PPCII::MO_TLSLD_FLAG, and llvm::PPCII::MO_TPREL_FLAG.
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Definition at line 2898 of file PPCInstrInfo.cpp.
References llvm::makeArrayRef(), llvm::MipsII::MO_DTPREL_LO, llvm::PPCII::MO_HA, llvm::AVRII::MO_LO, llvm::AArch64II::MO_TLS, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TOC_LO, llvm::PPCII::MO_TPREL_HA, and llvm::MipsII::MO_TPREL_LO.
unsigned PPCInstrInfo::getStoreOpcodeForSpill | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 1921 of file PPCInstrInfo.cpp.
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Definition at line 424 of file PPCInstrInfo.h.
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Definition at line 1480 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::BuildMI(), Cond, DL, get, getReg(), llvm::PPCSubtarget::isPPC64(), MBB, llvm::PPC::PRED_BIT_SET, and llvm::PPC::PRED_BIT_UNSET.
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Definition at line 1244 of file PPCInstrInfo.cpp.
References llvm::BuildMI(), llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPC::DIR_PWR9, DL, get, llvm::PPCSubtarget::getCPUDirective(), MBB, and MI.
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Definition at line 1576 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), get, llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::HexagonISD::ISEL, MBB, MI, MRI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::PPC::PRED_EQ, llvm::PPC::PRED_EQ_MINUS, llvm::PPC::PRED_EQ_PLUS, llvm::PPC::PRED_GE, llvm::PPC::PRED_GE_MINUS, llvm::PPC::PRED_GE_PLUS, llvm::PPC::PRED_GT, llvm::PPC::PRED_GT_MINUS, llvm::PPC::PRED_GT_PLUS, llvm::PPC::PRED_LE, llvm::PPC::PRED_LE_MINUS, llvm::PPC::PRED_LE_PLUS, llvm::PPC::PRED_LT, llvm::PPC::PRED_LT_MINUS, llvm::PPC::PRED_LT_PLUS, llvm::PPC::PRED_NE, llvm::PPC::PRED_NE_MINUS, llvm::PPC::PRED_NE_PLUS, llvm::PPC::PRED_NU, llvm::PPC::PRED_NU_MINUS, llvm::PPC::PRED_NU_PLUS, llvm::PPC::PRED_UN, llvm::PPC::PRED_UN_MINUS, and llvm::PPC::PRED_UN_PLUS.
bool PPCInstrInfo::instrHasImmForm | ( | unsigned | Opc, |
bool | IsVFReg, | ||
ImmInstrInfo & | III, | ||
bool | PostRA | ||
) | const |
Definition at line 3897 of file PPCInstrInfo.cpp.
References llvm::ISD::ADDC, llvm::PPCSubtarget::hasP9Vector(), llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::ImmInstrInfo::IsCommutative, llvm::ImmInstrInfo::IsSummingOperands, llvm::ARM_MB::LD, LLVM_FALLTHROUGH, llvm_unreachable, llvm::ImmInstrInfo::OpNoForForwarding, llvm::ISD::OR, llvm::ImmInstrInfo::SignedImm, llvm::RISCVISD::SRAW, llvm::ImmInstrInfo::TruncateImmTo, llvm::ISD::XOR, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.
Referenced by convertToImmediateForm(), and isImmInstrEligibleForFolding().
bool PPCInstrInfo::isADDIInstrEligibleForFolding | ( | MachineInstr & | ADDIMI, |
int64_t & | Imm | ||
) | const |
Definition at line 3596 of file PPCInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RISCVMatInt::Imm, and llvm::MachineOperand::isImm().
Referenced by isValidToBeChangedReg().
bool PPCInstrInfo::isADDInstrEligibleForFolding | ( | MachineInstr & | ADDMI | ) | const |
Definition at line 3613 of file PPCInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by foldFrameOffset().
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Definition at line 252 of file PPCInstrInfo.cpp.
References llvm::ISD::FADD, llvm::X86ISD::FADDS, llvm::ISD::FMUL, llvm::X86ISD::FMULS, llvm::MachineInstr::getFlag(), and llvm::MachineInstr::getOpcode().
bool PPCInstrInfo::isBDNZ | ( | unsigned | Opcode | ) | const |
Check Opcode
is BDNZ (Decrement CTR and branch if it is still nonzero).
Definition at line 5408 of file PPCInstrInfo.cpp.
References llvm::PPCISD::BDNZ, and llvm::PPCSubtarget::isPPC64().
Referenced by analyzeLoopForPipelining().
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Definition at line 1054 of file PPCInstrInfo.cpp.
References MI.
bool PPCInstrInfo::isImmInstrEligibleForFolding | ( | MachineInstr & | MI, |
unsigned & | BaseReg, | ||
unsigned & | XFormOpcode, | ||
int64_t & | OffsetOfImmInstr, | ||
ImmInstrInfo & | III | ||
) | const |
Definition at line 3620 of file PPCInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::PPCRegisterInfo::getMappedIdxOpcForImmOpc(), llvm::MachineOperand::getReg(), llvm::ImmInstrInfo::ImmOpNo, instrHasImmForm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::ImmInstrInfo::IsSummingOperands, isVFRegister(), MI, and llvm::ImmInstrInfo::OpNoForForwarding.
Referenced by foldFrameOffset().
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Definition at line 1069 of file PPCInstrInfo.cpp.
References MI.
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Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
Definition at line 300 of file PPCInstrInfo.h.
References llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_RM, llvm::ARCISD::BL, get, and llvm_unreachable.
Referenced by llvm::PPCMCCodeEmitter::getDirectBrEncoding().
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Definition at line 2162 of file PPCInstrInfo.cpp.
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Definition at line 294 of file PPCInstrInfo.h.
References get, and llvm::PPCII::Prefixed.
Referenced by llvm::PPCMCCodeEmitter::isPrefixedInstruction().
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Definition at line 593 of file PPCInstrInfo.h.
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Definition at line 581 of file PPCInstrInfo.h.
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Definition at line 2153 of file PPCInstrInfo.cpp.
References MBBDefinesCTR().
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Definition at line 598 of file PPCInstrInfo.h.
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Definition at line 1089 of file PPCInstrInfo.cpp.
References llvm_unreachable, MI, and llvm::PPCISD::XXSPLTI32DX.
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Definition at line 391 of file PPCInstrInfo.h.
References i, and llvm::ISD::OR.
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Definition at line 2173 of file PPCInstrInfo.cpp.
References llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, llvm::PPCISD::MFFS, and MI.
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Return true if the output of the instruction is always a sign-extended, i.e.
0 to 31-th bits are same as 32-th bit.
Definition at line 696 of file PPCInstrInfo.h.
References isSignOrZeroExtended(), and MI.
Referenced by optimizeCompareInstr().
bool PPCInstrInfo::isSignOrZeroExtended | ( | const MachineInstr & | MI, |
bool | SignExt, | ||
const unsigned | PhiDepth | ||
) | const |
Definition at line 5248 of file PPCInstrInfo.cpp.
References llvm::ISD::AND, assert(), Attrs, D, llvm::Depth, E, llvm::Function::getAttributes(), llvm::IntegerType::getBitWidth(), llvm::Function::getEntryBlock(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), llvm::AttributeList::getRetAttrs(), llvm::Function::getReturnType(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineInstr::isCall(), llvm::HexagonISD::ISEL, llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::PPCFunctionInfo::isLiveInSExt(), llvm::PPCFunctionInfo::isLiveInZExt(), isSignExtendingOp(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtualRegister(), isZeroExtendingOp(), MAX_DEPTH, MBB, MI, MRI, and llvm::ISD::OR.
Referenced by isSignExtended(), and isZeroExtended().
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Definition at line 1128 of file PPCInstrInfo.cpp.
References MI.
bool PPCInstrInfo::isTOCSaveMI | ( | const MachineInstr & | MI | ) | const |
Definition at line 5230 of file PPCInstrInfo.cpp.
References llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getTOCSaveOffset(), llvm::PPCSubtarget::isPPC64(), and MI.
bool PPCInstrInfo::isValidToBeChangedReg | ( | MachineInstr * | ADDMI, |
unsigned | Index, | ||
MachineInstr *& | ADDIMI, | ||
int64_t & | OffsetAddi, | ||
int64_t | OffsetImm | ||
) | const |
Definition at line 3663 of file PPCInstrInfo.cpp.
References assert(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), isADDIInstrEligibleForFolding(), llvm::isInt< 16 >(), and llvm::MachineOperand::isKill().
Referenced by foldFrameOffset().
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Definition at line 680 of file PPCInstrInfo.h.
Referenced by convertToImmediateForm(), getRegNumForOperand(), and isImmInstrEligibleForFolding().
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Definition at line 683 of file PPCInstrInfo.h.
Referenced by getRegNumForOperand().
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Definition at line 291 of file PPCInstrInfo.h.
References get, and llvm::PPCII::XFormMemOp.
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Return true if the output of the instruction is always zero-extended, i.e.
0 to 31-th bits are all zeros
Definition at line 702 of file PPCInstrInfo.h.
References isSignOrZeroExtended(), and MI.
Referenced by optimizeCompareInstr().
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Definition at line 2034 of file PPCInstrInfo.cpp.
References loadRegFromStackSlotNoUpd(), MBB, MI, TRI, and updatedRC().
void PPCInstrInfo::loadRegFromStackSlotNoUpd | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MBBI, | ||
unsigned | DestReg, | ||
int | FrameIndex, | ||
const TargetRegisterClass * | RC, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 2009 of file PPCInstrInfo.cpp.
References DL, llvm::numbers::e, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), i, llvm::MachineBasicBlock::insert(), MBB, MI, llvm::MachineMemOperand::MOLoad, and llvm::PPCFunctionInfo::setHasSpills().
Referenced by loadRegFromStackSlot().
void PPCInstrInfo::materializeImmPostRA | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MBBI, | ||
const DebugLoc & | DL, | ||
Register | Reg, | ||
int64_t | Imm | ||
) | const |
Definition at line 3237 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, get, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::RISCVMatInt::Imm, llvm::isInt< 16 >(), llvm::isInt< 32 >(), llvm::PPCSubtarget::isPPC64(), llvm::MachineRegisterInfo::isSSA(), llvm::RegState::Kill, MBB, and MBBI.
bool PPCInstrInfo::onlyFoldImmediate | ( | MachineInstr & | UseMI, |
MachineInstr & | DefMI, | ||
Register | Reg | ||
) | const |
Definition at line 2065 of file PPCInstrInfo.cpp.
References assert(), llvm::MCOperandInfo::Constraints, DefMI, llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstrBuilder::getReg(), llvm::MCOperandInfo::isLookupPtrRegClass(), llvm::PPCSubtarget::isPPC64(), llvm::MCInstrDesc::isPseudo(), llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and UseMI.
Referenced by FoldImmediate().
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Definition at line 2384 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DisableCmpOpt, llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), get, llvm::MachineInstr::getFlag(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), i, I, llvm::ARM_PROC::IE, llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, llvm::HexagonISD::ISEL, llvm::PPCSubtarget::isPPC64(), isSignExtended(), llvm::Register::isVirtual(), isZeroExtended(), llvm::RegState::Kill, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::BitmaskEnumDetail::Mask(), MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineInstr::NoSWrap, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::MachineInstr::readsRegister(), TRI, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.
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Definition at line 2184 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), B, llvm::object::BCTR, llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_RM, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, get, getReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::PPCSubtarget::isPPC64(), llvm_unreachable, MBB, MI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and llvm::AArch64::RM.
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Definition at line 1448 of file PPCInstrInfo.cpp.
References assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.
void PPCInstrInfo::replaceInstrOperandWithImm | ( | MachineInstr & | MI, |
unsigned | OpNo, | ||
int64_t | Imm | ||
) | const |
Definition at line 3166 of file PPCInstrInfo.cpp.
References assert(), getRegisterInfo(), llvm::RISCVMatInt::Imm, llvm::MachineOperand::isImplicit(), MI, and TRI.
void PPCInstrInfo::replaceInstrWithLI | ( | MachineInstr & | MI, |
const LoadImmediateInfo & | LII | ||
) | const |
Definition at line 3197 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), get, i, llvm::LoadImmediateInfo::Imm, llvm::RegState::ImplicitDefine, llvm::LoadImmediateInfo::Is64Bit, MI, and llvm::LoadImmediateInfo::SetCR.
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Definition at line 2052 of file PPCInstrInfo.cpp.
References assert(), Cond, getReg(), and llvm::PPC::InvertPredicate().
void PPCInstrInfo::setSpecialOperandAttr | ( | MachineInstr & | MI, |
uint16_t | Flags | ||
) | const |
Definition at line 239 of file PPCInstrInfo.cpp.
References MI.
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This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 221 of file PPCInstrInfo.cpp.
References llvm::MachineInstr::clearFlag(), llvm::MachineInstr::getFlags(), and llvm::MachineInstr::setFlags().
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Returns true if the two given memory operations should be scheduled adjacent.
Definition at line 2815 of file PPCInstrInfo.cpp.
References assert(), llvm::ArrayRef< T >::front(), llvm::MachineOperand::getIndex(), getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), isClusterableLdStOpcPair(), llvm::MachineOperand::isFI(), isLdStSafeToCluster(), llvm::MachineOperand::isReg(), llvm::ArrayRef< T >::size(), and TRI.
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On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.
Return true if register pressure for MBB
is high and ABI is supported to reduce register pressure. Otherwise return false.
Definition at line 613 of file PPCInstrInfo.cpp.
References assert(), llvm::RegPressureTracker::closeRegion(), llvm::RegisterOperands::collect(), EnableFMARegPressureReduction, llvm::MachineBasicBlock::end(), FMARPFactor, llvm::TargetMachine::getCodeModel(), llvm::MachineBasicBlock::getParent(), llvm::RegPressureTracker::getPos(), llvm::RegPressureTracker::getPressure(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getRegPressureSetLimit(), llvm::PPCSubtarget::getTargetMachine(), llvm::PPCSubtarget::hasP9Vector(), llvm::RegPressureTracker::init(), llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::PPCSubtarget::isPPC64(), llvm::RegisterPressure::MaxSetPressure, MBB, llvm::CodeModel::Medium, MI, MRI, llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), and TRI.
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Definition at line 1974 of file PPCInstrInfo.cpp.
References MBB, MI, storeRegToStackSlotNoUpd(), TRI, and updatedRC().
void PPCInstrInfo::storeRegToStackSlotNoUpd | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MBBI, | ||
unsigned | SrcReg, | ||
bool | isKill, | ||
int | FrameIndex, | ||
const TargetRegisterClass * | RC, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 1954 of file PPCInstrInfo.cpp.
References llvm::numbers::e, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), i, llvm::MachineBasicBlock::insert(), MBB, MI, and llvm::MachineMemOperand::MOStore.
Referenced by storeRegToStackSlot().
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Definition at line 2288 of file PPCInstrInfo.cpp.
References assert(), getReg(), P2, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, and llvm::ArrayRef< T >::size().
const TargetRegisterClass * PPCInstrInfo::updatedRC | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 5121 of file PPCInstrInfo.cpp.
References llvm::PPCSubtarget::hasVSX().
Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().
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Definition at line 433 of file PPCInstrInfo.h.