LLVM 19.0.0git
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:
Inheritance graph
[legend]

Public Member Functions

 PPCInstrInfo (PPCSubtarget &STI)
 
bool isLoadFromConstantPool (MachineInstr *I) const
 
const ConstantgetConstantFromConstantPool (MachineInstr *I) const
 
const PPCRegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
 
bool isXFormMemOp (unsigned Opcode) const
 
bool isPrefixed (unsigned Opcode) const
 
bool isSExt32To64 (unsigned Opcode) const
 
bool isZExt32To64 (unsigned Opcode) const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
std::optional< unsignedgetOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
std::optional< unsignedgetOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
 
bool useMachineCombiner () const override
 
void genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
 
bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
 Return true when there is potentially a faster code sequence for a fma chain ending in Root.
 
CombinerObjective getCombinerObjective (unsigned Pattern) const override
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
 
bool shouldReduceRegisterPressure (const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
 On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.
 
void finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
 Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
 
bool isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
 
int getExtendResourceLenLimit () const override
 On PowerPC, we try to reassociate FMA chain which will increase instruction size.
 
void setSpecialOperandAttr (MachineInstr &MI, uint32_t Flags) const
 
bool isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
 
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI) const override
 
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
void storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
void loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
unsigned getStoreOpcodeForSpill (const TargetRegisterClass *RC) const
 
unsigned getLoadOpcodeForSpill (const TargetRegisterClass *RC) const
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
 
bool onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
 
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
 
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
 Return true if get the base operand, byte offset of an instruction and the memory width.
 
bool optimizeCmpPostRA (MachineInstr &MI) const
 
bool getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
 Get the base operand and byte offset of an instruction that reads/writes memory.
 
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
 Returns true if the two given memory operations should be scheduled adjacent.
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 Return true if two MIs access different memory addresses and false otherwise.
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be.
 
MCInst getNop () const override
 Return the noop instruction to use for a noop.
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
bool expandVSXMemPseudo (MachineInstr &MI) const
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
const TargetRegisterClassupdatedRC (const TargetRegisterClass *RC) const
 
bool isTOCSaveMI (const MachineInstr &MI) const
 
std::pair< bool, boolisSignOrZeroExtended (const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
 
bool isSignExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
 
bool isZeroExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
 
bool convertToImmediateForm (MachineInstr &MI, SmallSet< Register, 4 > &RegsToUpdate, MachineInstr **KilledDef=nullptr) const
 
bool foldFrameOffset (MachineInstr &MI) const
 
bool combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const
 
bool isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const
 
bool isADDInstrEligibleForFolding (MachineInstr &ADDMI) const
 
bool isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
 
bool isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
 
void replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
 
void replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
 
bool instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
 
MachineInstrgetDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
 
void materializeImmPostRA (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
 
bool isBDNZ (unsigned Opcode) const
 Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
 
MachineInstrfindLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
 Find the hardware loop instruction used to set-up the specified loop.
 
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfoanalyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
 
virtual void setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
 This is an architecture-specific helper function of reassociateOps.
 

Static Public Member Functions

static bool isSameClassPhysRegCopy (unsigned Opcode)
 
static bool hasPCRelFlag (unsigned TF)
 
static bool hasGOTFlag (unsigned TF)
 
static bool hasTLSFlag (unsigned TF)
 
static int getRecordFormOpcode (unsigned Opcode)
 

Protected Member Functions

MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction.
 

Detailed Description

Definition at line 174 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

◆ PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( PPCSubtarget STI)
explicit

Definition at line 92 of file PPCInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

◆ analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr MI,
Register SrcReg,
Register SrcReg2,
int64_t &  Mask,
int64_t &  Value 
) const
override

Definition at line 2347 of file PPCInstrInfo.cpp.

References MI.

Referenced by optimizeCmpPostRA().

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > PPCInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock LoopBB) const
override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 5491 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().

◆ areMemAccessesTriviallyDisjoint()

bool PPCInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
override

◆ canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
Register  DstReg,
Register  TrueReg,
Register  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

◆ ClobbersPredicate()

bool PPCInstrInfo::ClobbersPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
override

Definition at line 2312 of file PPCInstrInfo.cpp.

References llvm::TargetRegisterClass::contains(), and MI.

◆ combineRLWINM()

bool PPCInstrInfo::combineRLWINM ( MachineInstr MI,
MachineInstr **  ToErase = nullptr 
) const

◆ commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 1131 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.

◆ convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm ( MachineInstr MI,
SmallSet< Register, 4 > &  RegsToUpdate,
MachineInstr **  KilledDef = nullptr 
) const

◆ copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 101 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 118 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 2967 of file PPCInstrInfo.cpp.

◆ expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo ( MachineInstr MI) const

Definition at line 3012 of file PPCInstrInfo.cpp.

References llvm::get(), llvm_unreachable, and MI.

Referenced by expandPostRAPseudo().

◆ finalizeInsInstrs()

void PPCInstrInfo::finalizeInsInstrs ( MachineInstr Root,
unsigned Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs 
) const
override

◆ findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override

◆ findLoopInstr()

MachineInstr * PPCInstrInfo::findLoopInstr ( MachineBasicBlock PreHeader,
SmallPtrSet< MachineBasicBlock *, 8 > &  Visited 
) const

Find the hardware loop instruction used to set-up the specified loop.

On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.

Definition at line 5511 of file PPCInstrInfo.cpp.

References I, llvm::MachineBasicBlock::instrs(), and llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

◆ foldFrameOffset()

bool PPCInstrInfo::foldFrameOffset ( MachineInstr MI) const

◆ foldImmediate()

bool PPCInstrInfo::foldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg,
MachineRegisterInfo MRI 
) const
override

Definition at line 2118 of file PPCInstrInfo.cpp.

References DefMI, MRI, onlyFoldImmediate(), and UseMI.

◆ genAlternativeCodeSequence()

void PPCInstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
unsigned  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 768 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

◆ getCombinerObjective()

CombinerObjective PPCInstrInfo::getCombinerObjective ( unsigned  Pattern) const
override

◆ getConstantFromConstantPool()

const Constant * PPCInstrInfo::getConstantFromConstantPool ( MachineInstr I) const

◆ getDefMIPostRA()

MachineInstr * PPCInstrInfo::getDefMIPostRA ( unsigned  Reg,
MachineInstr MI,
bool SeenIntermediateUse 
) const

Definition at line 3337 of file PPCInstrInfo.cpp.

References assert(), getRegisterInfo(), MI, and TRI.

Referenced by foldFrameOffset(), isValidToBeChangedReg(), and optimizeCmpPostRA().

◆ getExtendResourceLenLimit()

int llvm::PPCInstrInfo::getExtendResourceLenLimit ( ) const
inlineoverride

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.

Definition at line 411 of file PPCInstrInfo.h.

◆ getFMAPatterns()

bool PPCInstrInfo::getFMAPatterns ( MachineInstr Root,
SmallVectorImpl< unsigned > &  Patterns,
bool  DoRegPressureReduce 
) const

◆ getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned PredCost = nullptr 
) const
override

◆ getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 2948 of file PPCInstrInfo.cpp.

References llvm::get(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), and MI.

◆ getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill ( const TargetRegisterClass RC) const

Definition at line 1921 of file PPCInstrInfo.cpp.

◆ getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< unsigned > &  Patterns,
bool  DoRegPressureReduce 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 753 of file PPCInstrInfo.cpp.

References llvm::Aggressive, getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), and llvm::PPCSubtarget::getTargetMachine().

◆ getMemOperandsWithOffsetWidth()

bool PPCInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr LdSt,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool OffsetIsScalable,
LocationSize Width,
const TargetRegisterInfo TRI 
) const
override

Get the base operand and byte offset of an instruction that reads/writes memory.

Definition at line 2837 of file PPCInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

◆ getMemOperandWithOffsetWidth()

bool PPCInstrInfo::getMemOperandWithOffsetWidth ( const MachineInstr LdSt,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
LocationSize Width,
const TargetRegisterInfo TRI 
) const

◆ getNop()

MCInst PPCInstrInfo::getNop ( ) const
override

Return the noop instruction to use for a noop.

Definition at line 1251 of file PPCInstrInfo.cpp.

References llvm::MCInst::setOpcode().

◆ getOperandLatency() [1/2]

std::optional< unsigned > PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

◆ getOperandLatency() [2/2]

std::optional< unsigned > llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
inlineoverride

Definition at line 342 of file PPCInstrInfo.h.

◆ getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned  Opcode)
static

Definition at line 5114 of file PPCInstrInfo.cpp.

◆ getRegisterInfo()

const PPCRegisterInfo & llvm::PPCInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 274 of file PPCInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), finalizeInsInstrs(), foldFrameOffset(), getDefMIPostRA(), getFMAPatterns(), llvm::PPCSubtarget::getRegisterInfo(), optimizeCompareInstr(), replaceInstrOperandWithImm(), shouldClusterMemOps(), and shouldReduceRegisterPressure().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 2973 of file PPCInstrInfo.cpp.

◆ getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill ( const TargetRegisterClass RC) const

Definition at line 1915 of file PPCInstrInfo.cpp.

◆ hasGOTFlag()

static bool llvm::PPCInstrInfo::hasGOTFlag ( unsigned  TF)
inlinestatic

◆ hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel SchedModel,
const MachineInstr DefMI,
unsigned  DefIdx 
) const
inlineoverride

Definition at line 350 of file PPCInstrInfo.h.

◆ hasPCRelFlag()

static bool llvm::PPCInstrInfo::hasPCRelFlag ( unsigned  TF)
inlinestatic

◆ hasTLSFlag()

static bool llvm::PPCInstrInfo::hasTLSFlag ( unsigned  TF)
inlinestatic

◆ insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

◆ insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

◆ insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
Register  DstReg,
ArrayRef< MachineOperand Cond,
Register  TrueReg,
Register  FalseReg 
) const
override

◆ instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm ( unsigned  Opc,
bool  IsVFReg,
ImmInstrInfo III,
bool  PostRA 
) const

◆ isADDIInstrEligibleForFolding()

bool PPCInstrInfo::isADDIInstrEligibleForFolding ( MachineInstr ADDIMI,
int64_t &  Imm 
) const

◆ isADDInstrEligibleForFolding()

bool PPCInstrInfo::isADDInstrEligibleForFolding ( MachineInstr ADDMI) const

Definition at line 3639 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by foldFrameOffset().

◆ isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst,
bool  Invert 
) const
override

◆ isBDNZ()

bool PPCInstrInfo::isBDNZ ( unsigned  Opcode) const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

Definition at line 5417 of file PPCInstrInfo.cpp.

References llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

◆ isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
Register SrcReg,
Register DstReg,
unsigned SubIdx 
) const
override

Definition at line 1048 of file PPCInstrInfo.cpp.

References MI.

◆ isImmInstrEligibleForFolding()

bool PPCInstrInfo::isImmInstrEligibleForFolding ( MachineInstr MI,
unsigned BaseReg,
unsigned XFormOpcode,
int64_t &  OffsetOfImmInstr,
ImmInstrInfo III 
) const

◆ isLoadFromConstantPool()

bool PPCInstrInfo::isLoadFromConstantPool ( MachineInstr I) const

Definition at line 656 of file PPCInstrInfo.cpp.

References llvm::PseudoSourceValue::ConstantPool, and I.

Referenced by getFMAPatterns().

◆ isLoadFromStackSlot()

Register PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 1063 of file PPCInstrInfo.cpp.

References llvm::is_contained(), and MI.

◆ isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr MI) const
override

Definition at line 2149 of file PPCInstrInfo.cpp.

◆ isPrefixed()

bool llvm::PPCInstrInfo::isPrefixed ( unsigned  Opcode) const
inline

Definition at line 279 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::Prefixed.

◆ isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 518 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 506 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

Definition at line 2140 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

◆ isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
inlineoverride

Definition at line 523 of file PPCInstrInfo.h.

◆ isReallyTriviallyReMaterializable()

bool PPCInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI) const
override

◆ isSameClassPhysRegCopy()

static bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned  Opcode)
inlinestatic

Definition at line 289 of file PPCInstrInfo.h.

◆ isSchedulingBoundary()

bool PPCInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

Definition at line 2160 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, and MI.

◆ isSExt32To64()

bool llvm::PPCInstrInfo::isSExt32To64 ( unsigned  Opcode) const
inline

Definition at line 282 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::SExt32To64.

◆ isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const unsigned  Reg,
const MachineRegisterInfo MRI 
) const
inline

Definition at line 617 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), MRI, and Reg.

Referenced by optimizeCompareInstr().

◆ isSignOrZeroExtended()

std::pair< bool, bool > PPCInstrInfo::isSignOrZeroExtended ( const unsigned  Reg,
const unsigned  BinOpDepth,
const MachineRegisterInfo MRI 
) const

◆ isStoreToStackSlot()

Register PPCInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 1119 of file PPCInstrInfo.cpp.

References llvm::is_contained(), and MI.

◆ isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI ( const MachineInstr MI) const

◆ isValidToBeChangedReg()

bool PPCInstrInfo::isValidToBeChangedReg ( MachineInstr ADDMI,
unsigned  Index,
MachineInstr *&  ADDIMI,
int64_t &  OffsetAddi,
int64_t  OffsetImm 
) const

◆ isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned  Opcode) const
inline

Definition at line 276 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::XFormMemOp.

◆ isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const unsigned  Reg,
const MachineRegisterInfo MRI 
) const
inline

Definition at line 623 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), MRI, and Reg.

Referenced by optimizeCompareInstr().

◆ isZExt32To64()

bool llvm::PPCInstrInfo::isZExt32To64 ( unsigned  Opcode) const
inline

Definition at line 285 of file PPCInstrInfo.h.

References llvm::get(), and llvm::PPCII::ZExt32To64.

◆ loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
Register  VReg 
) const
override

Definition at line 2015 of file PPCInstrInfo.cpp.

References loadRegFromStackSlotNoUpd(), MBB, MI, TRI, and updatedRC().

◆ loadRegFromStackSlotNoUpd()

void PPCInstrInfo::loadRegFromStackSlotNoUpd ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const

◆ materializeImmPostRA()

void PPCInstrInfo::materializeImmPostRA ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
const DebugLoc DL,
Register  Reg,
int64_t  Imm 
) const

◆ onlyFoldImmediate()

bool PPCInstrInfo::onlyFoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg 
) const

◆ optimizeCmpPostRA()

bool PPCInstrInfo::optimizeCmpPostRA ( MachineInstr MI) const

◆ optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
Register  SrcReg,
Register  SrcReg2,
int64_t  Mask,
int64_t  Value,
const MachineRegisterInfo MRI 
) const
override

◆ PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm ( MachineInstr MI,
unsigned  OpNo,
int64_t  Imm 
) const

Definition at line 3283 of file PPCInstrInfo.cpp.

References assert(), getRegisterInfo(), llvm::MachineOperand::isImplicit(), MI, and TRI.

◆ replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI ( MachineInstr MI,
const LoadImmediateInfo LII 
) const

◆ reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 2033 of file PPCInstrInfo.cpp.

References assert(), Cond, getReg(), and llvm::PPC::InvertPredicate().

◆ setSpecialOperandAttr() [1/2]

void PPCInstrInfo::setSpecialOperandAttr ( MachineInstr MI,
uint32_t  Flags 
) const

◆ setSpecialOperandAttr() [2/2]

virtual void llvm::TargetInstrInfo::setSpecialOperandAttr ( MachineInstr OldMI1,
MachineInstr OldMI2,
MachineInstr NewMI1,
MachineInstr NewMI2 
) const
inline

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 1304 of file TargetInstrInfo.h.

◆ shouldClusterMemOps()

bool PPCInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
int64_t  Offset1,
bool  OffsetIsScalable1,
ArrayRef< const MachineOperand * >  BaseOps2,
int64_t  Offset2,
bool  OffsetIsScalable2,
unsigned  ClusterSize,
unsigned  NumBytes 
) const
override

◆ shouldReduceRegisterPressure()

bool PPCInstrInfo::shouldReduceRegisterPressure ( const MachineBasicBlock MBB,
const RegisterClassInfo RegClassInfo 
) const
override

◆ storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
Register  VReg 
) const
override

Definition at line 1968 of file PPCInstrInfo.cpp.

References MBB, MI, storeRegToStackSlotNoUpd(), TRI, and updatedRC().

◆ storeRegToStackSlotNoUpd()

void PPCInstrInfo::storeRegToStackSlotNoUpd ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const

◆ SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

◆ updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC ( const TargetRegisterClass RC) const

Definition at line 5108 of file PPCInstrInfo.cpp.

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

◆ useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 359 of file PPCInstrInfo.h.


The documentation for this class was generated from the following files: