llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:

Collaboration diagram for llvm::PPCInstrInfo:

Public Member Functions
	PPCInstrInfo (PPCSubtarget &STI)
const PPCRegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
bool	isXFormMemOp (unsigned Opcode) const
bool	isPrefixed (unsigned Opcode) const
bool	isSExt32To64 (unsigned Opcode) const
bool	isZExt32To64 (unsigned Opcode) const
bool	isNoTOCCallInstr (unsigned Opcode) const
	Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation. More...
ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
	CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG. More...
ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
	CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG. More...
unsigned	getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
int	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
int	getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
bool	hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
bool	useMachineCombiner () const override
void	genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
	When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
bool	getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
	Return true when there is potentially a faster code sequence for a fma chain ending in Root. More...
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
	Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
bool	shouldReduceRegisterPressure (const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const override
	On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB. More...
void	finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
	Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner. More...
bool	isAssociativeAndCommutative (const MachineInstr &Inst) const override
int	getExtendResourceLenLimit () const override
	On PowerPC, we try to reassociate FMA chain which will increase instruction size. More...
void	setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
	This is an architecture-specific helper function of reassociateOps. More...
void	setSpecialOperandAttr (MachineInstr &MI, uint16_t Flags) const
bool	isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	isReallyTriviallyReMaterializable (const MachineInstr &MI) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
unsigned	getStoreOpcodeForSpill (const TargetRegisterClass *RC) const
unsigned	getLoadOpcodeForSpill (const TargetRegisterClass *RC) const
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool	onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool	isPredicated (const MachineInstr &MI) const override
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
	Return true if get the base operand, byte offset of an instruction and the memory width. More...
bool	optimizeCmpPostRA (MachineInstr &MI) const
bool	getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
	Get the base operand and byte offset of an instruction that reads/writes memory. More...
bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
	Returns true if the two given memory operations should be scheduled adjacent. More...
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
	Return true if two MIs access different memory addresses and false otherwise. More...
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Return the number of bytes of code the specified instruction may be. More...
MCInst	getNop () const override
	Return the noop instruction to use for a noop. More...
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
bool	expandVSXMemPseudo (MachineInstr &MI) const
bool	expandPostRAPseudo (MachineInstr &MI) const override
const TargetRegisterClass *	updatedRC (const TargetRegisterClass *RC) const
bool	isTOCSaveMI (const MachineInstr &MI) const
std::pair< bool, bool >	isSignOrZeroExtended (const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
bool	isSignExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
bool	isZeroExtended (const unsigned Reg, const MachineRegisterInfo *MRI) const
bool	convertToImmediateForm (MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
bool	foldFrameOffset (MachineInstr &MI) const
bool	combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const
bool	isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const
bool	isADDInstrEligibleForFolding (MachineInstr &ADDMI) const
bool	isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
bool	isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
void	fixupIsDeadOrKill (MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
	Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI]. More...
void	replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
void	replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
bool	instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
MachineInstr *	getDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
void	materializeImmPostRA (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
bool	isBDNZ (unsigned Opcode) const
	Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). More...
MachineInstr *	findLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
	Find the hardware loop instruction used to set-up the specified loop. More...
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...

Static Public Member Functions
static bool	isSameClassPhysRegCopy (unsigned Opcode)
static bool	isVFRegister (unsigned Reg)
static bool	isVRRegister (unsigned Reg)
static int	getRecordFormOpcode (unsigned Opcode)
static unsigned	getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
	getRegNumForOperand - some operands use different numbering schemes for the same registers. More...

Protected Member Functions
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
	Commutes the operands in the given instruction. More...

Detailed Description

Definition at line 212 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( PPCSubtarget &  STI )

explicit

Definition at line 92 of file PPCInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify  ) const

override

Definition at line 1266 of file PPCInstrInfo.cpp.

References B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DisableCTRLoopAnal, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), llvm::PPCSubtarget::isPPC64(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr &  MI, Register &  SrcReg, Register &  SrcReg2, int64_t &  Mask, int64_t &  Value  ) const

override

Definition at line 2351 of file PPCInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and MI.

Referenced by optimizeCmpPostRA().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > PPCInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock *  LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 5590 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().

areMemAccessesTriviallyDisjoint()

bool PPCInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa, const MachineInstr &  MIb  ) const

override

Return true if two MIs access different memory addresses and false otherwise.

Definition at line 5648 of file PPCInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::max(), llvm::MachineInstr::mayLoadOrStore(), llvm::min(), and TRI.

canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB, ArrayRef< MachineOperand >  Cond, Register  DstReg, Register  TrueReg, Register  FalseReg, int &  CondCycles, int &  TrueCycles, int &  FalseCycles  ) const

override

Definition at line 1526 of file PPCInstrInfo.cpp.

References Cond, llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::Register::isPhysicalRegister(), MBB, and MRI.

ClobbersPredicate()

bool PPCInstrInfo::ClobbersPredicate ( MachineInstr &  MI, std::vector< MachineOperand > &  Pred, bool  SkipDead  ) const

override

Definition at line 2316 of file PPCInstrInfo.cpp.

References c, llvm::TargetRegisterClass::contains(), MI, and size.

combineRLWINM()

bool PPCInstrInfo::combineRLWINM	(	MachineInstr &	MI,
		MachineInstr **	ToErase = nullptr
	)		const

Definition at line 3843 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::Pass::dump(), llvm::MachineInstr::dump(), get, llvm::APInt::getBitsSetWithWrap(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::APInt::getZExtValue(), llvm::MachineInstr::hasImplicitDef(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::isRunOfOnes(), llvm::Register::isVirtualRegister(), llvm::APInt::isZero(), LLVM_DEBUG, MI, MRI, llvm::APInt::rotl(), llvm::MachineOperand::setIsKill(), llvm::JumpTable::Simplified, and llvm::MachineRegisterInfo::use_nodbg_empty().

commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr &  MI, bool  NewMI, unsigned  OpIdx1, unsigned  OpIdx2  ) const

overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 1137 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.

convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm	(	MachineInstr &	MI,
		MachineInstr **	KilledDef = nullptr
	)		const

Definition at line 3791 of file PPCInstrInfo.cpp.

References assert(), DefMI, llvm::PPCRegisterInfo::getMappedIdxOpcForImmOpc(), llvm::MachineFunction::getRegInfo(), instrHasImmForm(), llvm::MachineRegisterInfo::isSSA(), isVFRegister(), MI, and MRI.

copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  I, const DebugLoc &  DL, MCRegister  DestReg, MCRegister  SrcReg, bool  KillSrc  ) const

override

Definition at line 1681 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, llvm::PPCRegisterInfo::emitAccCopyInfo(), get, getCRBitValue(), llvm::getCRFromCRBit(), llvm::MCRegisterInfo::getEncodingValue(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MCInstrDesc::getNumOperands(), getRegisterInfo(), llvm::PPCSubtarget::hasDirectMove(), llvm::PPCSubtarget::hasP9Vector(), I, llvm::RegState::Kill, llvm_unreachable, MBB, llvm::PPCISD::MFOCRF, llvm::ISD::OR, llvm::PPCSubtarget::pairedVectorMemops(), TRI, VSXSelfCopyCrash, and llvm::PPCISD::XXMFACC.

CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo *  STI, const ScheduleDAG *  DAG  ) const

override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 101 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.

CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData *  II, const ScheduleDAG *  DAG  ) const

override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 118 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 2973 of file PPCInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::PPCII::MO_ACCESS_MASK.

expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr &  MI ) const

override

Definition at line 3084 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, expandVSXMemPseudo(), get, llvm::PPCSubtarget::hasP8Vector(), llvm::PPCSubtarget::hasP9Vector(), llvm::PPCSubtarget::hasVSX(), isAnImmediateOperand(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isTargetLinux(), llvm::ARM_MB::LD, MBB, MI, llvm::PPC::PRED_NE_MINUS, and R2.

expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo

(

MachineInstr &

MI

)

const

Definition at line 3018 of file PPCInstrInfo.cpp.

References get, llvm::PPCISD::LFIWAX, llvm::PPCISD::LFIWZX, llvm_unreachable, MI, and llvm::PPCISD::STFIWX.

Referenced by expandPostRAPseudo().

finalizeInsInstrs()

void PPCInstrInfo::finalizeInsInstrs ( MachineInstr &  Root, MachineCombinerPattern &  P, SmallVectorImpl< MachineInstr * > &  InsInstrs  ) const

override

Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.

Definition at line 545 of file PPCInstrInfo.cpp.

References assert(), llvm::APFloat::changeSign(), FMAOpIdxInfo, llvm::ConstantFP::get(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::DataLayout::getPrefTypeAlign(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), InfoArrayIdxMULOpIdx, llvm::TargetRegisterInfo::lookThruCopyLike(), MRI, P, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, and TRI.

findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( const MachineInstr &  MI, unsigned &  SrcOpIdx1, unsigned &  SrcOpIdx2  ) const

override

Definition at line 1221 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::PPC::getAltVSXFMAOpcode(), and MI.

findLoopInstr()

MachineInstr * PPCInstrInfo::findLoopInstr	(	MachineBasicBlock &	PreHeader,
		SmallPtrSet< MachineBasicBlock *, 8 > &	Visited
	)		const

Find the hardware loop instruction used to set-up the specified loop.

On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.

Definition at line 5610 of file PPCInstrInfo.cpp.

References I, llvm::MachineBasicBlock::instrs(), and llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

fixupIsDeadOrKill()

void PPCInstrInfo::fixupIsDeadOrKill	(	MachineInstr *	StartMI,
		MachineInstr *	EndMI,
		unsigned	RegNo
	)		const

Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].

Some pre-RA or post-RA transformations may violate register killed/dead flags semantics, this function can be called to fix up. Before calling this function,

1. Ensure that RegNo liveness is killed after instruction EndMI.
2. Ensure that there is no new definition between (StartMI, EndMI) and possible definition for RegNo is StartMI or EndMI. For pre-RA cases, definition may be StartMI through COPY, StartMI will be adjust to true definition.
3. We can do accurate fixup for the case when all instructions between [StartMI, EndMI] are in same basic block.
4. For the case when StartMI and EndMI are not in same basic block, we conservatively clear kill flag for all uses of RegNo for pre-RA and for post-RA, we give an assertion as without reaching definition analysis post-RA, StartMI and EndMI are hard to keep right.

Definition at line 3463 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::numbers::e, E, llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), i, Index, llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::MachineOperand::isUse(), llvm::Register::isVirtualRegister(), MI, MRI, llvm::MachineInstr::readsWritesVirtualRegister(), llvm::MachineBasicBlock::rend(), llvm::MachineOperand::setIsDead(), and llvm::MachineOperand::setIsKill().

Referenced by optimizeCmpPostRA().

foldFrameOffset()

bool PPCInstrInfo::foldFrameOffset

(

MachineInstr &

MI

)

const

Definition at line 3582 of file PPCInstrInfo.cpp.

References assert(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), isADDInstrEligibleForFolding(), isImmInstrEligibleForFolding(), llvm::MachineRegisterInfo::isSSA(), isValidToBeChangedReg(), MI, and MRI.

FoldImmediate()

bool PPCInstrInfo::FoldImmediate ( MachineInstr &  UseMI, MachineInstr &  DefMI, Register  Reg, MachineRegisterInfo *  MRI  ) const

override

Definition at line 2129 of file PPCInstrInfo.cpp.

References DefMI, MRI, onlyFoldImmediate(), llvm::MachineRegisterInfo::use_nodbg_empty(), and UseMI.

genAlternativeCodeSequence()

void PPCInstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root, MachineCombinerPattern  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  ) const

override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 774 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

getDefMIPostRA()

MachineInstr * PPCInstrInfo::getDefMIPostRA	(	unsigned	Reg,
		MachineInstr &	MI,
		bool &	SeenIntermediateUse
	)		const

Definition at line 3301 of file PPCInstrInfo.cpp.

References assert(), E, getRegisterInfo(), MI, and TRI.

Referenced by foldFrameOffset(), isValidToBeChangedReg(), and optimizeCmpPostRA().

getExtendResourceLenLimit()

int llvm::PPCInstrInfo::getExtendResourceLenLimit ( ) const

inlineoverride

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.

Definition at line 511 of file PPCInstrInfo.h.

getFMAPatterns()

bool PPCInstrInfo::getFMAPatterns	(	MachineInstr &	Root,
		SmallVectorImpl< MachineCombinerPattern > &	P,
		bool	DoRegPressureReduce
	)		const

Return true when there is potentially a faster code sequence for a fma chain ending in Root.

All potential patterns are output in the P array.

Definition at line 369 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), FMAOpIdxInfo, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), InfoArrayIdxAddOpIdx, InfoArrayIdxFAddInst, InfoArrayIdxFSubInst, InfoArrayIdxMULOpIdx, llvm::Register::isVirtualRegister(), LLVM_DEBUG, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), MBB, MRI, llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, llvm::REASSOC_XY_BCA, TRI, and true.

Referenced by getMachineCombinerPatterns().

getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData *  ItinData, const MachineInstr &  MI, unsigned *  PredCost = nullptr  ) const

override

Definition at line 138 of file PPCInstrInfo.cpp.

References llvm::numbers::e, llvm::InstrItineraryData::getOperandCycle(), i, llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::Latency, llvm::max(), MI, and UseOldLatencyCalc.

Referenced by getOperandLatency().

getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 2954 of file PPCInstrInfo.cpp.

References get, llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, MI, llvm::ISD::PATCHPOINT, and llvm::ISD::STACKMAP.

getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill

(

const TargetRegisterClass *

RC

)

const

Definition at line 1924 of file PPCInstrInfo.cpp.

getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  P, bool  DoRegPressureReduce  ) const

override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 759 of file PPCInstrInfo.cpp.

References llvm::CodeGenOpt::Aggressive, getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), and llvm::PPCSubtarget::getTargetMachine().

getMemOperandsWithOffsetWidth()

bool PPCInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr &  LdSt, SmallVectorImpl< const MachineOperand * > &  BaseOps, int64_t &  Offset, bool &  OffsetIsScalable, unsigned &  Width, const TargetRegisterInfo *  TRI  ) const

override

Get the base operand and byte offset of an instruction that reads/writes memory.

Definition at line 2845 of file PPCInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), and TRI.

getMemOperandWithOffsetWidth()

bool PPCInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Return true if get the base operand, byte offset of an instruction and the memory width.

Width is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).

Definition at line 5625 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), and llvm::MachineInstr::memoperands_begin().

Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), and shouldClusterMemOps().

getNop()

MCInst PPCInstrInfo::getNop ( ) const

override

Return the noop instruction to use for a noop.

Definition at line 1257 of file PPCInstrInfo.cpp.

References llvm::WebAssembly::Nop.

getOperandLatency() [1/2]

int PPCInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData, const MachineInstr &  DefMI, unsigned  DefIdx, const MachineInstr &  UseMI, unsigned  UseIdx  ) const

override

Definition at line 168 of file PPCInstrInfo.cpp.

References DefMI, llvm::PPC::DIR_7400, llvm::PPC::DIR_750, llvm::PPC::DIR_970, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR4, llvm::PPC::DIR_PWR5, llvm::PPC::DIR_PWR5X, llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR6X, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPCSubtarget::getCPUDirective(), getInstrLatency(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtualRegister(), llvm::Latency, MRI, and UseMI.

getOperandLatency() [2/2]

int llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData, SDNode *  DefNode, unsigned  DefIdx, SDNode *  UseNode, unsigned  UseIdx  ) const

inlineoverride

Definition at line 445 of file PPCInstrInfo.h.

getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned  Opcode )

static

Definition at line 5213 of file PPCInstrInfo.cpp.

getRegisterInfo()

const PPCRegisterInfo& llvm::PPCInstrInfo::getRegisterInfo ( ) const

inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 311 of file PPCInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), finalizeInsInstrs(), fixupIsDeadOrKill(), getDefMIPostRA(), getFMAPatterns(), llvm::PPCSubtarget::getRegisterInfo(), optimizeCompareInstr(), replaceInstrOperandWithImm(), shouldClusterMemOps(), and shouldReduceRegisterPressure().

getRegNumForOperand()

static unsigned llvm::PPCInstrInfo::getRegNumForOperand ( const MCInstrDesc &  Desc, unsigned  Reg, unsigned  OpNo  )

inlinestatic

getRegNumForOperand - some operands use different numbering schemes for the same registers.

For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).

Definition at line 793 of file PPCInstrInfo.h.

References isVFRegister(), isVRRegister(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().

getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Definition at line 2994 of file PPCInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::PPCII::MO_GOT_FLAG, llvm::PPCII::MO_GOT_TLSGD_PCREL_FLAG, llvm::PPCII::MO_GOT_TLSLD_PCREL_FLAG, llvm::PPCII::MO_GOT_TPREL_PCREL_FLAG, llvm::PPCII::MO_PCREL_FLAG, llvm::PPCII::MO_PCREL_OPT_FLAG, llvm::PPCII::MO_PIC_FLAG, llvm::M68kII::MO_PLT, llvm::PPCII::MO_TLSGD_FLAG, llvm::PPCII::MO_TLSGDM_FLAG, llvm::PPCII::MO_TLSLD_FLAG, and llvm::PPCII::MO_TPREL_FLAG.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 2979 of file PPCInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::MipsII::MO_DTPREL_LO, llvm::PPCII::MO_HA, llvm::AVRII::MO_LO, llvm::AArch64II::MO_TLS, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TOC_LO, llvm::PPCII::MO_TPREL_HA, and llvm::MipsII::MO_TPREL_LO.

getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill

(

const TargetRegisterClass *

RC

)

const

Definition at line 1918 of file PPCInstrInfo.cpp.

hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel &  SchedModel, const MachineInstr &  DefMI, unsigned  DefIdx  ) const

inlineoverride

Definition at line 452 of file PPCInstrInfo.h.

insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  DL, int *  BytesAdded = nullptr  ) const

override

Definition at line 1473 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::BuildMI(), Cond, DL, get, getReg(), llvm::PPCSubtarget::isPPC64(), MBB, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and TBB.

insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI  ) const

override

Definition at line 1237 of file PPCInstrInfo.cpp.

References llvm::BuildMI(), llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPC::DIR_PWR9, DL, get, llvm::PPCSubtarget::getCPUDirective(), MBB, and MI.

insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, const DebugLoc &  DL, Register  DstReg, ArrayRef< MachineOperand >  Cond, Register  TrueReg, Register  FalseReg  ) const

override

Definition at line 1569 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), get, llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::HexagonISD::ISEL, MBB, MI, MRI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::PPC::PRED_EQ, llvm::PPC::PRED_EQ_MINUS, llvm::PPC::PRED_EQ_PLUS, llvm::PPC::PRED_GE, llvm::PPC::PRED_GE_MINUS, llvm::PPC::PRED_GE_PLUS, llvm::PPC::PRED_GT, llvm::PPC::PRED_GT_MINUS, llvm::PPC::PRED_GT_PLUS, llvm::PPC::PRED_LE, llvm::PPC::PRED_LE_MINUS, llvm::PPC::PRED_LE_PLUS, llvm::PPC::PRED_LT, llvm::PPC::PRED_LT_MINUS, llvm::PPC::PRED_LT_PLUS, llvm::PPC::PRED_NE, llvm::PPC::PRED_NE_MINUS, llvm::PPC::PRED_NE_PLUS, llvm::PPC::PRED_NU, llvm::PPC::PRED_NU_MINUS, llvm::PPC::PRED_NU_PLUS, llvm::PPC::PRED_UN, llvm::PPC::PRED_UN_MINUS, and llvm::PPC::PRED_UN_PLUS.

instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm	(	unsigned	Opc,
		bool	IsVFReg,
		ImmInstrInfo &	III,
		bool	PostRA
	)		const

Definition at line 3980 of file PPCInstrInfo.cpp.

References llvm::ISD::ADDC, llvm::PPCSubtarget::hasP9Vector(), llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::ImmInstrInfo::IsCommutative, llvm::ImmInstrInfo::IsSummingOperands, llvm::ARM_MB::LD, llvm_unreachable, llvm::ImmInstrInfo::OpNoForForwarding, llvm::ISD::OR, llvm::ImmInstrInfo::SignedImm, llvm::RISCVISD::SRAW, llvm::ImmInstrInfo::TruncateImmTo, llvm::ISD::XOR, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

Referenced by convertToImmediateForm(), and isImmInstrEligibleForFolding().

isADDIInstrEligibleForFolding()

bool PPCInstrInfo::isADDIInstrEligibleForFolding	(	MachineInstr &	ADDIMI,
		int64_t &	Imm
	)		const

Definition at line 3679 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RISCVMatInt::Imm, and llvm::MachineOperand::isImm().

Referenced by isValidToBeChangedReg().

isADDInstrEligibleForFolding()

bool PPCInstrInfo::isADDInstrEligibleForFolding

(

MachineInstr &

ADDMI

)

const

Definition at line 3696 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by foldFrameOffset().

isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst ) const

override

Definition at line 254 of file PPCInstrInfo.cpp.

References llvm::ISD::FADD, llvm::X86ISD::FADDS, llvm::ISD::FMUL, llvm::X86ISD::FMULS, llvm::MachineInstr::getFlag(), and llvm::MachineInstr::getOpcode().

isBDNZ()

bool PPCInstrInfo::isBDNZ

(

unsigned

Opcode

)

const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

Definition at line 5516 of file PPCInstrInfo.cpp.

References llvm::PPCISD::BDNZ, and llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI, Register &  SrcReg, Register &  DstReg, unsigned &  SubIdx  ) const

override

Definition at line 1054 of file PPCInstrInfo.cpp.

References MI.

isImmInstrEligibleForFolding()

bool PPCInstrInfo::isImmInstrEligibleForFolding	(	MachineInstr &	MI,
		unsigned &	BaseReg,
		unsigned &	XFormOpcode,
		int64_t &	OffsetOfImmInstr,
		ImmInstrInfo &	III
	)		const

Definition at line 3703 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::PPCRegisterInfo::getMappedIdxOpcForImmOpc(), llvm::MachineOperand::getReg(), llvm::ImmInstrInfo::ImmOpNo, instrHasImmForm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::ImmInstrInfo::IsSummingOperands, isVFRegister(), MI, and llvm::ImmInstrInfo::OpNoForForwarding.

Referenced by foldFrameOffset().

isLoadFromStackSlot()

unsigned PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1069 of file PPCInstrInfo.cpp.

References llvm::ISD::FrameIndex, llvm::is_contained(), and MI.

isNoTOCCallInstr()

bool llvm::PPCInstrInfo::isNoTOCCallInstr ( unsigned  Opcode ) const

inline

Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.

Definition at line 328 of file PPCInstrInfo.h.

References llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_RM, llvm::ARCISD::BL, get, and llvm_unreachable.

isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr &  MI ) const

override

Definition at line 2159 of file PPCInstrInfo.cpp.

isPrefixed()

bool llvm::PPCInstrInfo::isPrefixed ( unsigned  Opcode ) const

inline

Definition at line 316 of file PPCInstrInfo.h.

References get, and llvm::PPCII::Prefixed.

isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock &  MBB, unsigned  NumCycles, BranchProbability  Probability  ) const

inlineoverride

Definition at line 620 of file PPCInstrInfo.h.

isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  MBB, unsigned  NumCycles, unsigned  ExtraPredCycles, BranchProbability  Probability  ) const

inlineoverride

Definition at line 608 of file PPCInstrInfo.h.

isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  TMBB, unsigned  NumT, unsigned  ExtraT, MachineBasicBlock &  FMBB, unsigned  NumF, unsigned  ExtraF, BranchProbability  Probability  ) const

override

Definition at line 2150 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock &  TMBB, MachineBasicBlock &  FMBB  ) const

inlineoverride

Definition at line 625 of file PPCInstrInfo.h.

isReallyTriviallyReMaterializable()

bool PPCInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr &  MI ) const

override

Definition at line 1085 of file PPCInstrInfo.cpp.

References llvm_unreachable, MI, and llvm::PPCISD::XXSPLTI32DX.

isSameClassPhysRegCopy()

static bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned  Opcode )

inlinestatic

Definition at line 419 of file PPCInstrInfo.h.

References i, and llvm::ISD::OR.

isSchedulingBoundary()

bool PPCInstrInfo::isSchedulingBoundary ( const MachineInstr &  MI, const MachineBasicBlock *  MBB, const MachineFunction &  MF  ) const

override

Definition at line 2170 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, llvm::PPCISD::MFFS, and MI.

isSExt32To64()

bool llvm::PPCInstrInfo::isSExt32To64 ( unsigned  Opcode ) const

inline

Definition at line 319 of file PPCInstrInfo.h.

References get, and llvm::PPCII::SExt32To64.

isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const unsigned  Reg, const MachineRegisterInfo *  MRI  ) const

inline

Definition at line 725 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and MRI.

Referenced by optimizeCompareInstr().

isSignOrZeroExtended()

std::pair< bool, bool > PPCInstrInfo::isSignOrZeroExtended	(	const unsigned	Reg,
		const unsigned	BinOpDepth,
		const MachineRegisterInfo *	MRI
	)		const

Definition at line 5348 of file PPCInstrInfo.cpp.

References llvm::ISD::AND, Attrs, definedBySignExtendingOp(), definedByZeroExtendingOp(), llvm::Function::getAttributes(), llvm::IntegerType::getBitWidth(), llvm::Function::getEntryBlock(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), llvm::AttributeList::getRetAttrs(), llvm::Function::getReturnType(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), I, llvm::RISCVMatInt::Imm, llvm::MachineBasicBlock::instr_begin(), llvm::MachineInstr::isCall(), llvm::HexagonISD::ISEL, llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::PPCFunctionInfo::isLiveInSExt(), llvm::PPCFunctionInfo::isLiveInZExt(), llvm::PPCSubtarget::isSVR4ABI(), llvm::Register::isVirtualRegister(), MAX_BINOP_DEPTH, MBB, MI, MRI, llvm::ISD::OR, and PHI.

Referenced by isSignExtended(), and isZeroExtended().

isStoreToStackSlot()

unsigned PPCInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1125 of file PPCInstrInfo.cpp.

References llvm::ISD::FrameIndex, llvm::is_contained(), and MI.

isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI

(

const MachineInstr &

MI

)

const

Definition at line 5326 of file PPCInstrInfo.cpp.

References llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getTOCSaveOffset(), llvm::PPCSubtarget::isPPC64(), and MI.

isValidToBeChangedReg()

bool PPCInstrInfo::isValidToBeChangedReg	(	MachineInstr *	ADDMI,
		unsigned	Index,
		MachineInstr *&	ADDIMI,
		int64_t &	OffsetAddi,
		int64_t	OffsetImm
	)		const

Definition at line 3746 of file PPCInstrInfo.cpp.

References assert(), getDefMIPostRA(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), isADDIInstrEligibleForFolding(), and llvm::MachineOperand::isKill().

Referenced by foldFrameOffset().

isVFRegister()

static bool llvm::PPCInstrInfo::isVFRegister ( unsigned  Reg )

inlinestatic

Definition at line 709 of file PPCInstrInfo.h.

Referenced by convertToImmediateForm(), getRegNumForOperand(), and isImmInstrEligibleForFolding().

isVRRegister()

static bool llvm::PPCInstrInfo::isVRRegister ( unsigned  Reg )

inlinestatic

Definition at line 712 of file PPCInstrInfo.h.

Referenced by getRegNumForOperand().

isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned  Opcode ) const

inline

Definition at line 313 of file PPCInstrInfo.h.

References get, and llvm::PPCII::XFormMemOp.

isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const unsigned  Reg, const MachineRegisterInfo *  MRI  ) const

inline

Definition at line 731 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and MRI.

Referenced by optimizeCompareInstr().

isZExt32To64()

bool llvm::PPCInstrInfo::isZExt32To64 ( unsigned  Opcode ) const

inline

Definition at line 322 of file PPCInstrInfo.h.

References get, and llvm::PPCII::ZExt32To64.

loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DestReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2031 of file PPCInstrInfo.cpp.

References loadRegFromStackSlotNoUpd(), MBB, MI, TRI, and updatedRC().

loadRegFromStackSlotNoUpd()

void PPCInstrInfo::loadRegFromStackSlotNoUpd	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 2006 of file PPCInstrInfo.cpp.

References DL, llvm::numbers::e, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), i, llvm::MachineBasicBlock::insert(), MBB, MI, llvm::MachineMemOperand::MOLoad, and llvm::PPCFunctionInfo::setHasSpills().

Referenced by loadRegFromStackSlot().

materializeImmPostRA()

void PPCInstrInfo::materializeImmPostRA	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	Reg,
		int64_t	Imm
	)		const

Definition at line 3318 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, get, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::RISCVMatInt::Imm, llvm::PPCSubtarget::isPPC64(), llvm::MachineRegisterInfo::isSSA(), llvm::RegState::Kill, MBB, and MBBI.

onlyFoldImmediate()

bool PPCInstrInfo::onlyFoldImmediate	(	MachineInstr &	UseMI,
		MachineInstr &	DefMI,
		Register	Reg
	)		const

Definition at line 2062 of file PPCInstrInfo.cpp.

References assert(), llvm::MCOperandInfo::Constraints, DefMI, llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstrBuilder::getReg(), llvm::MCOperandInfo::isLookupPtrRegClass(), llvm::PPCSubtarget::isPPC64(), llvm::MCInstrDesc::isPseudo(), llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and UseMI.

Referenced by FoldImmediate().

optimizeCmpPostRA()

bool PPCInstrInfo::optimizeCmpPostRA

(

MachineInstr &

MI

)

const

Definition at line 2766 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), analyzeCompare(), assert(), llvm::MachineInstr::clearRegisterDeads(), llvm::dbgs(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::dump(), fixupIsDeadOrKill(), get, getDefMIPostRA(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasImplicitDef(), llvm::RegState::ImplicitDefine, llvm::MachineOperand::isKill(), llvm::PPCSubtarget::isPPC64(), llvm::MachineRegisterInfo::isSSA(), LLVM_DEBUG, MRI, and llvm::MachineInstr::setDesc().

optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr, Register  SrcReg, Register  SrcReg2, int64_t  Mask, int64_t  Value, const MachineRegisterInfo *  MRI  ) const

override

Definition at line 2381 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DisableCmpOpt, llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), get, llvm::MachineInstr::getFlag(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), i, I, llvm::ARM_PROC::IE, llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, llvm::HexagonISD::ISEL, llvm::PPCSubtarget::isPPC64(), isSignExtended(), llvm::Register::isVirtual(), isZeroExtended(), llvm::RegState::Kill, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::BitmaskEnumDetail::Mask(), MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineInstr::NoSWrap, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setImm(), TRI, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.

PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr &  MI, ArrayRef< MachineOperand >  Pred  ) const

override

Definition at line 2181 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), B, llvm::object::BCTR, llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_RM, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, get, getReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::PPCSubtarget::isPPC64(), llvm_unreachable, MBB, MI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and llvm::AArch64::RM.

removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 1441 of file PPCInstrInfo.cpp.

References assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.

replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm	(	MachineInstr &	MI,
		unsigned	OpNo,
		int64_t	Imm
	)		const

Definition at line 3247 of file PPCInstrInfo.cpp.

References assert(), getRegisterInfo(), llvm::RISCVMatInt::Imm, llvm::MachineOperand::isImplicit(), MI, TRI, and UseOpIdx.

replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI	(	MachineInstr &	MI,
		const LoadImmediateInfo &	LII
	)		const

Definition at line 3278 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), get, i, llvm::LoadImmediateInfo::Imm, llvm::RegState::ImplicitDefine, llvm::LoadImmediateInfo::Is64Bit, MI, and llvm::LoadImmediateInfo::SetCR.

reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 2049 of file PPCInstrInfo.cpp.

References assert(), Cond, getReg(), and llvm::PPC::InvertPredicate().

setSpecialOperandAttr() [1/2]

void PPCInstrInfo::setSpecialOperandAttr	(	MachineInstr &	MI,
		uint16_t	Flags
	)		const

Definition at line 241 of file PPCInstrInfo.cpp.

References MI.

setSpecialOperandAttr() [2/2]

void PPCInstrInfo::setSpecialOperandAttr ( MachineInstr &  OldMI1, MachineInstr &  OldMI2, MachineInstr &  NewMI1, MachineInstr &  NewMI2  ) const

override

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 223 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::clearFlag(), llvm::MachineInstr::getFlags(), and llvm::MachineInstr::setFlags().

shouldClusterMemOps()

bool PPCInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1, ArrayRef< const MachineOperand * >  BaseOps2, unsigned  NumLoads, unsigned  NumBytes  ) const

override

Returns true if the two given memory operations should be scheduled adjacent.

Definition at line 2896 of file PPCInstrInfo.cpp.

References assert(), llvm::ArrayRef< T >::front(), llvm::MachineOperand::getIndex(), getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), isClusterableLdStOpcPair(), llvm::MachineOperand::isFI(), isLdStSafeToCluster(), llvm::MachineOperand::isReg(), llvm::ArrayRef< T >::size(), and TRI.

shouldReduceRegisterPressure()

bool PPCInstrInfo::shouldReduceRegisterPressure ( const MachineBasicBlock *  MBB, const RegisterClassInfo *  RegClassInfo  ) const

override

On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB.

Return true if register pressure for MBB is high and ABI is supported to reduce register pressure. Otherwise return false.

Definition at line 615 of file PPCInstrInfo.cpp.

References assert(), llvm::RegPressureTracker::closeRegion(), llvm::RegisterOperands::collect(), EnableFMARegPressureReduction, llvm::MachineBasicBlock::end(), FMARPFactor, llvm::TargetMachine::getCodeModel(), llvm::MachineBasicBlock::getParent(), llvm::RegPressureTracker::getPos(), llvm::RegPressureTracker::getPressure(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getRegPressureSetLimit(), llvm::PPCSubtarget::getTargetMachine(), llvm::PPCSubtarget::hasP9Vector(), llvm::RegPressureTracker::init(), llvm::PPCSubtarget::isPPC64(), llvm::RegisterPressure::MaxSetPressure, MBB, llvm::CodeModel::Medium, MI, MRI, llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), llvm::reverse(), and TRI.

storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  isKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 1971 of file PPCInstrInfo.cpp.

References MBB, MI, storeRegToStackSlotNoUpd(), TRI, and updatedRC().

storeRegToStackSlotNoUpd()

void PPCInstrInfo::storeRegToStackSlotNoUpd	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1951 of file PPCInstrInfo.cpp.

References llvm::numbers::e, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), i, llvm::MachineBasicBlock::insert(), MBB, MI, and llvm::MachineMemOperand::MOStore.

Referenced by storeRegToStackSlot().

SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand >  Pred1, ArrayRef< MachineOperand >  Pred2  ) const

override

Definition at line 2285 of file PPCInstrInfo.cpp.

References assert(), getReg(), P2, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, and llvm::ArrayRef< T >::size().

updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC

(

const TargetRegisterClass *

RC

)

const

Definition at line 5207 of file PPCInstrInfo.cpp.

References llvm::PPCSubtarget::hasVSX().

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const

inlineoverride

Definition at line 461 of file PPCInstrInfo.h.

---

The documentation for this class was generated from the following files:

• lib/Target/PowerPC/PPCInstrInfo.h
• lib/Target/PowerPC/PPCInstrInfo.cpp