LLVM 20.0.0git
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This is the complete list of members for llvm::SIInstrInfo, including all inherited members.
allowNegativeFlatOffset(uint64_t FlatVariant) const | llvm::SIInstrInfo | |
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override | llvm::SIInstrInfo | |
analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const | llvm::SIInstrInfo | |
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override | llvm::SIInstrInfo | |
areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override | llvm::SIInstrInfo | |
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override | llvm::SIInstrInfo | |
buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const | llvm::SIInstrInfo | |
buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const | llvm::SIInstrInfo | |
buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const | llvm::SIInstrInfo | |
canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override | llvm::SIInstrInfo | |
canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::SIInstrInfo | |
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override | llvm::SIInstrInfo | protected |
commuteOpcode(unsigned Opc) const | llvm::SIInstrInfo | |
commuteOpcode(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const | llvm::SIInstrInfo | |
convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const | llvm::SIInstrInfo | |
convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override | llvm::SIInstrInfo | |
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override | llvm::SIInstrInfo | |
createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override | llvm::SIInstrInfo | |
createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override | llvm::SIInstrInfo | |
CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override | llvm::SIInstrInfo | |
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override | llvm::SIInstrInfo | |
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override | llvm::SIInstrInfo | |
decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::SIInstrInfo | |
doesNotReadTiedSource(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
doesNotReadTiedSource(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | |
expandMovDPP64(MachineInstr &MI) const | llvm::SIInstrInfo | |
expandPostRAPseudo(MachineInstr &MI) const override | llvm::SIInstrInfo | |
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override | llvm::SIInstrInfo | |
findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const | llvm::SIInstrInfo | |
fixImplicitOperands(MachineInstr &MI) const | llvm::SIInstrInfo | |
foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final | llvm::SIInstrInfo | |
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override | llvm::SIInstrInfo | |
getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const | llvm::SIInstrInfo | |
getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, RegScavenger &RS) const | llvm::SIInstrInfo | |
getBranchDestBlock(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
getClampMask(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
getDefaultRsrcDataFormat() const | llvm::SIInstrInfo | |
getDSShaderTypeValue(const MachineFunction &MF) | llvm::SIInstrInfo | static |
getGenericInstructionUniformity(const MachineInstr &MI) const | llvm::SIInstrInfo | |
getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const | llvm::SIInstrInfo | |
getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const | llvm::SIInstrInfo | |
getInstBundleSize(const MachineInstr &MI) const | llvm::SIInstrInfo | |
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override | llvm::SIInstrInfo | |
getInstructionUniformity(const MachineInstr &MI) const override final | llvm::SIInstrInfo | |
getInstSizeInBytes(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
getKillTerminatorFromPseudo(unsigned Opcode) const | llvm::SIInstrInfo | |
getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const override | llvm::SIInstrInfo | |
getMachineCSELookAheadLimit() const override | llvm::SIInstrInfo | inline |
getMaxMUBUFImmOffset(const GCNSubtarget &ST) | llvm::SIInstrInfo | static |
getMCOpcodeFromPseudo(unsigned Opcode) const | llvm::SIInstrInfo | inline |
getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const final | llvm::SIInstrInfo | |
getMIRFormatter() const override | llvm::SIInstrInfo | inline |
getMovOpcode(const TargetRegisterClass *DstRC) const | llvm::SIInstrInfo | |
getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | inline |
getNamedOperand(MachineInstr &MI, unsigned OperandName) const | llvm::SIInstrInfo | |
getNamedOperand(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | inline |
getNonSoftWaitcntOpcode(unsigned Opcode) | llvm::SIInstrInfo | inlinestatic |
getNumWaitStates(const MachineInstr &MI) | llvm::SIInstrInfo | static |
getOpRegClass(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | |
getOpSize(uint16_t Opcode, unsigned OpNo) const | llvm::SIInstrInfo | inline |
getOpSize(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | inline |
getPreferredSelectRegClass(unsigned Size) const | llvm::SIInstrInfo | |
getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override | llvm::SIInstrInfo | |
getRegisterInfo() const | llvm::SIInstrInfo | inline |
getSchedModel() const | llvm::SIInstrInfo | inline |
getScratchRsrcWords23() const | llvm::SIInstrInfo | |
getSerializableDirectMachineOperandTargetFlags() const override | llvm::SIInstrInfo | |
getSerializableMachineMemOperandTargetFlags() const override | llvm::SIInstrInfo | |
getSerializableTargetIndices() const override | llvm::SIInstrInfo | |
getSubtarget() const | llvm::SIInstrInfo | inline |
getVALUOp(const MachineInstr &MI) const | llvm::SIInstrInfo | |
hasAnyModifiersSet(const MachineInstr &MI) const | llvm::SIInstrInfo | |
hasDivergentBranch(const MachineBasicBlock *MBB) const | llvm::SIInstrInfo | |
hasFPClamp(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
hasFPClamp(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
hasIntClamp(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
hasModifiers(unsigned Opcode) const | llvm::SIInstrInfo | |
hasModifiersSet(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | |
hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const | llvm::SIInstrInfo | |
hasVALU32BitEncoding(unsigned Opcode) const | llvm::SIInstrInfo | |
hasVGPRUses(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::SIInstrInfo | |
insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const | llvm::SIInstrInfo | |
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override | llvm::SIInstrInfo | |
insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const | llvm::SIInstrInfo | |
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::SIInstrInfo | |
insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override | llvm::SIInstrInfo | |
insertReturn(MachineBasicBlock &MBB) const | llvm::SIInstrInfo | |
insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, bool IsSCCLive, SlotIndexes *Indexes=nullptr) const | llvm::SIInstrInfo | |
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override | llvm::SIInstrInfo | |
insertSimulatedTrap(MachineRegisterInfo &MRI, MachineBasicBlock &MBB, MachineInstr &MI, const DebugLoc &DL) const | llvm::SIInstrInfo | |
insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const | llvm::SIInstrInfo | |
isAlwaysGDS(uint16_t Opcode) const | llvm::SIInstrInfo | |
isAsmOnlyOpcode(int MCOp) const | llvm::SIInstrInfo | |
isAtomic(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isAtomic(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isAtomicNoRet(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isAtomicNoRet(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isAtomicRet(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isAtomicRet(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isBarrier(unsigned Opcode) const | llvm::SIInstrInfo | inline |
isBarrierStart(unsigned Opcode) const | llvm::SIInstrInfo | inline |
isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const override | llvm::SIInstrInfo | |
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override | llvm::SIInstrInfo | |
isBufferSMRD(const MachineInstr &MI) const | llvm::SIInstrInfo | |
isChainCallOpcode(uint64_t Opcode) | llvm::SIInstrInfo | inlinestatic |
isCopyInstrImpl(const MachineInstr &MI) const override | llvm::SIInstrInfo | protected |
isDisableWQM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isDisableWQM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isDOT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isDOT(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isDPP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isDPP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isDS(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isDS(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isDualSourceBlendEXP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isEXP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isEXP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isF16PseudoScalarTrans(unsigned Opcode) | llvm::SIInstrInfo | inlinestatic |
isFixedSize(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isFixedSize(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isFLAT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isFLAT(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isFLATGlobal(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isFLATGlobal(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isFLATScratch(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isFLATScratch(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isFoldableCopy(const MachineInstr &MI) | llvm::SIInstrInfo | static |
isFPAtomic(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isFPAtomic(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isGather4(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isGather4(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isGWS(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isGWS(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isHighLatencyDef(int Opc) const override | llvm::SIInstrInfo | |
isIgnorableUse(const MachineOperand &MO) const override | llvm::SIInstrInfo | |
isImage(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isImage(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
isInlineConstant(const APInt &Imm) const | llvm::SIInstrInfo | |
isInlineConstant(const APFloat &Imm) const | llvm::SIInstrInfo | |
isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const | llvm::SIInstrInfo | |
isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | inline |
isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const | llvm::SIInstrInfo | inline |
isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const | llvm::SIInstrInfo | inline |
isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const | llvm::SIInstrInfo | inline |
isInlineConstant(const MachineOperand &MO) const | llvm::SIInstrInfo | inline |
isKillTerminator(unsigned Opcode) | llvm::SIInstrInfo | static |
isLDSDIR(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isLDSDIR(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isLDSDMA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isLDSDMA(uint16_t Opcode) | llvm::SIInstrInfo | inline |
isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const | llvm::SIInstrInfo | |
isLegalMUBUFImmOffset(unsigned Imm) const | llvm::SIInstrInfo | |
isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::SIInstrInfo | |
isLowLatencyInstruction(const MachineInstr &MI) const | llvm::SIInstrInfo | |
isMAI(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMAI(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isMFMA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMFMAorWMMA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMIMG(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMIMG(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isMTBUF(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMTBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isMUBUF(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isMUBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isNeverUniform(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isNonUniformBranchInstr(MachineInstr &Instr) const | llvm::SIInstrInfo | |
isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const | llvm::SIInstrInfo | |
isPacked(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isPacked(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isReallyTriviallyReMaterializable(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const override | llvm::SIInstrInfo | |
isSALU(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isScalarStore(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isScalarStore(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isScalarUnit(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::SIInstrInfo | |
isSDWA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSDWA(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSegmentSpecificFLAT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSegmentSpecificFLAT(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSGPRSpill(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSGPRSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const | llvm::SIInstrInfo | |
isSMRD(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSMRD(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSOP1(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSOP2(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSOPC(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSOPK(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSOPK(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSOPP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSOPP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isSpill(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isStackAccess(const MachineInstr &MI, int &FrameIndex) const | llvm::SIInstrInfo | |
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::SIInstrInfo | |
isSWMMAC(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isSWMMAC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isTRANS(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isTRANS(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVALU(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVGPRCopy(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
isVGPRSpill(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVGPRSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVIMAGE(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVIMAGE(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVINTERP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVINTERP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVINTRP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVINTRP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVMEM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVMEM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVOP1(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVOP2(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVOP3(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVOP3(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVOP3P(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVOP3P(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVOPC(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isVSAMPLE(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isVSAMPLE(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isWaitcnt(unsigned Opcode) const | llvm::SIInstrInfo | inline |
isWave32() const | llvm::SIInstrInfo | |
isWMMA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isWMMA(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isWQM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
isWQM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
isWWMRegSpillOpcode(uint16_t Opcode) | llvm::SIInstrInfo | inlinestatic |
legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const | llvm::SIInstrInfo | |
legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const | llvm::SIInstrInfo | |
legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const | llvm::SIInstrInfo | |
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::SIInstrInfo | |
materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const | llvm::SIInstrInfo | |
mayAccessFlatAddressSpace(const MachineInstr &MI) const | llvm::SIInstrInfo | |
mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const | llvm::SIInstrInfo | |
mayWriteLDSThroughDMA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
MO_ABS32_HI enum value | llvm::SIInstrInfo | |
MO_ABS32_LO enum value | llvm::SIInstrInfo | |
MO_FAR_BRANCH_OFFSET enum value | llvm::SIInstrInfo | |
MO_GOTPCREL enum value | llvm::SIInstrInfo | |
MO_GOTPCREL32 enum value | llvm::SIInstrInfo | |
MO_GOTPCREL32_HI enum value | llvm::SIInstrInfo | |
MO_GOTPCREL32_LO enum value | llvm::SIInstrInfo | |
MO_MASK enum value | llvm::SIInstrInfo | |
MO_NONE enum value | llvm::SIInstrInfo | |
MO_REL32 enum value | llvm::SIInstrInfo | |
MO_REL32_HI enum value | llvm::SIInstrInfo | |
MO_REL32_LO enum value | llvm::SIInstrInfo | |
modifiesModeRegister(const MachineInstr &MI) | llvm::SIInstrInfo | static |
moveFlatAddrToVGPR(MachineInstr &Inst) const | llvm::SIInstrInfo | |
moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const | llvm::SIInstrInfo | |
moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT, MachineInstr &Inst) const | llvm::SIInstrInfo | |
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override | llvm::SIInstrInfo | |
pseudoToMCOpcode(int Opcode) const | llvm::SIInstrInfo | |
readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const | llvm::SIInstrInfo | |
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override | llvm::SIInstrInfo | |
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::SIInstrInfo | |
removeModOperands(MachineInstr &MI) const | llvm::SIInstrInfo | |
restoreExec(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, SlotIndexes *Indexes=nullptr) const | llvm::SIInstrInfo | |
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::SIInstrInfo | |
shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override | llvm::SIInstrInfo | |
shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override | llvm::SIInstrInfo | |
SIInstrInfo(const GCNSubtarget &ST) | llvm::SIInstrInfo | explicit |
sopkIsZext(unsigned Opcode) | llvm::SIInstrInfo | inlinestatic |
splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const | llvm::SIInstrInfo | |
splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, Align Alignment=Align(4)) const | llvm::SIInstrInfo | |
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::SIInstrInfo | |
swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const | llvm::SIInstrInfo | protected |
TargetOperandFlags enum name | llvm::SIInstrInfo | |
usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | |
usesFPDPRounding(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
usesFPDPRounding(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
usesLGKM_CNT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
usesVM_CNT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override | llvm::SIInstrInfo |