LLVM  13.0.0git
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::SIInstrInfo Class Referencefinal

#include "Target/AMDGPU/SIInstrInfo.h"

Inheritance diagram for llvm::SIInstrInfo:
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Collaboration diagram for llvm::SIInstrInfo:
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Public Types

enum  TargetOperandFlags {
  MO_MASK = 0xf, MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2,
  MO_GOTPCREL32_LO = 2, MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4,
  MO_REL32_HI = 5, MO_LONG_BRANCH_FORWARD = 6, MO_LONG_BRANCH_BACKWARD = 7, MO_ABS32_LO = 8,
  MO_ABS32_HI = 9
}
 

Public Member Functions

unsigned buildExtractSubReg (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
MachineOperand buildExtractSubRegOrImm (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
 SIInstrInfo (const GCNSubtarget &ST)
 
const SIRegisterInfogetRegisterInfo () const
 
const GCNSubtargetgetSubtarget () const
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AAResults *AA) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 
bool getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
 
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
 
bool shouldScheduleLoadsNear (SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
 
void materializeImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
 
const TargetRegisterClassgetPreferredSelectRegClass (unsigned Size) const
 
Register insertNE (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
 
Register insertEQ (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64 (MachineInstr &MI) const
 
unsigned getMovOpcode (const TargetRegisterClass *DstRC) const
 
const MCInstrDescgetIndirectRegWriteMovRelPseudo (unsigned VecSize, unsigned EltSize, bool IsSGPR) const
 
const MCInstrDescgetIndirectGPRIDXPseudo (unsigned VecSize, bool IsIndirectSrc) const
 
LLVM_READONLY int commuteOpcode (unsigned Opc) const
 
LLVM_READONLY int commuteOpcode (const MachineInstr &MI) const
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool findCommutedOpIndices (MCInstrDesc Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
unsigned insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
 
bool analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
 
void insertVectorSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
 
unsigned getAddressSpaceForPseudoSourceKind (unsigned Kind) const override
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 
bool isFoldableCopy (const MachineInstr &MI) const
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
 
unsigned getMachineCSELookAheadLimit () const override
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isSALU (uint16_t Opcode) const
 
bool isVALU (uint16_t Opcode) const
 
bool isVMEM (uint16_t Opcode) const
 
bool isSOP1 (uint16_t Opcode) const
 
bool isSOP2 (uint16_t Opcode) const
 
bool isSOPC (uint16_t Opcode) const
 
bool isSOPK (uint16_t Opcode) const
 
bool isSOPP (uint16_t Opcode) const
 
bool isPacked (uint16_t Opcode) const
 
bool isVOP1 (uint16_t Opcode) const
 
bool isVOP2 (uint16_t Opcode) const
 
bool isVOP3 (uint16_t Opcode) const
 
bool isSDWA (uint16_t Opcode) const
 
bool isVOPC (uint16_t Opcode) const
 
bool isMUBUF (uint16_t Opcode) const
 
bool isMTBUF (uint16_t Opcode) const
 
bool isSMRD (uint16_t Opcode) const
 
bool isBufferSMRD (const MachineInstr &MI) const
 
bool isDS (uint16_t Opcode) const
 
bool isAlwaysGDS (uint16_t Opcode) const
 
bool isMIMG (uint16_t Opcode) const
 
bool isGather4 (uint16_t Opcode) const
 
bool isSegmentSpecificFLAT (uint16_t Opcode) const
 
bool isFLATGlobal (uint16_t Opcode) const
 
bool isFLATScratch (uint16_t Opcode) const
 
bool isFLAT (uint16_t Opcode) const
 
bool isEXP (uint16_t Opcode) const
 
bool isAtomicNoRet (uint16_t Opcode) const
 
bool isAtomicRet (uint16_t Opcode) const
 
bool isAtomic (uint16_t Opcode) const
 
bool isWQM (uint16_t Opcode) const
 
bool isDisableWQM (uint16_t Opcode) const
 
bool isVGPRSpill (uint16_t Opcode) const
 
bool isSGPRSpill (uint16_t Opcode) const
 
bool isDPP (uint16_t Opcode) const
 
bool isTRANS (uint16_t Opcode) const
 
bool isVOP3P (uint16_t Opcode) const
 
bool isVINTRP (uint16_t Opcode) const
 
bool isMAI (uint16_t Opcode) const
 
bool isDOT (uint16_t Opcode) const
 
bool sopkIsZext (uint16_t Opcode) const
 
bool isScalarStore (uint16_t Opcode) const
 
bool isFixedSize (uint16_t Opcode) const
 
bool hasFPClamp (uint16_t Opcode) const
 
uint64_t getClampMask (const MachineInstr &MI) const
 
bool usesFPDPRounding (uint16_t Opcode) const
 
bool isFPAtomic (uint16_t Opcode) const
 
bool isVGPRCopy (const MachineInstr &MI) const
 
bool hasVGPRUses (const MachineInstr &MI) const
 
bool hasUnwantedEffectsWhenEXECEmpty (const MachineInstr &MI) const
 Whether we must prevent this instruction from executing with EXEC = 0. More...
 
bool mayReadEXEC (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
 Returns true if the instruction could potentially depend on the value of exec. More...
 
bool isInlineConstant (const APInt &Imm) const
 
bool isInlineConstant (const APFloat &Imm) const
 
bool isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const
 
bool isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
 returns true if UseMO is substituted with DefMO in MI it would be an inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
 returns true if the operand OpIdx in MI is a valid inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
 
bool isInlineConstant (const MachineOperand &MO) const
 
bool isLiteralConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isLiteralConstant (const MachineInstr &MI, int OpIdx) const
 
bool isLiteralConstantLike (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
 
bool hasVALU32BitEncoding (unsigned Opcode) const
 Return true if this 64-bit VALU instruction has a 32-bit encoding. More...
 
bool usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 Returns true if this operand uses the constant bus. More...
 
bool hasModifiers (unsigned Opcode) const
 Return true if this instruction has any modifiers. More...
 
bool hasModifiersSet (const MachineInstr &MI, unsigned OpName) const
 
bool hasAnyModifiersSet (const MachineInstr &MI) const
 
bool canShrink (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
MachineInstrbuildShrunkInst (MachineInstr &MI, unsigned NewOpcode) const
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 
unsigned getVALUOp (const MachineInstr &MI) const
 
const TargetRegisterClassgetOpRegClass (const MachineInstr &MI, unsigned OpNo) const
 Return the correct register class for OpNo. More...
 
unsigned getOpSize (uint16_t Opcode, unsigned OpNo) const
 Return the size in bytes of the operand OpNo on the given. More...
 
unsigned getOpSize (const MachineInstr &MI, unsigned OpNo) const
 This form should usually be preferred since it handles operands with unknown register classes. More...
 
void legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
 Legalize the OpIndex operand of this instruction by inserting a MOV. More...
 
bool isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
 Check if MO is a legal operand if it was the OpIdx Operand for MI. More...
 
bool isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO would be a valid operand for the given operand definition OpInfo. More...
 
bool isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO (a register operand) is a legal register for the given operand description. More...
 
void legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Legalize operands in MI by either commuting it or inserting a copy of src1. More...
 
void legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Fix operands in MI to satisfy constant bus requirements. More...
 
Register readlaneVGPRToSGPR (Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
 Copy a value from a VGPR (SrcReg) to SGPR. More...
 
void legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const
 
void legalizeOperandsFLAT (MachineRegisterInfo &MRI, MachineInstr &MI) const
 
void legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
 
MachineBasicBlocklegalizeOperands (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
 Legalize all operands in this instruction. More...
 
bool moveFlatAddrToVGPR (MachineInstr &Inst) const
 Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR. More...
 
MachineBasicBlockmoveToVALU (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
 Replace this instruction's opcode with the equivalent VALU opcode. More...
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
void insertNoops (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
 
void insertReturn (MachineBasicBlock &MBB) const
 
LLVM_READONLY MachineOperandgetNamedOperand (MachineInstr &MI, unsigned OperandName) const
 Returns the operand named Op. More...
 
const LLVM_READONLY MachineOperandgetNamedOperand (const MachineInstr &MI, unsigned OpName) const
 
int64_t getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
 Get required immediate operand. More...
 
uint64_t getDefaultRsrcDataFormat () const
 
uint64_t getScratchRsrcWords23 () const
 
bool isLowLatencyInstruction (const MachineInstr &MI) const
 
bool isHighLatencyDef (int Opc) const override
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
unsigned isStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned getInstBundleSize (const MachineInstr &MI) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool mayAccessFlatAddressSpace (const MachineInstr &MI) const
 
bool isNonUniformBranchInstr (MachineInstr &Instr) const
 
void convertNonUniformIfRegion (MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
 
void convertNonUniformLoopRegion (MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 This is used by the post-RA scheduler (SchedulePostRAList.cpp). More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
 This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass. More...
 
bool isBasicBlockPrologue (const MachineInstr &MI) const override
 
MachineInstrcreatePHIDestinationCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
 
MachineInstrcreatePHISourceCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
 
bool isWave32 () const
 
MachineInstrBuilder getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
 Return a partially built integer add instruction without carry. More...
 
MachineInstrBuilder getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, RegScavenger &RS) const
 
const MCInstrDescgetKillTerminatorFromPseudo (unsigned Opcode) const
 
bool isLegalFLATOffset (int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
 Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction. More...
 
std::pair< int64_t, int64_t > splitFlatOffset (int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
 Split COffsetVal into {immediate offset field, remainder offset} values. More...
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
bool isAsmOnlyOpcode (int MCOp) const
 Check if this instruction should only be used by assembler. More...
 
const TargetRegisterClassgetRegClass (const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
 
void fixImplicitOperands (MachineInstr &MI) const
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
const MIRFormattergetMIRFormatter () const override
 

Static Public Member Functions

static bool isSALU (const MachineInstr &MI)
 
static bool isVALU (const MachineInstr &MI)
 
static bool isVMEM (const MachineInstr &MI)
 
static bool isSOP1 (const MachineInstr &MI)
 
static bool isSOP2 (const MachineInstr &MI)
 
static bool isSOPC (const MachineInstr &MI)
 
static bool isSOPK (const MachineInstr &MI)
 
static bool isSOPP (const MachineInstr &MI)
 
static bool isPacked (const MachineInstr &MI)
 
static bool isVOP1 (const MachineInstr &MI)
 
static bool isVOP2 (const MachineInstr &MI)
 
static bool isVOP3 (const MachineInstr &MI)
 
static bool isSDWA (const MachineInstr &MI)
 
static bool isVOPC (const MachineInstr &MI)
 
static bool isMUBUF (const MachineInstr &MI)
 
static bool isMTBUF (const MachineInstr &MI)
 
static bool isSMRD (const MachineInstr &MI)
 
static bool isDS (const MachineInstr &MI)
 
static bool isMIMG (const MachineInstr &MI)
 
static bool isGather4 (const MachineInstr &MI)
 
static bool isFLAT (const MachineInstr &MI)
 
static bool isSegmentSpecificFLAT (const MachineInstr &MI)
 
static bool isFLATGlobal (const MachineInstr &MI)
 
static bool isFLATScratch (const MachineInstr &MI)
 
static bool isEXP (const MachineInstr &MI)
 
static bool isAtomicNoRet (const MachineInstr &MI)
 
static bool isAtomicRet (const MachineInstr &MI)
 
static bool isAtomic (const MachineInstr &MI)
 
static bool isWQM (const MachineInstr &MI)
 
static bool isDisableWQM (const MachineInstr &MI)
 
static bool isVGPRSpill (const MachineInstr &MI)
 
static bool isSGPRSpill (const MachineInstr &MI)
 
static bool isDPP (const MachineInstr &MI)
 
static bool isTRANS (const MachineInstr &MI)
 
static bool isVOP3P (const MachineInstr &MI)
 
static bool isVINTRP (const MachineInstr &MI)
 
static bool isMAI (const MachineInstr &MI)
 
static bool isDOT (const MachineInstr &MI)
 
static bool isScalarUnit (const MachineInstr &MI)
 
static bool usesVM_CNT (const MachineInstr &MI)
 
static bool usesLGKM_CNT (const MachineInstr &MI)
 
static bool sopkIsZext (const MachineInstr &MI)
 
static bool isScalarStore (const MachineInstr &MI)
 
static bool isFixedSize (const MachineInstr &MI)
 
static bool hasFPClamp (const MachineInstr &MI)
 
static bool hasIntClamp (const MachineInstr &MI)
 
static bool usesFPDPRounding (const MachineInstr &MI)
 
static bool isFPAtomic (const MachineInstr &MI)
 
static bool modifiesModeRegister (const MachineInstr &MI)
 Return true if the instruction modifies the mode register.q. More...
 
static unsigned getNumWaitStates (const MachineInstr &MI)
 Return the number of wait states that result from executing this instruction. More...
 
static bool isKillTerminator (unsigned Opcode)
 
static bool isLegalMUBUFImmOffset (unsigned Imm)
 
static unsigned getDSShaderTypeValue (const MachineFunction &MF)
 

Protected Member Functions

bool swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
 

Detailed Description

Definition at line 38 of file SIInstrInfo.h.

Member Enumeration Documentation

◆ TargetOperandFlags

Enumerator
MO_MASK 
MO_NONE 
MO_GOTPCREL 
MO_GOTPCREL32 
MO_GOTPCREL32_LO 
MO_GOTPCREL32_HI 
MO_REL32 
MO_REL32_LO 
MO_REL32_HI 
MO_LONG_BRANCH_FORWARD 
MO_LONG_BRANCH_BACKWARD 
MO_ABS32_LO 
MO_ABS32_HI 

Definition at line 147 of file SIInstrInfo.h.

Constructor & Destructor Documentation

◆ SIInstrInfo()

SIInstrInfo::SIInstrInfo ( const GCNSubtarget ST)
explicit

Definition at line 64 of file SIInstrInfo.cpp.

References llvm::TargetSchedModel::init().

Member Function Documentation

◆ analyzeBranch()

bool SIInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

◆ analyzeBranchImpl()

bool SIInstrInfo::analyzeBranchImpl ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const

Definition at line 2305 of file SIInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, and MBB.

Referenced by analyzeBranch().

◆ areLoadsFromSameBasePtr()

bool SIInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

◆ areMemAccessesTriviallyDisjoint()

bool SIInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
override

◆ buildExtractSubReg()

unsigned SIInstrInfo::buildExtractSubReg ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo MRI,
MachineOperand SuperReg,
const TargetRegisterClass SuperRC,
unsigned  SubIdx,
const TargetRegisterClass SubRC 
) const

◆ buildExtractSubRegOrImm()

MachineOperand SIInstrInfo::buildExtractSubRegOrImm ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo MRI,
MachineOperand SuperReg,
const TargetRegisterClass SuperRC,
unsigned  SubIdx,
const TargetRegisterClass SubRC 
) const

◆ buildShrunkInst()

MachineInstr * SIInstrInfo::buildShrunkInst ( MachineInstr MI,
unsigned  NewOpcode 
) const

◆ canInsertSelect()

bool SIInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
Register  DstReg,
Register  TrueReg,
Register  FalseReg,
int CondCycles,
int TrueCycles,
int FalseCycles 
) const
override

◆ canShrink()

bool SIInstrInfo::canShrink ( const MachineInstr MI,
const MachineRegisterInfo MRI 
) const

◆ commuteInstructionImpl()

MachineInstr * SIInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx0,
unsigned  OpIdx1 
) const
overrideprotected

◆ commuteOpcode() [1/2]

LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr MI) const
inline

Definition at line 258 of file SIInstrInfo.h.

References commuteOpcode(), and MI.

◆ commuteOpcode() [2/2]

int SIInstrInfo::commuteOpcode ( unsigned  Opc) const

◆ convertNonUniformIfRegion()

void SIInstrInfo::convertNonUniformIfRegion ( MachineBasicBlock IfEntry,
MachineBasicBlock IfEnd 
) const

◆ convertNonUniformLoopRegion()

void SIInstrInfo::convertNonUniformLoopRegion ( MachineBasicBlock LoopEntry,
MachineBasicBlock LoopEnd 
) const

◆ convertToThreeAddress()

MachineInstr * SIInstrInfo::convertToThreeAddress ( MachineFunction::iterator MBB,
MachineInstr MI,
LiveVariables LV 
) const
override

◆ copyPhysReg()

void SIInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ createPHIDestinationCopy()

MachineInstr * SIInstrInfo::createPHIDestinationCopy ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsPt,
const DebugLoc DL,
Register  Src,
Register  Dst 
) const
override

◆ createPHISourceCopy()

MachineInstr * SIInstrInfo::createPHISourceCopy ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsPt,
const DebugLoc DL,
Register  Src,
unsigned  SrcSubReg,
Register  Dst 
) const
override

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 7265 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

◆ CreateTargetPostRAHazardRecognizer() [2/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction MF) const
override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 7273 of file SIInstrInfo.cpp.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > SIInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 7278 of file SIInstrInfo.cpp.

References MO_MASK.

◆ expandMovDPP64()

std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 ( MachineInstr MI) const

◆ expandPostRAPseudo()

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

Definition at line 1631 of file SIInstrInfo.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::RegState::Define, DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), get, llvm::APInt::getHiBits(), llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::APInt::getLoBits(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::APInt::getZExtValue(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::SIRegisterInfo::hasVGPRs(), llvm::MipsISD::Hi, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isAGPR(), isInlineConstant(), llvm::GCNSubtarget::isWave32(), llvm::MipsISD::Lo, llvm::M0(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Reg, llvm::AMDGPU::CPol::SCC, llvm::MachineOperand::setIsUndef(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, SubReg, llvm::MachineInstr::tieOperands(), TRI, llvm::RegState::Undef, and llvm::GCNSubtarget::useVGPRIndexMode().

◆ findCommutedOpIndices() [1/2]

bool SIInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
override

Definition at line 2121 of file SIInstrInfo.cpp.

References MI.

◆ findCommutedOpIndices() [2/2]

bool SIInstrInfo::findCommutedOpIndices ( MCInstrDesc  Desc,
unsigned &  SrcOpIdx0,
unsigned &  SrcOpIdx1 
) const

◆ fixImplicitOperands()

void SIInstrInfo::fixImplicitOperands ( MachineInstr MI) const

◆ FoldImmediate()

bool SIInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg,
MachineRegisterInfo MRI 
) const
final

◆ foldMemoryOperandImpl()

MachineInstr * SIInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned >  Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr,
VirtRegMap VRM = nullptr 
) const
override

◆ getAddNoCarry() [1/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  DestReg 
) const

Return a partially built integer add instruction without carry.

Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.

Definition at line 7303 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, MBB, MRI, and llvm::MachineRegisterInfo::setRegAllocationHint().

◆ getAddNoCarry() [2/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  DestReg,
RegScavenger RS 
) const

◆ getAddressSpaceForPseudoSourceKind()

unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned  Kind) const
override

◆ getBranchDestBlock()

MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override

Definition at line 2160 of file SIInstrInfo.cpp.

References MI.

◆ getClampMask()

uint64_t llvm::SIInstrInfo::getClampMask ( const MachineInstr MI) const
inline

◆ getDefaultRsrcDataFormat()

uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const

◆ getDSShaderTypeValue()

unsigned SIInstrInfo::getDSShaderTypeValue ( const MachineFunction MF)
static

◆ getIndirectGPRIDXPseudo()

const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo ( unsigned  VecSize,
bool  IsIndirectSrc 
) const

Definition at line 1211 of file SIInstrInfo.cpp.

References get, and llvm_unreachable.

◆ getIndirectRegWriteMovRelPseudo()

const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo ( unsigned  VecSize,
unsigned  EltSize,
bool  IsSGPR 
) const

◆ getInstBundleSize()

unsigned SIInstrInfo::getInstBundleSize ( const MachineInstr MI) const

Definition at line 7075 of file SIInstrInfo.cpp.

References assert(), E, getInstSizeInBytes(), I, MI, and llvm::Check::Size.

Referenced by getInstSizeInBytes().

◆ getInstrLatency()

unsigned SIInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned *  PredCost = nullptr 
) const
override

Definition at line 7818 of file SIInstrInfo.cpp.

References E, I, llvm::max(), and MI.

Referenced by llvm::GCNSubtarget::adjustSchedDependency().

◆ getInstSizeInBytes()

unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getKillTerminatorFromPseudo()

const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo ( unsigned  Opcode) const

Definition at line 7349 of file SIInstrInfo.cpp.

References get, and llvm_unreachable.

◆ getMachineCSELookAheadLimit()

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const
inlineoverride

Definition at line 329 of file SIInstrInfo.h.

◆ getMCOpcodeFromPseudo()

const MCInstrDesc& llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned  Opcode) const
inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 997 of file SIInstrInfo.h.

References get, and pseudoToMCOpcode().

Referenced by getInstSizeInBytes().

◆ getMemOperandsWithOffsetWidth()

bool SIInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr LdSt,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool &  OffsetIsScalable,
unsigned &  Width,
const TargetRegisterInfo TRI 
) const
final

◆ getMIRFormatter()

const MIRFormatter* llvm::SIInstrInfo::getMIRFormatter ( ) const
inlineoverride

Definition at line 1114 of file SIInstrInfo.h.

◆ getMovOpcode()

unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass DstRC) const

◆ getNamedImmOperand()

int64_t llvm::SIInstrInfo::getNamedImmOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

Get required immediate operand.

Definition at line 984 of file SIInstrInfo.h.

References llvm::AMDGPU::getNamedOperandIdx(), and MI.

◆ getNamedOperand() [1/2]

const LLVM_READONLY MachineOperand* llvm::SIInstrInfo::getNamedOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

Definition at line 978 of file SIInstrInfo.h.

References getNamedOperand(), and MI.

◆ getNamedOperand() [2/2]

MachineOperand * SIInstrInfo::getNamedOperand ( MachineInstr MI,
unsigned  OperandName 
) const

◆ getNumWaitStates()

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr MI)
static

Return the number of wait states that result from executing this instruction.

Definition at line 1622 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), and getWaitStatesSince().

◆ getOpRegClass()

const TargetRegisterClass * SIInstrInfo::getOpRegClass ( const MachineInstr MI,
unsigned  OpNo 
) const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 4484 of file SIInstrInfo.cpp.

References adjustAllocatableRegClass(), get, llvm::MCInstrDesc::getNumOperands(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), MI, MRI, llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), and verifyInstruction().

◆ getOpSize() [1/2]

unsigned llvm::SIInstrInfo::getOpSize ( const MachineInstr MI,
unsigned  OpNo 
) const
inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 882 of file SIInstrInfo.h.

References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), MI, and SubReg.

◆ getOpSize() [2/2]

unsigned llvm::SIInstrInfo::getOpSize ( uint16_t  Opcode,
unsigned  OpNo 
) const
inline

◆ getPreferredSelectRegClass()

const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass ( unsigned  Size) const

Definition at line 1040 of file SIInstrInfo.cpp.

◆ getRegClass()

const TargetRegisterClass * SIInstrInfo::getRegClass ( const MCInstrDesc TID,
unsigned  OpNum,
const TargetRegisterInfo TRI,
const MachineFunction MF 
) const
override

◆ getRegisterInfo()

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const
inline

Definition at line 173 of file SIInstrInfo.h.

Referenced by llvm::GCNSubtarget::getRegisterInfo().

◆ getScratchRsrcWords23()

uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > SIInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getSerializableTargetIndices()

ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const
override

◆ getSubtarget()

const GCNSubtarget& llvm::SIInstrInfo::getSubtarget ( ) const
inline

Definition at line 177 of file SIInstrInfo.h.

◆ getVALUOp()

unsigned SIInstrInfo::getVALUOp ( const MachineInstr MI) const

◆ hasAnyModifiersSet()

bool SIInstrInfo::hasAnyModifiersSet ( const MachineInstr MI) const

Definition at line 3484 of file SIInstrInfo.cpp.

References hasModifiersSet(), and MI.

Referenced by FoldImmediate().

◆ hasFPClamp() [1/2]

static bool llvm::SIInstrInfo::hasFPClamp ( const MachineInstr MI)
inlinestatic

Definition at line 692 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, and MI.

◆ hasFPClamp() [2/2]

bool llvm::SIInstrInfo::hasFPClamp ( uint16_t  Opcode) const
inline

Definition at line 696 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, and get.

◆ hasIntClamp()

static bool llvm::SIInstrInfo::hasIntClamp ( const MachineInstr MI)
inlinestatic

Definition at line 700 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IntClamp, and MI.

◆ hasModifiers()

bool SIInstrInfo::hasModifiers ( unsigned  Opcode) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 3470 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

◆ hasModifiersSet()

bool SIInstrInfo::hasModifiersSet ( const MachineInstr MI,
unsigned  OpName 
) const

Definition at line 3478 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.

Referenced by canShrink(), and hasAnyModifiersSet().

◆ hasUnwantedEffectsWhenEXECEmpty()

bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr MI) const

Whether we must prevent this instruction from executing with EXEC = 0.

Definition at line 3230 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT, isEXP(), isSMRD(), MI, and modifiesModeRegister().

◆ hasVALU32BitEncoding()

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned  Opcode) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 3458 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), llvm::GCNSubtarget::hasGFX90AInsts(), and pseudoToMCOpcode().

Referenced by canShrink().

◆ hasVGPRUses()

bool llvm::SIInstrInfo::hasVGPRUses ( const MachineInstr MI) const
inline

Definition at line 736 of file SIInstrInfo.h.

References llvm::any_of(), llvm::MachineFunction::getRegInfo(), MI, and MRI.

◆ insertBranch()

unsigned SIInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
override

◆ insertEQ()

Register SIInstrInfo::insertEQ ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  SrcReg,
int  Value 
) const

◆ insertIndirectBranch()

unsigned SIInstrInfo::insertIndirectBranch ( MachineBasicBlock MBB,
MachineBasicBlock NewDestBB,
const DebugLoc DL,
int64_t  BrOffset,
RegScavenger RS = nullptr 
) const
override

◆ insertNE()

Register SIInstrInfo::insertNE ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  SrcReg,
int  Value 
) const

◆ insertNoop()

void SIInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 1588 of file SIInstrInfo.cpp.

References insertNoops(), MBB, and MI.

◆ insertNoops()

void SIInstrInfo::insertNoops ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  Quantity 
) const
override

◆ insertReturn()

void SIInstrInfo::insertReturn ( MachineBasicBlock MBB) const

◆ insertSelect()

void SIInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  DstReg,
ArrayRef< MachineOperand Cond,
Register  TrueReg,
Register  FalseReg 
) const
override

◆ insertVectorSelect()

void SIInstrInfo::insertVectorSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
Register  DstReg,
ArrayRef< MachineOperand Cond,
Register  TrueReg,
Register  FalseReg 
) const

◆ isAlwaysGDS()

bool SIInstrInfo::isAlwaysGDS ( uint16_t  Opcode) const

Definition at line 3206 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT.

◆ isAsmOnlyOpcode()

bool SIInstrInfo::isAsmOnlyOpcode ( int  MCOp) const

Check if this instruction should only be used by assembler.

Return true if this opcode should not be used by codegen.

Definition at line 7502 of file SIInstrInfo.cpp.

Referenced by pseudoToMCOpcode().

◆ isAtomic() [1/2]

static bool llvm::SIInstrInfo::isAtomic ( const MachineInstr MI)
inlinestatic

Definition at line 564 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, and MI.

Referenced by isValidClauseInst().

◆ isAtomic() [2/2]

bool llvm::SIInstrInfo::isAtomic ( uint16_t  Opcode) const
inline

◆ isAtomicNoRet() [1/2]

static bool llvm::SIInstrInfo::isAtomicNoRet ( const MachineInstr MI)
inlinestatic

Definition at line 548 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicNoRet, and MI.

◆ isAtomicNoRet() [2/2]

bool llvm::SIInstrInfo::isAtomicNoRet ( uint16_t  Opcode) const
inline

Definition at line 552 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::IsAtomicNoRet.

◆ isAtomicRet() [1/2]

static bool llvm::SIInstrInfo::isAtomicRet ( const MachineInstr MI)
inlinestatic

Definition at line 556 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicRet, and MI.

◆ isAtomicRet() [2/2]

bool llvm::SIInstrInfo::isAtomicRet ( uint16_t  Opcode) const
inline

Definition at line 560 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::IsAtomicRet.

◆ isBasicBlockPrologue()

bool SIInstrInfo::isBasicBlockPrologue ( const MachineInstr MI) const
override

Definition at line 7297 of file SIInstrInfo.cpp.

References MI.

◆ isBranchOffsetInRange()

bool SIInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

Definition at line 2144 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

◆ isBufferSMRD()

bool SIInstrInfo::isBufferSMRD ( const MachineInstr MI) const

◆ isDisableWQM() [1/2]

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr MI)
inlinestatic

Definition at line 582 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, and MI.

◆ isDisableWQM() [2/2]

bool llvm::SIInstrInfo::isDisableWQM ( uint16_t  Opcode) const
inline

Definition at line 586 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, and get.

◆ isDOT() [1/2]

static bool llvm::SIInstrInfo::isDOT ( const MachineInstr MI)
inlinestatic

Definition at line 646 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsDOT, and MI.

◆ isDOT() [2/2]

bool llvm::SIInstrInfo::isDOT ( uint16_t  Opcode) const
inline

Definition at line 650 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::IsDOT.

◆ isDPP() [1/2]

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr MI)
inlinestatic

◆ isDPP() [2/2]

bool llvm::SIInstrInfo::isDPP ( uint16_t  Opcode) const
inline

Definition at line 610 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP, and get.

◆ isDS() [1/2]

static bool llvm::SIInstrInfo::isDS ( const MachineInstr MI)
inlinestatic

◆ isDS() [2/2]

bool llvm::SIInstrInfo::isDS ( uint16_t  Opcode) const
inline

Definition at line 481 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, and get.

◆ isEXP() [1/2]

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr MI)
inlinestatic

◆ isEXP() [2/2]

bool llvm::SIInstrInfo::isEXP ( uint16_t  Opcode) const
inline

Definition at line 544 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP, and get.

◆ isFixedSize() [1/2]

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr MI)
inlinestatic

Definition at line 684 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, and MI.

Referenced by getInstSizeInBytes().

◆ isFixedSize() [2/2]

bool llvm::SIInstrInfo::isFixedSize ( uint16_t  Opcode) const
inline

Definition at line 688 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, and get.

◆ isFLAT() [1/2]

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr MI)
inlinestatic

◆ isFLAT() [2/2]

bool llvm::SIInstrInfo::isFLAT ( uint16_t  Opcode) const
inline

Definition at line 536 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, and get.

◆ isFLATGlobal() [1/2]

static bool llvm::SIInstrInfo::isFLATGlobal ( const MachineInstr MI)
inlinestatic

Definition at line 519 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, and MI.

◆ isFLATGlobal() [2/2]

bool llvm::SIInstrInfo::isFLATGlobal ( uint16_t  Opcode) const
inline

Definition at line 523 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, and get.

◆ isFLATScratch() [1/2]

static bool llvm::SIInstrInfo::isFLATScratch ( const MachineInstr MI)
inlinestatic

◆ isFLATScratch() [2/2]

bool llvm::SIInstrInfo::isFLATScratch ( uint16_t  Opcode) const
inline

Definition at line 531 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatScratch, and get.

◆ isFoldableCopy()

bool SIInstrInfo::isFoldableCopy ( const MachineInstr MI) const

Definition at line 2641 of file SIInstrInfo.cpp.

References MI.

◆ isFPAtomic() [1/2]

static bool llvm::SIInstrInfo::isFPAtomic ( const MachineInstr MI)
inlinestatic

Definition at line 720 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic, and MI.

◆ isFPAtomic() [2/2]

bool llvm::SIInstrInfo::isFPAtomic ( uint16_t  Opcode) const
inline

Definition at line 724 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic, and get.

◆ isGather4() [1/2]

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr MI)
inlinestatic

Definition at line 495 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, and MI.

Referenced by verifyInstruction().

◆ isGather4() [2/2]

bool llvm::SIInstrInfo::isGather4 ( uint16_t  Opcode) const
inline

Definition at line 499 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, and get.

◆ isHighLatencyDef()

bool SIInstrInfo::isHighLatencyDef ( int  Opc) const
override

Definition at line 7021 of file SIInstrInfo.cpp.

References get, isFLAT(), isMIMG(), isMTBUF(), and isMUBUF().

Referenced by llvm::SIScheduleDAGMI::schedule().

◆ isImmOperandLegal()

bool SIInstrInfo::isImmOperandLegal ( const MachineInstr MI,
unsigned  OpNo,
const MachineOperand MO 
) const

◆ isInlineConstant() [1/8]

bool llvm::SIInstrInfo::isInlineConstant ( const APFloat Imm) const
inline

Definition at line 756 of file SIInstrInfo.h.

References llvm::APFloat::bitcastToAPInt(), and isInlineConstant().

◆ isInlineConstant() [2/8]

bool SIInstrInfo::isInlineConstant ( const APInt Imm) const

◆ isInlineConstant() [3/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
const MachineOperand UseMO,
const MachineOperand DefMO 
) const
inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 769 of file SIInstrInfo.h.

References assert(), llvm::MachineOperand::getParent(), isInlineConstant(), and MI.

◆ isInlineConstant() [4/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx 
) const
inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 783 of file SIInstrInfo.h.

References isInlineConstant(), and MI.

◆ isInlineConstant() [5/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO 
) const
inline

◆ isInlineConstant() [6/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO) const
inline

◆ isInlineConstant() [7/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline

Definition at line 762 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isInlineConstant() [8/8]

bool SIInstrInfo::isInlineConstant ( const MachineOperand MO,
uint8_t  OperandType 
) const

Definition at line 3316 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::MachineOperand::isImm(), llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableIntLiteralV216(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralV216(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), llvm_unreachable, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

◆ isKillTerminator()

bool SIInstrInfo::isKillTerminator ( unsigned  Opcode)
static

Definition at line 7339 of file SIInstrInfo.cpp.

◆ isLegalFLATOffset()

bool SIInstrInfo::isLegalFLATOffset ( int64_t  Offset,
unsigned  AddrSpace,
uint64_t  FlatVariant 
) const

◆ isLegalMUBUFImmOffset()

static bool llvm::SIInstrInfo::isLegalMUBUFImmOffset ( unsigned  Imm)
inlinestatic

◆ isLegalRegOperand()

bool SIInstrInfo::isLegalRegOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const

◆ isLegalVSrcOperand()

bool SIInstrInfo::isLegalVSrcOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 4617 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), and MRI.

◆ isLiteralConstant() [1/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineInstr MI,
int  OpIdx 
) const
inline

Definition at line 815 of file SIInstrInfo.h.

References llvm::MachineOperand::isImm(), isInlineConstant(), and MI.

◆ isLiteralConstant() [2/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline

◆ isLiteralConstantLike()

bool SIInstrInfo::isLiteralConstantLike ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const

◆ isLoadFromStackSlot()

unsigned SIInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

◆ isLowLatencyInstruction()

bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr MI) const

Definition at line 7015 of file SIInstrInfo.cpp.

References isSMRD(), and MI.

Referenced by llvm::SIScheduleDAGMI::schedule().

◆ isMAI() [1/2]

static bool llvm::SIInstrInfo::isMAI ( const MachineInstr MI)
inlinestatic

◆ isMAI() [2/2]

bool llvm::SIInstrInfo::isMAI ( uint16_t  Opcode) const
inline

Definition at line 642 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::IsMAI.

◆ isMIMG() [1/2]

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr MI)
inlinestatic

◆ isMIMG() [2/2]

bool llvm::SIInstrInfo::isMIMG ( uint16_t  Opcode) const
inline

Definition at line 491 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::MIMG.

◆ isMTBUF() [1/2]

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr MI)
inlinestatic

◆ isMTBUF() [2/2]

bool llvm::SIInstrInfo::isMTBUF ( uint16_t  Opcode) const
inline

Definition at line 463 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::MTBUF.

◆ isMUBUF() [1/2]

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr MI)
inlinestatic

◆ isMUBUF() [2/2]

bool llvm::SIInstrInfo::isMUBUF ( uint16_t  Opcode) const
inline

Definition at line 455 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::MUBUF.

◆ isNonUniformBranchInstr()

bool SIInstrInfo::isNonUniformBranchInstr ( MachineInstr Instr) const

Definition at line 7175 of file SIInstrInfo.cpp.

References llvm::MCID::Branch.

◆ isOperandLegal()

bool SIInstrInfo::isOperandLegal ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO = nullptr 
) const

Check if MO is a legal operand if it was the OpIdx Operand for MI.

Definition at line 4628 of file SIInstrInfo.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::count(), llvm::numbers::e, llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), llvm::GCNSubtarget::hasVOP3Literal(), i, llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert(), llvm::SIRegisterInfo::isAGPR(), isDS(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLegalRegOperand(), isLiteralConstantLike(), isMIMG(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVALU(), isVOP3(), MI, MRI, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, llvm::MachineRegisterInfo::reservedRegsFrozen(), and usesConstantBus().

Referenced by commuteInstructionImpl(), convertToThreeAddress(), and legalizeOperandsVOP3().

◆ isPacked() [1/2]

static bool llvm::SIInstrInfo::isPacked ( const MachineInstr MI)
inlinestatic

Definition at line 403 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsPacked, and MI.

◆ isPacked() [2/2]

bool llvm::SIInstrInfo::isPacked ( uint16_t  Opcode) const
inline

Definition at line 407 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::IsPacked.

◆ isReallyTriviallyReMaterializable()

bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AAResults AA 
) const
override

Definition at line 108 of file SIInstrInfo.cpp.

References assert(), and MI.

◆ isSALU() [1/2]

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr MI)
inlinestatic

Definition at line 339 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SALU.

Referenced by getInstSizeInBytes(), mayReadEXEC(), and shouldReadExec().

◆ isSALU() [2/2]

bool llvm::SIInstrInfo::isSALU ( uint16_t  Opcode) const
inline

Definition at line 343 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SALU.

◆ isScalarStore() [1/2]

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr MI)
inlinestatic
Returns
true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.

Definition at line 676 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarStore() [2/2]

bool llvm::SIInstrInfo::isScalarStore ( uint16_t  Opcode) const
inline

Definition at line 680 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarUnit()

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr MI)
inlinestatic

Definition at line 654 of file SIInstrInfo.h.

References MI, llvm::SIInstrFlags::SALU, and llvm::SIInstrFlags::SMRD.

◆ isSchedulingBoundary()

bool SIInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

Definition at line 3179 of file SIInstrInfo.cpp.

References changesVGPRIndexingMode(), llvm::ISD::INLINEASM_BR, and MI.

◆ isSDWA() [1/2]

static bool llvm::SIInstrInfo::isSDWA ( const MachineInstr MI)
inlinestatic

Definition at line 435 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SDWA.

Referenced by verifyInstruction().

◆ isSDWA() [2/2]

bool llvm::SIInstrInfo::isSDWA ( uint16_t  Opcode) const
inline

Definition at line 439 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SDWA.

◆ isSegmentSpecificFLAT() [1/2]

static bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( const MachineInstr MI)
inlinestatic

◆ isSegmentSpecificFLAT() [2/2]

bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( uint16_t  Opcode) const
inline

◆ isSGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr MI)
inlinestatic

Definition at line 598 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SGPRSpill.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSGPRSpill() [2/2]

bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 602 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SGPRSpill.

◆ isSGPRStackAccess()

unsigned SIInstrInfo::isSGPRStackAccess ( const MachineInstr MI,
int FrameIndex 
) const

◆ isSMRD() [1/2]

static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr MI)
inlinestatic

◆ isSMRD() [2/2]

bool llvm::SIInstrInfo::isSMRD ( uint16_t  Opcode) const
inline

Definition at line 471 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SMRD.

◆ isSOP1() [1/2]

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr MI)
inlinestatic

Definition at line 363 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOP1.

◆ isSOP1() [2/2]

bool llvm::SIInstrInfo::isSOP1 ( uint16_t  Opcode) const
inline

Definition at line 367 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOP1.

◆ isSOP2() [1/2]

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr MI)
inlinestatic

Definition at line 371 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOP2.

Referenced by verifyInstruction().

◆ isSOP2() [2/2]

bool llvm::SIInstrInfo::isSOP2 ( uint16_t  Opcode) const
inline

Definition at line 375 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOP2.

◆ isSOPC() [1/2]

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr MI)
inlinestatic

Definition at line 379 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPC.

Referenced by verifyInstruction().

◆ isSOPC() [2/2]

bool llvm::SIInstrInfo::isSOPC ( uint16_t  Opcode) const
inline

Definition at line 383 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOPC.

◆ isSOPK() [1/2]

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr MI)
inlinestatic

Definition at line 387 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPK.

Referenced by verifyInstruction().

◆ isSOPK() [2/2]

bool llvm::SIInstrInfo::isSOPK ( uint16_t  Opcode) const
inline

Definition at line 391 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOPK.

◆ isSOPP() [1/2]

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr MI)
inlinestatic

Definition at line 395 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPP.

◆ isSOPP() [2/2]

bool llvm::SIInstrInfo::isSOPP ( uint16_t  Opcode) const
inline

Definition at line 399 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOPP.

◆ isStackAccess()

unsigned SIInstrInfo::isStackAccess ( const MachineInstr MI,
int FrameIndex 
) const

◆ isStoreToStackSlot()

unsigned SIInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

◆ isTRANS() [1/2]

static bool llvm::SIInstrInfo::isTRANS ( const MachineInstr MI)
inlinestatic

Definition at line 614 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::TRANS.

◆ isTRANS() [2/2]

bool llvm::SIInstrInfo::isTRANS ( uint16_t  Opcode) const
inline

Definition at line 618 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::TRANS.

◆ isVALU() [1/2]

static bool llvm::SIInstrInfo::isVALU ( const MachineInstr MI)
inlinestatic

◆ isVALU() [2/2]

bool llvm::SIInstrInfo::isVALU ( uint16_t  Opcode) const
inline

Definition at line 351 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VALU.

◆ isVGPRCopy()

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr MI) const
inline

◆ isVGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr MI)
inlinestatic

Definition at line 590 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VGPRSpill.

Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().

◆ isVGPRSpill() [2/2]

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 594 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VGPRSpill.

◆ isVINTRP() [1/2]

static bool llvm::SIInstrInfo::isVINTRP ( const MachineInstr MI)
inlinestatic

◆ isVINTRP() [2/2]

bool llvm::SIInstrInfo::isVINTRP ( uint16_t  Opcode) const
inline

Definition at line 634 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VINTRP.

◆ isVMEM() [1/2]

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr MI)
inlinestatic

◆ isVMEM() [2/2]

bool llvm::SIInstrInfo::isVMEM ( uint16_t  Opcode) const
inline

Definition at line 359 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

◆ isVOP1() [1/2]

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr MI)
inlinestatic

Definition at line 411 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP1.

Referenced by verifyInstruction().

◆ isVOP1() [2/2]

bool llvm::SIInstrInfo::isVOP1 ( uint16_t  Opcode) const
inline

Definition at line 415 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VOP1.

◆ isVOP2() [1/2]

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr MI)
inlinestatic

Definition at line 419 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP2.

Referenced by legalizeOperands(), and verifyInstruction().

◆ isVOP2() [2/2]

bool llvm::SIInstrInfo::isVOP2 ( uint16_t  Opcode) const
inline

Definition at line 423 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VOP2.

◆ isVOP3() [1/2]

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr MI)
inlinestatic

◆ isVOP3() [2/2]

bool llvm::SIInstrInfo::isVOP3 ( uint16_t  Opcode) const
inline

Definition at line 431 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VOP3.

◆ isVOP3P() [1/2]

static bool llvm::SIInstrInfo::isVOP3P ( const MachineInstr MI)
inlinestatic

Definition at line 622 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP3P.

◆ isVOP3P() [2/2]

bool llvm::SIInstrInfo::isVOP3P ( uint16_t  Opcode) const
inline

Definition at line 626 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VOP3P.

◆ isVOPC() [1/2]

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr MI)
inlinestatic

Definition at line 443 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOPC.

Referenced by legalizeOperands(), and verifyInstruction().

◆ isVOPC() [2/2]

bool llvm::SIInstrInfo::isVOPC ( uint16_t  Opcode) const
inline

Definition at line 447 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::VOPC.

◆ isWave32()

bool llvm::SIInstrInfo::isWave32 ( ) const

Definition at line 7779 of file SIInstrInfo.cpp.

References llvm::GCNSubtarget::isWave32().

◆ isWQM() [1/2]

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr MI)
inlinestatic

Definition at line 574 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::WQM.

◆ isWQM() [2/2]

bool llvm::SIInstrInfo::isWQM ( uint16_t  Opcode) const
inline

Definition at line 578 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::WQM.

◆ legalizeGenericOperand()

void SIInstrInfo::legalizeGenericOperand ( MachineBasicBlock InsertMBB,
MachineBasicBlock::iterator  I,
const TargetRegisterClass DstRC,
MachineOperand Op,
MachineRegisterInfo MRI,
const DebugLoc DL 
) const

◆ legalizeOperands()

MachineBasicBlock * SIInstrInfo::legalizeOperands ( MachineInstr MI,
MachineDominatorTree MDT = nullptr 
) const

◆ legalizeOperandsFLAT()

void SIInstrInfo::legalizeOperandsFLAT ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOperandsSMRD()

void SIInstrInfo::legalizeOperandsSMRD ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOperandsVOP2()

void SIInstrInfo::legalizeOperandsVOP2 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOperandsVOP3()

void SIInstrInfo::legalizeOperandsVOP3 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const

◆ legalizeOpWithMove()

void SIInstrInfo::legalizeOpWithMove ( MachineInstr MI,
unsigned  OpIdx 
) const

◆ loadRegFromStackSlot()

void SIInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ materializeImmediate()

void SIInstrInfo::materializeImmediate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
int64_t  Value 
) const

◆ mayAccessFlatAddressSpace()

bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr MI) const

Definition at line 7161 of file SIInstrInfo.cpp.

References llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), and MI.

◆ mayReadEXEC()

bool SIInstrInfo::mayReadEXEC ( const MachineRegisterInfo MRI,
const MachineInstr MI 
) const

Returns true if the instruction could potentially depend on the value of exec.

If false, exec dependencies may safely be ignored.

Definition at line 3271 of file SIInstrInfo.cpp.

References isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), MI, and MRI.

◆ modifiesModeRegister()

bool SIInstrInfo::modifiesModeRegister ( const MachineInstr MI)
static

Return true if the instruction modifies the mode register.q.

Definition at line 3216 of file SIInstrInfo.cpp.

References MI.

Referenced by hasUnwantedEffectsWhenEXECEmpty().

◆ moveFlatAddrToVGPR()

bool SIInstrInfo::moveFlatAddrToVGPR ( MachineInstr Inst) const

◆ moveToVALU()

MachineBasicBlock * SIInstrInfo::moveToVALU ( MachineInstr MI,
MachineDominatorTree MDT = nullptr 
) const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary. If present, MDT is updated.

Definition at line 5688 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BitWidth, llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, DL, llvm::SetVector< T, Vector, Set >::empty(), llvm::MachineInstr::eraseFromParent(), fixImplicitOperands(), get, llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), getVALUOp(), llvm::GCNSubtarget::hasDLInsts(), llvm::GCNSubtarget::hasOnlyRevVALUShifts(), i, I, llvm::SetVector< T, Vector, Set >::insert(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::GCNSubtarget::isWave32(), legalizeOperands(), llvm_unreachable, MBB, MRI, Offset, llvm::SetVector< T, Vector, Set >::pop_back_val(), llvm::MachineInstr::RemoveOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::AMDGPU::CPol::SCC, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), and llvm::Check::Size.

◆ pseudoToMCOpcode()

int SIInstrInfo::pseudoToMCOpcode ( int  Opcode) const

◆ readlaneVGPRToSGPR()

Register SIInstrInfo::readlaneVGPRToSGPR ( Register  SrcReg,
MachineInstr UseMI,
MachineRegisterInfo MRI 
) const

Copy a value from a VGPR (SrcReg) to SGPR.

This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.

Returns
The SGPR register that SrcReg was copied to.

Definition at line 4922 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), get, llvm::SIRegisterInfo::getEquivalentSGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::SIRegisterInfo::hasAGPRs(), i, MRI, and UseMI.

Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().

◆ removeBranch()

unsigned SIInstrInfo::removeBranch ( MachineBasicBlock MBB,
int BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 2478 of file SIInstrInfo.cpp.

References Cond.

◆ shouldClusterMemOps()

bool SIInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
ArrayRef< const MachineOperand * >  BaseOps2,
unsigned  NumLoads,
unsigned  NumBytes 
) const
override

◆ shouldScheduleLoadsNear()

bool SIInstrInfo::shouldScheduleLoadsNear ( SDNode Load0,
SDNode Load1,
int64_t  Offset0,
int64_t  Offset1,
unsigned  NumLoads 
) const
override

Definition at line 470 of file SIInstrInfo.cpp.

References assert().

◆ sopkIsZext() [1/2]

static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr MI)
inlinestatic

Definition at line 666 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPK_ZEXT.

Referenced by verifyInstruction().

◆ sopkIsZext() [2/2]

bool llvm::SIInstrInfo::sopkIsZext ( uint16_t  Opcode) const
inline

Definition at line 670 of file SIInstrInfo.h.

References get, and llvm::SIInstrFlags::SOPK_ZEXT.

◆ splitFlatOffset()

std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset ( int64_t  COffsetVal,
unsigned  AddrSpace,
uint64_t  FlatVariant 
) const

◆ storeRegToStackSlot()

void SIInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ swapSourceModifiers()

bool SIInstrInfo::swapSourceModifiers ( MachineInstr MI,
MachineOperand Src0,
unsigned  Src0OpName,
MachineOperand Src1,
unsigned  Src1OpName 
) const
protected

◆ usesConstantBus()

bool SIInstrInfo::usesConstantBus ( const MachineRegisterInfo MRI,
const MachineOperand MO,
const MCOperandInfo OpInfo 
) const

◆ usesFPDPRounding() [1/2]

static bool llvm::SIInstrInfo::usesFPDPRounding ( const MachineInstr MI)
inlinestatic

Definition at line 712 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, and MI.

◆ usesFPDPRounding() [2/2]

bool llvm::SIInstrInfo::usesFPDPRounding ( uint16_t  Opcode) const
inline

Definition at line 716 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, and get.

◆ usesLGKM_CNT()

static bool llvm::SIInstrInfo::usesLGKM_CNT ( const MachineInstr MI)
inlinestatic

Definition at line 662 of file SIInstrInfo.h.

References llvm::SIInstrFlags::LGKM_CNT, and MI.

◆ usesVM_CNT()

static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr MI)
inlinestatic

Definition at line 658 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VM_CNT.

◆ verifyInstruction()

bool SIInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
override

Definition at line 3695 of file SIInstrInfo.cpp.

References llvm::SISrcMods::ABS, llvm::all_of(), assert(), llvm::AMDGPU::DPP::BCAST15, llvm::AMDGPU::DPP::BCAST31, compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::countPopulation(), llvm::Data, llvm::dbgs(), DC, llvm::SIInstrFlags::DPP, llvm::AMDGPU::DPP::DPP_LAST, llvm::AMDGPU::DPP::DPP_UNUSED1, llvm::AMDGPU::DPP::DPP_UNUSED2, llvm::AMDGPU::DPP::DPP_UNUSED3, llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED4_LAST, llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED5_LAST, llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED6_LAST, llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED7_LAST, llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED8_LAST, llvm::numbers::e, E, findImplicitSGPRRead(), get, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::SIRegisterInfo::getCompatibleSubRegClass(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::getOpcode(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::getSubRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::AMDGPUSubtarget::GFX10, llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasG16(), llvm::GCNSubtarget::hasGFX10A16(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasR128A16(), llvm::AMDGPUSubtarget::hasSDWA(), llvm::GCNSubtarget::hasSDWAOmod(), llvm::GCNSubtarget::hasSDWAOutModsVOPC(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::GCNSubtarget::hasSDWASdst(), llvm::GCNSubtarget::hasUnpackedD16VMem(), llvm::SIRegisterInfo::hasVGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), i, I, Info, llvm::SIRegisterInfo::isAGPR(), llvm::MCInstrDesc::isBranch(), isDS(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::isInt< 16 >(), llvm::AMDGPU::isLegal64BitDPPControl(), isMIMG(), llvm::Register::isPhysical(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::MachineOperand::isReg(), isSDWA(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSubRegOf(), llvm::MachineOperand::isTied(), llvm::isUInt< 16 >(), llvm::MachineOperand::isUse(), llvm::MCInstrDesc::isVariadic(), isVGPRSpill(), isVOP1(), isVOP2(), isVOP3(), isVOPC(), LLVM_DEBUG, LLVM_FALLTHROUGH, llvm::M0(), MI, llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::GCNSubtarget::needsAlignedVGPRs(), Offset, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, Reg, llvm::MCOperandInfo::RegClass, llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST, llvm::AMDGPU::DPP::ROW_SHARE_FIRST, llvm::AMDGPU::DPP::ROW_XMASK_LAST, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, usesConstantBus(), llvm::AMDGPU::DPP::WAVE_ROR1, and llvm::AMDGPU::DPP::WAVE_SHL1.


The documentation for this class was generated from the following files: