#include "Target/AMDGPU/SIInstrInfo.h"
Public Types | |
| enum | TargetOperandFlags { MO_MASK = 0xf, MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2, MO_GOTPCREL32_LO = 2, MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4, MO_REL32_HI = 5, MO_FAR_BRANCH_OFFSET = 6, MO_ABS32_LO = 8, MO_ABS32_HI = 9 } |
Protected Member Functions | |
| bool | swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override |
Detailed Description
Definition at line 44 of file SIInstrInfo.h.
Member Enumeration Documentation
◆ TargetOperandFlags
| Enumerator | |
|---|---|
| MO_MASK | |
| MO_NONE | |
| MO_GOTPCREL | |
| MO_GOTPCREL32 | |
| MO_GOTPCREL32_LO | |
| MO_GOTPCREL32_HI | |
| MO_REL32 | |
| MO_REL32_LO | |
| MO_REL32_HI | |
| MO_FAR_BRANCH_OFFSET | |
| MO_ABS32_LO | |
| MO_ABS32_HI | |
Definition at line 154 of file SIInstrInfo.h.
Constructor & Destructor Documentation
◆ SIInstrInfo()
|
explicit |
Definition at line 67 of file SIInstrInfo.cpp.
References llvm::TargetSchedModel::init().
Member Function Documentation
◆ analyzeBranch()
|
override |
Definition at line 2572 of file SIInstrInfo.cpp.
References analyzeBranchImpl(), Cond, E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), I, llvm_unreachable, and MBB.
◆ analyzeBranchImpl()
| bool SIInstrInfo::analyzeBranchImpl | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify | ||
| ) | const |
Definition at line 2529 of file SIInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, and MBB.
Referenced by analyzeBranch().
◆ analyzeCompare()
|
override |
Definition at line 8239 of file SIInstrInfo.cpp.
References MI.
◆ areLoadsFromSameBasePtr()
|
override |
Definition at line 175 of file SIInstrInfo.cpp.
References assert(), get, llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().
◆ areMemAccessesTriviallyDisjoint()
|
override |
Definition at line 3154 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), and llvm::MachineInstr::mayLoadOrStore().
◆ buildExtractSubReg()
| unsigned SIInstrInfo::buildExtractSubReg | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC | ||
| ) | const |
Definition at line 4859 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), MBB, MI, MRI, and SubReg.
Referenced by buildExtractSubRegOrImm().
◆ buildExtractSubRegOrImm()
| MachineOperand SIInstrInfo::buildExtractSubRegOrImm | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC | ||
| ) | const |
Definition at line 4891 of file SIInstrInfo.cpp.
References buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm_unreachable, MRI, and SubReg.
◆ buildShrunkInst()
| MachineInstr * SIInstrInfo::buildShrunkInst | ( | MachineInstr & | MI, |
| unsigned | NewOpcode | ||
| ) | const |
Definition at line 3842 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), copyFlagsToImplicitVCC(), fixImplicitOperands(), get, getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), MBB, MI, and llvm::MachineInstrBuilder::setMIFlags().
◆ canInsertSelect()
|
override |
Definition at line 2715 of file SIInstrInfo.cpp.
References Cond, llvm::TargetRegisterClass::getID(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::SIRegisterInfo::isSGPRClass(), MBB, and MRI.
◆ canShrink()
| bool SIInstrInfo::canShrink | ( | const MachineInstr & | MI, |
| const MachineRegisterInfo & | MRI | ||
| ) | const |
Definition at line 3773 of file SIInstrInfo.cpp.
References llvm::misexpect::clamp(), getNamedOperand(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isVGPR(), MI, and MRI.
◆ commuteInstructionImpl()
|
overrideprotected |
Definition at line 2276 of file SIInstrInfo.cpp.
References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), get, llvm::AMDGPU::getNamedOperandIdx(), isOperandLegal(), llvm::MachineOperand::isReg(), MI, llvm::MachineInstr::setDesc(), swapRegAndNonRegOperand(), and swapSourceModifiers().
◆ commuteOpcode() [1/2]
|
inline |
Definition at line 266 of file SIInstrInfo.h.
References commuteOpcode(), and MI.
◆ commuteOpcode() [2/2]
| int SIInstrInfo::commuteOpcode | ( | unsigned | Opc | ) | const |
Definition at line 1038 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().
Referenced by commuteInstructionImpl(), commuteOpcode(), and legalizeOperandsVOP2().
◆ convertNonUniformIfRegion()
| void SIInstrInfo::convertNonUniformIfRegion | ( | MachineBasicBlock * | IfEntry, |
| MachineBasicBlock * | IfEnd | ||
| ) | const |
Definition at line 7526 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCID::Branch, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineBasicBlock::insert(), and MRI.
◆ convertNonUniformLoopRegion()
| void SIInstrInfo::convertNonUniformLoopRegion | ( | MachineBasicBlock * | LoopEntry, |
| MachineBasicBlock * | LoopEnd | ||
| ) | const |
Definition at line 7551 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::MCID::Branch, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineBasicBlock::insert(), materializeImmediate(), MRI, and llvm::MachineBasicBlock::predecessors().
◆ convertToThreeAddress()
|
override |
Definition at line 3239 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::BuildMI(), llvm::misexpect::clamp(), DefMI, E, get, llvm::GCNSubtarget::getConstantBusLimit(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), I, llvm::RISCVMatInt::Imm, llvm::MachineOperand::isImm(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), isWMMA(), llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(), MBB, MI, MRI, pseudoToMCOpcode(), llvm::MachineInstr::removeOperand(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::MachineInstr::setDesc(), llvm::MachineInstrBuilder::setMIFlags(), and updateLiveVariables().
◆ copyPhysReg()
|
override |
Definition at line 707 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), Builder, llvm::BuildMI(), contains(), llvm::RegState::Define, DL, expandSGPRCopy(), Fix16BitCopies, get, llvm::SIRegisterInfo::get32BitRegister(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::getVGPR64Class(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::GCNSubtarget::hasScalarCompareEq64(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RegState::Implicit, indirectCopyToAGPR(), llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::SIRegisterInfo::isSGPRClass(), lo16(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, reportIllegalCopy(), llvm::AMDGPU::CPol::SCC, llvm::ArrayRef< T >::size(), llvm::MachineInstr::tieOperands(), llvm::RegState::Undef, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.
◆ createPHIDestinationCopy()
|
override |
Definition at line 8126 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), DL, llvm::MachineBasicBlock::end(), get, and MBB.
◆ createPHISourceCopy()
|
override |
Definition at line 8141 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), DL, llvm::MachineBasicBlock::end(), get, llvm::RegState::Implicit, llvm::GCNSubtarget::isWave32(), and MBB.
◆ CreateTargetMIHazardRecognizer()
|
override |
Definition at line 7624 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
override |
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
The post-RA version of misched uses CreateTargetMIHazardRecognizer.
Definition at line 7609 of file SIInstrInfo.cpp.
References llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
override |
This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.
Definition at line 7617 of file SIInstrInfo.cpp.
◆ decomposeMachineOperandsTargetFlags()
|
override |
Definition at line 7636 of file SIInstrInfo.cpp.
References MO_MASK.
◆ enforceOperandRCAlignment()
| void SIInstrInfo::enforceOperandRCAlignment | ( | MachineInstr & | MI, |
| unsigned | OpName | ||
| ) | const |
Definition at line 8445 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), BB, llvm::BuildMI(), llvm::MachineOperand::CreateReg(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::AMDGPU::getNamedOperandIdx(), getOpSize(), llvm::SIRegisterInfo::isAGPR(), MI, MRI, llvm::GCNSubtarget::needsAlignedVGPRs(), and llvm::RegState::Undef.
◆ expandMovDPP64()
| std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 | ( | MachineInstr & | MI | ) | const |
Definition at line 2163 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::findDebugLoc(), get, llvm::SrcOp::getImm(), getNamedOperand(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::hasMovB64(), I, llvm::RISCVMatInt::Imm, llvm::AMDGPU::isLegal64BitDPPControl(), llvm::MachineRegisterInfo::isSSA(), MBB, MI, MRI, and llvm::RegState::Undef.
Referenced by expandPostRAPseudo().
◆ expandPostRAPseudo()
|
override |
Definition at line 1778 of file SIInstrInfo.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), get, llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RISCVMatInt::Imm, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isAGPR(), isInlineConstant(), isLiteralConstant(), llvm::isUInt< 32 >(), llvm::GCNSubtarget::isWave32(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::AMDGPU::CPol::SCC, llvm::MachineOperand::setIsUndef(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, SubReg, llvm::MachineInstr::tieOperands(), TRI, llvm::RegState::Undef, and llvm::GCNSubtarget::useVGPRIndexMode().
◆ findCommutedOpIndices() [1/2]
|
override |
Definition at line 2328 of file SIInstrInfo.cpp.
References MI.
◆ findCommutedOpIndices() [2/2]
| bool SIInstrInfo::findCommutedOpIndices | ( | MCInstrDesc | Desc, |
| unsigned & | SrcOpIdx0, | ||
| unsigned & | SrcOpIdx1 | ||
| ) | const |
Definition at line 2334 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), and llvm::MCInstrDesc::isCommutable().
◆ fixImplicitOperands()
| void SIInstrInfo::fixImplicitOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 7728 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::isWave32(), and MI.
Referenced by buildShrunkInst(), insertBranch(), insertSelect(), legalizeOperandsVOP2(), and moveToVALU().
◆ FoldImmediate()
|
final |
Definition at line 2894 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToImmediate(), llvm::tgtok::Def, DefMI, get, llvm::SIRegisterInfo::get32BitRegister(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getOpSize(), llvm::MachineInstr::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), hasAnyModifiersSet(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineRegisterInfo::hasOneUse(), llvm::RISCVMatInt::Imm, llvm::SIRegisterInfo::isAGPR(), llvm::MachineOperand::isImm(), isInlineConstant(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVGPR(), isVGPRCopy(), llvm::Register::isVirtual(), legalizeOperands(), lo16(), MRI, pseudoToMCOpcode(), removeModOperands(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MachineRegisterInfo::use_nodbg_empty(), and UseMI.
Referenced by legalizeGenericOperand().
◆ foldMemoryOperandImpl()
|
override |
Definition at line 8163 of file SIInstrInfo.cpp.
References llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtual(), MI, and MRI.
◆ getAddNoCarry() [1/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg | ||
| ) | const |
Return a partially built integer add instruction without carry.
Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.
Definition at line 7671 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, MBB, MRI, and llvm::MachineRegisterInfo::setRegAllocationHint().
◆ getAddNoCarry() [2/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg, | ||
| RegScavenger & | RS | ||
| ) | const |
Definition at line 7686 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, llvm::RegScavenger::isRegUsed(), llvm::Register::isValid(), MBB, and llvm::RegScavenger::scavengeRegister().
◆ getBranchDestBlock()
|
override |
Definition at line 2367 of file SIInstrInfo.cpp.
References MI.
◆ getClampMask()
|
inline |
Definition at line 754 of file SIInstrInfo.h.
References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::SIInstrFlags::IntClamp, and MI.
◆ getDefaultRsrcDataFormat()
| uint64_t SIInstrInfo::getDefaultRsrcDataFormat | ( | ) | const |
Definition at line 7326 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::getGeneration(), llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX11, llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getScratchRsrcWords23().
◆ getDSShaderTypeValue()
|
static |
Definition at line 8217 of file SIInstrInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::report_fatal_error().
◆ getIndirectGPRIDXPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo | ( | unsigned | VecSize, |
| bool | IsIndirectSrc | ||
| ) | const |
Definition at line 1284 of file SIInstrInfo.cpp.
References get, llvm_unreachable, and llvm::ARMII::VecSize.
◆ getIndirectRegWriteMovRelPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo | ( | unsigned | VecSize, |
| unsigned | EltSize, | ||
| bool | IsSGPR | ||
| ) | const |
Definition at line 1385 of file SIInstrInfo.cpp.
References assert(), get, getIndirectSGPRWriteMovRelPseudo32(), getIndirectSGPRWriteMovRelPseudo64(), getIndirectVGPRWriteMovRelPseudoOpc(), llvm_unreachable, and llvm::ARMII::VecSize.
◆ getInstBundleSize()
| unsigned SIInstrInfo::getInstBundleSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 7435 of file SIInstrInfo.cpp.
References assert(), E, getInstSizeInBytes(), I, and MI.
Referenced by getInstSizeInBytes().
◆ getInstrLatency()
|
override |
Definition at line 8200 of file SIInstrInfo.cpp.
References E, I, llvm::max(), and MI.
Referenced by llvm::GCNSubtarget::adjustSchedDependency().
◆ getInstSizeInBytes()
|
override |
Definition at line 7447 of file SIInstrInfo.cpp.
References E, getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getTarget(), llvm::GCNSubtarget::hasOffset3fBug(), I, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, isDPP(), isFixedSize(), isLiteralConstantLike(), isMIMG(), isSALU(), isVALU(), MI, and llvm::MCInstrDesc::OpInfo.
Referenced by getInstBundleSize(), and removeBranch().
◆ getKillTerminatorFromPseudo()
| const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo | ( | unsigned | Opcode | ) | const |
Definition at line 7717 of file SIInstrInfo.cpp.
References get, and llvm_unreachable.
◆ getMachineCSELookAheadLimit()
|
inlineoverride |
Definition at line 343 of file SIInstrInfo.h.
◆ getMCOpcodeFromPseudo()
|
inline |
Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.
Definition at line 1047 of file SIInstrInfo.h.
References get, and pseudoToMCOpcode().
Referenced by getInstSizeInBytes().
◆ getMemOperandsWithOffsetWidth()
|
final |
Definition at line 290 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::TargetRegisterInfo::getRegSizeInBits(), I, isDS(), llvm::MachineOperand::isFI(), isFLAT(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::mayStore(), and TRI.
◆ getMIRFormatter()
|
inlineoverride |
Definition at line 1171 of file SIInstrInfo.h.
◆ getMovOpcode()
| unsigned SIInstrInfo::getMovOpcode | ( | const TargetRegisterClass * | DstRC | ) | const |
Definition at line 1269 of file SIInstrInfo.cpp.
References llvm::SIRegisterInfo::isAGPRClass(), and llvm::SIRegisterInfo::isSGPRClass().
◆ getNamedImmOperand()
|
inline |
Get required immediate operand.
Definition at line 1034 of file SIInstrInfo.h.
References llvm::AMDGPU::getNamedOperandIdx(), and MI.
◆ getNamedOperand() [1/2]
|
inline |
Definition at line 1028 of file SIInstrInfo.h.
References getNamedOperand(), and MI.
◆ getNamedOperand() [2/2]
| MachineOperand * SIInstrInfo::getNamedOperand | ( | MachineInstr & | MI, |
| unsigned | OperandName | ||
| ) | const |
Returns the operand named Op.
If MI does not have an operand named Op, this function returns nullptr.
Definition at line 7317 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), and MI.
Referenced by buildShrunkInst(), canShrink(), convertToThreeAddress(), expandMovDPP64(), FoldImmediate(), getMemOperandsWithOffsetWidth(), getNamedOperand(), hasModifiersSet(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), swapSourceModifiers(), and verifyInstruction().
◆ getNumWaitStates()
|
static |
Return the number of wait states that result from executing this instruction.
Definition at line 1764 of file SIInstrInfo.cpp.
References MI.
Referenced by llvm::GCNHazardRecognizer::AdvanceCycle().
◆ getOpRegClass()
| const TargetRegisterClass * SIInstrInfo::getOpRegClass | ( | const MachineInstr & | MI, |
| unsigned | OpNo | ||
| ) | const |
Return the correct register class for OpNo.
For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.
Definition at line 4815 of file SIInstrInfo.cpp.
References adjustAllocatableRegClass(), get, llvm::MCInstrDesc::getNumOperands(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), MI, MRI, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), and verifyInstruction().
◆ getOpSize() [1/2]
|
inline |
This form should usually be preferred since it handles operands with unknown register classes.
Definition at line 932 of file SIInstrInfo.h.
References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), MI, and SubReg.
◆ getOpSize() [2/2]
|
inline |
Return the size in bytes of the operand OpNo on the given.
Definition at line 918 of file SIInstrInfo.h.
References assert(), get, llvm::SIRegisterInfo::getRegClass(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by enforceOperandRCAlignment(), FoldImmediate(), getMemOperandsWithOffsetWidth(), and isInlineConstant().
◆ getPreferredSelectRegClass()
| const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass | ( | unsigned | Size | ) | const |
Definition at line 1113 of file SIInstrInfo.cpp.
◆ getRegClass()
|
override |
Definition at line 4784 of file SIInstrInfo.cpp.
References adjustAllocatableRegClass(), llvm::SIInstrFlags::DS, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineFunction::getRegInfo(), llvm::MCInstrDesc::Opcode, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and llvm::MCInstrDesc::TSFlags.
◆ getRegisterInfo()
|
inline |
Definition at line 179 of file SIInstrInfo.h.
Referenced by llvm::GCNSubtarget::getRegisterInfo().
◆ getSchedModel()
|
inline |
Definition at line 1179 of file SIInstrInfo.h.
Referenced by llvm::GCNSubtarget::adjustSchedDependency().
◆ getScratchRsrcWords23()
| uint64_t SIInstrInfo::getScratchRsrcWords23 | ( | ) | const |
Definition at line 7351 of file SIInstrInfo.cpp.
References getDefaultRsrcDataFormat(), llvm::GCNSubtarget::getGeneration(), llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 7641 of file SIInstrInfo.cpp.
References llvm::makeArrayRef(), MO_ABS32_HI, MO_ABS32_LO, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_REL32_HI, and MO_REL32_LO.
◆ getSerializableMachineMemOperandTargetFlags()
|
override |
Definition at line 7656 of file SIInstrInfo.cpp.
References llvm::makeArrayRef(), and llvm::MONoClobber.
◆ getSerializableTargetIndices()
|
override |
Definition at line 7596 of file SIInstrInfo.cpp.
References llvm::makeArrayRef(), llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.
◆ getSubtarget()
|
inline |
Definition at line 183 of file SIInstrInfo.h.
◆ getVALUOp()
| unsigned SIInstrInfo::getVALUOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 4667 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::hasAddNoCarry(), llvm::GCNSubtarget::hasDLInsts(), llvm::SIRegisterInfo::isAGPR(), llvm_unreachable, MI, MRI, and llvm::SIInstrFlags::WQM.
Referenced by moveToVALU().
◆ hasAnyModifiersSet()
| bool SIInstrInfo::hasAnyModifiersSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 3768 of file SIInstrInfo.cpp.
References llvm::any_of(), hasModifiersSet(), MI, and ModifierOpNames.
Referenced by FoldImmediate().
◆ hasFPClamp() [1/2]
|
inlinestatic |
Definition at line 742 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and MI.
◆ hasFPClamp() [2/2]
|
inline |
Definition at line 746 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPClamp, and get.
◆ hasIntClamp()
|
inlinestatic |
Definition at line 750 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IntClamp, and MI.
◆ hasModifiers()
| bool SIInstrInfo::hasModifiers | ( | unsigned | Opcode | ) | const |
Return true if this instruction has any modifiers.
e.g. src[012]_mod, omod, clamp.
Definition at line 3754 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
◆ hasModifiersSet()
| bool SIInstrInfo::hasModifiersSet | ( | const MachineInstr & | MI, |
| unsigned | OpName | ||
| ) | const |
Definition at line 3762 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.
Referenced by canShrink(), and hasAnyModifiersSet().
◆ hasUnwantedEffectsWhenEXECEmpty()
| bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty | ( | const MachineInstr & | MI | ) | const |
Whether we must prevent this instruction from executing with EXEC = 0.
Definition at line 3509 of file SIInstrInfo.cpp.
References llvm::AMDGPUISD::DS_ORDERED_COUNT, isEXP(), isSMRD(), MI, and modifiesModeRegister().
◆ hasVALU32BitEncoding()
| bool SIInstrInfo::hasVALU32BitEncoding | ( | unsigned | Opcode | ) | const |
Return true if this 64-bit VALU instruction has a 32-bit encoding.
This function will return false if you pass it a 32-bit instruction.
Definition at line 3742 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getVOPe32(), llvm::GCNSubtarget::hasGFX90AInsts(), and pseudoToMCOpcode().
Referenced by canShrink().
◆ hasVGPRUses()
|
inline |
Definition at line 786 of file SIInstrInfo.h.
References llvm::any_of(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ insertBranch()
|
override |
Definition at line 2641 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), get, llvm::MachineInstr::getOperand(), llvm::GCNSubtarget::hasOffset3fBug(), isImm(), isUndef(), MBB, preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setIsUndef().
◆ insertEQ()
| Register SIInstrInfo::insertEQ | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value | ||
| ) | const |
Definition at line 1243 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.
◆ insertIndirectBranch()
|
override |
Definition at line 2378 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MCConstantExpr::create(), llvm::MCSymbolRefExpr::create(), llvm::MCBinaryExpr::createAnd(), llvm::MCBinaryExpr::createAShr(), llvm::MCBinaryExpr::createSub(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), get, llvm::MachineFunction::getContext(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::getSymbol(), I, llvm::BitmaskEnumDetail::Mask(), MBB, MO_FAR_BRANCH_OFFSET, MRI, llvm::MachineBasicBlock::pred_size(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setPostInstrSymbol(), llvm::RegScavenger::setRegUsed(), llvm::MCSymbol::setVariableValue(), and TRI.
◆ insertNE()
| Register SIInstrInfo::insertNE | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | SrcReg, | ||
| int | Value | ||
| ) | const |
Definition at line 1256 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.
◆ insertNoop()
|
override |
Definition at line 1730 of file SIInstrInfo.cpp.
References insertNoops(), MBB, and MI.
◆ insertNoops()
|
override |
Definition at line 1735 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), Arg, llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), get, MBB, MI, and llvm::min().
Referenced by insertNoop().
◆ insertReturn()
| void SIInstrInfo::insertReturn | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 1746 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), get, llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), Info, MBB, and llvm::MachineBasicBlock::succ_empty().
◆ insertSelect()
|
override |
Definition at line 2757 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), Cond, llvm::MachineRegisterInfo::createVirtualRegister(), DL, fixImplicitOperands(), get, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), I, MBB, MRI, preserveCondRegFlags(), llvm::MCID::Select, and std::swap().
◆ insertVectorSelect()
| void SIInstrInfo::insertVectorSelect | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DstReg, | ||
| ArrayRef< MachineOperand > | Cond, | ||
| Register | TrueReg, | ||
| Register | FalseReg | ||
| ) | const |
Definition at line 1117 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), I, isImm(), llvm::GCNSubtarget::isWave32(), llvm_unreachable, MBB, MRI, and llvm::MachineOperand::setImplicit().
◆ isAlwaysGDS()
| bool SIInstrInfo::isAlwaysGDS | ( | uint16_t | Opcode | ) | const |
Definition at line 3485 of file SIInstrInfo.cpp.
References llvm::AMDGPUISD::DS_ORDERED_COUNT.
◆ isAsmOnlyOpcode()
| bool SIInstrInfo::isAsmOnlyOpcode | ( | int | MCOp | ) | const |
Check if this instruction should only be used by assembler.
Return true if this opcode should not be used by codegen.
Definition at line 7875 of file SIInstrInfo.cpp.
Referenced by pseudoToMCOpcode().
◆ isAtomic() [1/2]
|
inlinestatic |
Definition at line 585 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, and MI.
Referenced by isValidClauseInst().
◆ isAtomic() [2/2]
|
inline |
Definition at line 590 of file SIInstrInfo.h.
References get, llvm::SIInstrFlags::IsAtomicNoRet, and llvm::SIInstrFlags::IsAtomicRet.
◆ isAtomicNoRet() [1/2]
|
inlinestatic |
Definition at line 569 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicNoRet, and MI.
◆ isAtomicNoRet() [2/2]
|
inline |
Definition at line 573 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsAtomicNoRet.
◆ isAtomicRet() [1/2]
|
inlinestatic |
Definition at line 577 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsAtomicRet, and MI.
◆ isAtomicRet() [2/2]
|
inline |
Definition at line 581 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsAtomicRet.
◆ isBasicBlockPrologue()
|
override |
Definition at line 7665 of file SIInstrInfo.cpp.
References MI.
◆ isBranchOffsetInRange()
|
override |
Definition at line 2351 of file SIInstrInfo.cpp.
References assert(), BranchOffsetBits, and llvm::isIntN().
◆ isBufferSMRD()
| bool SIInstrInfo::isBufferSMRD | ( | const MachineInstr & | MI | ) | const |
Definition at line 7738 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), llvm::SIRegisterInfo::getRegClass(), llvm::TargetRegisterClass::hasSubClassEq(), isSMRD(), and MI.
◆ isDisableWQM() [1/2]
|
inlinestatic |
Definition at line 603 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and MI.
◆ isDisableWQM() [2/2]
|
inline |
Definition at line 607 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DisableWQM, and get.
◆ isDOT() [1/2]
|
inlinestatic |
Definition at line 672 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsDOT, and MI.
◆ isDOT() [2/2]
|
inline |
Definition at line 684 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsDOT.
◆ isDPP() [1/2]
|
inlinestatic |
Definition at line 627 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isDPP() [2/2]
|
inline |
Definition at line 631 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DPP, and get.
◆ isDS() [1/2]
|
inlinestatic |
Definition at line 490 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isOperandLegal(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldRunLdsBranchVmemWARHazardFixup(), and verifyInstruction().
◆ isDS() [2/2]
|
inline |
Definition at line 494 of file SIInstrInfo.h.
References llvm::SIInstrFlags::DS, and get.
◆ isDualSourceBlendEXP()
|
inlinestatic |
Definition at line 557 of file SIInstrInfo.h.
References llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0, llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1, isEXP(), and MI.
◆ isEXP() [1/2]
|
inlinestatic |
Definition at line 553 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), hasUnwantedEffectsWhenEXECEmpty(), isDualSourceBlendEXP(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isEXP() [2/2]
|
inline |
Definition at line 565 of file SIInstrInfo.h.
References llvm::SIInstrFlags::EXP, and get.
◆ isFixedSize() [1/2]
|
inlinestatic |
Definition at line 734 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and MI.
Referenced by getInstSizeInBytes().
◆ isFixedSize() [2/2]
|
inline |
Definition at line 738 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FIXED_SIZE, and get.
◆ isFLAT() [1/2]
|
inlinestatic |
Definition at line 516 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isLdsDma(), isVMEMClauseInst(), legalizeOperands(), mayAccessFlatAddressSpace(), mayWriteLDSThroughDMA(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and verifyInstruction().
◆ isFLAT() [2/2]
|
inline |
Definition at line 549 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FLAT, and get.
◆ isFLATGlobal() [1/2]
|
inlinestatic |
Definition at line 532 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and MI.
◆ isFLATGlobal() [2/2]
|
inline |
Definition at line 536 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, and get.
◆ isFLATScratch() [1/2]
|
inlinestatic |
Definition at line 540 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isFLATScratch() [2/2]
|
inline |
Definition at line 544 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatScratch, and get.
◆ isFoldableCopy()
|
static |
◆ isFPAtomic() [1/2]
|
inlinestatic |
Definition at line 770 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and MI.
◆ isFPAtomic() [2/2]
|
inline |
Definition at line 774 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPAtomic, and get.
◆ isGather4() [1/2]
|
inlinestatic |
Definition at line 508 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and MI.
Referenced by verifyInstruction().
◆ isGather4() [2/2]
|
inline |
Definition at line 512 of file SIInstrInfo.h.
References llvm::SIInstrFlags::Gather4, and get.
◆ isHighLatencyDef()
|
override |
Definition at line 7381 of file SIInstrInfo.cpp.
References get, isFLAT(), isMIMG(), isMTBUF(), and isMUBUF().
Referenced by llvm::SIScheduleDAGMI::schedule().
◆ isIgnorableUse()
|
override |
Definition at line 169 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), isVALU(), and resultDependsOnExec().
◆ isImmOperandLegal()
| bool SIInstrInfo::isImmOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpNo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Definition at line 3712 of file SIInstrInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isInlineConstant(), isMAI(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVOP3(), MI, llvm::SIRegisterInfo::opCanUseInlineConstant(), llvm::SIRegisterInfo::opCanUseLiteralConstant(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by isOperandLegal().
◆ isInlineConstant() [1/8]
Definition at line 806 of file SIInstrInfo.h.
References llvm::RISCVMatInt::Imm, and isInlineConstant().
◆ isInlineConstant() [2/8]
Definition at line 3575 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::RISCVMatInt::Imm, llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), and llvm_unreachable.
Referenced by convertToThreeAddress(), expandPostRAPseudo(), FoldImmediate(), isImmOperandLegal(), isInlineConstant(), isLiteralConstant(), isLiteralConstantLike(), usesConstantBus(), and verifyInstruction().
◆ isInlineConstant() [3/8]
|
inline |
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition at line 819 of file SIInstrInfo.h.
References assert(), llvm::MachineOperand::getParent(), isInlineConstant(), and MI.
◆ isInlineConstant() [4/8]
|
inline |
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition at line 833 of file SIInstrInfo.h.
References isInlineConstant(), and MI.
◆ isInlineConstant() [5/8]
|
inline |
Definition at line 838 of file SIInstrInfo.h.
References assert(), getOpSize(), isInlineConstant(), MI, llvm::AMDGPU::OPERAND_REG_IMM_INT32, and llvm::AMDGPU::OPERAND_REG_IMM_INT64.
◆ isInlineConstant() [6/8]
|
inline |
Definition at line 855 of file SIInstrInfo.h.
References llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().
◆ isInlineConstant() [7/8]
|
inline |
Definition at line 812 of file SIInstrInfo.h.
References isInlineConstant(), and llvm::MCOperandInfo::OperandType.
◆ isInlineConstant() [8/8]
| bool SIInstrInfo::isInlineConstant | ( | const MachineOperand & | MO, |
| uint8_t | OperandType | ||
| ) | const |
Definition at line 3595 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::RISCVMatInt::Imm, llvm::MachineOperand::isImm(), llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableIntLiteralV216(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralV216(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), llvm_unreachable, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.
◆ isKillTerminator()
|
static |
Definition at line 7707 of file SIInstrInfo.cpp.
◆ isLDSDIR() [1/2]
|
inlinestatic |
Definition at line 688 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LDSDIR, and MI.
◆ isLDSDIR() [2/2]
|
inline |
Definition at line 692 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::LDSDIR.
◆ isLegalFLATOffset()
| bool SIInstrInfo::isLegalFLATOffset | ( | int64_t | Offset, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant | ||
| ) | const |
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
If Signed, this is for an instruction that interprets the offset as signed.
Definition at line 7781 of file SIInstrInfo.cpp.
References llvm::SIInstrFlags::FLAT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasFlatSegmentOffsetBug(), llvm::GCNSubtarget::hasNegativeScratchOffsetBug(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), llvm::isIntN(), llvm::isUIntN(), N, and Signed.
Referenced by llvm::SITargetLowering::isLegalGlobalAddressingMode(), and splitFlatOffset().
◆ isLegalMUBUFImmOffset()
|
inlinestatic |
Definition at line 1128 of file SIInstrInfo.h.
References llvm::RISCVMatInt::Imm.
Referenced by llvm::SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::isFrameOffsetLegal(), llvm::SIRegisterInfo::needsFrameBaseReg(), and llvm::SIRegisterInfo::resolveFrameIndex().
◆ isLegalRegOperand()
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Check if MO (a register operand) is a legal register for the given operand description.
Definition at line 4920 of file SIInstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::SIRegisterInfo::getLargestLegalSuperClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::MachineOperand::isReg(), MRI, and llvm::MCOperandInfo::RegClass.
Referenced by isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().
◆ isLegalVSrcOperand()
| bool SIInstrInfo::isLegalVSrcOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO | ||
| ) | const |
Check if MO would be a valid operand for the given operand definition OpInfo.
Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).
Definition at line 4947 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), and MRI.
◆ isLiteralConstant() [1/2]
|
inline |
Definition at line 865 of file SIInstrInfo.h.
References llvm::MachineOperand::isImm(), isInlineConstant(), and MI.
◆ isLiteralConstant() [2/2]
|
inline |
Definition at line 860 of file SIInstrInfo.h.
References llvm::MachineOperand::isImm(), isInlineConstant(), and llvm::MCOperandInfo::OperandType.
Referenced by expandPostRAPseudo().
◆ isLiteralConstantLike()
| bool SIInstrInfo::isLiteralConstantLike | ( | const MachineOperand & | MO, |
| const MCOperandInfo & | OpInfo | ||
| ) | const |
Definition at line 3679 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getType(), isInlineConstant(), llvm_unreachable, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_FrameIndex, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_Immediate, llvm::MachineOperand::MO_MachineBasicBlock, llvm::MachineOperand::MO_MCSymbol, and llvm::MachineOperand::MO_Register.
Referenced by getInstSizeInBytes(), isOperandLegal(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().
◆ isLoadFromStackSlot()
|
override |
Definition at line 7407 of file SIInstrInfo.cpp.
References llvm::ISD::FrameIndex, isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.
◆ isLowLatencyInstruction()
| bool SIInstrInfo::isLowLatencyInstruction | ( | const MachineInstr & | MI | ) | const |
Definition at line 7375 of file SIInstrInfo.cpp.
Referenced by llvm::SIScheduleDAGMI::schedule().
◆ isMAI() [1/2]
|
inlinestatic |
Definition at line 659 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsMAI, and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), isImmOperandLegal(), isMFMA(), isXDL(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and pseudoToMCOpcode().
◆ isMAI() [2/2]
|
inline |
Definition at line 663 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsMAI.
◆ isMFMA()
|
inlinestatic |
Definition at line 667 of file SIInstrInfo.h.
Referenced by llvm::GCNHazardRecognizer::ShouldPreferAnother().
◆ isMIMG() [1/2]
|
inlinestatic |
Definition at line 500 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MIMG.
Referenced by getInstSizeInBytes(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isOperandLegal(), isVMEM(), legalizeOperands(), and verifyInstruction().
◆ isMIMG() [2/2]
|
inline |
Definition at line 504 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::MIMG.
◆ isMTBUF() [1/2]
|
inlinestatic |
Definition at line 472 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MTBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isVMEM(), and legalizeOperands().
◆ isMTBUF() [2/2]
|
inline |
Definition at line 476 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::MTBUF.
◆ isMUBUF() [1/2]
|
inlinestatic |
Definition at line 464 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::MUBUF.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyDef(), isLdsDma(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), legalizeOperands(), mayWriteLDSThroughDMA(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isMUBUF() [2/2]
|
inline |
Definition at line 468 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::MUBUF.
◆ isNonUniformBranchInstr()
| bool SIInstrInfo::isNonUniformBranchInstr | ( | MachineInstr & | Instr | ) | const |
Definition at line 7522 of file SIInstrInfo.cpp.
References llvm::MCID::Branch.
◆ isOperandLegal()
| bool SIInstrInfo::isOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand * | MO = nullptr |
||
| ) | const |
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition at line 4958 of file SIInstrInfo.cpp.
References assert(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::count(), llvm::numbers::e, llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), llvm::GCNSubtarget::hasVOP3Literal(), i, llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert(), llvm::SIRegisterInfo::isAGPR(), isDS(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLegalRegOperand(), isLiteralConstantLike(), isMIMG(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVALU(), isVOP3(), MI, MRI, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, llvm::MachineRegisterInfo::reservedRegsFrozen(), and usesConstantBus().
Referenced by commuteInstructionImpl(), convertToThreeAddress(), and legalizeOperandsVOP3().
◆ isPacked() [1/2]
|
inlinestatic |
Definition at line 416 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsPacked, and MI.
◆ isPacked() [2/2]
|
inline |
Definition at line 420 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsPacked.
◆ isReallyTriviallyReMaterializable()
|
override |
◆ isSALU() [1/2]
|
inlinestatic |
Definition at line 352 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SALU.
Referenced by getInstSizeInBytes(), isReallyTriviallyReMaterializable(), mayReadEXEC(), and shouldReadExec().
◆ isSALU() [2/2]
|
inline |
Definition at line 356 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SALU.
◆ isScalarStore() [1/2]
|
inlinestatic |
- Returns
- true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.
Definition at line 726 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarStore() [2/2]
|
inline |
Definition at line 730 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SCALAR_STORE.
◆ isScalarUnit()
|
inlinestatic |
Definition at line 704 of file SIInstrInfo.h.
References MI, llvm::SIInstrFlags::SALU, and llvm::SIInstrFlags::SMRD.
◆ isSchedulingBoundary()
|
override |
Definition at line 3455 of file SIInstrInfo.cpp.
References changesVGPRIndexingMode(), llvm::ISD::INLINEASM_BR, and MI.
◆ isSDWA() [1/2]
|
inlinestatic |
Definition at line 448 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SDWA.
Referenced by isReallyTriviallyReMaterializable(), and verifyInstruction().
◆ isSDWA() [2/2]
|
inline |
Definition at line 452 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SDWA.
◆ isSegmentSpecificFLAT() [1/2]
|
inlinestatic |
Definition at line 522 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and MI.
Referenced by areMemAccessesTriviallyDisjoint(), legalizeOperandsFLAT(), moveFlatAddrToVGPR(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isSegmentSpecificFLAT() [2/2]
|
inline |
Definition at line 527 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and get.
◆ isSGPRSpill() [1/2]
|
inlinestatic |
Definition at line 619 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SGPRSpill.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSGPRSpill() [2/2]
|
inline |
Definition at line 623 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SGPRSpill.
◆ isSGPRStackAccess()
| unsigned SIInstrInfo::isSGPRStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 7399 of file SIInstrInfo.cpp.
References Addr, assert(), llvm::ISD::FrameIndex, getNamedOperand(), llvm::MachineOperand::getReg(), and MI.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSMRD() [1/2]
|
inlinestatic |
Definition at line 480 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SMRD.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), breaksSMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isSMRD() [2/2]
|
inline |
Definition at line 484 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SMRD.
◆ isSOP1() [1/2]
|
inlinestatic |
Definition at line 376 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP1.
◆ isSOP1() [2/2]
|
inline |
Definition at line 380 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOP1.
◆ isSOP2() [1/2]
|
inlinestatic |
Definition at line 384 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOP2.
Referenced by verifyInstruction().
◆ isSOP2() [2/2]
|
inline |
Definition at line 388 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOP2.
◆ isSOPC() [1/2]
|
inlinestatic |
Definition at line 392 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPC.
Referenced by verifyInstruction().
◆ isSOPC() [2/2]
|
inline |
Definition at line 396 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOPC.
◆ isSOPK() [1/2]
|
inlinestatic |
Definition at line 400 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPK.
Referenced by verifyInstruction().
◆ isSOPK() [2/2]
|
inline |
Definition at line 404 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOPK.
◆ isSOPP() [1/2]
|
inlinestatic |
Definition at line 408 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPP.
◆ isSOPP() [2/2]
|
inline |
Definition at line 412 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOPP.
◆ isStackAccess()
| unsigned SIInstrInfo::isStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex | ||
| ) | const |
Definition at line 7386 of file SIInstrInfo.cpp.
References Addr, assert(), llvm::ISD::FrameIndex, getNamedOperand(), llvm::MachineOperand::getReg(), MI, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isStoreToStackSlot()
|
override |
Definition at line 7421 of file SIInstrInfo.cpp.
References llvm::ISD::FrameIndex, isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.
◆ isTRANS() [1/2]
|
inlinestatic |
Definition at line 635 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TRANS.
◆ isTRANS() [2/2]
|
inline |
Definition at line 639 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::TRANS.
◆ isVALU() [1/2]
|
inlinestatic |
Definition at line 360 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VALU.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isIgnorableUse(), isLdsDma(), isOperandLegal(), mayWriteLDSThroughDMA(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isVALU() [2/2]
|
inline |
Definition at line 364 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VALU.
◆ isVGPRCopy()
|
inline |
Definition at line 778 of file SIInstrInfo.h.
References assert(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isSGPRReg(), MI, and MRI.
Referenced by FoldImmediate().
◆ isVGPRSpill() [1/2]
|
inlinestatic |
Definition at line 611 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VGPRSpill.
Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().
◆ isVGPRSpill() [2/2]
|
inline |
Definition at line 615 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VGPRSpill.
◆ isVINTERP() [1/2]
|
inlinestatic |
Definition at line 696 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTERP.
◆ isVINTERP() [2/2]
|
inline |
Definition at line 700 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VINTERP.
◆ isVINTRP() [1/2]
|
inlinestatic |
Definition at line 651 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VINTRP.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isVINTRP() [2/2]
|
inline |
Definition at line 655 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VINTRP.
◆ isVMEM() [1/2]
|
inlinestatic |
Definition at line 368 of file SIInstrInfo.h.
References isMIMG(), isMTBUF(), isMUBUF(), and MI.
Referenced by breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), isVMEMClauseInst(), isVMEMLoad(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isVMEM() [2/2]
|
inline |
Definition at line 372 of file SIInstrInfo.h.
◆ isVOP1() [1/2]
|
inlinestatic |
Definition at line 424 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP1.
Referenced by isReallyTriviallyReMaterializable().
◆ isVOP1() [2/2]
|
inline |
Definition at line 428 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VOP1.
◆ isVOP2() [1/2]
|
inlinestatic |
Definition at line 432 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP2.
Referenced by isReallyTriviallyReMaterializable(), legalizeOperands(), and verifyInstruction().
◆ isVOP2() [2/2]
|
inline |
Definition at line 436 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VOP2.
◆ isVOP3() [1/2]
|
inlinestatic |
Definition at line 440 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP3.
Referenced by isImmOperandLegal(), isOperandLegal(), isReallyTriviallyReMaterializable(), legalizeOperands(), and verifyInstruction().
◆ isVOP3() [2/2]
|
inline |
Definition at line 444 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VOP3.
◆ isVOP3P() [1/2]
|
inlinestatic |
Definition at line 643 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOP3P.
◆ isVOP3P() [2/2]
|
inline |
Definition at line 647 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VOP3P.
◆ isVOPC() [1/2]
|
inlinestatic |
Definition at line 456 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VOPC.
Referenced by legalizeOperands(), and verifyInstruction().
◆ isVOPC() [2/2]
|
inline |
Definition at line 460 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::VOPC.
◆ isWave32()
| bool llvm::SIInstrInfo::isWave32 | ( | ) | const |
Definition at line 8161 of file SIInstrInfo.cpp.
References llvm::GCNSubtarget::isWave32().
◆ isWMMA() [1/2]
|
inlinestatic |
Definition at line 676 of file SIInstrInfo.h.
References llvm::SIInstrFlags::IsWMMA, and MI.
Referenced by convertToThreeAddress().
◆ isWMMA() [2/2]
|
inline |
Definition at line 680 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::IsWMMA.
◆ isWQM() [1/2]
|
inlinestatic |
Definition at line 595 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::WQM.
◆ isWQM() [2/2]
|
inline |
Definition at line 599 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::WQM.
◆ legalizeGenericOperand()
| void SIInstrInfo::legalizeGenericOperand | ( | MachineBasicBlock & | InsertMBB, |
| MachineBasicBlock::iterator | I, | ||
| const TargetRegisterClass * | DstRC, | ||
| MachineOperand & | Op, | ||
| MachineRegisterInfo & | MRI, | ||
| const DebugLoc & | DL | ||
| ) | const |
Definition at line 5412 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::tgtok::Def, DL, FoldImmediate(), get, llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::getVRegDef(), I, llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), and MRI.
Referenced by legalizeOperands().
◆ legalizeOperands()
| MachineBasicBlock * SIInstrInfo::legalizeOperands | ( | MachineInstr & | MI, |
| MachineDominatorTree * | MDT = nullptr |
||
| ) | const |
Legalize all operands in this instruction.
This function may create new instructions and control-flow around MI. If present, MDT is updated.
- Returns
- A new basic block that contains
MIif new blocks were created.
Definition at line 5696 of file SIInstrInfo.cpp.
References assert(), llvm::numbers::e, E, llvm::Function::getCallingConv(), llvm::SIRegisterInfo::getEquivalentAGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), getNamedOperand(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVectorRegisters(), llvm::SIRegisterInfo::hasVGPRs(), i, I, Insert, llvm::SIRegisterInfo::isAGPRClass(), isFLAT(), llvm::AMDGPU::isGraphics(), isMIMG(), isMTBUF(), isMUBUF(), llvm::SIRegisterInfo::isSGPRClass(), isSMRD(), isVOP2(), isVOP3(), isVOPC(), legalizeGenericOperand(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), loadSRsrcFromVGPR(), MBB, MI, MRI, and readlaneVGPRToSGPR().
Referenced by FoldImmediate(), and moveToVALU().
◆ legalizeOperandsFLAT()
| void SIInstrInfo::legalizeOperandsFLAT | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Definition at line 5394 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRClass(), MI, moveFlatAddrToVGPR(), MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsSMRD()
| void SIInstrInfo::legalizeOperandsSMRD | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Definition at line 5294 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::isSGPRClass(), MI, MRI, readlaneVGPRToSGPR(), llvm::sys::unicode::SBase, and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP2()
| void SIInstrInfo::legalizeOperandsVOP2 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition at line 5054 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, findImplicitSGPRRead(), fixImplicitOperands(), get, llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::isAGPR(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::SIRegisterInfo::isVGPR(), legalizeOpWithMove(), llvm_unreachable, MI, MRI, llvm::MCInstrDesc::OpInfo, and llvm::MachineOperand::setSubReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP3()
| void SIInstrInfo::legalizeOperandsVOP3 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI | ||
| ) | const |
Fix operands in MI to satisfy constant bus requirements.
Definition at line 5166 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::count(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, get, llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, 4, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert(), isLiteralConstantLike(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), legalizeOpWithMove(), MI, and MRI.
Referenced by legalizeOperands().
◆ legalizeOpWithMove()
| void SIInstrInfo::legalizeOpWithMove | ( | MachineInstr & | MI, |
| unsigned | OpIdx | ||
| ) | const |
Legalize the OpIndex operand of this instruction by inserting a MOV.
For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1
If the operand being legalized is a register, then a COPY will be used instead of MOV.
Definition at line 4832 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::findDebugLoc(), get, llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVGPR64Class(), I, llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, and MRI.
Referenced by legalizeOperandsVOP2(), and legalizeOperandsVOP3().
◆ loadRegFromStackSlot()
|
override |
Definition at line 1677 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::ISD::FrameIndex, get, getAGPRSpillRestoreOpcode(), getAVSpillRestoreOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillRestoreOpcode(), llvm::TargetRegisterInfo::getSpillSize(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillRestoreOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVectorSuperClass(), llvm::Register::isVirtual(), llvm::M0(), MBB, MI, llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.
◆ materializeImmediate()
| void SIInstrInfo::materializeImmediate | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| const DebugLoc & | DL, | ||
| unsigned | DestReg, | ||
| int64_t | Value | ||
| ) | const |
Definition at line 1056 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), Builder, llvm::BuildMI(), DL, get, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, MRI, and llvm::ArrayRef< T >::size().
Referenced by convertNonUniformLoopRegion().
◆ mayAccessFlatAddressSpace()
| bool SIInstrInfo::mayAccessFlatAddressSpace | ( | const MachineInstr & | MI | ) | const |
Definition at line 7508 of file SIInstrInfo.cpp.
References llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), and MI.
◆ mayReadEXEC()
| bool SIInstrInfo::mayReadEXEC | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI | ||
| ) | const |
Returns true if the instruction could potentially depend on the value of exec.
If false, exec dependencies may safely be ignored.
Definition at line 3550 of file SIInstrInfo.cpp.
References isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), MI, and MRI.
◆ modifiesModeRegister()
|
static |
Return true if the instruction modifies the mode register.q.
Definition at line 3495 of file SIInstrInfo.cpp.
References MI.
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ moveFlatAddrToVGPR()
| bool SIInstrInfo::moveFlatAddrToVGPR | ( | MachineInstr & | Inst | ) | const |
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
- Returns
- true if succeeded.
Definition at line 5313 of file SIInstrInfo.cpp.
References llvm::MachineRegisterInfo::addRegOperandToUseList(), assert(), llvm::MachineInstr::eraseFromParent(), get, llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getGlobalVaddrOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isImm(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRReg(), llvm::MachineRegisterInfo::moveOperands(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), llvm::MachineInstr::setDesc(), llvm::MachineInstr::tieOperands(), llvm::MachineInstr::untieRegOperand(), and llvm::MachineRegisterInfo::use_nodbg_empty().
Referenced by legalizeOperandsFLAT().
◆ moveToVALU()
| MachineBasicBlock * SIInstrInfo::moveToVALU | ( | MachineInstr & | MI, |
| MachineDominatorTree * | MDT = nullptr |
||
| ) | const |
Replace this instruction's opcode with the equivalent VALU opcode.
This function will also move the users of MI to the VALU if necessary. If present, MDT is updated.
Definition at line 6022 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BitWidth, llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, DL, llvm::SetVector< T, Vector, Set >::empty(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), fixImplicitOperands(), get, llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), getVALUOp(), llvm::SIRegisterInfo::getVCC(), llvm::SIRegisterInfo::getWaveMaskRegClass(), llvm::GCNSubtarget::hasDLInsts(), llvm::GCNSubtarget::hasOnlyRevVALUShifts(), i, I, llvm::RISCVMatInt::Imm, llvm::SetVector< T, Vector, Set >::insert(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::GCNSubtarget::isWave32(), legalizeOperands(), llvm_unreachable, MBB, MRI, llvm::SetVector< T, Vector, Set >::pop_back_val(), llvm::MachineInstr::removeOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::AMDGPU::CPol::SCC, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setReg().
◆ optimizeCompareInstr()
|
override |
Definition at line 8298 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::countTrailingZeros(), llvm::tgtok::Def, E, llvm::MachineInstr::eraseFromParent(), get, getFoldableImm(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), I, llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::isPowerOf2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::maxUIntN(), MBB, MRI, llvm::AMDGPU::CPol::SCC, llvm::MachineOperand::setIsDead(), and llvm::MachineRegisterInfo::use_nodbg_empty().
◆ pseudoToMCOpcode()
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 7895 of file SIInstrInfo.cpp.
References llvm::SIInstrFlags::D16Buf, get, llvm::GCNSubtarget::getGeneration(), llvm::AMDGPU::getMCOpcode(), llvm::AMDGPU::getMFMAEarlyClobberOp(), llvm::AMDGPUSubtarget::GFX10, GFX80, llvm::AMDGPUSubtarget::GFX9, GFX9, GFX90A, GFX940, llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasGFX940Insts(), llvm::GCNSubtarget::hasUnpackedD16VMem(), isAsmOnlyOpcode(), isMAI(), llvm::SIInstrFlags::renamedInGFX9, llvm::SIInstrFlags::SDWA, SDWA, SDWA10, SDWA9, and subtargetEncodingFamily().
Referenced by commuteOpcode(), convertToThreeAddress(), FoldImmediate(), getMCOpcodeFromPseudo(), llvm::GCNSubtarget::hasMadF16(), and hasVALU32BitEncoding().
◆ readlaneVGPRToSGPR()
| Register SIInstrInfo::readlaneVGPRToSGPR | ( | Register | SrcReg, |
| MachineInstr & | UseMI, | ||
| MachineRegisterInfo & | MRI | ||
| ) | const |
Copy a value from a VGPR (SrcReg) to SGPR.
This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.
- Returns
- The SGPR register that
SrcRegwas copied to.
Definition at line 5252 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), get, llvm::SIRegisterInfo::getEquivalentSGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::SIRegisterInfo::hasAGPRs(), i, MRI, and UseMI.
Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().
◆ removeBranch()
|
override |
Definition at line 2615 of file SIInstrInfo.cpp.
References getInstSizeInBytes(), llvm::make_early_inc_range(), MBB, MI, and llvm::MachineBasicBlock::terminators().
◆ removeModOperands()
| void SIInstrInfo::removeModOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 2888 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), MI, ModifierOpNames, and llvm::reverse().
Referenced by FoldImmediate().
◆ reverseBranchCondition()
|
override |
Definition at line 2701 of file SIInstrInfo.cpp.
◆ shouldClusterMemOps()
|
override |
Definition at line 477 of file SIInstrInfo.cpp.
References llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineOperand::getParent(), and memOpsHaveSameBasePtr().
◆ shouldScheduleLoadsNear()
|
override |
Definition at line 520 of file SIInstrInfo.cpp.
References assert().
◆ sopkIsZext() [1/2]
|
inlinestatic |
Definition at line 716 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::SOPK_ZEXT.
Referenced by verifyInstruction().
◆ sopkIsZext() [2/2]
|
inline |
Definition at line 720 of file SIInstrInfo.h.
References get, and llvm::SIInstrFlags::SOPK_ZEXT.
◆ splitFlatOffset()
| std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset | ( | int64_t | COffsetVal, |
| unsigned | AddrSpace, | ||
| uint64_t | FlatVariant | ||
| ) | const |
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition at line 7808 of file SIInstrInfo.cpp.
References assert(), D, llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::GCNSubtarget::hasNegativeScratchOffsetBug(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), isLegalFLATOffset(), and Signed.
◆ storeRegToStackSlot()
|
override |
Definition at line 1510 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::ISD::FrameIndex, get, getAGPRSpillSaveOpcode(), getAVSpillSaveOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillSaveOpcode(), llvm::TargetRegisterInfo::getSpillSize(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillSaveOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVectorSuperClass(), llvm::Register::isVirtual(), llvm::M0(), MBB, MI, llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.
◆ swapSourceModifiers()
|
protected |
Definition at line 2226 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), MI, and llvm::MachineOperand::setImm().
Referenced by commuteInstructionImpl().
◆ usesConstantBus()
| bool SIInstrInfo::usesConstantBus | ( | const MachineRegisterInfo & | MRI, |
| const MachineOperand & | MO, | ||
| const MCOperandInfo & | OpInfo | ||
| ) | const |
Returns true if this operand uses the constant bus.
Definition at line 3888 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), llvm::Register::isVirtual(), llvm::M0(), and MRI.
Referenced by isOperandLegal(), and verifyInstruction().
◆ usesFPDPRounding() [1/2]
|
inlinestatic |
Definition at line 762 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and MI.
◆ usesFPDPRounding() [2/2]
|
inline |
Definition at line 766 of file SIInstrInfo.h.
References llvm::SIInstrFlags::FPDPRounding, and get.
◆ usesLGKM_CNT()
|
inlinestatic |
Definition at line 712 of file SIInstrInfo.h.
References llvm::SIInstrFlags::LGKM_CNT, and MI.
◆ usesVM_CNT()
|
inlinestatic |
Definition at line 708 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::VM_CNT.
◆ verifyInstruction()
|
override |
Definition at line 3973 of file SIInstrInfo.cpp.
References llvm::SISrcMods::ABS, llvm::all_of(), assert(), llvm::AMDGPU::DPP::BCAST15, llvm::AMDGPU::DPP::BCAST31, llvm::misexpect::clamp(), compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::countPopulation(), llvm::Data, llvm::dbgs(), DC, llvm::SIInstrFlags::DPP, llvm::AMDGPU::DPP::DPP_LAST, llvm::AMDGPU::DPP::DPP_UNUSED1, llvm::AMDGPU::DPP::DPP_UNUSED2, llvm::AMDGPU::DPP::DPP_UNUSED3, llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED4_LAST, llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED5_LAST, llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED6_LAST, llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED7_LAST, llvm::AMDGPU::DPP::DPP_UNUSED8_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED8_LAST, llvm::numbers::e, E, findImplicitSGPRRead(), get, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::SIRegisterInfo::getChannelFromSubReg(), llvm::SIRegisterInfo::getCompatibleSubRegClass(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::GCNSubtarget::getGeneration(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::getOpcode(), getOpRegClass(), llvm::SrcOp::getReg(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::getSubRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::AMDGPUSubtarget::GFX10, llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasG16(), llvm::GCNSubtarget::hasGFX10A16(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasR128A16(), llvm::AMDGPUSubtarget::hasSDWA(), llvm::GCNSubtarget::hasSDWAOmod(), llvm::GCNSubtarget::hasSDWAOutModsVOPC(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::GCNSubtarget::hasSDWASdst(), llvm::GCNSubtarget::hasUnpackedD16VMem(), llvm::SIRegisterInfo::hasVectorRegisters(), llvm::SIRegisterInfo::hasVGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), i, I, llvm::RISCVMatInt::Imm, Info, llvm::SIRegisterInfo::isAGPR(), llvm::MCInstrDesc::isBranch(), isDS(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::isInt< 16 >(), llvm::AMDGPU::isLegal64BitDPPControl(), isMIMG(), llvm::Register::isPhysical(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::MachineOperand::isReg(), isSDWA(), llvm::SIRegisterInfo::isSGPRReg(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSubRegOf(), llvm::isUInt< 16 >(), llvm::MachineOperand::isUse(), isVALU(), llvm::MCInstrDesc::isVariadic(), isVGPRSpill(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), LLVM_DEBUG, LLVM_FALLTHROUGH, llvm::M0(), MI, llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::GCNSubtarget::needsAlignedVGPRs(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST, llvm::AMDGPU::DPP::ROW_SHARE_FIRST, llvm::AMDGPU::DPP::ROW_XMASK_LAST, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, usesConstantBus(), llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS, llvm::AMDGPU::DPP::WAVE_ROR1, and llvm::AMDGPU::DPP::WAVE_SHL1.
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/SIInstrInfo.h
- lib/Target/AMDGPU/SIInstrInfo.cpp
