#include "Target/AMDGPU/SIInstrInfo.h"
Classes | |
| struct | ThreeAddressUpdates |
| Helper struct for the implementation of 3-address conversion to communicate updates made to instruction operands. More... | |
Public Types | |
| enum | TargetOperandFlags { MO_MASK = 0xf , MO_NONE = 0 , MO_GOTPCREL = 1 , MO_GOTPCREL32 = 2 , MO_GOTPCREL32_LO = 2 , MO_GOTPCREL32_HI = 3 , MO_GOTPCREL64 = 4 , MO_REL32 = 5 , MO_REL32_LO = 5 , MO_REL32_HI = 6 , MO_REL64 = 7 , MO_FAR_BRANCH_OFFSET = 8 , MO_ABS32_LO = 9 , MO_ABS32_HI = 10 , MO_ABS64 = 11 } |
Protected Member Functions | |
| std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
| bool | swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, AMDGPU::OpName Src0OpName, MachineOperand &Src1, AMDGPU::OpName Src1OpName) const |
| bool | isLegalToSwap (const MachineInstr &MI, unsigned fromIdx, unsigned toIdx) const |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override |
Detailed Description
Definition at line 107 of file SIInstrInfo.h.
Member Enumeration Documentation
◆ TargetOperandFlags
| Enumerator | |
|---|---|
| MO_MASK | |
| MO_NONE | |
| MO_GOTPCREL | |
| MO_GOTPCREL32 | |
| MO_GOTPCREL32_LO | |
| MO_GOTPCREL32_HI | |
| MO_GOTPCREL64 | |
| MO_REL32 | |
| MO_REL32_LO | |
| MO_REL32_HI | |
| MO_REL64 | |
| MO_FAR_BRANCH_OFFSET | |
| MO_ABS32_LO | |
| MO_ABS32_HI | |
| MO_ABS64 | |
Definition at line 239 of file SIInstrInfo.h.
Constructor & Destructor Documentation
◆ SIInstrInfo()
|
explicit |
Definition at line 66 of file SIInstrInfo.cpp.
Referenced by insertScratchExecCopy().
Member Function Documentation
◆ allowNegativeFlatOffset()
| bool SIInstrInfo::allowNegativeFlatOffset | ( | AMDGPU::FlatAddrSpace | FlatVariant | ) | const |
Returns true if negative offsets are allowed for the given FlatVariant.
Definition at line 10330 of file SIInstrInfo.cpp.
References llvm::AMDGPU::FLAT, llvm::AMDGPU::FlatScratch, and llvm::AMDGPU::isGFX12Plus().
Referenced by isLegalFLATOffset(), and splitFlatOffset().
◆ analyzeBranch()
|
override |
Definition at line 3095 of file SIInstrInfo.cpp.
References analyzeBranchImpl(), Cond, I, llvm_unreachable, MBB, and TBB.
◆ analyzeBranchImpl()
| bool SIInstrInfo::analyzeBranchImpl | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify ) const |
Definition at line 3058 of file SIInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), I, MBB, and TBB.
Referenced by analyzeBranch().
◆ analyzeCompare()
|
override |
Definition at line 10983 of file SIInstrInfo.cpp.
◆ areLoadsFromSameBasePtr()
|
override |
Definition at line 222 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), llvm::dyn_cast(), llvm::get(), llvm::SDNode::getAsZExtVal(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::AMDGPU::hasNamedOperand(), llvm::isa(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().
◆ areMemAccessesTriviallyDisjoint()
|
override |
Definition at line 3961 of file SIInstrInfo.cpp.
References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::isBundle(), isDS(), isFLAT(), isFLATGlobal(), isFLATScratch(), isLDSDMA(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), and llvm::MachineInstr::mayLoadOrStore().
◆ buildExtractSubReg()
| unsigned SIInstrInfo::buildExtractSubReg | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC ) const |
Definition at line 6220 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::Register::isVirtual(), MBB, and MI.
Referenced by buildExtractSubRegOrImm().
◆ buildExtractSubRegOrImm()
| MachineOperand SIInstrInfo::buildExtractSubRegOrImm | ( | MachineBasicBlock::iterator | MI, |
| MachineRegisterInfo & | MRI, | ||
| const MachineOperand & | SuperReg, | ||
| const TargetRegisterClass * | SuperRC, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | SubRC ) const |
Definition at line 6237 of file SIInstrInfo.cpp.
References buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), and llvm_unreachable.
◆ buildShrunkInst()
| MachineInstr * SIInstrInfo::buildShrunkInst | ( | MachineInstr & | MI, |
| unsigned | NewOpcode ) const |
Definition at line 4911 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), copyFlagsToImplicitVCC(), fixImplicitOperands(), llvm::get(), getNamedOperand(), llvm::MCInstrDesc::getNumDefs(), I, MBB, MI, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INPUT_MODS, and llvm::MachineInstrBuilder::setMIFlags().
◆ canAddToBBProlog()
| bool SIInstrInfo::canAddToBBProlog | ( | const MachineInstr & | MI | ) | const |
Definition at line 10046 of file SIInstrInfo.cpp.
References llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), isSGPRSpill(), llvm::SIMachineFunctionInfo::isWWMReg(), isWWMRegSpillOpcode(), llvm::MachineInstr::LRSplit, and MI.
Referenced by isBasicBlockPrologue().
◆ canInsertSelect()
|
override |
Definition at line 3232 of file SIInstrInfo.cpp.
References Cond, llvm::getImm(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineRegisterInfo::getRegClass(), and MBB.
◆ canShrink()
| bool SIInstrInfo::canShrink | ( | const MachineInstr & | MI, |
| const MachineRegisterInfo & | MRI ) const |
Definition at line 4835 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), and MI.
◆ commuteInstructionImpl()
|
overrideprotected |
Definition at line 2765 of file SIInstrInfo.cpp.
References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::get(), llvm::MachineOperand::isImm(), isLegalToSwap(), llvm::MachineOperand::isReg(), MI, Opc, llvm::MachineInstr::setDesc(), std::swap(), swapImmOperands(), swapRegAndNonRegOperand(), and swapSourceModifiers().
◆ commuteOpcode() [1/2]
|
inline |
Definition at line 378 of file SIInstrInfo.h.
References commuteOpcode(), and MI.
◆ commuteOpcode() [2/2]
| int SIInstrInfo::commuteOpcode | ( | unsigned | Opc | ) | const |
Definition at line 1140 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().
Referenced by commuteInstructionImpl(), commuteOpcode(), and legalizeOperandsVOP2().
◆ convertToThreeAddress()
|
override |
Definition at line 4104 of file SIInstrInfo.cpp.
References llvm::LiveVariables::VarInfo::AliveBlocks, llvm::AnalyzeVirtRegInBundle(), assert(), llvm::SparseBitVector< ElementSize >::clear(), llvm::MachineRegisterInfo::cloneVirtualRegister(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::eraseFromBundle(), llvm::get(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineInstr::getOperand(), llvm::SlotIndex::getRegSlot(), llvm::LiveVariables::getVarInfo(), llvm::LiveIntervals::hasInterval(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), I, MBB, MI, llvm::VirtRegInfo::Reads, llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::LiveIntervals::shrinkToUses(), updateLiveVariables(), and llvm::VirtRegInfo::Writes.
◆ copyPhysReg()
|
override |
Definition at line 798 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysReg(), llvm::Define, DL, expandSGPRCopy(), Fix16BitCopies, llvm::get(), llvm::getKillRegState(), llvm::Implicit, indirectCopyToAGPR(), llvm::AMDGPU::isHi16Reg(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, Register, reportIllegalCopy(), Size, llvm::ArrayRef< T >::size(), llvm::MachineInstr::tieOperands(), llvm::Undef, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.
Referenced by copyPhysReg().
◆ createPHIDestinationCopy()
|
override |
Definition at line 10655 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), DL, llvm::get(), and MBB.
◆ createPHISourceCopy()
|
override |
Definition at line 10670 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), DL, llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::Implicit, and MBB.
◆ createReadFirstLaneFromCopyToPhysReg()
| void SIInstrInfo::createReadFirstLaneFromCopyToPhysReg | ( | MachineRegisterInfo & | MRI, |
| Register | DstReg, | ||
| MachineInstr & | Inst ) const |
Definition at line 7796 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ArrayRef< T >::size().
Referenced by handleCopyToPhysHelper().
◆ CreateTargetMIHazardRecognizer()
|
override |
Definition at line 9989 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), II, and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
override |
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
The post-RA version of misched uses CreateTargetMIHazardRecognizer.
Definition at line 9973 of file SIInstrInfo.cpp.
References II, and llvm::ScheduleDAG::MF.
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
override |
This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.
Definition at line 9981 of file SIInstrInfo.cpp.
◆ createWaterFallForSiCall()
| void SIInstrInfo::createWaterFallForSiCall | ( | MachineInstr * | MI, |
| MachineDominatorTree * | MDT, | ||
| ArrayRef< MachineOperand * > | ScalarOps, | ||
| ArrayRef< Register > | PhySGPRs = {} ) const |
Wrapper function for generating waterfall for instruction MI This function take into consideration of related pre & succ instructions (e.g.
calling process) into consideratioin
Definition at line 7738 of file SIInstrInfo.cpp.
References assert(), generateWaterFallLoop(), MBB, and MI.
Referenced by legalizeOperands(), and moveToVALU().
◆ decomposeMachineOperandsTargetFlags()
|
override |
Definition at line 10001 of file SIInstrInfo.cpp.
References MO_MASK.
◆ doesNotReadTiedSource() [1/2]
|
inlinestatic |
Definition at line 1179 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isTiedSourceNotRead(), and MI.
◆ doesNotReadTiedSource() [2/2]
Definition at line 1183 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isTiedSourceNotRead().
◆ enforceOperandRCAlignment()
| void SIInstrInfo::enforceOperandRCAlignment | ( | MachineInstr & | MI, |
| AMDGPU::OpName | OpName ) const |
Definition at line 11382 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::get(), getOpSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MI, and llvm::Undef.
◆ expandMovDPP64()
| std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 | ( | MachineInstr & | MI | ) | const |
Definition at line 2588 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::drop_begin(), llvm::get(), llvm::getImm(), llvm::SrcOp::getImm(), getNamedOperand(), getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::getUndefRegState(), I, llvm::AMDGPU::isLegalDPALU_DPPControl(), llvm::MachineRegisterInfo::isSSA(), MBB, MI, and llvm::Sub.
Referenced by expandPostRAPseudo().
◆ expandPostRAPseudo()
|
override |
Definition at line 1929 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::TargetRegisterClass::contains(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::MachineOperand::CreateImm(), DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, llvm::AMDGPU::EncodingFields< HwregId, HwregOffset, HwregSize >::encode(), llvm::AMDGPU::LaneMaskConstants::ExecReg, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), getNamedOperand(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::SrcOp::getReg(), getRegClass(), llvm::SIMachineFunctionInfo::getScratchReservedForDynamicVGPRs(), llvm::MachineFunction::getSubtarget(), llvm::getUndefRegState(), llvm::Hi, llvm::AMDGPU::Hwreg::ID_HW_ID2, llvm::Implicit, llvm::MCInstrDesc::implicit_uses(), llvm::ImplicitDefine, llvm::SIRegisterInfo::isAGPRClass(), llvm::MachineOperand::isGlobal(), isInlineConstant(), llvm::isUInt(), llvm::Lo, MBB, MI, llvm::AMDGPU::LaneMaskConstants::MovOpc, llvm::AMDGPU::Hwreg::OFFSET_ME_ID, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, llvm::AMDGPU::LaneMaskConstants::OrSaveExecOpc, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setOffset(), llvm::SignExtend64(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, llvm::MachineInstr::tieOperands(), TRI, llvm::Undef, and llvm::AMDGPU::LaneMaskConstants::WQMOpc.
◆ extractSubregFromImm()
|
static |
Return the extracted immediate value in a subregister use from a constant materialized in a super register.
e.g. imm = S_MOV_B64 K[0:63] USE imm.sub1 This will return K[32:63]
Definition at line 3488 of file SIInstrInfo.cpp.
References llvm_unreachable, and llvm::SignExtend64().
Referenced by foldImmediate(), and getImmOrMaterializedImm().
◆ findCommutedOpIndices() [1/2]
|
override |
Definition at line 2821 of file SIInstrInfo.cpp.
References findCommutedOpIndices(), and MI.
Referenced by findCommutedOpIndices().
◆ findCommutedOpIndices() [2/2]
| bool SIInstrInfo::findCommutedOpIndices | ( | const MCInstrDesc & | Desc, |
| unsigned & | SrcOpIdx0, | ||
| unsigned & | SrcOpIdx1 ) const |
Definition at line 2827 of file SIInstrInfo.cpp.
References Opc.
◆ fixImplicitOperands()
| void SIInstrInfo::fixImplicitOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 10162 of file SIInstrInfo.cpp.
References MI.
Referenced by buildShrunkInst(), insertBranch(), insertSelect(), legalizeOperandsVOP2(), and moveToVALUImpl().
◆ foldImmediate()
|
final |
Definition at line 3580 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::Register::asMCReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetRegisterClass::contains(), llvm::MachineRegisterInfo::createVirtualRegister(), DefMI, extractSubregFromImm(), llvm::get(), getConstValDefinedInReg(), getNamedOperand(), getNewFMAAKInst(), getNewFMAMKInst(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), hasAnyModifiersSet(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), isInlineConstant(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), llvm::Kill, legalizeOperands(), MI, Opc, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::MCInstrDesc::operands(), pseudoToMCOpcode(), removeModOperands(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MachineRegisterInfo::use_nodbg_empty(), and UseMI.
Referenced by legalizeGenericOperand().
◆ foldMemoryOperandImpl()
|
override |
Definition at line 10708 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtual(), and MI.
◆ getAddNoCarry() [1/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg ) const |
Return a partially built integer add instruction without carry.
Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.
Definition at line 10092 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Dead, llvm::Define, DL, llvm::get(), I, MBB, and llvm::MachineRegisterInfo::setRegAllocationHint().
◆ getAddNoCarry() [2/2]
| MachineInstrBuilder SIInstrInfo::getAddNoCarry | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| Register | DestReg, | ||
| RegScavenger & | RS ) const |
Definition at line 10107 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::Dead, llvm::Define, DL, llvm::get(), I, llvm::Register::isValid(), MBB, and Register.
◆ getBranchDestBlock()
|
override |
Definition at line 2862 of file SIInstrInfo.cpp.
References MI.
◆ getCalleeOperand()
|
override |
Definition at line 10764 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::getCalleeOperand(), getNamedOperand(), and MI.
◆ getConstValDefinedInReg()
|
override |
Definition at line 1158 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), MI, and llvm::reverseBits().
Referenced by foldImmediate().
◆ getDefaultRsrcDataFormat()
| uint64_t SIInstrInfo::getDefaultRsrcDataFormat | ( | ) | const |
Definition at line 9717 of file SIInstrInfo.cpp.
References llvm::Format, llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX11, llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getScratchRsrcWords23().
◆ getDSShaderTypeValue()
|
static |
Definition at line 10957 of file SIInstrInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallingConv::C, F, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), and llvm::MachineFunction::getFunction().
◆ getFoldableCopySrcIdx()
|
static |
Definition at line 3433 of file SIInstrInfo.cpp.
References llvm_unreachable, and MI.
◆ getGenericValueUniformity()
| ValueUniformity SIInstrInfo::getGenericValueUniformity | ( | const MachineInstr & | MI | ) | const |
Definition at line 10772 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, llvm::dyn_cast(), llvm::AMDGPUAS::FLAT_ADDRESS, llvm::LLT::getAddressSpace(), llvm::MachineRegisterInfo::getType(), llvm::isa(), llvm::AMDGPU::isGenericAtomic(), llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), MI, llvm::NeverUniform, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
Referenced by getValueUniformity().
◆ getImmOrMaterializedImm()
| std::optional< int64_t > SIInstrInfo::getImmOrMaterializedImm | ( | MachineOperand & | Op | ) | const |
Definition at line 1218 of file SIInstrInfo.cpp.
References extractSubregFromImm(), llvm::MachineOperand::getImm(), llvm::MachineRegisterInfo::getVRegDef(), and llvm::MachineOperand::isImm().
◆ getIndirectGPRIDXPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo | ( | unsigned | VecSize, |
| bool | IsIndirectSrc ) const |
Definition at line 1254 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getIndirectRegWriteMovRelPseudo()
| const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo | ( | unsigned | VecSize, |
| unsigned | EltSize, | ||
| bool | IsSGPR ) const |
Definition at line 1403 of file SIInstrInfo.cpp.
References assert(), llvm::get(), getIndirectSGPRWriteMovRelPseudo32(), getIndirectSGPRWriteMovRelPseudo64(), getIndirectVGPRWriteMovRelPseudoOpc(), and llvm_unreachable.
◆ getInstrLatency()
|
override |
Definition at line 10746 of file SIInstrInfo.cpp.
References llvm::Count, E(), I, and MI.
◆ getInstSizeInBytes()
|
override |
Definition at line 9836 of file SIInstrInfo.cpp.
References llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::MachineFunction::getTarget(), I, isDPP(), isFixedSize(), isInlineConstant(), llvm::isInt(), isMIMG(), isSALU(), llvm::isUInt(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), MI, Opc, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, and Size.
Referenced by removeBranch().
◆ getInstSizeVerifyMode()
|
override |
Definition at line 9939 of file SIInstrInfo.cpp.
References MI.
◆ getKillTerminatorFromPseudo()
| const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo | ( | unsigned | Opcode | ) | const |
Definition at line 10140 of file SIInstrInfo.cpp.
References llvm::get(), and llvm_unreachable.
◆ getLiveRangeSplitOpcode()
|
override |
Definition at line 10036 of file SIInstrInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::checkFlag(), llvm::MachineFunction::getInfo(), llvm::Register::isVirtual(), and llvm::AMDGPU::VirtRegFlag::WWM_REG.
◆ getMachineCSELookAheadLimit()
|
inlineoverride |
Definition at line 467 of file SIInstrInfo.h.
◆ getMaxMUBUFImmOffset()
|
static |
Definition at line 10155 of file SIInstrInfo.cpp.
References llvm::AMDGPUSubtarget::GFX12.
Referenced by isLegalMUBUFImmOffset(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), llvm::AMDGPURegisterBankInfo::splitBufferOffsets(), and splitMUBUFOffset().
◆ getMCOpcodeFromPseudo()
|
inline |
Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.
Definition at line 1601 of file SIInstrInfo.h.
References llvm::get(), and pseudoToMCOpcode().
Referenced by getInstSizeInBytes().
◆ getMemOperandsWithOffsetWidth()
|
final |
Definition at line 348 of file SIInstrInfo.cpp.
References assert(), llvm::TypeSize::getFixed(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), getOpSize(), llvm::LocationSize::getValue(), I, isDS(), llvm::MachineOperand::isFI(), isFLAT(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::mayStore(), llvm::Offset, Opc, llvm::LocationSize::precise(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
◆ getMIRFormatter()
|
override |
Definition at line 10854 of file SIInstrInfo.cpp.
◆ getMovOpcode()
| unsigned SIInstrInfo::getMovOpcode | ( | const TargetRegisterClass * | DstRC | ) | const |
Definition at line 1235 of file SIInstrInfo.cpp.
◆ getNamedImmOperand()
|
inline |
Get required immediate operand.
Definition at line 1587 of file SIInstrInfo.h.
References MI.
Referenced by legalizeOperands().
◆ getNamedOperand() [1/2]
|
inline |
Definition at line 1581 of file SIInstrInfo.h.
References getNamedOperand(), and MI.
◆ getNamedOperand() [2/2]
| MachineOperand * SIInstrInfo::getNamedOperand | ( | MachineInstr & | MI, |
| AMDGPU::OpName | OperandName ) const |
Returns the operand named Op.
If MI does not have an operand named Op, this function returns nullptr.
Definition at line 9705 of file SIInstrInfo.cpp.
References MI.
Referenced by buildShrunkInst(), canShrink(), expandMovDPP64(), expandPostRAPseudo(), foldImmediate(), getCalleeOperand(), getMemOperandsWithOffsetWidth(), getNamedOperand(), hasModifiersSet(), isLegalRegOperand(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), reMaterialize(), swapSourceModifiers(), and verifyInstruction().
◆ getNonSoftWaitcntOpcode()
Definition at line 1200 of file SIInstrInfo.h.
Referenced by isWaitcnt(), isWaitInstr(), and pseudoToMCOpcode().
◆ getNumWaitStates()
|
static |
Return the number of wait states that result from executing this instruction.
Definition at line 1915 of file SIInstrInfo.cpp.
References MI.
Referenced by getWaitStatesSince(), and getWaitStatesSince().
◆ getOpRegClass()
| const TargetRegisterClass * SIInstrInfo::getOpRegClass | ( | const MachineInstr & | MI, |
| unsigned | OpNo ) const |
Return the correct register class for OpNo.
For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.
Definition at line 6179 of file SIInstrInfo.cpp.
References llvm::get(), llvm::MachineRegisterInfo::getRegClass(), and MI.
Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), moveToVALUImpl(), and verifyInstruction().
◆ getOpSize() [1/2]
|
inline |
This form should usually be preferred since it handles operands with unknown register classes.
Definition at line 1442 of file SIInstrInfo.h.
References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), and MI.
◆ getOpSize() [2/2]
Return the size in bytes of the operand OpNo on the given.
Definition at line 1428 of file SIInstrInfo.h.
References assert(), llvm::get(), and llvm::MCOI::OPERAND_IMMEDIATE.
Referenced by enforceOperandRCAlignment(), getMemOperandsWithOffsetWidth(), isInlineConstant(), isSGPRStackAccess(), isStackAccess(), and verifyInstruction().
◆ getRegisterInfo()
|
inline |
Definition at line 268 of file SIInstrInfo.h.
◆ getSchedModel()
|
inline |
Definition at line 1755 of file SIInstrInfo.h.
◆ getScratchRsrcWords23()
| uint64_t SIInstrInfo::getScratchRsrcWords23 | ( | ) | const |
Definition at line 9742 of file SIInstrInfo.cpp.
References getDefaultRsrcDataFormat(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 10006 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), MO_ABS32_HI, MO_ABS32_LO, MO_ABS64, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_GOTPCREL64, MO_REL32_HI, MO_REL32_LO, and MO_REL64.
◆ getSerializableMachineMemOperandTargetFlags()
|
override |
Definition at line 10024 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), llvm::MOCooperative, llvm::MOLastUse, llvm::MONoClobber, and llvm::MOThreadPrivate.
◆ getSerializableTargetIndices()
|
override |
Definition at line 9960 of file SIInstrInfo.cpp.
References llvm::ArrayRef(), llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.
◆ getSubtarget()
|
inline |
Definition at line 272 of file SIInstrInfo.h.
Referenced by shouldScheduleVOPDAdjacent().
◆ getValueUniformity()
|
final |
Definition at line 10860 of file SIInstrInfo.cpp.
References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, getGenericValueUniformity(), llvm::RegisterBank::getID(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::RegisterBankInfo::getRegBank(), I, isAtomic(), llvm::MachineOperand::isDef(), isFLAT(), isNeverUniform(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), MI, and llvm::NeverUniform.
◆ getVALUOp() [1/2]
| unsigned SIInstrInfo::getVALUOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 5893 of file SIInstrInfo.cpp.
References getVALUOp(), and MI.
Referenced by getVALUOp(), and moveToVALUImpl().
◆ getVALUOp() [2/2]
Definition at line 5906 of file SIInstrInfo.cpp.
References llvm_unreachable, and Opc.
◆ getVectorRegSpillRestoreOpcode()
| unsigned SIInstrInfo::getVectorRegSpillRestoreOpcode | ( | Register | Reg, |
| const TargetRegisterClass * | RC, | ||
| unsigned | Size, | ||
| const SIMachineFunctionInfo & | MFI ) const |
Definition at line 1774 of file SIInstrInfo.cpp.
References assert(), llvm::SIMachineFunctionInfo::checkFlag(), getAVSpillRestoreOpcode(), getVGPRSpillRestoreOpcode(), getWWMRegSpillRestoreOpcode(), Size, and llvm::AMDGPU::VirtRegFlag::WWM_REG.
Referenced by loadRegFromStackSlot().
◆ getVectorRegSpillSaveOpcode()
| unsigned SIInstrInfo::getVectorRegSpillSaveOpcode | ( | Register | Reg, |
| const TargetRegisterClass * | RC, | ||
| unsigned | Size, | ||
| const SIMachineFunctionInfo & | MFI, | ||
| bool | NeedsCFI ) const |
Definition at line 1566 of file SIInstrInfo.cpp.
References llvm::SIMachineFunctionInfo::checkFlag(), getAVSpillSaveOpcode(), getVGPRSpillSaveOpcode(), getWWMRegSpillSaveOpcode(), Size, and llvm::AMDGPU::VirtRegFlag::WWM_REG.
◆ getWholeWaveFunctionSetup()
| MachineInstr * SIInstrInfo::getWholeWaveFunctionSetup | ( | MachineFunction & | MF | ) | const |
Definition at line 6167 of file SIInstrInfo.cpp.
References assert(), llvm::MachineFunction::begin(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::isWholeWaveFunction(), llvm_unreachable, MBB, and MI.
◆ handleCopyToPhysHelper()
| void SIInstrInfo::handleCopyToPhysHelper | ( | SIInstrWorklist & | Worklist, |
| Register | DstReg, | ||
| MachineInstr & | Inst, | ||
| MachineRegisterInfo & | MRI, | ||
| DenseMap< MachineInstr *, V2PhysSCopyInfo > & | WaterFalls, | ||
| DenseMap< MachineInstr *, bool > & | V2SPhyCopiesToErase ) const |
Definition at line 7830 of file SIInstrInfo.cpp.
References createReadFirstLaneFromCopyToPhysReg(), llvm::MachineBasicBlock::end(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::setReg(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::try_emplace(), and UseMI.
Referenced by moveToVALUImpl().
◆ hasAnyModifiersSet()
| bool SIInstrInfo::hasAnyModifiersSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 4830 of file SIInstrInfo.cpp.
References llvm::any_of(), hasModifiersSet(), MI, and ModifierOpNames.
Referenced by foldImmediate().
◆ hasDivergentBranch()
| bool SIInstrInfo::hasDivergentBranch | ( | const MachineBasicBlock * | MBB | ) | const |
Return whether the block terminate with divergent branch.
Note this only work before lowering the pseudo control flow instructions.
Definition at line 2866 of file SIInstrInfo.cpp.
Referenced by isSafeToSink().
◆ hasFPClamp() [1/2]
|
inlinestatic |
Definition at line 1089 of file SIInstrInfo.h.
References llvm::SIInstrFlags::hasFPClamp(), and MI.
◆ hasFPClamp() [2/2]
Definition at line 1093 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::hasFPClamp().
◆ hasIntClamp()
|
inlinestatic |
Definition at line 1097 of file SIInstrInfo.h.
References llvm::SIInstrFlags::hasIntClamp(), and MI.
◆ hasModifiers()
Return true if this instruction has any modifiers.
e.g. src[012]_mod, omod, clamp.
Definition at line 4817 of file SIInstrInfo.cpp.
References llvm::AMDGPU::hasNamedOperand().
◆ hasModifiersSet()
| bool SIInstrInfo::hasModifiersSet | ( | const MachineInstr & | MI, |
| AMDGPU::OpName | OpName ) const |
Definition at line 4824 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.
Referenced by canShrink(), and hasAnyModifiersSet().
◆ hasRAWDependency()
| bool SIInstrInfo::hasRAWDependency | ( | const MachineInstr & | FirstMI, |
| const MachineInstr & | SecondMI ) const |
Definition at line 10690 of file SIInstrInfo.cpp.
References llvm::MachineInstr::all_uses(), and llvm::MachineInstr::modifiesRegister().
◆ hasSameClamp()
|
inlinestatic |
Definition at line 1101 of file SIInstrInfo.h.
References A(), B(), llvm::SIInstrFlags::hasClampHi(), llvm::SIInstrFlags::hasClampLo(), llvm::SIInstrFlags::hasFPClamp(), and llvm::SIInstrFlags::hasIntClamp().
◆ hasUnwantedEffectsWhenEXECEmpty()
| bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty | ( | const MachineInstr & | MI | ) | const |
This function is used to determine if an instruction can be safely executed under EXEC = 0 without hardware error, indeterminate results, and/or visible effects on future vector execution or outside the shader.
Note: as of 2024 the only use of this is SIPreEmitPeephole where it is used in removing branches over short EXEC = 0 sequences. As such it embeds certain assumptions which may not apply to every case of EXEC = 0 execution.
Definition at line 4533 of file SIInstrInfo.cpp.
References isBarrier(), isEXP(), isSMRD(), MI, and modifiesModeRegister().
◆ hasVALU32BitEncoding()
Return true if this 64-bit VALU instruction has a 32-bit encoding.
This function will return false if you pass it a 32-bit instruction.
Definition at line 4805 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getVOPe32(), and pseudoToMCOpcode().
Referenced by canShrink().
◆ hasVGPRUses()
|
inline |
Definition at line 1257 of file SIInstrInfo.h.
References llvm::any_of(), llvm::MachineFunction::getRegInfo(), and MI.
◆ insertBranch()
|
override |
Definition at line 3166 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::getImm(), llvm::MachineInstr::getOperand(), isUndef(), MBB, preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and TBB.
◆ insertIndirectBranch()
|
override |
Definition at line 2875 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MCConstantExpr::create(), llvm::MCSymbolRefExpr::create(), llvm::MCBinaryExpr::createAnd(), llvm::MCBinaryExpr::createAShr(), llvm::MCBinaryExpr::createSub(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Define, DL, llvm::MachineBasicBlock::empty(), llvm::AMDGPU::DepCtr::encodeFieldSaSdst(), llvm::get(), llvm::MachineFunction::getContext(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getLongBranchReservedReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::getSymbol(), I, MBB, MO_FAR_BRANCH_OFFSET, llvm::Offset, llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstr::setPostInstrSymbol(), llvm::MCSymbol::setVariableValue(), and TRI.
◆ insertNoop()
|
override |
Definition at line 1842 of file SIInstrInfo.cpp.
References insertNoops(), MBB, and MI.
◆ insertNoops()
|
override |
Definition at line 1847 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
Referenced by insertNoop().
◆ insertScratchExecCopy()
| void SIInstrInfo::insertScratchExecCopy | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| bool | IsSCCLive, | ||
| SlotIndexes * | Indexes = nullptr ) const |
Definition at line 6125 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::AMDGPU::LaneMaskConstants::get(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::Kill, MBB, MBBI, llvm::AMDGPU::LaneMaskConstants::MovOpc, llvm::AMDGPU::LaneMaskConstants::OrSaveExecOpc, llvm::MachineOperand::setIsDead(), SIInstrInfo(), and TII.
◆ insertSelect()
|
override |
Definition at line 3274 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), Cond, llvm::MachineRegisterInfo::createVirtualRegister(), DL, fixImplicitOperands(), llvm::get(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineRegisterInfo::getRegClass(), I, MBB, preserveCondRegFlags(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Select, and std::swap().
◆ insertSimulatedTrap()
| MachineBasicBlock * SIInstrInfo::insertSimulatedTrap | ( | MachineRegisterInfo & | MRI, |
| MachineBasicBlock & | MBB, | ||
| MachineInstr & | MI, | ||
| const DebugLoc & | DL ) const |
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely, gfx11) that runs in PRIV=1 mode.
There, s_trap is interpreted as a nop.
Definition at line 1859 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineInstrBuilder::addUse(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::AMDGPU::SendMsg::ID_INTERRUPT, llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL, llvm::GCNSubtarget::LLVMAMDHSATrap, MBB, MI, and llvm::MachineFunction::push_back().
◆ isAlwaysGDS()
Definition at line 4436 of file SIInstrInfo.cpp.
References isGWS().
◆ isAsmOnlyOpcode()
| bool SIInstrInfo::isAsmOnlyOpcode | ( | int | MCOp | ) | const |
Check if this instruction should only be used by assembler.
Return true if this opcode should not be used by codegen.
Definition at line 10363 of file SIInstrInfo.cpp.
Referenced by pseudoToMCOpcode().
◆ isAtomic() [1/2]
|
inlinestatic |
Definition at line 828 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isAtomic(), and MI.
Referenced by getValueUniformity(), and isValidClauseInst().
◆ isAtomic() [2/2]
Definition at line 832 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isAtomic().
◆ isAtomicNoRet() [1/2]
|
inlinestatic |
Definition at line 812 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isAtomicNoRet(), and MI.
Referenced by llvm::AMDGPU::getVmemHWEvent().
◆ isAtomicNoRet() [2/2]
Definition at line 816 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isAtomicNoRet().
◆ isAtomicRet() [1/2]
|
inlinestatic |
Definition at line 820 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isAtomicRet(), and MI.
Referenced by llvm::AMDGPU::getEventsForImpl().
◆ isAtomicRet() [2/2]
Definition at line 824 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isAtomicRet().
◆ isBarrier()
Definition at line 1140 of file SIInstrInfo.h.
References isBarrierStart().
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ isBarrierStart()
Definition at line 1132 of file SIInstrInfo.h.
Referenced by isBarrier().
◆ isBasicBlockPrologue()
|
override |
Definition at line 10070 of file SIInstrInfo.cpp.
References canAddToBBProlog(), llvm::MachineFunction::getRegInfo(), and MI.
◆ isBlockLoadStore()
Definition at line 739 of file SIInstrInfo.h.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().
◆ isBranchOffsetInRange()
Definition at line 2845 of file SIInstrInfo.cpp.
References assert(), BranchOffsetBits, llvm::isIntN(), isSOPK(), and isSOPP().
◆ isBUF()
|
inlinestatic |
Definition at line 625 of file SIInstrInfo.h.
References isMTBUF(), isMUBUF(), and MI.
Referenced by mayAccessScratch().
◆ isBufferSMRD()
| bool SIInstrInfo::isBufferSMRD | ( | const MachineInstr & | MI | ) | const |
Definition at line 10178 of file SIInstrInfo.cpp.
◆ isCBranchVCCZRead()
|
inlinestatic |
Definition at line 850 of file SIInstrInfo.h.
◆ isChainCallOpcode()
Definition at line 914 of file SIInstrInfo.h.
◆ isCopyInstrImpl()
|
overrideprotected |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 2652 of file SIInstrInfo.cpp.
References MI.
◆ isDGEMM()
Definition at line 1015 of file SIInstrInfo.h.
References llvm::AMDGPU::getMAIIsDGEMM().
Referenced by isXDL().
◆ isDisableWQM() [1/2]
|
inlinestatic |
Definition at line 860 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isDisableWQM(), and MI.
◆ isDisableWQM() [2/2]
Definition at line 864 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isDisableWQM().
◆ isDOT() [1/2]
|
inlinestatic |
Definition at line 983 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isDOT(), and MI.
Referenced by isNeverCoissue(), and isXDL().
◆ isDOT() [2/2]
Definition at line 1009 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isDOT().
◆ isDPP() [1/2]
|
inlinestatic |
Definition at line 919 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isDPP(), and MI.
Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isLegalRegOperand(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and verifyInstruction().
◆ isDPP() [2/2]
Definition at line 921 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isDPP().
◆ isDS() [1/2]
|
inlinestatic |
Definition at line 639 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isDS(), and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::AMDGPU::classifyFlavor(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isLegalRegOperand(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldRunLdsBranchVmemWARHazardFixup(), and verifyInstruction().
◆ isDS() [2/2]
Definition at line 641 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isDS().
◆ isDualSourceBlendEXP()
|
inlinestatic |
Definition at line 802 of file SIInstrInfo.h.
References llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0, llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1, isEXP(), and MI.
◆ isEXP() [1/2]
|
inlinestatic |
Definition at line 800 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isEXP(), and MI.
Referenced by llvm::AMDGPU::getEventsForImpl(), llvm::GCNHazardRecognizer::getHazardType(), hasUnwantedEffectsWhenEXECEmpty(), isDualSourceBlendEXP(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().
◆ isEXP() [2/2]
Definition at line 810 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isEXP().
◆ isF16PseudoScalarTrans()
Definition at line 1171 of file SIInstrInfo.h.
Referenced by isOperandLegal().
◆ isFixedSize() [1/2]
|
inlinestatic |
Definition at line 1081 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isFixedSize(), and MI.
Referenced by getInstSizeInBytes().
◆ isFixedSize() [2/2]
Definition at line 1085 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isFixedSize().
◆ isFLAT() [1/2]
|
inlinestatic |
Definition at line 692 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isFLAT(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), getValueUniformity(), llvm::AMDGPU::getVmemHWEvent(), isHighLatencyDef(), isLDSDMA(), isLDSDMA(), isLdsDma(), legalizeOperands(), mayAccessFlatAddressSpace(), mayAccessLDSThroughFlat(), mayAccessScratch(), mayAccessVMEMThroughFlat(), moveFlatAddrToVGPR(), and verifyInstruction().
◆ isFLAT() [2/2]
Definition at line 723 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isFLAT().
◆ isFLATGlobal() [1/2]
|
inlinestatic |
Definition at line 706 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isFlatGlobal(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), and mayAccessScratch().
◆ isFLATGlobal() [2/2]
Definition at line 710 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isFlatGlobal().
◆ isFLATScratch() [1/2]
|
inlinestatic |
Definition at line 714 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isFlatScratch(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), mayAccessScratch(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isFLATScratch() [2/2]
Definition at line 718 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isFlatScratch().
◆ isFoldableCopy()
|
static |
◆ isFPAtomic() [1/2]
|
inlinestatic |
Definition at line 1117 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isFPAtomic(), and MI.
◆ isFPAtomic() [2/2]
Definition at line 1121 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isFPAtomic().
◆ isGather4() [1/2]
|
inlinestatic |
Definition at line 684 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isGather4(), and MI.
Referenced by verifyInstruction().
◆ isGather4() [2/2]
Definition at line 688 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isGather4().
◆ isGFX12CacheInvOrWBInst()
Definition at line 1166 of file SIInstrInfo.h.
References Opc.
Referenced by llvm::AMDGPU::getEventsForImpl().
◆ isGlobalMemoryObject()
|
override |
Definition at line 11416 of file SIInstrInfo.cpp.
References llvm::TargetInstrInfo::isGlobalMemoryObject(), isIGLP(), and MI.
◆ isGWS() [1/2]
|
inlinestatic |
Definition at line 654 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isGWS(), and MI.
Referenced by isAlwaysGDS().
◆ isGWS() [2/2]
Definition at line 656 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isGWS().
◆ isHighLatencyDef()
|
override |
Definition at line 9772 of file SIInstrInfo.cpp.
References llvm::get(), isFLAT(), isMIMG(), isMTBUF(), isMUBUF(), and Opc.
◆ isIGLP() [1/2]
|
inline |
◆ isIGLP() [2/2]
Definition at line 1187 of file SIInstrInfo.h.
Referenced by isGlobalMemoryObject().
◆ isIGLPMutationOnly()
Definition at line 1196 of file SIInstrInfo.h.
Referenced by hasIGLPInstrs(), llvm::GCNSchedStage::initGCNRegion(), and llvm::GCNIterativeScheduler::swapIGLPMutations().
◆ isIgnorableUse()
|
override |
Definition at line 175 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), and isVALU().
◆ isImage() [1/2]
|
inlinestatic |
Definition at line 502 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isImage(), and MI.
Referenced by getMemOperandsWithOffsetWidth(), llvm::AMDGPU::getVmemHWEvent(), legalizeOperands(), and verifyInstruction().
◆ isImage() [2/2]
Definition at line 506 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isImage().
◆ isImmOperandLegal() [1/3]
|
inline |
Definition at line 1359 of file SIInstrInfo.h.
References isImmOperandLegal(), and MI.
◆ isImmOperandLegal() [2/3]
| bool SIInstrInfo::isImmOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| unsigned | OpNo, | ||
| const MachineOperand & | MO ) const |
Definition at line 4788 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLiteralOperandLegal(), llvm::MachineOperand::isTargetIndex(), and llvm::MCInstrDesc::operands().
Referenced by isImmOperandLegal(), isImmOperandLegal(), isLegalToSwap(), and isOperandLegal().
◆ isImmOperandLegal() [3/3]
| bool SIInstrInfo::isImmOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| unsigned | OpNo, | ||
| int64_t | ImmVal ) const |
Definition at line 4774 of file SIInstrInfo.cpp.
References llvm::MCInstrDesc::getOpcode(), isInlineConstant(), isLiteralOperandLegal(), isMAI(), and llvm::MCInstrDesc::operands().
◆ isInlineConstant() [1/10]
Definition at line 4625 of file SIInstrInfo.cpp.
References llvm::APInt::getSExtValue(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), isInlineConstant(), llvm_unreachable, llvm::APFloatBase::S_BFloat, llvm::APFloatBase::S_IEEEdouble, llvm::APFloatBase::S_IEEEhalf, llvm::APFloatBase::S_IEEEsingle, and llvm::APFloatBase::SemanticsToEnum().
◆ isInlineConstant() [2/10]
Definition at line 4605 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralI16(), and llvm_unreachable.
Referenced by expandPostRAPseudo(), foldImmediate(), getInstSizeInBytes(), isImmOperandLegal(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isInlineConstant(), isLegalToSwap(), isOperandLegal(), legalizeOperandsVOP3(), usesConstantBus(), and verifyInstruction().
◆ isInlineConstant() [3/10]
|
inline |
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition at line 1306 of file SIInstrInfo.h.
References assert(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [4/10]
|
inline |
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition at line 1319 of file SIInstrInfo.h.
References isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [5/10]
|
inline |
Definition at line 1341 of file SIInstrInfo.h.
References llvm::MachineOperand::getImm(), isInlineConstant(), MI, and OpIdx.
◆ isInlineConstant() [6/10]
|
inline |
Definition at line 1324 of file SIInstrInfo.h.
References assert(), getOpSize(), isInlineConstant(), MI, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, OpIdx, and Size.
◆ isInlineConstant() [7/10]
|
inline |
Definition at line 1346 of file SIInstrInfo.h.
References llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().
◆ isInlineConstant() [8/10]
|
inline |
Definition at line 1299 of file SIInstrInfo.h.
References isInlineConstant().
◆ isInlineConstant() [9/10]
|
inline |
Definition at line 1292 of file SIInstrInfo.h.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and isInlineConstant().
◆ isInlineConstant() [10/10]
Definition at line 4644 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), llvm::AMDGPU::isInlinableLiteralV2BF16(), llvm::AMDGPU::isInlinableLiteralV2F16(), llvm::AMDGPU::isInlinableLiteralV2I16(), llvm::isInt(), isLegalAV64PseudoImm(), llvm::AMDGPU::isPKFMACF16InlineConstant(), llvm::isUInt(), llvm_unreachable, llvm::MCOI::OPERAND_GENERIC_0, llvm::MCOI::OPERAND_GENERIC_1, llvm::MCOI::OPERAND_GENERIC_2, llvm::MCOI::OPERAND_GENERIC_3, llvm::MCOI::OPERAND_GENERIC_4, llvm::MCOI::OPERAND_GENERIC_5, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM64, llvm::MCOI::OPERAND_PCREL, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOI::OPERAND_REGISTER, and llvm::MCOI::OPERAND_UNKNOWN.
◆ isKillTerminator()
Definition at line 10130 of file SIInstrInfo.cpp.
◆ isLDSDIR() [1/2]
|
inlinestatic |
Definition at line 1017 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isLDSDIR(), and MI.
Referenced by llvm::AMDGPU::getEventsForImpl().
◆ isLDSDIR() [2/2]
Definition at line 1021 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isLDSDIR().
◆ isLDSDMA() [1/2]
|
inlinestatic |
Definition at line 643 of file SIInstrInfo.h.
References isFLAT(), isMUBUF(), llvm::SIInstrFlags::isVALU(), MI, and llvm::SIInstrFlags::usesTENSOR_CNT().
Referenced by areMemAccessesTriviallyDisjoint(), llvm::AMDGPU::classifyFlavor(), llvm::AMDGPU::getExpertSchedulingEventType(), isCoexecutableVALUInst(), isVALU(), isVALU(), mayWriteLDSThroughDMA(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isLDSDMA() [2/2]
Definition at line 648 of file SIInstrInfo.h.
References llvm::get(), isFLAT(), isMUBUF(), llvm::SIInstrFlags::isVALU(), and llvm::SIInstrFlags::usesTENSOR_CNT().
◆ isLegalAV64PseudoImm()
Check if this immediate value can be used for AV_MOV_B64_IMM_PSEUDO.
Definition at line 4799 of file SIInstrInfo.cpp.
References llvm::Hi_32(), llvm::AMDGPU::isInlinableLiteral32(), and llvm::Lo_32().
Referenced by isInlineConstant().
◆ isLegalFLATOffset()
| bool SIInstrInfo::isLegalFLATOffset | ( | int64_t | Offset, |
| unsigned | AddrSpace, | ||
| AMDGPU::FlatAddrSpace | FlatVariant ) const |
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction with the given FlatVariant.
Definition at line 10274 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::isIntN(), N, and llvm::Offset.
Referenced by splitFlatOffset().
◆ isLegalGFX12PlusPackedMathFP32or64BitOperand()
| bool SIInstrInfo::isLegalGFX12PlusPackedMathFP32or64BitOperand | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI, | ||
| unsigned | SrcN, | ||
| const MachineOperand * | MO = nullptr ) const |
Check if MO would be a legal operand for gfx12+ packed math FP32 or 64 instructions.
Packed math FP32/FP64/U64 instructions typically accept SGPRs or VGPRs as source operands. On gfx12+, if a source operand uses SGPRs, the HW can only read the first SGPR and use it for both the low and high operations. SrcN can be 0, 1, or 2, representing src0, src1, and src2, respectively. If MO is nullptr, the operand corresponding to SrcN will be used.
Definition at line 6372 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, llvm::SISrcMods::OP_SEL_0, and llvm::SISrcMods::OP_SEL_1.
Referenced by isLegalRegOperand(), legalizeOperandsVOP3(), and verifyInstruction().
◆ isLegalMUBUFImmOffset()
Definition at line 10151 of file SIInstrInfo.cpp.
References getMaxMUBUFImmOffset().
◆ isLegalRegOperand() [1/2]
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand & | MO ) const |
Definition at line 6288 of file SIInstrInfo.cpp.
References llvm::enumerate(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::AMDGPU::getRegBitWidth(), I, isDPP(), isDS(), llvm::AMDGPU::isGFX12Plus(), isLegalGFX12PlusPackedMathFP32or64BitOperand(), isLegalRegOperand(), isMIMG(), llvm::AMDGPU::isPackedFP32or64BitInst(), llvm::MachineOperand::isReg(), isSALU(), MI, Opc, OpIdx, and llvm::MachineRegisterInfo::reservedRegsFrozen().
◆ isLegalRegOperand() [2/2]
| bool SIInstrInfo::isLegalRegOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO ) const |
Check if MO (a register operand) is a legal register for the given operand description or operand index.
The operand index version provide more legality checks
Definition at line 6263 of file SIInstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::MachineInstr::getMF(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::isReg().
Referenced by isLegalRegOperand(), isLegalToSwap(), isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().
◆ isLegalToSwap()
|
protected |
Definition at line 2721 of file SIInstrInfo.cpp.
References isImmOperandLegal(), isInlineConstant(), isLegalRegOperand(), llvm::MachineOperand::isReg(), isVALU(), MI, Opc, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.
Referenced by commuteInstructionImpl().
◆ isLegalVSrcOperand()
| bool SIInstrInfo::isLegalVSrcOperand | ( | const MachineRegisterInfo & | MRI, |
| const MCOperandInfo & | OpInfo, | ||
| const MachineOperand & | MO ) const |
Check if MO would be a valid operand for the given operand definition OpInfo.
Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).
Definition at line 6361 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTargetIndex().
◆ isLiteralOperandLegal()
| bool SIInstrInfo::isLiteralOperandLegal | ( | const MCInstrDesc & | InstDesc, |
| const MCOperandInfo & | OpInfo ) const |
Definition at line 4760 of file SIInstrInfo.cpp.
References llvm::AMDGPU::isSISrcOperand(), isVOP3(), and llvm::MCOI::OPERAND_IMMEDIATE.
Referenced by isImmOperandLegal(), and isImmOperandLegal().
◆ isLoadFromStackSlot() [1/2]
|
inlineoverride |
Definition at line 1610 of file SIInstrInfo.h.
References llvm::TypeSize::getZero(), isLoadFromStackSlot(), and MI.
Referenced by isLoadFromStackSlot().
◆ isLoadFromStackSlot() [2/2]
|
override |
Definition at line 9806 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), MI, and Register.
◆ isLoadMonitor()
Definition at line 1149 of file SIInstrInfo.h.
References Opc.
◆ isLowLatencyInstruction()
| bool SIInstrInfo::isLowLatencyInstruction | ( | const MachineInstr & | MI | ) | const |
Definition at line 9766 of file SIInstrInfo.cpp.
◆ isMAI() [1/3]
|
inlinestatic |
◆ isMAI() [2/3]
|
inlinestatic |
Definition at line 965 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isMAI().
Referenced by llvm::GCNHazardRecognizer::getHazardType(), isImmOperandLegal(), isMFMA(), isMFMA(), isXDL(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and pseudoToMCOpcode().
◆ isMAI() [3/3]
Definition at line 971 of file SIInstrInfo.h.
References llvm::get(), and isMAI().
Referenced by isMAI().
◆ isMFMA() [1/2]
|
inlinestatic |
Definition at line 973 of file SIInstrInfo.h.
Referenced by isMFMAorWMMA(), isMFMAorWMMA(), isNeverCoissue(), and llvm::GCNHazardRecognizer::ShouldPreferAnother().
◆ isMFMA() [2/2]
Definition at line 978 of file SIInstrInfo.h.
References isMAI().
◆ isMFMAorWMMA() [1/2]
|
inlinestatic |
Definition at line 993 of file SIInstrInfo.h.
References isMFMA(), isSWMMAC(), isWMMA(), and MI.
Referenced by llvm::AMDGPU::classifyFlavor().
◆ isMFMAorWMMA() [2/2]
Definition at line 997 of file SIInstrInfo.h.
References isMFMA(), isSWMMAC(), and isWMMA().
◆ isMIMG() [1/2]
|
inlinestatic |
Definition at line 660 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isMIMG(), and MI.
Referenced by getInstSizeInBytes(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isLegalRegOperand(), legalizeOperands(), and verifyInstruction().
◆ isMIMG() [2/2]
Definition at line 664 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isMIMG().
◆ isMTBUF() [1/2]
|
inlinestatic |
Definition at line 617 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isMTBUF(), and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), isBUF(), isHighLatencyDef(), and legalizeOperands().
◆ isMTBUF() [2/2]
Definition at line 621 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isMTBUF().
◆ isMUBUF() [1/2]
|
inlinestatic |
Definition at line 609 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isMUBUF(), and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getScratchInstrOffset(), isBUF(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyDef(), isLDSDMA(), isLDSDMA(), isLdsDma(), isLoadFromStackSlot(), isStoreToStackSlot(), legalizeOperands(), and llvm::SIRegisterInfo::needsFrameBaseReg().
◆ isMUBUF() [2/2]
Definition at line 613 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isMUBUF().
◆ isNeverCoissue()
| bool SIInstrInfo::isNeverCoissue | ( | MachineInstr & | MI | ) | const |
◆ isNeverUniform()
|
inlinestatic |
Definition at line 1125 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isNeverUniform(), and MI.
Referenced by getValueUniformity().
◆ isOperandLegal()
| bool SIInstrInfo::isOperandLegal | ( | const MachineInstr & | MI, |
| unsigned | OpIdx, | ||
| const MachineOperand * | MO = nullptr ) const |
Check if MO is a legal operand if it was the OpIdx Operand for MI.
Definition at line 6405 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSubReg(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), isF16PseudoScalarTrans(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isImm(), isImmOperandLegal(), llvm::AMDGPU::isInlinableLiteral64(), isInlineConstant(), isLegalRegOperand(), llvm::MachineOperand::isReg(), isSALU(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), isVOP3(), MI, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), OpIdx, regUsesConstantBus(), and usesConstantBus().
◆ isPacked() [1/2]
|
inlinestatic |
Definition at line 561 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isPacked(), and MI.
◆ isPacked() [2/2]
Definition at line 565 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isPacked().
◆ isReMaterializableImpl()
|
override |
Definition at line 129 of file SIInstrInfo.cpp.
References canRemat(), llvm::TargetInstrInfo::isReMaterializableImpl(), and MI.
◆ isSafeToSink()
|
override |
Definition at line 182 of file SIInstrInfo.cpp.
References llvm::GenericCycle< ContextT >::contains(), llvm::GenericCycleInfo< ContextT >::getCycle(), llvm::GenericCycle< ContextT >::getExitingBlocks(), llvm::MachineInstr::getParent(), llvm::GenericCycle< ContextT >::getParentCycle(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getVRegDef(), hasDivergentBranch(), and MI.
◆ isSALU() [1/2]
|
inlinestatic |
Definition at line 476 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSALU(), and MI.
Referenced by canRemat(), llvm::AMDGPU::classifyFlavor(), getInstSizeInBytes(), isLegalRegOperand(), isOperandLegal(), isSGPRSpill(), isSGPRSpill(), mayReadEXEC(), shouldReadExec(), and verifyInstruction().
◆ isSALU() [2/2]
Definition at line 480 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSALU().
◆ isSBarrierSCCWrite()
Definition at line 844 of file SIInstrInfo.h.
Referenced by llvm::AMDGPU::getEventsForImpl().
◆ isScalarStore() [1/2]
|
inlinestatic |
- Returns
- true if this is an s_store_dword* instruction. This is more specific than isSMEM && mayStore.
Definition at line 1073 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isScalarStore(), and MI.
◆ isScalarStore() [2/2]
Definition at line 1077 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isScalarStore().
◆ isScalarUnit()
|
inlinestatic |
Definition at line 1033 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSALU(), llvm::SIInstrFlags::isSMRD(), and MI.
◆ isSchedulingBoundary()
|
override |
Definition at line 4404 of file SIInstrInfo.cpp.
References changesVGPRIndexingMode(), MBB, and MI.
◆ isSDWA() [1/2]
|
inlinestatic |
Definition at line 593 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSDWA(), and MI.
Referenced by canRemat(), getDstSelForwardingOperand(), and verifyInstruction().
◆ isSDWA() [2/2]
Definition at line 597 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSDWA().
◆ isSegmentSpecificFLAT() [1/2]
|
inlinestatic |
Definition at line 698 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSegmentSpecificFLAT(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), legalizeOperandsFLAT(), and moveFlatAddrToVGPR().
◆ isSegmentSpecificFLAT() [2/2]
Definition at line 702 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSegmentSpecificFLAT().
◆ isSGPRSpill() [1/2]
|
inlinestatic |
Definition at line 885 of file SIInstrInfo.h.
References isSALU(), isSpill(), and MI.
Referenced by canAddToBBProlog(), isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSGPRSpill() [2/2]
Definition at line 891 of file SIInstrInfo.h.
◆ isSGPRStackAccess()
| Register SIInstrInfo::isSGPRStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex, | ||
| TypeSize & | MemBytes ) const |
Definition at line 9794 of file SIInstrInfo.cpp.
References assert(), llvm::TypeSize::getFixed(), llvm::MachineOperand::getIndex(), getNamedOperand(), getOpSize(), llvm::MachineOperand::isFI(), and MI.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isSMRD() [1/2]
|
inlinestatic |
Definition at line 629 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSMRD(), and MI.
Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), breaksSMEMSoftClause(), canRemat(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isSMRD() [2/2]
Definition at line 633 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSMRD().
◆ isSOP1() [1/2]
|
inlinestatic |
Definition at line 521 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSOP1(), and MI.
◆ isSOP1() [2/2]
Definition at line 525 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSOP1().
◆ isSOP2() [1/2]
|
inlinestatic |
Definition at line 529 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSOP2(), and MI.
Referenced by verifyInstruction().
◆ isSOP2() [2/2]
Definition at line 533 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSOP2().
◆ isSOPC() [1/2]
|
inlinestatic |
Definition at line 537 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSOPC(), and MI.
Referenced by verifyInstruction().
◆ isSOPC() [2/2]
Definition at line 541 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSOPC().
◆ isSOPK() [1/2]
|
inlinestatic |
Definition at line 545 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSOPK(), and MI.
Referenced by isBranchOffsetInRange(), and verifyInstruction().
◆ isSOPK() [2/2]
Definition at line 549 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSOPK().
◆ isSOPP() [1/2]
|
inlinestatic |
Definition at line 553 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSOPP(), and MI.
Referenced by isBranchOffsetInRange().
◆ isSOPP() [2/2]
Definition at line 557 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSOPP().
◆ isSpill() [1/3]
|
inlinestatic |
Definition at line 905 of file SIInstrInfo.h.
Referenced by isSpill().
◆ isSpill() [2/3]
|
inlinestatic |
Definition at line 901 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSpill().
◆ isSpill() [3/3]
Definition at line 897 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSpill().
Referenced by isSGPRSpill(), isSGPRSpill(), isVGPRSpill(), isVGPRSpill(), and verifyInstruction().
◆ isStackAccess()
| Register SIInstrInfo::isStackAccess | ( | const MachineInstr & | MI, |
| int & | FrameIndex, | ||
| TypeSize & | MemBytes ) const |
Definition at line 9777 of file SIInstrInfo.cpp.
References assert(), llvm::TypeSize::getFixed(), llvm::MachineOperand::getIndex(), getNamedOperand(), getOpSize(), llvm::MachineOperand::isFI(), MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, and Register.
Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().
◆ isStoreToStackSlot() [1/2]
|
inlineoverride |
Definition at line 1619 of file SIInstrInfo.h.
References llvm::TypeSize::getZero(), isStoreToStackSlot(), and MI.
Referenced by isStoreToStackSlot().
◆ isStoreToStackSlot() [2/2]
|
override |
Definition at line 9821 of file SIInstrInfo.cpp.
References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), MI, and Register.
◆ isSWMMAC() [1/2]
|
inlinestatic |
Definition at line 1001 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isSWMMAC(), and MI.
Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), getWMMAHazardInstInCategory(), isCoexecutableVALUInst(), isMFMAorWMMA(), isMFMAorWMMA(), and isXDLWMMA().
◆ isSWMMAC() [2/2]
Definition at line 1005 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isSWMMAC().
◆ isTRANS() [1/2]
|
inlinestatic |
Definition at line 923 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isTRANS(), and MI.
Referenced by llvm::AMDGPU::classifyFlavor(), and isNeverCoissue().
◆ isTRANS() [2/2]
Definition at line 927 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isTRANS().
◆ isVALU() [1/2]
|
inlinestatic |
Definition at line 484 of file SIInstrInfo.h.
References isLDSDMA(), llvm::SIInstrFlags::isVALU(), and MI.
Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), llvm::AMDGPU::classifyFlavor(), getDstSelForwardingOperand(), llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isCoexecutableVALUInst(), isIgnorableUse(), isLdsDma(), isLegalToSwap(), isNeverCoissue(), isOperandLegal(), isVGPRSpill(), isVGPRSpill(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().
◆ isVALU() [2/2]
LDSDMA instructions act as both VALU and memory instructions, thus we also tag them as VALU.
However, in many places, we do not actually want to include LDSDMA instructions in this query. By setting AllowLDSDMA to false, this will return false for LDSDMA instructions.
Definition at line 495 of file SIInstrInfo.h.
References llvm::get(), isLDSDMA(), and llvm::SIInstrFlags::isVALU().
◆ isVGPRCopy()
|
inline |
Definition at line 1249 of file SIInstrInfo.h.
References assert(), llvm::MachineFunction::getRegInfo(), and MI.
◆ isVGPRSpill() [1/2]
|
inlinestatic |
Definition at line 873 of file SIInstrInfo.h.
References isSpill(), isVALU(), and MI.
Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().
◆ isVGPRSpill() [2/2]
Definition at line 879 of file SIInstrInfo.h.
◆ isVIMAGE() [1/2]
|
inlinestatic |
Definition at line 668 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVIMAGE(), and MI.
Referenced by legalizeOperands().
◆ isVIMAGE() [2/2]
Definition at line 672 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVIMAGE().
◆ isVINTERP() [1/2]
|
inlinestatic |
Definition at line 1025 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVINTERP(), and MI.
◆ isVINTERP() [2/2]
Definition at line 1029 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVINTERP().
◆ isVINTRP() [1/2]
|
inlinestatic |
Definition at line 957 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVINTRP(), and MI.
◆ isVINTRP() [2/2]
Definition at line 961 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVINTRP().
◆ isVMEM() [1/2]
|
inlinestatic |
Definition at line 510 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVMEM(), and MI.
Referenced by breaksVMEMSoftClause(), llvm::AMDGPU::classifyFlavor(), llvm::AMDGPU::getEventsForImpl(), llvm::GCNHazardRecognizer::getHazardType(), llvm::AMDGPU::getVmemHWEvent(), isVMEMClauseInst(), isVMEMLoad(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldRunLdsBranchVmemWARHazardFixup().
◆ isVMEM() [2/2]
Definition at line 514 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVMEM().
◆ isVOP1() [1/2]
|
inlinestatic |
Definition at line 569 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVOP1(), and MI.
Referenced by canRemat().
◆ isVOP1() [2/2]
Definition at line 573 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVOP1().
◆ isVOP2() [1/2]
|
inlinestatic |
Definition at line 577 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVOP2(), and MI.
Referenced by canRemat(), legalizeOperands(), and verifyInstruction().
◆ isVOP2() [2/2]
Definition at line 581 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVOP2().
◆ isVOP3() [1/3]
|
inlinestatic |
◆ isVOP3() [2/3]
|
inlinestatic |
Definition at line 585 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVOP3().
Referenced by canRemat(), llvm::SIRegisterInfo::eliminateFrameIndex(), isLiteralOperandLegal(), isOperandLegal(), legalizeOperands(), moveToVALUImpl(), and verifyInstruction().
◆ isVOP3() [3/3]
Definition at line 591 of file SIInstrInfo.h.
References llvm::get(), and isVOP3().
Referenced by isVOP3().
◆ isVOP3P() [1/2]
|
inlinestatic |
Definition at line 931 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVOP3P(), and MI.
◆ isVOP3P() [2/2]
Definition at line 935 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVOP3P().
◆ isVOP3PMix() [1/2]
|
inline |
Definition at line 939 of file SIInstrInfo.h.
References isVOP3PMix(), and MI.
Referenced by isVOP3PMix().
◆ isVOP3PMix() [2/2]
Definition at line 943 of file SIInstrInfo.h.
◆ isVOPC() [1/2]
|
inlinestatic |
Definition at line 601 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVOPC(), and MI.
Referenced by legalizeOperands(), and verifyInstruction().
◆ isVOPC() [2/2]
Definition at line 605 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVOPC().
◆ isVOPDAntidependencyAllowed()
| bool llvm::SIInstrInfo::isVOPDAntidependencyAllowed | ( | const MachineInstr & | OpX | ) | const |
If OpX is multicycle, anti-dependencies are not allowed.
isDPMACCInstruction was not designed for VOPD, but it is fit for the purpose.
Definition at line 10702 of file SIInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm::AMDGPU::isDPMACCInstruction().
◆ isVSAMPLE() [1/2]
|
inlinestatic |
Definition at line 676 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isVSAMPLE(), and MI.
Referenced by llvm::AMDGPU::getVmemHWEvent(), legalizeOperands(), and verifyInstruction().
◆ isVSAMPLE() [2/2]
Definition at line 680 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isVSAMPLE().
◆ isWaitcnt()
Definition at line 1225 of file SIInstrInfo.h.
References getNonSoftWaitcntOpcode().
◆ isWave32()
| bool llvm::SIInstrInfo::isWave32 | ( | ) | const |
Definition at line 10688 of file SIInstrInfo.cpp.
◆ isWMMA() [1/2]
|
inlinestatic |
Definition at line 985 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isWMMA(), and MI.
Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), isCoexecutableVALUInst(), isMFMAorWMMA(), isMFMAorWMMA(), and isXDLWMMA().
◆ isWMMA() [2/2]
Definition at line 989 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isWMMA().
◆ isWQM() [1/2]
|
inlinestatic |
Definition at line 856 of file SIInstrInfo.h.
References llvm::SIInstrFlags::isWQM(), and MI.
◆ isWQM() [2/2]
Definition at line 858 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::isWQM().
◆ isWWMRegSpillOpcode()
Definition at line 907 of file SIInstrInfo.h.
Referenced by canAddToBBProlog().
◆ isXcntDrain()
|
static |
◆ isXDL()
| bool SIInstrInfo::isXDL | ( | const MachineInstr & | MI | ) | const |
Definition at line 11433 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getMAIIsGFX940XDL(), isDGEMM(), isDOT(), llvm::AMDGPU::isGFX12Plus(), isMAI(), isXDLWMMA(), and MI.
◆ isXDLWMMA()
| bool SIInstrInfo::isXDLWMMA | ( | const MachineInstr & | MI | ) | const |
Definition at line 11423 of file SIInstrInfo.cpp.
References llvm::AMDGPU::getWMMAIsXDL(), isSWMMAC(), isWMMA(), and MI.
Referenced by isXDL().
◆ legalizeGenericOperand()
| void SIInstrInfo::legalizeGenericOperand | ( | MachineBasicBlock & | InsertMBB, |
| MachineBasicBlock::iterator | I, | ||
| const TargetRegisterClass * | DstRC, | ||
| MachineOperand & | Op, | ||
| MachineRegisterInfo & | MRI, | ||
| const DebugLoc & | DL ) const |
Definition at line 6971 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, foldImmediate(), llvm::get(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::getVRegDef(), I, and llvm::Implicit.
Referenced by legalizeOperands().
◆ legalizeOperands()
| MachineBasicBlock * SIInstrInfo::legalizeOperands | ( | MachineInstr & | MI, |
| MachineDominatorTree * | MDT = nullptr ) const |
Legalize all operands in this instruction.
This function may create new instructions and control-flow around MI. If present, MDT is updated.
- Returns
- A new basic block that contains
MIif new blocks were created.
Definition at line 7331 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineRegisterInfo::createVirtualRegister(), createWaterFallForSiCall(), llvm::Dead, DL, extractRsrcPtr(), generateWaterFallLoop(), llvm::get(), llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::AMDGPU::getIfAddr64Inst(), getNamedImmOperand(), getNamedOperand(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), I, isFLAT(), llvm::AMDGPU::isGraphics(), isImage(), isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isVIMAGE(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), llvm::Kill, legalizeGenericOperand(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), MBB, MI, llvm::Offset, readlaneVGPRToSGPR(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by foldImmediate(), and moveToVALUImpl().
◆ legalizeOperandsFLAT()
| void SIInstrInfo::legalizeOperandsFLAT | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Definition at line 6950 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineRegisterInfo::getRegClass(), isSegmentSpecificFLAT(), MI, moveFlatAddrToVGPR(), readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsSMRD()
| void SIInstrInfo::legalizeOperandsSMRD | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Definition at line 6850 of file SIInstrInfo.cpp.
References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), MI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVALUt16() [1/2]
| void SIInstrInfo::legalizeOperandsVALUt16 | ( | MachineInstr & | Inst, |
| MachineRegisterInfo & | MRI ) const |
Fix operands in Inst to fix 16bit SALU to VALU lowering.
Definition at line 7732 of file SIInstrInfo.cpp.
References legalizeOperandsVALUt16(), MI, and OpIdx.
Referenced by legalizeOperandsVALUt16(), and moveToVALUImpl().
◆ legalizeOperandsVALUt16() [2/2]
| void SIInstrInfo::legalizeOperandsVALUt16 | ( | MachineInstr & | Inst, |
| unsigned | OpIdx, | ||
| MachineRegisterInfo & | MRI ) const |
Definition at line 7694 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::get(), llvm::MachineRegisterInfo::getRegClass(), MBB, MI, OpIdx, and llvm::Undef.
◆ legalizeOperandsVOP2()
| void SIInstrInfo::legalizeOperandsVOP2 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Legalize operands in MI by either commuting it or inserting a copy of src1.
Definition at line 6591 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, findImplicitSGPRRead(), fixImplicitOperands(), llvm::get(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), llvm_unreachable, MI, Opc, llvm::MCInstrDesc::operands(), and llvm::MachineOperand::setSubReg().
Referenced by legalizeOperands().
◆ legalizeOperandsVOP3()
| void SIInstrInfo::legalizeOperandsVOP3 | ( | MachineRegisterInfo & | MRI, |
| MachineInstr & | MI ) const |
Fix operands in MI to satisfy constant bus requirements.
Definition at line 6702 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), I, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::AMDGPU::isGFX12Plus(), isInlineConstant(), isLegalGFX12PlusPackedMathFP32or64BitOperand(), llvm::AMDGPU::isPackedFP32or64BitInst(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), MI, and Opc.
Referenced by legalizeOperands().
◆ legalizeOpWithMove()
| void SIInstrInfo::legalizeOpWithMove | ( | MachineInstr & | MI, |
| unsigned | OpIdx ) const |
Legalize the OpIndex operand of this instruction by inserting a MOV.
For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1
If the operand being legalized is a register, then a COPY will be used instead of MOV.
Definition at line 6197 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::get(), I, llvm::MachineOperand::isReg(), MBB, MI, OpIdx, and Size.
Referenced by legalizeOperandsVOP2(), and legalizeOperandsVOP3().
◆ loadRegFromStackSlot()
|
override |
Definition at line 1791 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), DL, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFunction::getRegInfo(), getSGPRSpillRestoreOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVectorRegSpillRestoreOpcode(), llvm::Implicit, llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), and llvm::TargetStackID::SGPRSpill.
◆ mayAccessFlatAddressSpace()
| bool SIInstrInfo::mayAccessFlatAddressSpace | ( | const MachineInstr & | MI | ) | const |
Definition at line 9945 of file SIInstrInfo.cpp.
References llvm::AMDGPUAS::FLAT_ADDRESS, llvm::MachineMemOperand::getAddrSpace(), isFLAT(), and MI.
◆ mayAccessLDSThroughFlat()
| bool SIInstrInfo::mayAccessLDSThroughFlat | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for FLAT instructions that can access LDS.
Definition at line 4500 of file SIInstrInfo.cpp.
References assert(), llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, and usesLGKM_CNT().
◆ mayAccessScratch()
| bool SIInstrInfo::mayAccessScratch | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for SCRATCH_ instructions, or FLAT/BUF instructions unless the MMOs do not include scratch. Conservatively correct; will return true if
MIcannot be proven to not hit scratch.
Definition at line 4442 of file SIInstrInfo.cpp.
References llvm::any_of(), isBUF(), isFLAT(), isFLATGlobal(), isFLATScratch(), MI, and llvm::AMDGPUAS::PRIVATE_ADDRESS.
◆ mayAccessVMEMThroughFlat()
| bool SIInstrInfo::mayAccessVMEMThroughFlat | ( | const MachineInstr & | MI | ) | const |
- Returns
- true for FLAT instructions that can access VMEM.
Definition at line 4473 of file SIInstrInfo.cpp.
References assert(), isFLAT(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, llvm::AMDGPUAS::REGION_ADDRESS, and usesVM_CNT().
◆ mayReadEXEC()
| bool SIInstrInfo::mayReadEXEC | ( | const MachineRegisterInfo & | MRI, |
| const MachineInstr & | MI ) const |
Returns true if the instruction could potentially depend on the value of exec.
If false, exec dependencies may safely be ignored.
Definition at line 4580 of file SIInstrInfo.cpp.
References isSALU(), llvm::isTargetSpecificOpcode(), and MI.
◆ mayWriteLDSThroughDMA()
|
inlinestatic |
Definition at line 836 of file SIInstrInfo.h.
References isLDSDMA(), MI, and Opc.
Referenced by llvm::AMDGPU::getVmemHWEvent().
◆ modifiesModeRegister()
|
static |
Return true if the instruction modifies the mode register.q.
Definition at line 4526 of file SIInstrInfo.cpp.
References llvm::is_contained(), and MI.
Referenced by hasUnwantedEffectsWhenEXECEmpty().
◆ moveFlatAddrToVGPR()
| bool SIInstrInfo::moveFlatAddrToVGPR | ( | MachineInstr & | Inst | ) | const |
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
- Returns
- true if succeeded.
Definition at line 6869 of file SIInstrInfo.cpp.
References llvm::MachineRegisterInfo::addRegOperandToUseList(), assert(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getGlobalVaddrOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), isFLAT(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isMoveImmediate(), isSegmentSpecificFLAT(), llvm::MachineRegisterInfo::moveOperands(), Opc, llvm::MachineInstr::removeOperand(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), llvm::MachineInstr::setDesc(), llvm::MachineInstr::tieOperands(), llvm::MachineInstr::untieRegOperand(), and llvm::MachineRegisterInfo::use_nodbg_empty().
Referenced by legalizeOperandsFLAT().
◆ moveToVALU()
| void SIInstrInfo::moveToVALU | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT ) const |
Replace the instructions opcode with the equivalent VALU opcode.
This function will also move the users of MachineInstruntions in the WorkList to the VALU if necessary. If present, MDT is updated.
Definition at line 7765 of file SIInstrInfo.cpp.
References assert(), createWaterFallForSiCall(), llvm::SIInstrWorklist::empty(), llvm::SIInstrWorklist::erase_top(), llvm::SIInstrWorklist::getDeferredList(), llvm::SIInstrWorklist::isDeferred(), moveToVALUImpl(), and llvm::SIInstrWorklist::top().
◆ moveToVALUImpl()
| void SIInstrInfo::moveToVALUImpl | ( | SIInstrWorklist & | Worklist, |
| MachineDominatorTree * | MDT, | ||
| MachineInstr & | Inst, | ||
| DenseMap< MachineInstr *, V2PhysSCopyInfo > & | WaterFalls, | ||
| DenseMap< MachineInstr *, bool > & | V2SPhyCopiesToErase ) const |
Definition at line 7875 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::LaneMaskConstants::AndOpc, assert(), llvm::BitWidth, llvm::BuildMI(), Changed, llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Define, DL, llvm::MachineInstr::eraseFromParent(), llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::MachineInstr::explicit_operands(), llvm::MachineInstr::findRegisterDefOperandIdx(), fixImplicitOperands(), llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineRegisterInfo::getRegClass(), getVALUOp(), llvm::AMDGPUSubtarget::GFX12, handleCopyToPhysHelper(), llvm::AMDGPU::hasNamedOperand(), llvm::MachineInstr::implicit_operands(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::Register::isVirtual(), isVOP3(), legalizeOperands(), legalizeOperandsVALUt16(), llvm_unreachable, llvm::make_early_inc_range(), MBB, llvm::Offset, Opc, OpIdx, llvm::MachineInstr::removeOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstrBuilder::setMIFlags(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), Size, llvm::Undef, llvm::MachineRegisterInfo::use_operands(), UseMI, and llvm::AMDGPU::LaneMaskConstants::VccReg.
Referenced by moveToVALU().
◆ mutateAndCleanupImplicit()
| void SIInstrInfo::mutateAndCleanupImplicit | ( | MachineInstr & | MI, |
| const MCInstrDesc & | NewDesc ) const |
Definition at line 3473 of file SIInstrInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, I, and MI.
◆ optimizeCompareInstr()
|
override |
Definition at line 11171 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::countr_zero(), foldableSelect(), llvm::get(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::has_single_bit(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isImm(), llvm::Register::isPhysical(), llvm::isPowerOf2_64(), llvm::MachineOperand::isReg(), llvm::maxUIntN(), MBB, Select, setsSCCIfResultIsNonZero(), setsSCCIfResultIsZero(), and llvm::MachineRegisterInfo::use_nodbg_empty().
◆ physRegUsesConstantBus()
| bool SIInstrInfo::physRegUsesConstantBus | ( | const MachineOperand & | Reg | ) | const |
Definition at line 4956 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImplicit().
Referenced by regUsesConstantBus(), and usesConstantBus().
◆ pseudoToMCOpcode()
| int SIInstrInfo::pseudoToMCOpcode | ( | int | Opcode | ) | const |
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 10416 of file SIInstrInfo.cpp.
References assert(), llvm::get(), llvm::AMDGPU::getMCOpcode(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNonSoftWaitcntOpcode(), llvm::AMDGPUSubtarget::GFX10, llvm::SIEncodingFamily::GFX11, llvm::SIEncodingFamily::GFX12, llvm::SIEncodingFamily::GFX80, llvm::AMDGPUSubtarget::GFX9, llvm::SIEncodingFamily::GFX9, llvm::SIEncodingFamily::GFX90A, llvm::SIEncodingFamily::GFX940, isAsmOnlyOpcode(), llvm::SIInstrFlags::isD16Buf(), isMAI(), isRenamedInGFX9(), llvm::SIInstrFlags::isSDWA(), llvm::SIEncodingFamily::SDWA, llvm::SIEncodingFamily::SDWA10, llvm::SIEncodingFamily::SDWA9, and subtargetEncodingFamily().
Referenced by commuteOpcode(), foldImmediate(), getMCOpcodeFromPseudo(), and hasVALU32BitEncoding().
◆ readlaneVGPRToSGPR()
| Register SIInstrInfo::readlaneVGPRToSGPR | ( | Register | SrcReg, |
| MachineInstr & | UseMI, | ||
| MachineRegisterInfo & | MRI, | ||
| const TargetRegisterClass * | DstRC = nullptr ) const |
Copy a value from a VGPR (SrcReg) to SGPR.
The desired register class for the dst register (DstRC) can be optionally supplied. This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.
- Returns
- The SGPR register that
SrcRegwas copied to.
Definition at line 6804 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::get(), llvm::MachineRegisterInfo::getRegClass(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.
Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().
◆ regUsesConstantBus()
| bool SIInstrInfo::regUsesConstantBus | ( | const MachineOperand & | Reg, |
| const MachineRegisterInfo & | MRI ) const |
Definition at line 4974 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::Register::isVirtual(), and physRegUsesConstantBus().
Referenced by isOperandLegal().
◆ reMaterialize()
|
override |
Definition at line 2465 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::LaneBitmask::all(), assert(), llvm::BuildMI(), llvm::Define, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getMachineMemOperand(), getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::Hi_32(), I, llvm::MachineOperand::isImm(), llvm::Lo_32(), MBB, llvm::MachineInstr::memoperands(), MI, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::reMaterialize(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setReg(), llvm::MachineRegisterInfo::setRegClass(), llvm::MachineOperand::setSubReg(), llvm::Undef, and llvm::MachineRegisterInfo::use_nodbg_empty().
◆ removeBranch()
|
override |
Definition at line 3140 of file SIInstrInfo.cpp.
References llvm::Count, getInstSizeInBytes(), llvm::make_early_inc_range(), MBB, and MI.
◆ removeModOperands()
| void SIInstrInfo::removeModOperands | ( | MachineInstr & | MI | ) | const |
Definition at line 3464 of file SIInstrInfo.cpp.
References MI, ModifierOpNames, Opc, and llvm::reverse().
Referenced by foldImmediate().
◆ restoreExec()
| void SIInstrInfo::restoreExec | ( | MachineFunction & | MF, |
| MachineBasicBlock & | MBB, | ||
| MachineBasicBlock::iterator | MBBI, | ||
| const DebugLoc & | DL, | ||
| Register | Reg, | ||
| SlotIndexes * | Indexes = nullptr ) const |
Definition at line 6155 of file SIInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::AMDGPU::LaneMaskConstants::ExecReg, llvm::AMDGPU::LaneMaskConstants::get(), llvm::get(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::Kill, MBB, MBBI, and llvm::AMDGPU::LaneMaskConstants::MovOpc.
◆ reverseBranchCondition()
|
override |
Definition at line 3218 of file SIInstrInfo.cpp.
References Cond, and llvm::getImm().
◆ setsSCCIfResultIsNonZero()
|
inlinestatic |
◆ shouldClusterMemOps()
|
override |
Definition at line 545 of file SIInstrInfo.cpp.
References llvm::DefaultMemoryClusterDWordsLimit, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaxMemoryClusterDWords(), llvm::MachineInstr::getMF(), and memOpsHaveSameBasePtr().
◆ shouldScheduleLoadsNear()
|
override |
Definition at line 597 of file SIInstrInfo.cpp.
References assert().
◆ sopkIsZext()
Definition at line 1063 of file SIInstrInfo.h.
Referenced by verifyInstruction().
◆ splitFlatOffset()
| std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset | ( | int64_t | COffsetVal, |
| unsigned | AddrSpace, | ||
| AMDGPU::FlatAddrSpace | FlatVariant ) const |
Split COffsetVal into {immediate offset field, remainder offset} values.
Definition at line 10299 of file SIInstrInfo.cpp.
References allowNegativeFlatOffset(), assert(), D(), llvm::AMDGPU::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), isLegalFLATOffset(), and llvm::maskTrailingOnes().
◆ splitMUBUFOffset()
| bool SIInstrInfo::splitMUBUFOffset | ( | uint32_t | Imm, |
| uint32_t & | SOffset, | ||
| uint32_t & | ImmOffset, | ||
| Align | Alignment = Align(4) ) const |
Definition at line 10198 of file SIInstrInfo.cpp.
References llvm::alignDown(), getMaxMUBUFImmOffset(), High, llvm::Low, llvm::AMDGPUSubtarget::SEA_ISLANDS, and llvm::Align::value().
◆ storeRegToStackSlot()
|
override |
Definition at line 1638 of file SIInstrInfo.cpp.
◆ storeRegToStackSlotCFI()
| void SIInstrInfo::storeRegToStackSlotCFI | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| Register | SrcReg, | ||
| bool | isKill, | ||
| int | FrameIndex, | ||
| const TargetRegisterClass * | RC ) const |
Definition at line 1646 of file SIInstrInfo.cpp.
References MBB, MI, llvm::MachineInstr::NoFlags, and Register.
◆ swapSourceModifiers()
|
protected |
Definition at line 2659 of file SIInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), MI, and llvm::MachineOperand::setImm().
Referenced by commuteInstructionImpl().
◆ usesASYNC_CNT() [1/2]
|
inlinestatic |
Definition at line 1045 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::usesASYNC_CNT().
◆ usesASYNC_CNT() [2/2]
Definition at line 1049 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::usesASYNC_CNT().
◆ usesConstantBus() [1/2]
|
inline |
Definition at line 1382 of file SIInstrInfo.h.
References MI, OpIdx, and usesConstantBus().
◆ usesConstantBus() [2/2]
| bool SIInstrInfo::usesConstantBus | ( | const MachineRegisterInfo & | MRI, |
| const MachineOperand & | MO, | ||
| const MCOperandInfo & | OpInfo ) const |
Returns true if this operand uses the constant bus.
Definition at line 4981 of file SIInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), and physRegUsesConstantBus().
Referenced by isOperandLegal(), usesConstantBus(), and verifyInstruction().
◆ usesFPDPRounding() [1/2]
|
inlinestatic |
Definition at line 1109 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::usesFPDPRounding().
◆ usesFPDPRounding() [2/2]
Definition at line 1113 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::usesFPDPRounding().
◆ usesLGKM_CNT()
|
inlinestatic |
Definition at line 1041 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::usesLGKM_CNT().
Referenced by mayAccessLDSThroughFlat().
◆ usesTENSOR_CNT() [1/2]
|
inlinestatic |
Definition at line 1053 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::TENSOR_CNT.
◆ usesTENSOR_CNT() [2/2]
Definition at line 1057 of file SIInstrInfo.h.
References llvm::get(), and llvm::SIInstrFlags::TENSOR_CNT.
◆ usesVM_CNT()
|
inlinestatic |
Definition at line 1037 of file SIInstrInfo.h.
References MI, and llvm::SIInstrFlags::usesVM_CNT().
Referenced by mayAccessVMEMThroughFlat().
◆ verifyInstruction()
|
override |
Definition at line 5065 of file SIInstrInfo.cpp.
References llvm::SISrcMods::ABS, llvm::all_of(), assert(), compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::Data, llvm::dbgs(), llvm::divideCeil(), llvm::AMDGPU::SDWA::DWORD, findImplicitSGPRRead(), llvm::get(), llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::getImm(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), getOpRegClass(), getOpSize(), llvm::MachineOperand::getReg(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::AMDGPUSubtarget::GFX10, I, llvm::is_contained(), llvm::AMDGPU::isDPALU_DPP(), isDPP(), isDS(), llvm::MachineOperand::isFI(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::AMDGPU::isGFX12Plus(), llvm::MachineOperand::isIdenticalTo(), isImage(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::isInt(), llvm::AMDGPU::isLegalDPALU_DPPControl(), isLegalGFX12PlusPackedMathFP32or64BitOperand(), isMIMG(), llvm::AMDGPU::isPackedFP32or64BitInst(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), isRegOrFI(), isSALU(), isSDWA(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSpill(), llvm::MachineRegisterInfo::isSSA(), isSubRegOf(), llvm::isUInt(), llvm::MachineOperand::isUse(), llvm::AMDGPU::isValid32BitLiteral(), isVALU(), isVGPRSpill(), llvm::Register::isVirtual(), isVOP2(), isVOP3(), isVOPC(), isVSAMPLE(), LLVM_DEBUG, MI, llvm::InlineAsm::MIOp_FirstOperand, llvm::SISrcMods::NEG, llvm::Offset, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM64, llvm::MCOI::OPERAND_MEMORY, llvm::MCOI::OPERAND_PCREL, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOI::OPERAND_REGISTER, llvm::AMDGPU::OPERAND_SDWA_VOPC_DST, llvm::MCOI::OPERAND_UNKNOWN, OpIdx, llvm::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::CPol::SCAL, llvm::SISrcMods::SEXT, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::supportsScaleOffset(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, usesConstantBus(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/SIInstrInfo.h
- lib/Target/AMDGPU/SIInstrInfo.cpp
Generated on for LLVM by
1.14.0