addDispatchID(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addDispatchPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addFlatScratchInit(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addImplicitBufferPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addKernargSegmentPtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addPrivateSegmentBuffer(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addPrivateSegmentWaveByteOffset() | llvm::SIMachineFunctionInfo | inline |
addQueuePtr(const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
addReservedUserSGPR() | llvm::SIMachineFunctionInfo | inline |
addToSpilledSGPRs(unsigned num) | llvm::SIMachineFunctionInfo | inline |
addToSpilledVGPRs(unsigned num) | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDX() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDY() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupIDZ() | llvm::SIMachineFunctionInfo | inline |
addWorkGroupInfo() | llvm::SIMachineFunctionInfo | inline |
allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV) | llvm::AMDGPUMachineFunction | |
allocateModuleLDSGlobal(const Function &F) | llvm::AMDGPUMachineFunction | |
allocateSGPRSpillToVGPR(MachineFunction &MF, int FI) | llvm::SIMachineFunctionInfo | |
allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR) | llvm::SIMachineFunctionInfo | |
allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
AMDGPUMachineFunction(const MachineFunction &MF) | llvm::AMDGPUMachineFunction | |
BasePointerSaveIndex | llvm::SIMachineFunctionInfo | |
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override | llvm::SIMachineFunctionInfo | virtual |
create(BumpPtrAllocator &Allocator, MachineFunction &MF) | llvm::MachineFunctionInfo | inlinestatic |
create(BumpPtrAllocator &Allocator, const Ty &MFI) | llvm::MachineFunctionInfo | inlinestatic |
DynLDSAlign | llvm::AMDGPUMachineFunction | protected |
ExplicitKernArgSize | llvm::AMDGPUMachineFunction | protected |
FramePointerSaveIndex | llvm::SIMachineFunctionInfo | |
GCNTargetMachine class | llvm::SIMachineFunctionInfo | friend |
GDSSize | llvm::AMDGPUMachineFunction | protected |
get32BitAddressHighBits() const | llvm::SIMachineFunctionInfo | inline |
getAGPRSpillVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getArgInfo() | llvm::SIMachineFunctionInfo | inline |
getArgInfo() const | llvm::SIMachineFunctionInfo | inline |
getBufferPSV(const AMDGPUTargetMachine &TM) | llvm::SIMachineFunctionInfo | inline |
getBytesInStackArgArea() const | llvm::SIMachineFunctionInfo | inline |
getDynLDSAlign() const | llvm::AMDGPUMachineFunction | inline |
getExplicitKernArgSize() const | llvm::AMDGPUMachineFunction | inline |
getFlatWorkGroupSizes() const | llvm::SIMachineFunctionInfo | inline |
getFrameOffsetReg() const | llvm::SIMachineFunctionInfo | inline |
getGDSSize() const | llvm::AMDGPUMachineFunction | inline |
getGITPtrHigh() const | llvm::SIMachineFunctionInfo | inline |
getGITPtrLoReg(const MachineFunction &MF) const | llvm::SIMachineFunctionInfo | |
getGWSPSV(const AMDGPUTargetMachine &TM) | llvm::SIMachineFunctionInfo | inline |
getImagePSV(const AMDGPUTargetMachine &TM) | llvm::SIMachineFunctionInfo | inline |
getImplicitBufferPtrUserSGPR() const | llvm::SIMachineFunctionInfo | inline |
getLDSSize() const | llvm::AMDGPUMachineFunction | inline |
getMaxFlatWorkGroupSize() const | llvm::SIMachineFunctionInfo | inline |
getMaxKernArgAlign() const | llvm::AMDGPUMachineFunction | inline |
getMaxWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getMinAllowedOccupancy() const | llvm::SIMachineFunctionInfo | inline |
getMinFlatWorkGroupSize() const | llvm::SIMachineFunctionInfo | inline |
getMinWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getMode() const | llvm::AMDGPUMachineFunction | inline |
getNumPreloadedSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumSpilledSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumSpilledVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getNumUserSGPRs() const | llvm::SIMachineFunctionInfo | inline |
getOccupancy() const | llvm::SIMachineFunctionInfo | inline |
getOptionalScavengeFI() const | llvm::SIMachineFunctionInfo | inline |
getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const | llvm::SIMachineFunctionInfo | inline |
getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const | llvm::SIMachineFunctionInfo | inline |
getPrivateSegmentWaveByteOffsetSystemSGPR() const | llvm::SIMachineFunctionInfo | inline |
getPSInputAddr() const | llvm::SIMachineFunctionInfo | inline |
getPSInputEnable() const | llvm::SIMachineFunctionInfo | inline |
getQueuePtrUserSGPR() const | llvm::SIMachineFunctionInfo | inline |
getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI) | llvm::SIMachineFunctionInfo | |
getScratchRSrcReg() const | llvm::SIMachineFunctionInfo | inline |
getSGPRSpillVGPRs() const | llvm::SIMachineFunctionInfo | inline |
getSGPRToVGPRSpills(int FrameIndex) const | llvm::SIMachineFunctionInfo | inline |
getStackPtrOffsetReg() const | llvm::SIMachineFunctionInfo | inline |
getVGPRForAGPRCopy() const | llvm::SIMachineFunctionInfo | inline |
getVGPRSpillAGPRs() const | llvm::SIMachineFunctionInfo | inline |
getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const | llvm::SIMachineFunctionInfo | inline |
getWavesPerEU() const | llvm::SIMachineFunctionInfo | inline |
getWorkGroupIDSGPR(unsigned Dim) const | llvm::SIMachineFunctionInfo | inline |
hasDispatchID() const | llvm::SIMachineFunctionInfo | inline |
hasDispatchPtr() const | llvm::SIMachineFunctionInfo | inline |
hasFlatScratchInit() const | llvm::SIMachineFunctionInfo | inline |
hasImplicitArgPtr() const | llvm::SIMachineFunctionInfo | inline |
hasImplicitBufferPtr() const | llvm::SIMachineFunctionInfo | inline |
hasKernargSegmentPtr() const | llvm::SIMachineFunctionInfo | inline |
hasNonSpillStackObjects() const | llvm::SIMachineFunctionInfo | inline |
hasNoSignedZerosFPMath() const | llvm::AMDGPUMachineFunction | inline |
hasPrivateSegmentBuffer() const | llvm::SIMachineFunctionInfo | inline |
hasPrivateSegmentWaveByteOffset() const | llvm::SIMachineFunctionInfo | inline |
hasQueuePtr() const | llvm::SIMachineFunctionInfo | inline |
hasSpilledSGPRs() const | llvm::SIMachineFunctionInfo | inline |
hasSpilledVGPRs() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDX() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDY() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupIDZ() const | llvm::SIMachineFunctionInfo | inline |
hasWorkGroupInfo() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDX() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDY() const | llvm::SIMachineFunctionInfo | inline |
hasWorkItemIDZ() const | llvm::SIMachineFunctionInfo | inline |
haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const | llvm::SIMachineFunctionInfo | |
increaseOccupancy(const MachineFunction &MF, unsigned Limit) | llvm::SIMachineFunctionInfo | inline |
initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) | llvm::SIMachineFunctionInfo | |
isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) | llvm::SIMachineFunctionInfo | |
IsEntryFunction | llvm::AMDGPUMachineFunction | protected |
isEntryFunction() const | llvm::AMDGPUMachineFunction | inline |
isMemoryBound() const | llvm::AMDGPUMachineFunction | inline |
isModuleEntryFunction() const | llvm::AMDGPUMachineFunction | inline |
IsModuleEntryFunction | llvm::AMDGPUMachineFunction | protected |
isPSInputAllocated(unsigned Index) const | llvm::SIMachineFunctionInfo | inline |
isStackRealigned() const | llvm::SIMachineFunctionInfo | inline |
LDSSize | llvm::AMDGPUMachineFunction | protected |
limitOccupancy(const MachineFunction &MF) | llvm::SIMachineFunctionInfo | |
limitOccupancy(unsigned Limit) | llvm::SIMachineFunctionInfo | inline |
markPSInputAllocated(unsigned Index) | llvm::SIMachineFunctionInfo | inline |
markPSInputEnabled(unsigned Index) | llvm::SIMachineFunctionInfo | inline |
MaxKernArgAlign | llvm::AMDGPUMachineFunction | protected |
mayNeedAGPRs() const | llvm::SIMachineFunctionInfo | inline |
mayUseAGPRs(const MachineFunction &MF) const | llvm::SIMachineFunctionInfo | |
MemoryBound | llvm::AMDGPUMachineFunction | protected |
Mode | llvm::AMDGPUMachineFunction | protected |
needsWaveLimiter() const | llvm::AMDGPUMachineFunction | inline |
NoSignedZerosFPMath | llvm::AMDGPUMachineFunction | protected |
removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) | llvm::SIMachineFunctionInfo | |
reserveWWMRegister(Register Reg) | llvm::SIMachineFunctionInfo | inline |
returnsVoid() const | llvm::SIMachineFunctionInfo | inline |
setBytesInStackArgArea(unsigned Bytes) | llvm::SIMachineFunctionInfo | inline |
setDynLDSAlign(const DataLayout &DL, const GlobalVariable &GV) | llvm::AMDGPUMachineFunction | |
setFrameOffsetReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setHasNonSpillStackObjects(bool StackObject=true) | llvm::SIMachineFunctionInfo | inline |
setHasSpilledSGPRs(bool Spill=true) | llvm::SIMachineFunctionInfo | inline |
setHasSpilledVGPRs(bool Spill=true) | llvm::SIMachineFunctionInfo | inline |
setIfReturnsVoid(bool Value) | llvm::SIMachineFunctionInfo | inline |
setIsStackRealigned(bool Realigned=true) | llvm::SIMachineFunctionInfo | inline |
setPrivateSegmentWaveByteOffset(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setScratchRSrcReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setStackPtrOffsetReg(Register Reg) | llvm::SIMachineFunctionInfo | inline |
setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy) | llvm::SIMachineFunctionInfo | inline |
setVGPRToAGPRSpillDead(int FrameIndex) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDX(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDY(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
setWorkItemIDZ(ArgDescriptor Arg) | llvm::SIMachineFunctionInfo | inline |
SGPRForBPSaveRestoreCopy | llvm::SIMachineFunctionInfo | |
SGPRForFPSaveRestoreCopy | llvm::SIMachineFunctionInfo | |
SIMachineFunctionInfo(const MachineFunction &MF) | llvm::SIMachineFunctionInfo | |
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default | llvm::SIMachineFunctionInfo | |
StaticGDSSize | llvm::AMDGPUMachineFunction | protected |
StaticLDSSize | llvm::AMDGPUMachineFunction | protected |
usesAGPRs(const MachineFunction &MF) const | llvm::SIMachineFunctionInfo | |
WaveLimiter | llvm::AMDGPUMachineFunction | protected |
wwmAllocation() const | llvm::SIMachineFunctionInfo | inline |
WWMReservedFrameIndexes | llvm::SIMachineFunctionInfo | |
WWMReservedRegs | llvm::SIMachineFunctionInfo | |
~MachineFunctionInfo() | llvm::MachineFunctionInfo | virtual |