LLVM  13.0.0git
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llvm::SIMachineFunctionInfo Class Referencefinal

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load. More...

#include "Target/AMDGPU/SIMachineFunctionInfo.h"

Inheritance diagram for llvm::SIMachineFunctionInfo:
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Collaboration diagram for llvm::SIMachineFunctionInfo:
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Classes

struct  SGPRSpillVGPR
 
struct  SpilledReg
 
struct  VGPRSpillToAGPR
 

Public Member Functions

bool isCalleeSavedReg (const MCPhysReg *CSRegs, MCPhysReg Reg)
 
 SIMachineFunctionInfo (const MachineFunction &MF)
 
bool initializeBaseYamlFields (const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
 
void reserveWWMRegister (Register Reg, Optional< int > FI)
 
ArrayRef< SpilledReg > getSGPRToVGPRSpills (int FrameIndex) const
 
ArrayRef< SGPRSpillVGPR > getSGPRSpillVGPRs () const
 
void setSGPRSpillVGPRs (Register NewVGPR, Optional< int > newFI, int Index)
 
bool removeVGPRForSGPRSpill (Register ReservedVGPR, MachineFunction &MF)
 
ArrayRef< MCPhysReg > getAGPRSpillVGPRs () const
 
ArrayRef< MCPhysReg > getVGPRSpillAGPRs () const
 
MCPhysReg getVGPRToAGPRSpill (int FrameIndex, unsigned Lane) const
 
bool haveFreeLanesForSGPRSpill (const MachineFunction &MF, unsigned NumLane) const
 returns true if NumLanes slots are available in VGPRs already used for SGPR spilling. More...
 
bool allocateSGPRSpillToVGPR (MachineFunction &MF, int FI)
 Reserve a slice of a VGPR to support spilling for FrameIndex FI. More...
 
bool reserveVGPRforSGPRSpills (MachineFunction &MF)
 Reserve a VGPR for spilling of SGPRs. More...
 
bool allocateVGPRSpillToAGPR (MachineFunction &MF, int FI, bool isAGPRtoVGPR)
 Reserve AGPRs or VGPRs to support spilling for FrameIndex FI. More...
 
void removeDeadFrameIndices (MachineFrameInfo &MFI)
 
int getScavengeFI (MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
 
Optional< int > getOptionalScavengeFI () const
 
bool hasCalculatedTID () const
 
Register getTIDReg () const
 
void setTIDReg (Register Reg)
 
unsigned getBytesInStackArgArea () const
 
void setBytesInStackArgArea (unsigned Bytes)
 
Register addPrivateSegmentBuffer (const SIRegisterInfo &TRI)
 
Register addDispatchPtr (const SIRegisterInfo &TRI)
 
Register addQueuePtr (const SIRegisterInfo &TRI)
 
Register addKernargSegmentPtr (const SIRegisterInfo &TRI)
 
Register addDispatchID (const SIRegisterInfo &TRI)
 
Register addFlatScratchInit (const SIRegisterInfo &TRI)
 
Register addImplicitBufferPtr (const SIRegisterInfo &TRI)
 
Register addWorkGroupIDX ()
 
Register addWorkGroupIDY ()
 
Register addWorkGroupIDZ ()
 
Register addWorkGroupInfo ()
 
void setWorkItemIDX (ArgDescriptor Arg)
 
void setWorkItemIDY (ArgDescriptor Arg)
 
void setWorkItemIDZ (ArgDescriptor Arg)
 
Register addPrivateSegmentWaveByteOffset ()
 
void setPrivateSegmentWaveByteOffset (Register Reg)
 
bool hasPrivateSegmentBuffer () const
 
bool hasDispatchPtr () const
 
bool hasQueuePtr () const
 
bool hasKernargSegmentPtr () const
 
bool hasDispatchID () const
 
bool hasFlatScratchInit () const
 
bool hasWorkGroupIDX () const
 
bool hasWorkGroupIDY () const
 
bool hasWorkGroupIDZ () const
 
bool hasWorkGroupInfo () const
 
bool hasPrivateSegmentWaveByteOffset () const
 
bool hasWorkItemIDX () const
 
bool hasWorkItemIDY () const
 
bool hasWorkItemIDZ () const
 
bool hasImplicitArgPtr () const
 
bool hasImplicitBufferPtr () const
 
AMDGPUFunctionArgInfo & getArgInfo ()
 
const AMDGPUFunctionArgInfo & getArgInfo () const
 
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue (AMDGPUFunctionArgInfo::PreloadedValue Value) const
 
MCRegister getPreloadedReg (AMDGPUFunctionArgInfo::PreloadedValue Value) const
 
unsigned getGITPtrHigh () const
 
Register getGITPtrLoReg (const MachineFunction &MF) const
 
uint32_t get32BitAddressHighBits () const
 
unsigned getGDSSize () const
 
unsigned getNumUserSGPRs () const
 
unsigned getNumPreloadedSGPRs () const
 
Register getPrivateSegmentWaveByteOffsetSystemSGPR () const
 
Register getScratchRSrcReg () const
 Returns the physical register reserved for use as the resource descriptor for scratch accesses. More...
 
void setScratchRSrcReg (Register Reg)
 
Register getFrameOffsetReg () const
 
void setFrameOffsetReg (Register Reg)
 
void setStackPtrOffsetReg (Register Reg)
 
Register getStackPtrOffsetReg () const
 
Register getQueuePtrUserSGPR () const
 
Register getImplicitBufferPtrUserSGPR () const
 
bool hasSpilledSGPRs () const
 
void setHasSpilledSGPRs (bool Spill=true)
 
bool hasSpilledVGPRs () const
 
void setHasSpilledVGPRs (bool Spill=true)
 
bool hasNonSpillStackObjects () const
 
void setHasNonSpillStackObjects (bool StackObject=true)
 
bool isStackRealigned () const
 
void setIsStackRealigned (bool Realigned=true)
 
unsigned getNumSpilledSGPRs () const
 
unsigned getNumSpilledVGPRs () const
 
void addToSpilledSGPRs (unsigned num)
 
void addToSpilledVGPRs (unsigned num)
 
unsigned getPSInputAddr () const
 
unsigned getPSInputEnable () const
 
bool isPSInputAllocated (unsigned Index) const
 
void markPSInputAllocated (unsigned Index)
 
void markPSInputEnabled (unsigned Index)
 
bool returnsVoid () const
 
void setIfReturnsVoid (bool Value)
 
std::pair< unsigned, unsigned > getFlatWorkGroupSizes () const
 
unsigned getMinFlatWorkGroupSize () const
 
unsigned getMaxFlatWorkGroupSize () const
 
std::pair< unsigned, unsigned > getWavesPerEU () const
 
unsigned getMinWavesPerEU () const
 
unsigned getMaxWavesPerEU () const
 
Register getWorkGroupIDSGPR (unsigned Dim) const
 
unsigned getLDSWaveSpillSize () const
 
const AMDGPUBufferPseudoSourceValue * getBufferPSV (const SIInstrInfo &TII)
 
const AMDGPUImagePseudoSourceValue * getImagePSV (const SIInstrInfo &TII)
 
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV (const SIInstrInfo &TII)
 
unsigned getOccupancy () const
 
unsigned getMinAllowedOccupancy () const
 
void limitOccupancy (const MachineFunction &MF)
 
void limitOccupancy (unsigned Limit)
 
void increaseOccupancy (const MachineFunction &MF, unsigned Limit)
 
- Public Member Functions inherited from llvm::AMDGPUMachineFunction
 AMDGPUMachineFunction (const MachineFunction &MF)
 
uint64_t getExplicitKernArgSize () const
 
unsigned getMaxKernArgAlign () const
 
unsigned getLDSSize () const
 
AMDGPU::SIModeRegisterDefaults getMode () const
 
bool isEntryFunction () const
 
bool isModuleEntryFunction () const
 
bool hasNoSignedZerosFPMath () const
 
bool isMemoryBound () const
 
bool needsWaveLimiter () const
 
unsigned allocateLDSGlobal (const DataLayout &DL, const GlobalVariable &GV)
 
void allocateModuleLDSGlobal (const Module *M)
 
Align getDynLDSAlign () const
 
void setDynLDSAlign (const DataLayout &DL, const GlobalVariable &GV)
 
- Public Member Functions inherited from llvm::MachineFunctionInfo
virtual ~MachineFunctionInfo ()
 

Public Attributes

MapVector< Register, Optional< int > > WWMReservedRegs
 
Register SGPRForFPSaveRestoreCopy
 If this is set, an SGPR used for save/restore of the register used for the frame pointer. More...
 
Optional< int > FramePointerSaveIndex
 
Register SGPRForBPSaveRestoreCopy
 If this is set, an SGPR used for save/restore of the register used for the base pointer. More...
 
Optional< int > BasePointerSaveIndex
 
Register VGPRReservedForSGPRSpill
 

Friends

class GCNTargetMachine
 

Additional Inherited Members

- Static Public Member Functions inherited from llvm::MachineFunctionInfo
template<typename Ty >
static Ty * create (BumpPtrAllocator &Allocator, MachineFunction &MF)
 Factory function: default behavior is to call new using the supplied allocator. More...
 
- Protected Attributes inherited from llvm::AMDGPUMachineFunction
uint64_t ExplicitKernArgSize = 0
 
Align MaxKernArgAlign
 
unsigned LDSSize = 0
 Number of bytes in the LDS that are being used. More...
 
unsigned StaticLDSSize = 0
 Number of bytes in the LDS allocated statically. More...
 
Align DynLDSAlign
 Align for dynamic shared memory if any. More...
 
AMDGPU::SIModeRegisterDefaults Mode
 
bool IsEntryFunction = false
 
bool IsModuleEntryFunction = false
 
bool NoSignedZerosFPMath = false
 
bool MemoryBound = false
 
bool WaveLimiter = false
 

Detailed Description

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load.

Definition at line 335 of file SIMachineFunctionInfo.h.

Constructor & Destructor Documentation

◆ SIMachineFunctionInfo()

SIMachineFunctionInfo::SIMachineFunctionInfo ( const MachineFunction &  MF)

Definition at line 17 of file SIMachineFunctionInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_PS, llvm::ArgDescriptor::createRegister(), llvm::AMDGPUTargetMachine::EnableFixedFunctionABI, F, llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo, llvm::MachineFunction::getFunction(), llvm::AMDGPU::getInitialPSInputAddr(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::MachineFunction::getSubtarget(), llvm::AMDGPUSubtarget::GFX9, HasCalls, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::max(), llvm::AMDGPUMachineFunction::MaxKernArgAlign, llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer, llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset, S, llvm::CallingConv::SPIR_KERNEL, and llvm::ARM_MB::ST.

Member Function Documentation

◆ addDispatchID()

Register SIMachineFunctionInfo::addDispatchID ( const SIRegisterInfo &  TRI)

Definition at line 226 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::AMDGPUFunctionArgInfo::DispatchID, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), and TRI.

◆ addDispatchPtr()

Register SIMachineFunctionInfo::addDispatchPtr ( const SIRegisterInfo &  TRI)

Definition at line 204 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::AMDGPUFunctionArgInfo::DispatchPtr, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), and TRI.

◆ addFlatScratchInit()

Register SIMachineFunctionInfo::addFlatScratchInit ( const SIRegisterInfo &  TRI)

Definition at line 233 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::AMDGPUFunctionArgInfo::FlatScratchInit, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), and TRI.

◆ addImplicitBufferPtr()

Register SIMachineFunctionInfo::addImplicitBufferPtr ( const SIRegisterInfo &  TRI)

Definition at line 240 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr, and TRI.

◆ addKernargSegmentPtr()

Register SIMachineFunctionInfo::addKernargSegmentPtr ( const SIRegisterInfo &  TRI)

Definition at line 218 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr, and TRI.

◆ addPrivateSegmentBuffer()

Register SIMachineFunctionInfo::addPrivateSegmentBuffer ( const SIRegisterInfo &  TRI)

Definition at line 195 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer, and TRI.

◆ addPrivateSegmentWaveByteOffset()

Register llvm::SIMachineFunctionInfo::addPrivateSegmentWaveByteOffset ( )
inline

Definition at line 616 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset.

◆ addQueuePtr()

Register SIMachineFunctionInfo::addQueuePtr ( const SIRegisterInfo &  TRI)

Definition at line 211 of file SIMachineFunctionInfo.cpp.

References llvm::ArgDescriptor::createRegister(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ArgDescriptor::getRegister(), llvm::AMDGPUFunctionArgInfo::QueuePtr, and TRI.

◆ addToSpilledSGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledSGPRs ( unsigned  num)
inline

Definition at line 816 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::spillSGPR().

◆ addToSpilledVGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledVGPRs ( unsigned  num)
inline

Definition at line 820 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::buildVGPRSpillLoadStore(), and llvm::SIRegisterInfo::eliminateFrameIndex().

◆ addWorkGroupIDX()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDX ( )
inline

Definition at line 579 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::WorkGroupIDX.

◆ addWorkGroupIDY()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDY ( )
inline

Definition at line 585 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::WorkGroupIDY.

◆ addWorkGroupIDZ()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDZ ( )
inline

Definition at line 591 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ.

◆ addWorkGroupInfo()

Register llvm::SIMachineFunctionInfo::addWorkGroupInfo ( )
inline

Definition at line 597 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::WorkGroupInfo.

◆ allocateSGPRSpillToVGPR()

bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR ( MachineFunction &  MF,
int  FI 
)

Reserve a slice of a VGPR to support spilling for FrameIndex FI.

Definition at line 269 of file SIMachineFunctionInfo.cpp.

References Align, assert(), BB, llvm::MachineFrameInfo::CreateSpillStackObject(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), I, llvm::AMDGPUMachineFunction::isEntryFunction(), MRI, llvm::Check::Size, llvm::ARM_MB::ST, TRI, and VGPRReservedForSGPRSpill.

Referenced by getVGPRSpillLaneOrTempRegister().

◆ allocateVGPRSpillToAGPR()

bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR ( MachineFunction &  MF,
int  FI,
bool  isAGPRtoVGPR 
)

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.

Either AGPR is spilled to VGPR to vice versa. Returns true if a FI can be eliminated completely.

Definition at line 359 of file SIMachineFunctionInfo.cpp.

References assert(), llvm::find_if(), llvm::Function::getCallingConv(), llvm::TargetRegisterInfo::getCallPreservedMask(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegisters(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineFrameInfo::isSpillSlotObjectIndex(), MRI, llvm::BitVector::push_back(), Reg, llvm::BitVector::resize(), llvm::BitVector::set(), llvm::BitVector::setBitsInMask(), llvm::Check::Size, llvm::ARM_MB::ST, and TRI.

◆ get32BitAddressHighBits()

uint32_t llvm::SIMachineFunctionInfo::get32BitAddressHighBits ( ) const
inline

Definition at line 715 of file SIMachineFunctionInfo.h.

◆ getAGPRSpillVGPRs()

ArrayRef<MCPhysReg> llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs ( ) const
inline

Definition at line 533 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::getReservedRegs().

◆ getArgInfo() [1/2]

AMDGPUFunctionArgInfo& llvm::SIMachineFunctionInfo::getArgInfo ( )
inline

Definition at line 691 of file SIMachineFunctionInfo.h.

Referenced by llvm::AMDGPUCallLowering::passSpecialInputs().

◆ getArgInfo() [2/2]

const AMDGPUFunctionArgInfo& llvm::SIMachineFunctionInfo::getArgInfo ( ) const
inline

Definition at line 695 of file SIMachineFunctionInfo.h.

◆ getBufferPSV()

const AMDGPUBufferPseudoSourceValue* llvm::SIMachineFunctionInfo::getBufferPSV ( const SIInstrInfo &  TII)
inline

Definition at line 904 of file SIMachineFunctionInfo.h.

References TII.

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic(), and llvm::AMDGPUMIRFormatter::parseCustomPseudoSourceValue().

◆ getBytesInStackArgArea()

unsigned llvm::SIMachineFunctionInfo::getBytesInStackArgArea ( ) const
inline

Definition at line 561 of file SIMachineFunctionInfo.h.

Referenced by llvm::SITargetLowering::isEligibleForTailCallOptimization().

◆ getFlatWorkGroupSizes()

std::pair<unsigned, unsigned> llvm::SIMachineFunctionInfo::getFlatWorkGroupSizes ( ) const
inline
Returns
A pair of default/requested minimum/maximum flat work group sizes for this function.

Definition at line 854 of file SIMachineFunctionInfo.h.

◆ getFrameOffsetReg()

Register llvm::SIMachineFunctionInfo::getFrameOffsetReg ( ) const
inline

Definition at line 746 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getFrameRegister(), llvm::SIRegisterInfo::getReservedRegs(), and llvm::SIRegisterInfo::spillSGPR().

◆ getGDSSize()

unsigned llvm::SIMachineFunctionInfo::getGDSSize ( ) const
inline

Definition at line 719 of file SIMachineFunctionInfo.h.

◆ getGITPtrHigh()

unsigned llvm::SIMachineFunctionInfo::getGITPtrHigh ( ) const
inline

Definition at line 709 of file SIMachineFunctionInfo.h.

Referenced by buildGitPtr().

◆ getGITPtrLoReg()

Register SIMachineFunctionInfo::getGITPtrLoReg ( const MachineFunction &  MF) const

Definition at line 469 of file SIMachineFunctionInfo.cpp.

References llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getSubtarget(), and llvm::ARM_MB::ST.

Referenced by buildGitPtr(), and llvm::SIFrameLowering::emitEntryFunctionPrologue().

◆ getGWSPSV()

const AMDGPUGWSResourcePseudoSourceValue* llvm::SIMachineFunctionInfo::getGWSPSV ( const SIInstrInfo &  TII)
inline

Definition at line 918 of file SIMachineFunctionInfo.h.

References TII.

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic(), and llvm::AMDGPUMIRFormatter::parseCustomPseudoSourceValue().

◆ getImagePSV()

const AMDGPUImagePseudoSourceValue* llvm::SIMachineFunctionInfo::getImagePSV ( const SIInstrInfo &  TII)
inline

Definition at line 911 of file SIMachineFunctionInfo.h.

References TII.

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic(), and llvm::AMDGPUMIRFormatter::parseCustomPseudoSourceValue().

◆ getImplicitBufferPtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getImplicitBufferPtrUserSGPR ( ) const
inline

Definition at line 772 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr.

◆ getLDSWaveSpillSize()

unsigned llvm::SIMachineFunctionInfo::getLDSWaveSpillSize ( ) const
inline

Definition at line 900 of file SIMachineFunctionInfo.h.

◆ getMaxFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMaxFlatWorkGroupSize ( ) const
inline
Returns
Default/requested maximum flat work group size for this function.

Definition at line 864 of file SIMachineFunctionInfo.h.

◆ getMaxWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMaxWavesPerEU ( ) const
inline
Returns
Default/requested maximum number of waves per execution unit.

Definition at line 880 of file SIMachineFunctionInfo.h.

Referenced by limitOccupancy().

◆ getMinAllowedOccupancy()

unsigned llvm::SIMachineFunctionInfo::getMinAllowedOccupancy ( ) const
inline

Definition at line 931 of file SIMachineFunctionInfo.h.

References llvm::AMDGPUMachineFunction::isMemoryBound(), and llvm::AMDGPUMachineFunction::needsWaveLimiter().

Referenced by llvm::GCNScheduleDAGMILive::schedule().

◆ getMinFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMinFlatWorkGroupSize ( ) const
inline
Returns
Default/requested minimum flat work group size for this function.

Definition at line 859 of file SIMachineFunctionInfo.h.

◆ getMinWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMinWavesPerEU ( ) const
inline
Returns
Default/requested minimum number of waves per execution unit.

Definition at line 875 of file SIMachineFunctionInfo.h.

Referenced by llvm::GCNScheduleDAGMILive::schedule().

◆ getNumPreloadedSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumPreloadedSGPRs ( ) const
inline

Definition at line 727 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), and llvm::GCNSubtarget::getMaxNumSGPRs().

◆ getNumSpilledSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledSGPRs ( ) const
inline

Definition at line 808 of file SIMachineFunctionInfo.h.

◆ getNumSpilledVGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledVGPRs ( ) const
inline

Definition at line 812 of file SIMachineFunctionInfo.h.

◆ getNumUserSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumUserSGPRs ( ) const
inline

Definition at line 723 of file SIMachineFunctionInfo.h.

◆ getOccupancy()

unsigned llvm::SIMachineFunctionInfo::getOccupancy ( ) const
inline

Definition at line 927 of file SIMachineFunctionInfo.h.

Referenced by llvm::GCNScheduleDAGMILive::schedule().

◆ getOptionalScavengeFI()

Optional<int> llvm::SIMachineFunctionInfo::getOptionalScavengeFI ( ) const
inline

Definition at line 555 of file SIMachineFunctionInfo.h.

Referenced by llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getPreloadedReg()

MCRegister llvm::SIMachineFunctionInfo::getPreloadedReg ( AMDGPUFunctionArgInfo::PreloadedValue  Value) const
inline

Definition at line 704 of file SIMachineFunctionInfo.h.

References Arg, and llvm::AMDGPUFunctionArgInfo::getPreloadedValue().

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue().

◆ getPreloadedValue()

std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT> llvm::SIMachineFunctionInfo::getPreloadedValue ( AMDGPUFunctionArgInfo::PreloadedValue  Value) const
inline

Definition at line 700 of file SIMachineFunctionInfo.h.

References llvm::AMDGPUFunctionArgInfo::getPreloadedValue().

Referenced by llvm::AMDGPULegalizerInfo::loadInputValue().

◆ getPrivateSegmentWaveByteOffsetSystemSGPR()

Register llvm::SIMachineFunctionInfo::getPrivateSegmentWaveByteOffsetSystemSGPR ( ) const
inline

Definition at line 731 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset.

◆ getPSInputAddr()

unsigned llvm::SIMachineFunctionInfo::getPSInputAddr ( ) const
inline

Definition at line 824 of file SIMachineFunctionInfo.h.

◆ getPSInputEnable()

unsigned llvm::SIMachineFunctionInfo::getPSInputEnable ( ) const
inline

Definition at line 828 of file SIMachineFunctionInfo.h.

◆ getQueuePtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getQueuePtrUserSGPR ( ) const
inline

Definition at line 768 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::getRegister(), and llvm::AMDGPUFunctionArgInfo::QueuePtr.

◆ getScavengeFI()

int SIMachineFunctionInfo::getScavengeFI ( MachineFrameInfo &  MFI,
const SIRegisterInfo &  TRI 
)

Definition at line 444 of file SIMachineFunctionInfo.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::TargetRegisterInfo::getSpillAlign(), llvm::TargetRegisterInfo::getSpillSize(), llvm::AMDGPUMachineFunction::isEntryFunction(), and TRI.

Referenced by llvm::SGPRSpillBuilder::prepare(), and llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ getScratchRSrcReg()

Register llvm::SIMachineFunctionInfo::getScratchRSrcReg ( ) const
inline

Returns the physical register reserved for use as the resource descriptor for scratch accesses.

Definition at line 737 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getReservedRegs(), and llvm::AMDGPUCallLowering::lowerCall().

◆ getSGPRSpillVGPRs()

ArrayRef<SGPRSpillVGPR> llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs ( ) const
inline

Definition at line 523 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getReservedRegs(), and lowerShiftReservedVGPR().

◆ getSGPRToVGPRSpills()

ArrayRef<SpilledReg> llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills ( int  FrameIndex) const
inline

Definition at line 517 of file SIMachineFunctionInfo.h.

References llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find(), llvm::ISD::FrameIndex, I, and llvm::makeArrayRef().

Referenced by llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), getVGPRSpillLaneOrTempRegister(), llvm::SIRegisterInfo::restoreSGPR(), and llvm::SIRegisterInfo::spillSGPR().

◆ getStackPtrOffsetReg()

Register llvm::SIMachineFunctionInfo::getStackPtrOffsetReg ( ) const
inline

Definition at line 764 of file SIMachineFunctionInfo.h.

Referenced by buildEpilogRestore(), buildPrologSpill(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::eliminateCallFramePseudoInstr(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getFrameRegister(), llvm::SIRegisterInfo::getReservedRegs(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIRegisterInfo::spillSGPR(), and llvm::SIInstrInfo::storeRegToStackSlot().

◆ getTIDReg()

Register llvm::SIMachineFunctionInfo::getTIDReg ( ) const
inline

Definition at line 558 of file SIMachineFunctionInfo.h.

◆ getVGPRSpillAGPRs()

ArrayRef<MCPhysReg> llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs ( ) const
inline

Definition at line 537 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::getReservedRegs().

◆ getVGPRToAGPRSpill()

MCPhysReg llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill ( int  FrameIndex,
unsigned  Lane 
) const
inline

Definition at line 541 of file SIMachineFunctionInfo.h.

References llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find(), llvm::ISD::FrameIndex, and I.

Referenced by spillVGPRtoAGPR().

◆ getWavesPerEU()

std::pair<unsigned, unsigned> llvm::SIMachineFunctionInfo::getWavesPerEU ( ) const
inline
Returns
A pair of default/requested minimum/maximum number of waves per execution unit.

Definition at line 870 of file SIMachineFunctionInfo.h.

Referenced by llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::GCNSubtarget::getMaxNumVGPRs().

◆ getWorkGroupIDSGPR()

Register llvm::SIMachineFunctionInfo::getWorkGroupIDSGPR ( unsigned  Dim) const
inline
Returns
SGPR used for Dim's work group ID.

Definition at line 885 of file SIMachineFunctionInfo.h.

References assert(), llvm::ArgDescriptor::getRegister(), hasWorkGroupIDX(), hasWorkGroupIDY(), hasWorkGroupIDZ(), llvm_unreachable, llvm::AMDGPUFunctionArgInfo::WorkGroupIDX, llvm::AMDGPUFunctionArgInfo::WorkGroupIDY, and llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ.

◆ hasCalculatedTID()

bool llvm::SIMachineFunctionInfo::hasCalculatedTID ( ) const
inline

Definition at line 557 of file SIMachineFunctionInfo.h.

◆ hasDispatchID()

bool llvm::SIMachineFunctionInfo::hasDispatchID ( ) const
inline

Definition at line 643 of file SIMachineFunctionInfo.h.

◆ hasDispatchPtr()

bool llvm::SIMachineFunctionInfo::hasDispatchPtr ( ) const
inline

Definition at line 631 of file SIMachineFunctionInfo.h.

◆ hasFlatScratchInit()

bool llvm::SIMachineFunctionInfo::hasFlatScratchInit ( ) const
inline

Definition at line 647 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), and llvm::GCNSubtarget::getReservedNumSGPRs().

◆ hasImplicitArgPtr()

bool llvm::SIMachineFunctionInfo::hasImplicitArgPtr ( ) const
inline

Definition at line 683 of file SIMachineFunctionInfo.h.

◆ hasImplicitBufferPtr()

bool llvm::SIMachineFunctionInfo::hasImplicitBufferPtr ( ) const
inline

Definition at line 687 of file SIMachineFunctionInfo.h.

◆ hasKernargSegmentPtr()

bool llvm::SIMachineFunctionInfo::hasKernargSegmentPtr ( ) const
inline

Definition at line 639 of file SIMachineFunctionInfo.h.

◆ hasNonSpillStackObjects()

bool llvm::SIMachineFunctionInfo::hasNonSpillStackObjects ( ) const
inline

Definition at line 792 of file SIMachineFunctionInfo.h.

◆ hasPrivateSegmentBuffer()

bool llvm::SIMachineFunctionInfo::hasPrivateSegmentBuffer ( ) const
inline

Definition at line 627 of file SIMachineFunctionInfo.h.

◆ hasPrivateSegmentWaveByteOffset()

bool llvm::SIMachineFunctionInfo::hasPrivateSegmentWaveByteOffset ( ) const
inline

Definition at line 667 of file SIMachineFunctionInfo.h.

◆ hasQueuePtr()

bool llvm::SIMachineFunctionInfo::hasQueuePtr ( ) const
inline

Definition at line 635 of file SIMachineFunctionInfo.h.

◆ hasSpilledSGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledSGPRs ( ) const
inline

Definition at line 776 of file SIMachineFunctionInfo.h.

◆ hasSpilledVGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledVGPRs ( ) const
inline

Definition at line 784 of file SIMachineFunctionInfo.h.

◆ hasWorkGroupIDX()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDX ( ) const
inline

Definition at line 651 of file SIMachineFunctionInfo.h.

Referenced by getWorkGroupIDSGPR().

◆ hasWorkGroupIDY()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDY ( ) const
inline

Definition at line 655 of file SIMachineFunctionInfo.h.

Referenced by getWorkGroupIDSGPR().

◆ hasWorkGroupIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDZ ( ) const
inline

Definition at line 659 of file SIMachineFunctionInfo.h.

Referenced by getWorkGroupIDSGPR().

◆ hasWorkGroupInfo()

bool llvm::SIMachineFunctionInfo::hasWorkGroupInfo ( ) const
inline

Definition at line 663 of file SIMachineFunctionInfo.h.

◆ hasWorkItemIDX()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDX ( ) const
inline

Definition at line 671 of file SIMachineFunctionInfo.h.

◆ hasWorkItemIDY()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDY ( ) const
inline

Definition at line 675 of file SIMachineFunctionInfo.h.

◆ hasWorkItemIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDZ ( ) const
inline

Definition at line 679 of file SIMachineFunctionInfo.h.

◆ haveFreeLanesForSGPRSpill()

bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill ( const MachineFunction &  MF,
unsigned  NumLane 
) const

returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.

Definition at line 261 of file SIMachineFunctionInfo.cpp.

References llvm::MachineFunction::getSubtarget(), and llvm::ARM_MB::ST.

Referenced by getVGPRSpillLaneOrTempRegister().

◆ increaseOccupancy()

void llvm::SIMachineFunctionInfo::increaseOccupancy ( const MachineFunction &  MF,
unsigned  Limit 
)
inline

Definition at line 944 of file SIMachineFunctionInfo.h.

References limitOccupancy().

◆ initializeBaseYamlFields()

bool SIMachineFunctionInfo::initializeBaseYamlFields ( const yaml::SIMachineFunctionInfo &  YamlMFI,
const MachineFunction &  MF,
PerFunctionMIParsingState &  PFS,
SMDiagnostic &  Error,
SMRange &  SourceRange 
)

Definition at line 575 of file SIMachineFunctionInfo.cpp.

References llvm::assumeAligned(), llvm::SourceMgr::DK_Error, llvm::yaml::SIMachineFunctionInfo::DynLDSAlign, llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize, llvm::MemoryBuffer::getBufferIdentifier(), llvm::MachineFunction::getFrameInfo(), llvm::SourceMgr::getMainFileID(), llvm::SourceMgr::getMemoryBuffer(), llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs, llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs, llvm::yaml::SIMachineFunctionInfo::HighBitsOf32BitAddress, llvm::yaml::SIMachineFunctionInfo::IsEntryFunction, llvm::yaml::SIMachineFunctionInfo::LDSSize, llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign, llvm::yaml::SIMachineFunctionInfo::MemoryBound, llvm::None, llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath, llvm::yaml::SIMachineFunctionInfo::Occupancy, llvm::yaml::SIMachineFunctionInfo::ScavengeFI, llvm::PerFunctionMIParsingState::SM, llvm::toString(), and llvm::yaml::SIMachineFunctionInfo::WaveLimiter.

Referenced by llvm::GCNTargetMachine::parseMachineFunctionInfo().

◆ isCalleeSavedReg()

bool SIMachineFunctionInfo::isCalleeSavedReg ( const MCPhysReg *  CSRegs,
MCPhysReg  Reg 
)

Definition at line 247 of file SIMachineFunctionInfo.cpp.

References I, and Reg.

◆ isPSInputAllocated()

bool llvm::SIMachineFunctionInfo::isPSInputAllocated ( unsigned  Index) const
inline

Definition at line 832 of file SIMachineFunctionInfo.h.

References Index.

◆ isStackRealigned()

bool llvm::SIMachineFunctionInfo::isStackRealigned ( ) const
inline

Definition at line 800 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitEpilogue().

◆ limitOccupancy() [1/2]

void SIMachineFunctionInfo::limitOccupancy ( const MachineFunction &  MF)

Definition at line 188 of file SIMachineFunctionInfo.cpp.

References llvm::MachineFunction::getFunction(), llvm::AMDGPUMachineFunction::getLDSSize(), getMaxWavesPerEU(), llvm::MachineFunction::getSubtarget(), and llvm::ARM_MB::ST.

Referenced by increaseOccupancy(), and llvm::GCNScheduleDAGMILive::schedule().

◆ limitOccupancy() [2/2]

void llvm::SIMachineFunctionInfo::limitOccupancy ( unsigned  Limit)
inline

Definition at line 939 of file SIMachineFunctionInfo.h.

◆ markPSInputAllocated()

void llvm::SIMachineFunctionInfo::markPSInputAllocated ( unsigned  Index)
inline

Definition at line 836 of file SIMachineFunctionInfo.h.

References Index.

◆ markPSInputEnabled()

void llvm::SIMachineFunctionInfo::markPSInputEnabled ( unsigned  Index)
inline

Definition at line 840 of file SIMachineFunctionInfo.h.

References Index.

◆ removeDeadFrameIndices()

void SIMachineFunctionInfo::removeDeadFrameIndices ( MachineFrameInfo &  MFI)

Definition at line 424 of file SIMachineFunctionInfo.cpp.

References BasePointerSaveIndex, llvm::TargetStackID::Default, llvm::numbers::e, FramePointerSaveIndex, llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectIndexEnd(), i, llvm::MachineFrameInfo::RemoveStackObject(), and llvm::MachineFrameInfo::setStackID().

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ removeVGPRForSGPRSpill()

bool SIMachineFunctionInfo::removeVGPRForSGPRSpill ( Register  ReservedVGPR,
MachineFunction &  MF 
)

Definition at line 612 of file SIMachineFunctionInfo.cpp.

References i, MBB, llvm::MachineBasicBlock::removeLiveIn(), and llvm::MachineBasicBlock::sortUniqueLiveIns().

◆ reserveVGPRforSGPRSpills()

bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills ( MachineFunction &  MF)

Reserve a VGPR for spilling of SGPRs.

Definition at line 342 of file SIMachineFunctionInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::None, llvm::ARM_MB::ST, TRI, and VGPRReservedForSGPRSpill.

◆ reserveWWMRegister()

void llvm::SIMachineFunctionInfo::reserveWWMRegister ( Register  Reg,
Optional< int >  FI 
)
inline

Definition at line 513 of file SIMachineFunctionInfo.h.

References Reg, and WWMReservedRegs.

◆ returnsVoid()

bool llvm::SIMachineFunctionInfo::returnsVoid ( ) const
inline

Definition at line 844 of file SIMachineFunctionInfo.h.

Referenced by llvm::AMDGPUCallLowering::lowerReturn().

◆ setBytesInStackArgArea()

void llvm::SIMachineFunctionInfo::setBytesInStackArgArea ( unsigned  Bytes)
inline

Definition at line 565 of file SIMachineFunctionInfo.h.

◆ setFrameOffsetReg()

void llvm::SIMachineFunctionInfo::setFrameOffsetReg ( Register  Reg)
inline

Definition at line 750 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

◆ setHasNonSpillStackObjects()

void llvm::SIMachineFunctionInfo::setHasNonSpillStackObjects ( bool  StackObject = true)
inline

Definition at line 796 of file SIMachineFunctionInfo.h.

◆ setHasSpilledSGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledSGPRs ( bool  Spill = true)
inline

Definition at line 780 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().

◆ setHasSpilledVGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledVGPRs ( bool  Spill = true)
inline

Definition at line 788 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ setIfReturnsVoid()

void llvm::SIMachineFunctionInfo::setIfReturnsVoid ( bool  Value)
inline

Definition at line 848 of file SIMachineFunctionInfo.h.

Referenced by llvm::AMDGPUCallLowering::lowerReturn().

◆ setIsStackRealigned()

void llvm::SIMachineFunctionInfo::setIsStackRealigned ( bool  Realigned = true)
inline

Definition at line 804 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitPrologue().

◆ setPrivateSegmentWaveByteOffset()

void llvm::SIMachineFunctionInfo::setPrivateSegmentWaveByteOffset ( Register  Reg)
inline

Definition at line 623 of file SIMachineFunctionInfo.h.

References llvm::ArgDescriptor::createRegister(), llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset, and Reg.

◆ setScratchRSrcReg()

void llvm::SIMachineFunctionInfo::setScratchRSrcReg ( Register  Reg)
inline

Definition at line 741 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

◆ setSGPRSpillVGPRs()

void llvm::SIMachineFunctionInfo::setSGPRSpillVGPRs ( Register  NewVGPR,
Optional< int >  newFI,
int  Index 
)
inline

Definition at line 525 of file SIMachineFunctionInfo.h.

References Index, and VGPRReservedForSGPRSpill.

Referenced by lowerShiftReservedVGPR().

◆ setStackPtrOffsetReg()

void llvm::SIMachineFunctionInfo::setStackPtrOffsetReg ( Register  Reg)
inline

Definition at line 755 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

◆ setTIDReg()

void llvm::SIMachineFunctionInfo::setTIDReg ( Register  Reg)
inline

Definition at line 559 of file SIMachineFunctionInfo.h.

References Reg.

◆ setWorkItemIDX()

void llvm::SIMachineFunctionInfo::setWorkItemIDX ( ArgDescriptor  Arg)
inline

Definition at line 604 of file SIMachineFunctionInfo.h.

References Arg, and llvm::AMDGPUFunctionArgInfo::WorkItemIDX.

◆ setWorkItemIDY()

void llvm::SIMachineFunctionInfo::setWorkItemIDY ( ArgDescriptor  Arg)
inline

Definition at line 608 of file SIMachineFunctionInfo.h.

References Arg, and llvm::AMDGPUFunctionArgInfo::WorkItemIDY.

◆ setWorkItemIDZ()

void llvm::SIMachineFunctionInfo::setWorkItemIDZ ( ArgDescriptor  Arg)
inline

Definition at line 612 of file SIMachineFunctionInfo.h.

References Arg, and llvm::AMDGPUFunctionArgInfo::WorkItemIDZ.

Friends And Related Function Documentation

◆ GCNTargetMachine

friend class GCNTargetMachine
friend

Definition at line 336 of file SIMachineFunctionInfo.h.

Member Data Documentation

◆ BasePointerSaveIndex

Optional<int> llvm::SIMachineFunctionInfo::BasePointerSaveIndex

Definition at line 500 of file SIMachineFunctionInfo.h.

Referenced by allSGPRSpillsAreDead(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), and removeDeadFrameIndices().

◆ FramePointerSaveIndex

Optional<int> llvm::SIMachineFunctionInfo::FramePointerSaveIndex

Definition at line 495 of file SIMachineFunctionInfo.h.

Referenced by allSGPRSpillsAreDead(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), and removeDeadFrameIndices().

◆ SGPRForBPSaveRestoreCopy

Register llvm::SIMachineFunctionInfo::SGPRForBPSaveRestoreCopy

If this is set, an SGPR used for save/restore of the register used for the base pointer.

Definition at line 499 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ SGPRForFPSaveRestoreCopy

Register llvm::SIMachineFunctionInfo::SGPRForFPSaveRestoreCopy

If this is set, an SGPR used for save/restore of the register used for the frame pointer.

Definition at line 494 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ VGPRReservedForSGPRSpill

Register llvm::SIMachineFunctionInfo::VGPRReservedForSGPRSpill

Definition at line 502 of file SIMachineFunctionInfo.h.

Referenced by allocateSGPRSpillToVGPR(), lowerShiftReservedVGPR(), reserveVGPRforSGPRSpills(), and setSGPRSpillVGPRs().

◆ WWMReservedRegs

MapVector<Register, Optional<int> > llvm::SIMachineFunctionInfo::WWMReservedRegs

Definition at line 470 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitEpilogue(), llvm::SIFrameLowering::emitPrologue(), llvm::SIRegisterInfo::getReservedRegs(), and reserveWWMRegister().

The documentation for this class was generated from the following files:
Generated on Fri May 7 2021 16:43:31 for LLVM by   doxygen 1.8.17