LLVM 19.0.0git
llvm::X86InstrInfo Member List

This is the complete list of members for llvm::X86InstrInfo, including all inherited members.

accumulateInstrSeqToRootLatency(MachineInstr &Root) const overridellvm::X86InstrInfoinlineprotected
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::X86InstrInfo
analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const overridellvm::X86InstrInfo
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const overridellvm::X86InstrInfo
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const overridellvm::X86InstrInfo
breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const overridellvm::X86InstrInfo
buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const overridellvm::X86InstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const overridellvm::X86InstrInfo
canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const overridellvm::X86InstrInfo
classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) constllvm::X86InstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const overridellvm::X86InstrInfoprotected
convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const overridellvm::X86InstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const overridellvm::X86InstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::X86InstrInfo
describeLoadedValue(const MachineInstr &MI, Register Reg) const overridellvm::X86InstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::X86InstrInfo
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::X86InstrInfo
foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const overridellvm::X86InstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, Align Alignment, bool AllowCommute) constllvm::X86InstrInfo
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const overridellvm::X86InstrInfoprotected
getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const overridellvm::X86InstrInfo
getExecutionDomain(const MachineInstr &MI) const overridellvm::X86InstrInfo
getExecutionDomainCustom(const MachineInstr &MI) constllvm::X86InstrInfo
getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) constllvm::X86InstrInfo
getFrameAdjustment(const MachineInstr &I) constllvm::X86InstrInfoinline
getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const overridellvm::X86InstrInfoprotected
getGlobalBaseReg(MachineFunction *MF) constllvm::X86InstrInfo
getJumpTableIndex(const MachineInstr &MI) const overridellvm::X86InstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const overridellvm::X86InstrInfoprotected
getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getNop() const overridellvm::X86InstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const overridellvm::X86InstrInfo
getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const overridellvm::X86InstrInfo
getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const overridellvm::X86InstrInfo
getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const overridellvm::X86InstrInfo
getRegisterInfo() constllvm::X86InstrInfoinline
getSerializableDirectMachineOperandTargetFlags() const overridellvm::X86InstrInfo
getSPAdjust(const MachineInstr &MI) const overridellvm::X86InstrInfo
getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
hasCommutePreference(MachineInstr &MI, bool &Commute) const overridellvm::X86InstrInfo
hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::X86InstrInfo
hasLiveCondCodeDef(MachineInstr &MI) constllvm::X86InstrInfo
hasLockPrefix(const MachineInstr &MI)llvm::X86InstrInfoinlinestatic
hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const overridellvm::X86InstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::X86InstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::X86InstrInfo
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const overridellvm::X86InstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const overridellvm::X86InstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const overridellvm::X86InstrInfo
isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const overridellvm::X86InstrInfo
isCopyInstrImpl(const MachineInstr &MI) const overridellvm::X86InstrInfoprotected
isDataInvariant(MachineInstr &MI)llvm::X86InstrInfostatic
isDataInvariantLoad(MachineInstr &MI)llvm::X86InstrInfostatic
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const overridellvm::X86InstrInfo
isHighLatencyDef(int opc) const overridellvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::X86InstrInfo
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isReallyTriviallyReMaterializable(const MachineInstr &MI) const overridellvm::X86InstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const overridellvm::X86InstrInfo
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const overridellvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::X86InstrInfo
isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::X86InstrInfo
isSubregFoldable() const overridellvm::X86InstrInfoinline
isUnconditionalTailCall(const MachineInstr &MI) const overridellvm::X86InstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::X86InstrInfo
loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) constllvm::X86InstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const overridellvm::X86InstrInfo
optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const overridellvm::X86InstrInfo
preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const overridellvm::X86InstrInfo
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const overridellvm::X86InstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::X86InstrInfo
replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const overridellvm::X86InstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::X86InstrInfo
setExecutionDomain(MachineInstr &MI, unsigned Domain) const overridellvm::X86InstrInfo
setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) constllvm::X86InstrInfo
setFrameAdjustment(MachineInstr &I, int64_t V) constllvm::X86InstrInfoinline
setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const overridellvm::X86InstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const overridellvm::X86InstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::X86InstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const overridellvm::X86InstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const overridellvm::X86InstrInfo
useMachineCombiner() const overridellvm::X86InstrInfoinline
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const overridellvm::X86InstrInfo
X86InstrInfo(X86Subtarget &STI)llvm::X86InstrInfoexplicit