#include "Target/X86/X86InstrInfo.h"
Public Member Functions | |
| X86InstrInfo (X86Subtarget &STI) | |
| const X86RegisterInfo & | getRegisterInfo () const |
| getRegisterInfo - TargetInstrInfo is a superset of MRegister info. | |
| int64_t | getFrameAdjustment (const MachineInstr &I) const |
| Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g. | |
| void | setFrameAdjustment (MachineInstr &I, int64_t V) const |
| Sets the stack pointer adjustment made inside the frame made up by this instruction. | |
| int | getSPAdjust (const MachineInstr &MI) const override |
| getSPAdjust - This returns the stack pointer adjustment made by this instruction. | |
| bool | isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override |
| isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. | |
| unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override |
| unsigned | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. | |
| unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override |
| unsigned | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. | |
| bool | isReallyTriviallyReMaterializable (const MachineInstr &MI) const override |
| void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override |
| bool | classifyLEAReg (MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const |
| Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. | |
| MachineInstr * | convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override |
| convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. | |
| bool | findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override |
| Returns true iff the routine could find two commutable operands in the given machine instruction. | |
| bool | hasCommutePreference (MachineInstr &MI, bool &Commute) const override |
| Returns true if we have preference on the operands order in MI, the commute decision is returned in Commute. | |
| unsigned | getFMA3OpcodeToCommuteOperands (const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted. | |
| bool | isUnconditionalTailCall (const MachineInstr &MI) const override |
| bool | canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override |
| void | replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override |
| bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
| int | getJumpTableIndex (const MachineInstr &MI) const override |
| std::optional< ExtAddrMode > | getAddrModeFromMemoryOp (const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override |
| bool | getConstValDefinedInReg (const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override |
| bool | preservesZeroValueInReg (const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override |
| bool | getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override |
| bool | analyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override |
| unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
| unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
| bool | canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override |
| void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override |
| void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override |
| void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override |
| void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override |
| void | loadStoreTileReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const |
| bool | expandPostRAPseudo (MachineInstr &MI) const override |
| bool | isSubregFoldable () const override |
| Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override |
| foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override |
| foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. | |
| bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. | |
| bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override |
| unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override |
| getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. | |
| bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override |
| areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. | |
| bool | isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override |
| isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled. | |
| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. | |
| MCInst | getNop () const override |
| Return the noop instruction to use for a noop. | |
| bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
| bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override |
| isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. | |
| bool | hasLiveCondCodeDef (MachineInstr &MI) const |
| True if MI has a condition code def, e.g. | |
| unsigned | getGlobalBaseReg (MachineFunction *MF) const |
| getGlobalBaseReg - Return a virtual register initialized with the the global base register value. | |
| std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const override |
| uint16_t | getExecutionDomainCustom (const MachineInstr &MI) const |
| void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const override |
| bool | setExecutionDomainCustom (MachineInstr &MI, unsigned Domain) const |
| unsigned | getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update. | |
| unsigned | getUndefRegClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads. | |
| void | breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, Align Alignment, bool AllowCommute) const |
| bool | isHighLatencyDef (int opc) const override |
| bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override |
| bool | useMachineCombiner () const override |
| bool | isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override |
| bool | hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override |
| void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override |
| This is an architecture-specific helper function of reassociateOps. | |
| bool | analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override |
| analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. | |
| bool | optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override |
| optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. | |
| MachineInstr * | optimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override |
| optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. | |
| std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned TF) const override |
| ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const override |
| std::optional< outliner::OutlinedFunction > | getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override |
| bool | isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override |
| outliner::InstrType | getOutliningTypeImpl (MachineBasicBlock::iterator &MIT, unsigned Flags) const override |
| void | buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override |
| MachineBasicBlock::iterator | insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override |
| bool | verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override |
| std::optional< ParamLoadedValue > | describeLoadedValue (const MachineInstr &MI, Register Reg) const override |
Static Public Member Functions | |
| static bool | isDataInvariant (MachineInstr &MI) |
| Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands. | |
| static bool | isDataInvariantLoad (MachineInstr &MI) |
| Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands. | |
| static bool | hasLockPrefix (const MachineInstr &MI) |
Protected Member Functions | |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override |
| Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand. | |
| std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
| bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root. | |
| void | genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override |
| When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence. | |
| bool | accumulateInstrSeqToRootLatency (MachineInstr &Root) const override |
| When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency. | |
Detailed Description
Definition at line 138 of file X86InstrInfo.h.
Constructor & Destructor Documentation
◆ X86InstrInfo()
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explicit |
Definition at line 85 of file X86InstrInfo.cpp.
Member Function Documentation
◆ accumulateInstrSeqToRootLatency()
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inlineoverrideprotected |
When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency.
- Parameters
-
Root - Instruction that could be combined with one of its operands For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd is not in the critical path, so the root latency only include vpmaddwd.
Definition at line 631 of file X86InstrInfo.h.
◆ analyzeBranch()
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override |
Definition at line 3182 of file X86InstrInfo.cpp.
◆ analyzeBranchPredicate()
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override |
Definition at line 3250 of file X86InstrInfo.cpp.
References assert(), Cond, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), llvm::drop_begin(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), llvm::MachineOperand::isIdenticalTo(), MBB, MI, llvm::reverse(), llvm::MachineBasicBlock::successors(), and TRI.
◆ analyzeCompare()
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override |
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 4021 of file X86InstrInfo.cpp.
References MI.
◆ areLoadsFromSameBasePtr()
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override |
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 7231 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), I, and llvm::SDNode::isMachineOpcode().
◆ breakPartialRegDependency()
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override |
Definition at line 5866 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::get(), llvm::X86Subtarget::hasAVX(), llvm::RegState::ImplicitDefine, MI, TRI, and llvm::RegState::Undef.
◆ buildOutlinedFrame()
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override |
Definition at line 9719 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::get(), llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, and MBB.
◆ canInsertSelect()
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override |
Definition at line 3401 of file X86InstrInfo.cpp.
References llvm::X86Subtarget::canUseCMOV(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::X86::LAST_VALID_COND, MBB, and MRI.
◆ canMakeTailCallConditional()
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override |
Definition at line 2946 of file X86InstrInfo.cpp.
References assert(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getTCReturnAddrDelta(), llvm::MachineFunction::hasWinCFI(), llvm::X86Subtarget::isTargetWin64(), llvm::CodeModel::Kernel, llvm::X86::LAST_VALID_COND, and llvm::SmallVectorBase< Size_T >::size().
Referenced by replaceBranchWithTailCall().
◆ classifyLEAReg()
| bool X86InstrInfo::classifyLEAReg | ( | MachineInstr & | MI, |
| const MachineOperand & | Src, | ||
| unsigned | LEAOpcode, | ||
| bool | AllowSP, | ||
| Register & | NewSrc, | ||
| bool & | isKill, | ||
| MachineOperand & | ImplicitOp, | ||
| LiveVariables * | LV, | ||
| LiveIntervals * | LIS | ||
| ) | const |
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.
This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.
Reference parameters are set to indicate how caller should add this operand to the LEA instruction.
Definition at line 1064 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::LiveRange::Segment::end, llvm::get(), llvm::SlotIndex::getBaseIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineFunction::getRegInfo(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), llvm::getX86SubSuperRegister(), Idx, llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::Register::isPhysical(), llvm::Register::isValid(), llvm::Register::isVirtual(), MI, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), and llvm::RegState::Undef.
Referenced by convertToThreeAddress().
◆ commuteInstructionImpl()
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overrideprotected |
Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand.
The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands to be commuted.
Do not call this method for a non-commutable instruction or non-commutable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 1974 of file X86InstrInfo.cpp.
References assert(), CC, llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::countr_zero(), llvm::MachineOperand::CreateImm(), llvm::get(), getCommutedVPERMV3Opcode(), llvm::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::X86::GetOppositeBranchCondition(), llvm::X86::getSwappedVCMPImm(), llvm::X86::getSwappedVPCMPImm(), llvm::X86::getSwappedVPCOMImm(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), isCommutableVPERMV3Instruction(), llvm_unreachable, MI, llvm::popcount(), and Size.
◆ convertToThreeAddress()
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override |
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
FIXME: Support these similar to ADD8ri/ADD16ri*.
Definition at line 1309 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::get(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::LiveVariables::getVarInfo(), hasLiveCondCodeDef(), I, llvm::MachineBasicBlock::insert(), isTruncatedShiftCountForLEA(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), and llvm::LiveIntervals::ReplaceMachineInstrInMaps().
◆ copyPhysReg()
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override |
Definition at line 3537 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), CopyToFromAsymmetricReg(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), llvm::X86Subtarget::hasAVX(), isHReg(), LLVM_DEBUG, MBB, MI, llvm::report_fatal_error(), and TRI.
◆ decomposeMachineOperandsTargetFlags()
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override |
Definition at line 9309 of file X86InstrInfo.cpp.
◆ describeLoadedValue()
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override |
Definition at line 9120 of file X86InstrInfo.cpp.
References llvm::DIExpression::appendExt(), llvm::DIExpression::appendOffset(), assert(), contains(), llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), llvm::MDNode::get(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::isFI(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), MI, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
◆ expandPostRAPseudo()
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override |
Definition at line 4941 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), expandSHXDROT(), expandXorFP(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), getRegisterInfo(), llvm::getRegState(), llvm::X86Subtarget::hasAVX(), llvm::RegState::ImplicitDefine, MBB, MI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), TRI, and llvm::RegState::Undef.
◆ findCommutedOpIndices()
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override |
Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 2429 of file X86InstrInfo.cpp.
References llvm::X86II::EncodingMask, llvm::X86II::EVEX, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::getFMA3Group(), llvm::MCInstrDesc::getNumDefs(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::MCInstrDesc::isCommutable(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), MI, llvm::MCOI::TIED_TO, and llvm::MCInstrDesc::TSFlags.
Referenced by foldMemoryOperandImpl().
◆ foldMemoryOperandImpl() [1/3]
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override |
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.
Definition at line 6333 of file X86InstrInfo.cpp.
References llvm::MachineOperand::CreateFI(), foldMemoryOperandImpl(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineOperand::getSubReg(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), MI, NoFusing, shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), Size, and SubReg.
Referenced by foldMemoryOperandImpl().
◆ foldMemoryOperandImpl() [2/3]
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override |
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 6675 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), llvm::CallingConv::C, llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::get(), llvm::FixedVectorType::get(), llvm::getAlign(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::Type::getFP128Ty(), llvm::MachineFunction::getFunction(), llvm::Type::getHalfTy(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::MachineInstr::hasOneMemOperand(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), MI, NoFusing, llvm::MachineInstr::operands_begin(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), and llvm::CodeModel::Small.
◆ foldMemoryOperandImpl() [3/3]
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr & | MI, | ||
| unsigned | OpNum, | ||
| ArrayRef< MachineOperand > | MOs, | ||
| MachineBasicBlock::iterator | InsertPt, | ||
| unsigned | Size, | ||
| Align | Alignment, | ||
| bool | AllowCommute | ||
| ) | const |
Definition at line 6143 of file X86InstrInfo.cpp.
References llvm::X86::AddrDisp, llvm::X86::AddrNumOperands, llvm::dbgs(), llvm::MachineInstr::eraseFromParent(), findCommutedOpIndices(), foldMemoryOperandImpl(), FuseInst(), FuseTwoAddrInst(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasMinSize(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), I, llvm::Register::isPhysical(), llvm::lookupFoldTable(), llvm::lookupTwoAddrFoldTable(), MakeM0Inst(), MI, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTTPOFF, PrintFailedFusing, llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), Size, llvm::TB_ALIGN_MASK, llvm::TB_ALIGN_SHIFT, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::MCOI::TIED_TO, and TRI.
◆ genAlternativeCodeSequence()
|
overrideprotected |
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 9872 of file X86InstrInfo.cpp.
References llvm::DPWSSD, llvm::TargetInstrInfo::genAlternativeCodeSequence(), and genAlternativeDpCodeSequence().
◆ getAddrModeFromMemoryOp()
|
override |
Definition at line 3779 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and llvm::MCInstrDesc::TSFlags.
Referenced by verifyInstruction().
◆ getConstValDefinedInReg()
|
override |
Definition at line 3834 of file X86InstrInfo.cpp.
References MI.
◆ getExecutionDomain()
|
override |
Definition at line 8318 of file X86InstrInfo.cpp.
References getExecutionDomainCustom(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX512(), MI, ReplaceableInstrs, ReplaceableInstrsAVX2, ReplaceableInstrsAVX2InsertExtract, ReplaceableInstrsAVX512, ReplaceableInstrsAVX512DQ, ReplaceableInstrsAVX512DQMasked, ReplaceableInstrsFP, and llvm::X86II::SSEDomainShift.
◆ getExecutionDomainCustom()
| uint16_t X86InstrInfo::getExecutionDomainCustom | ( | const MachineInstr & | MI | ) | const |
Definition at line 8087 of file X86InstrInfo.cpp.
References AdjustBlendMask(), llvm::X86Subtarget::hasAVX2(), and MI.
Referenced by getExecutionDomain().
◆ getFMA3OpcodeToCommuteOperands()
| unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands | ( | const MachineInstr & | MI, |
| unsigned | SrcOpIdx1, | ||
| unsigned | SrcOpIdx2, | ||
| const X86InstrFMA3Group & | FMA3Group | ||
| ) | const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.
It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1
Definition at line 1805 of file X86InstrInfo.cpp.
References assert(), llvm::X86InstrFMA3Group::get132Opcode(), llvm::X86InstrFMA3Group::get213Opcode(), llvm::X86InstrFMA3Group::get231Opcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm_unreachable, and MI.
Referenced by commuteInstructionImpl().
◆ getFrameAdjustment()
|
inline |
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g.
by pushes, or inside the callee).
Definition at line 161 of file X86InstrInfo.h.
Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), and getSPAdjust().
◆ getGlobalBaseReg()
| unsigned X86InstrInfo::getGlobalBaseReg | ( | MachineFunction * | MF | ) | const |
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Return a virtual register initialized with the the global base register value.
Output instructions required to initialize the register in the function entry block, if necessary.
Output instructions required to initialize the register in the function entry block, if necessary.
TODO: Eliminate this and move the code to X86MachineFunctionInfo.
Definition at line 7513 of file X86InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetMachine::getCodeModel(), llvm::X86MachineFunctionInfo::getGlobalBaseReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getTarget(), llvm::CodeModel::Large, llvm::CodeModel::Medium, and llvm::X86MachineFunctionInfo::setGlobalBaseReg().
◆ getJumpTableIndex()
|
override |
Definition at line 3217 of file X86InstrInfo.cpp.
References llvm::Add, getJumpTableIndexFromAddr(), getJumpTableIndexFromReg(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
◆ getMachineCombinerPatterns()
|
overrideprotected |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
Definition at line 9754 of file X86InstrInfo.cpp.
References llvm::DPWSSD, llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::MachineInstr::getOpcode(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getMemOperandsWithOffsetWidth()
|
override |
Definition at line 3874 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::MCInstrDesc::TSFlags.
◆ getNop()
|
override |
Return the noop instruction to use for a noop.
Definition at line 8409 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode().
◆ getOpcodeAfterMemoryUnfold()
|
override |
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 7213 of file X86InstrInfo.cpp.
References I, llvm::lookupUnfoldTable(), llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and llvm::TB_INDEX_MASK.
◆ getOutliningCandidateInfo()
|
override |
Definition at line 9603 of file X86InstrInfo.cpp.
References llvm::CallingConv::C, I, MachineOutlinerDefault, MachineOutlinerTailCall, llvm::make_range(), and MI.
◆ getOutliningTypeImpl()
|
override |
Definition at line 9683 of file X86InstrInfo.cpp.
References llvm::outliner::Illegal, llvm::outliner::Legal, and MI.
◆ getPartialRegUpdateClearance()
|
override |
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update.
Definition at line 5487 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getReg(), hasPartialRegUpdate(), MI, PartialRegUpdateClearance, llvm::MachineOperand::readsReg(), and TRI.
◆ getRegisterInfo()
|
inline |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 157 of file X86InstrInfo.h.
Referenced by analyzeBranchPredicate(), copyPhysReg(), describeLoadedValue(), expandPostRAPseudo(), llvm::X86Subtarget::getRegisterInfo(), optimizeCompareInstr(), and replaceBranchWithTailCall().
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 9314 of file X86InstrInfo.cpp.
◆ getSPAdjust()
|
override |
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
For x86, we need to handle more complex call sequences involving PUSHes.
Definition at line 398 of file X86InstrInfo.cpp.
References llvm::alignTo(), E, llvm::MachineBasicBlock::end(), getFrameAdjustment(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineFunction::getSubtarget(), I, MBB, and MI.
◆ getUndefRegClearance()
|
override |
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads.
This catches the VCVTSI2SD family of instructions:
vcvtsi2sdq rax, undef xmm0, xmm14
We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:
vxorps undef xmm1, undef xmm1, xmm1
Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.
Definition at line 5857 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::Register::isPhysical(), MI, and UndefRegClearance.
◆ hasCommutePreference()
|
override |
Returns true if we have preference on the operands order in MI, the commute decision is returned in Commute.
Definition at line 2685 of file X86InstrInfo.cpp.
References isConvertibleLEA(), MI, and MRI.
◆ hasHighOperandLatency()
|
override |
Definition at line 8725 of file X86InstrInfo.cpp.
References DefMI, and isHighLatencyDef().
◆ hasLiveCondCodeDef()
| bool X86InstrInfo::hasLiveCondCodeDef | ( | MachineInstr & | MI | ) | const |
True if MI has a condition code def, e.g.
True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
EFLAGS, that is not marked dead.
Definition at line 938 of file X86InstrInfo.cpp.
References MI.
Referenced by convertToThreeAddress().
◆ hasLockPrefix()
|
inlinestatic |
Definition at line 578 of file X86InstrInfo.h.
References llvm::X86II::LOCK, and MI.
◆ hasReassociableOperands()
|
override |
Definition at line 8734 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::getNumDefs(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::MachineOperand::isDead(), and MBB.
◆ insertBranch()
|
override |
Definition at line 3342 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), CC, Cond, llvm::X86::COND_E_AND_NP, llvm::X86::COND_NE, llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP, llvm::X86::COND_P, DL, llvm::get(), getFallThroughMBB(), MBB, and TBB.
◆ insertOutlinedCall()
|
override |
Definition at line 9734 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::CallingConv::C, llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, and MBB.
◆ insertSelect()
|
override |
Definition at line 3438 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::X86::getCMovOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, MRI, and TRI.
◆ isAssociativeAndCommutative()
|
override |
Definition at line 8758 of file X86InstrInfo.cpp.
References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), and llvm::MachineInstr::getOpcode().
◆ isCoalescableExtInstr()
|
override |
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 96 of file X86InstrInfo.cpp.
References llvm_unreachable, and MI.
◆ isCopyInstrImpl()
|
overrideprotected |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 3623 of file X86InstrInfo.cpp.
References MI.
◆ isDataInvariant()
|
static |
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands.
Instructions are considered data invariant even if they set EFLAGS.
A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.
FIXME: This should become part of our instruction tables.
Definition at line 144 of file X86InstrInfo.cpp.
◆ isDataInvariantLoad()
|
static |
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands.
For example, if the latency of the instruction is dependent on the particular bits set in any of the registers or any of the bits loaded from memory.
Instructions are considered data invariant even if they set EFLAGS.
A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.
FIXME: This should become part of our instruction tables.
Definition at line 211 of file X86InstrInfo.cpp.
References MI.
◆ isFunctionSafeToOutlineFrom()
|
override |
Definition at line 9660 of file X86InstrInfo.cpp.
References F, llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::X86MachineFunctionInfo::getUsesRedZone(), and llvm::X86FrameLowering::has128ByteRedZone().
◆ isHighLatencyDef()
|
override |
Definition at line 8415 of file X86InstrInfo.cpp.
Referenced by hasHighOperandLatency().
◆ isLoadFromStackSlot() [1/2]
|
override |
Definition at line 656 of file X86InstrInfo.cpp.
References isLoadFromStackSlot(), and MI.
Referenced by foldMemoryOperandImpl(), isLoadFromStackSlot(), and isLoadFromStackSlotPostFE().
◆ isLoadFromStackSlot() [2/2]
|
override |
Definition at line 662 of file X86InstrInfo.cpp.
References isFrameLoadOpcode(), and MI.
◆ isLoadFromStackSlotPostFE()
|
override |
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 671 of file X86InstrInfo.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::front(), isFrameLoadOpcode(), isLoadFromStackSlot(), and MI.
◆ isReallyTriviallyReMaterializable()
|
override |
Definition at line 742 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, regIsPICBase(), and ReMatPICStubLoad.
◆ isSafeToMoveRegClassDefs()
|
override |
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 7498 of file X86InstrInfo.cpp.
◆ isSchedulingBoundary()
|
override |
isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled.
Definition at line 7477 of file X86InstrInfo.cpp.
References llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, and MI.
◆ isStoreToStackSlot() [1/2]
|
override |
Definition at line 690 of file X86InstrInfo.cpp.
References isStoreToStackSlot(), and MI.
Referenced by llvm::X86FrameLowering::emitPrologue(), isStoreToStackSlot(), and isStoreToStackSlotPostFE().
◆ isStoreToStackSlot() [2/2]
|
override |
Definition at line 696 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, isFrameStoreOpcode(), and MI.
◆ isStoreToStackSlotPostFE()
|
override |
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 706 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorTemplateCommon< T, typename >::front(), isFrameStoreOpcode(), isStoreToStackSlot(), and MI.
◆ isSubregFoldable()
|
inlineoverride |
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).
Definition at line 389 of file X86InstrInfo.h.
◆ isUnconditionalTailCall()
|
override |
Definition at line 2932 of file X86InstrInfo.cpp.
References MI.
◆ loadRegFromStackSlot()
|
override |
Definition at line 3998 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), assert(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), getLoadRegOpcode(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlign(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, and TRI.
Referenced by llvm::X86FrameLowering::restoreCalleeSavedRegisters().
◆ loadStoreTileReg()
| void X86InstrInfo::loadStoreTileReg | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | Opc, | ||
| Register | Reg, | ||
| int | FrameIdx, | ||
| bool | isKill = false |
||
| ) | const |
Definition at line 3941 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrIndexReg, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::get(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MBB, MI, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setReg().
Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().
◆ optimizeCompareInstr()
|
override |
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Definition at line 4336 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::addLiveIn(), assert(), llvm::BitWidth, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_S, llvm::MachineInstr::dropDebugNumber(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), findRedundantFlagInstr(), llvm::MachineInstr::findRegisterDefOperand(), From, llvm::get(), llvm::X86::getCondFromMI(), llvm::APInt::getMaxValue(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), getSwappedCondition(), llvm::MachineBasicBlock::insert(), isDefConvertible(), llvm::MachineBasicBlock::isLiveIn(), llvm::Register::isPhysical(), isUseDefConvertible(), llvm_unreachable, llvm::make_range(), MBB, MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_size(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineBasicBlock::rbegin(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::removeOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Successor, llvm::MachineBasicBlock::successors(), and TRI.
◆ optimizeLoadInstr()
|
override |
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.
Definition at line 4697 of file X86InstrInfo.cpp.
References assert(), DefMI, llvm::SmallVectorBase< Size_T >::empty(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), MI, MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ preservesZeroValueInReg()
|
override |
Definition at line 3846 of file X86InstrInfo.cpp.
References llvm::all_of(), assert(), llvm_unreachable, MI, and TRI.
◆ reMaterialize()
|
override |
Definition at line 905 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineBasicBlock::computeRegisterLiveness(), DL, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineBasicBlock::insert(), llvm_unreachable, llvm::MachineBasicBlock::LQR_Dead, MBB, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::substituteRegister(), and TRI.
◆ removeBranch()
|
override |
Definition at line 3319 of file X86InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), llvm::X86::getCondFromBranch(), I, and MBB.
◆ replaceBranchWithTailCall()
|
override |
Definition at line 2990 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::LivePhysRegs::addLiveOuts(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::CallingConv::C, canMakeTailCallConditional(), CC, llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::X86::getCondFromBranch(), getRegisterInfo(), I, llvm::RegState::Implicit, MBB, llvm::SmallVectorBase< Size_T >::size(), and llvm::LivePhysRegs::stepForward().
◆ reverseBranchCondition()
|
override |
Definition at line 7490 of file X86InstrInfo.cpp.
References assert(), CC, Cond, and GetOppositeBranchCondition().
◆ setExecutionDomain()
|
override |
Definition at line 8358 of file X86InstrInfo.cpp.
References assert(), llvm::get(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), lookup(), lookupAVX512(), MI, ReplaceableInstrs, ReplaceableInstrsAVX2, ReplaceableInstrsAVX2InsertExtract, ReplaceableInstrsAVX512, ReplaceableInstrsAVX512DQ, ReplaceableInstrsAVX512DQMasked, ReplaceableInstrsFP, setExecutionDomainCustom(), and llvm::X86II::SSEDomainShift.
◆ setExecutionDomainCustom()
| bool X86InstrInfo::setExecutionDomainCustom | ( | MachineInstr & | MI, |
| unsigned | Domain | ||
| ) | const |
Definition at line 8185 of file X86InstrInfo.cpp.
References AdjustBlendMask(), assert(), llvm::get(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX512(), MI, ReplaceableBlendAVX2Instrs, ReplaceableBlendInstrs, ReplaceableCustomAVX512LogicInstrs, and llvm::X86II::SSEDomainShift.
Referenced by setExecutionDomain().
◆ setFrameAdjustment()
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Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition at line 170 of file X86InstrInfo.h.
◆ setSpecialOperandAttr()
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This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 9263 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::clearFlag(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::getFlags(), llvm::MachineOperand::isDead(), llvm::MachineInstr::IsExact, llvm::MachineInstr::NoSWrap, llvm::MachineInstr::NoUWrap, llvm::MachineInstr::setFlags(), and llvm::MachineOperand::setIsDead().
◆ shouldScheduleLoadsNear()
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 7429 of file X86InstrInfo.cpp.
References assert(), llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), and llvm::MVT::SimpleTy.
◆ storeRegToStackSlot()
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Definition at line 3976 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlign(), getStoreRegOpcode(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, and TRI.
Referenced by llvm::X86FrameLowering::spillCalleeSavedRegisters().
◆ unfoldMemoryOperand() [1/2]
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unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 6948 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, DL, extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), getLoadRegOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), llvm::getUndefRegState(), I, llvm::RegState::Implicit, llvm::isAligned(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::RegState::Kill, llvm_unreachable, llvm::lookupUnfoldTable(), MI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), llvm::SmallVectorBase< Size_T >::size(), llvm::TB_FOLDED_BCAST, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.
◆ unfoldMemoryOperand() [2/2]
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Definition at line 7088 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::append_range(), extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::MCInstrDesc::getNumDefs(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), I, llvm::isAligned(), llvm::isNullConstant(), llvm_unreachable, llvm::lookupUnfoldTable(), N, llvm::MCInstrDesc::NumDefs, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::setNodeMemRefs(), llvm::TB_FOLDED_BCAST, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.
◆ useMachineCombiner()
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Definition at line 511 of file X86InstrInfo.h.
◆ verifyInstruction()
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Definition at line 3805 of file X86InstrInfo.cpp.
References llvm::ExtAddrMode::Displacement, getAddrModeFromMemoryOp(), MI, llvm::ExtAddrMode::Scale, and llvm::ExtAddrMode::ScaledReg.
The documentation for this class was generated from the following files:
- lib/Target/X86/X86InstrInfo.h
- lib/Target/X86/X86InstrInfo.cpp
