LLVM  14.0.0git
llvm::X86TargetLowering Member List

This is the complete list of members for llvm::X86TargetLowering, including all inherited members.

addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) constllvm::TargetLoweringvirtual
aggressivelyPreferBuildVectorSources(EVT VecVT) constllvm::TargetLoweringBaseinlinevirtual
alignLoopsWithOptSize() constllvm::TargetLoweringBaseinlinevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) constllvm::TargetLoweringBasevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, bool *Fast=nullptr) constllvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const overridellvm::X86TargetLoweringvirtual
llvm::TargetLowering::allowsMisalignedMemoryAccesses(LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) constllvm::TargetLoweringBaseinlinevirtual
allowTruncateForTailCall(Type *Ty1, Type *Ty2) const overridellvm::X86TargetLoweringvirtual
areJTsAllowed(const Function *Fn) const overridellvm::X86TargetLoweringvirtual
ArgListTy typedefllvm::TargetLoweringBase
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer, MachinePointerInfo PtrInfo, Align Alignment, SelectionDAG &DAG) constllvm::X86TargetLowering
buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) constllvm::TargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
C_Immediate enum valuellvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) constllvm::TargetLoweringBaseinlinevirtual
canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) constllvm::TargetLoweringBaseinlinevirtual
canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const overridellvm::X86TargetLoweringvirtual
canOpTrap(unsigned Op, EVT VT) constllvm::TargetLoweringBasevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) constllvm::TargetLoweringvirtual
computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::X86TargetLoweringvirtual
computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) constllvm::TargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const overridellvm::X86TargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
convertSelectOfConstantsToMath(EVT VT) const overridellvm::X86TargetLoweringvirtual
convertSetCCLogicToBitwiseLogic(EVT VT) const overridellvm::X86TargetLoweringinlinevirtual
createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const overridellvm::X86TargetLoweringvirtual
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const overridellvm::X86TargetLoweringvirtual
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) constllvm::TargetLoweringBaseinlinevirtual
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const overridellvm::X86TargetLoweringvirtual
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const overridellvm::X86TargetLoweringvirtual
emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
enableAggressiveFMAFusion(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
enableAggressiveFMAFusion(LLT Ty) constllvm::TargetLoweringBaseinlinevirtual
Enabled enum valuellvm::TargetLoweringBase
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
enableExtLdPromotion() constllvm::TargetLoweringBaseinline
Expand enum valuellvm::TargetLoweringBase
expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) constllvm::TargetLowering
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandBITREVERSE(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandBSWAP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTLZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTPOP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTTZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
ExpandInlineAsm(CallInst *CI) const overridellvm::X86TargetLoweringvirtual
expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandROT(SDNode *N, bool AllowVectorOps, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) constllvm::TargetLowering
expandShlSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduce(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVectorSplice(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
fallBackToDAGISel(const Instruction &Inst) constllvm::TargetLoweringBaseinlinevirtual
finalizeLowering(MachineFunction &MF) constllvm::TargetLoweringBasevirtual
findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) constllvm::TargetLowering
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const overridellvm::X86TargetLoweringprotectedvirtual
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
generateFMAsInMachineCombiner(EVT VT, CodeGenOpt::Level OptLevel) constllvm::TargetLoweringBaseinlinevirtual
getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) constllvm::TargetLoweringBaseinlinevirtual
getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinlinevirtual
getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) constllvm::TargetLoweringBase
getBooleanContents(bool isVec, bool isFloat) constllvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) constllvm::TargetLoweringBaseinline
getBypassSlowDivWidths() constllvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) const overridellvm::X86TargetLoweringvirtual
getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, SDValue Offsets) constllvm::TargetLowering
getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getClearCacheBuiltinName() const overridellvm::X86TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getCmpLibcallReturnType() constllvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
getConstraintType(StringRef Constraint) const overridellvm::X86TargetLoweringvirtual
getCustomCtpopCost(EVT VT, ISD::CondCode Cond) constllvm::TargetLoweringBaseinlinevirtual
getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) constllvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getExceptionPointerRegister(const Constant *PersonalityFn) const overridellvm::X86TargetLoweringvirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) const overridellvm::X86TargetLoweringvirtual
getExtendForAtomicCmpSwapArg() constllvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicOps() constllvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getFenceOperandTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinline
getFrameIndexTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getGatherAllAliasesMaxDepth() constllvm::TargetLoweringBaseinline
getIndexedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getInlineAsmMemConstraint(StringRef ConstraintCode) const overridellvm::X86TargetLoweringinlinevirtual
getIRStackGuard(IRBuilderBase &IRB) const overridellvm::X86TargetLoweringvirtual
getJumpTableEncoding() const overridellvm::X86TargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) constllvm::TargetLoweringBase
getMaxAtomicSizeInBitsSupported() constllvm::TargetLoweringBaseinline
getMaxExpandSizeMemcmp(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxGluedStoresPerMemcpy() constllvm::TargetLoweringBaseinlinevirtual
getMaximumJumpTableSize() constllvm::TargetLoweringBase
getMaxStoresPerMemcpy(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() const overridellvm::X86TargetLoweringinlinevirtual
getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getMinCmpXchgSizeInBits() constllvm::TargetLoweringBaseinline
getMinFunctionAlignment() constllvm::TargetLoweringBaseinline
getMinimumJumpTableDensity(bool OptForSize) constllvm::TargetLoweringBase
getMinimumJumpTableEntries() constllvm::TargetLoweringBasevirtual
getMinStackArgumentAlignment() constllvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) constllvm::TargetLoweringvirtual
getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const overridellvm::X86TargetLoweringvirtual
llvm::TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) constllvm::TargetLoweringBaseinlinevirtual
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::X86TargetLoweringvirtual
getOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getOptimalMemOpLLT(const MemOp &Op, const AttributeList &) constllvm::TargetLoweringBaseinlinevirtual
getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const overridellvm::X86TargetLoweringvirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const overridellvm::X86TargetLoweringvirtual
getPointerMemTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPointerTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getPreferredShiftAmountTy(LLT ShiftValueTy) constllvm::TargetLoweringBaseinlinevirtual
getPreferredVectorAction(MVT VT) const overridellvm::X86TargetLoweringvirtual
getPrefFunctionAlignment() constllvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML) const overridellvm::X86TargetLoweringvirtual
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getProgramPointerTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRegClassFor(MVT VT, bool isDivergent=false) constllvm::TargetLoweringBaseinlinevirtual
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const overridellvm::X86TargetLoweringvirtual
getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const overridellvm::X86TargetLoweringvirtual
getRegisterType(MVT VT) constllvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::X86TargetLoweringvirtual
getRepRegClassCostFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getReturnAddressFrameIndex(SelectionDAG &DAG) constllvm::X86TargetLowering
getSafeStackPointerLocation(IRBuilderBase &IRB) const overridellvm::X86TargetLoweringvirtual
getScalarShiftAmountTy(const DataLayout &, EVT VT) const overridellvm::X86TargetLoweringinlinevirtual
getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const overridellvm::X86TargetLoweringvirtual
getSchedulingPreference() constllvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) constllvm::TargetLoweringBaseinlinevirtual
getSDagStackGuard(const Module &M) const overridellvm::X86TargetLoweringvirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const overridellvm::X86TargetLoweringvirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) constllvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const overridellvm::X86TargetLoweringvirtual
getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) constllvm::TargetLoweringvirtual
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
getSSPStackGuardCheck(const Module &M) const overridellvm::X86TargetLoweringvirtual
getStackPointerRegisterToSaveRestore() constllvm::TargetLoweringBaseinline
getStackProbeSize(MachineFunction &MF) constllvm::X86TargetLowering
getStackProbeSymbolName(MachineFunction &MF) const overridellvm::X86TargetLoweringvirtual
getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) constllvm::TargetLoweringBase
getStrictFPOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getTargetConstantFromLoad(LoadSDNode *LD) const overridellvm::X86TargetLoweringvirtual
getTargetMachine() constllvm::TargetLoweringBaseinline
getTargetMMOFlags(const Instruction &I) constllvm::TargetLoweringBaseinlinevirtual
getTargetNodeName(unsigned Opcode) const overridellvm::X86TargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const overridellvm::X86TargetLoweringvirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeAction(MVT VT) constllvm::TargetLoweringBaseinline
getTypeLegalizationCost(const DataLayout &DL, Type *Ty) constllvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) constllvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getVaListSizeInBits(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getValueTypeActions() constllvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) constllvm::TargetLowering
getVectorIdxTy(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) constllvm::TargetLowering
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBase
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const overridellvm::X86TargetLoweringvirtual
getVPExplicitVectorLengthTy() constllvm::TargetLoweringBaseinlinevirtual
HandleByVal(CCState *, unsigned &, Align) constllvm::TargetLoweringinlinevirtual
hasAndNot(SDValue Y) const overridellvm::X86TargetLoweringvirtual
hasAndNotCompare(SDValue Y) const overridellvm::X86TargetLoweringvirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) constllvm::TargetLoweringBaseinline
hasBitPreservingFPLogic(EVT VT) const overridellvm::X86TargetLoweringinlinevirtual
hasBitTest(SDValue X, SDValue Y) const overridellvm::X86TargetLoweringvirtual
hasExtractBitsInsn() constllvm::TargetLoweringBaseinline
hasFastEqualityCompare(unsigned NumBits) const overridellvm::X86TargetLoweringvirtual
hasInlineStackProbe(MachineFunction &MF) const overridellvm::X86TargetLoweringvirtual
hasMultipleConditionRegisters() constllvm::TargetLoweringBaseinline
hasPairedLoad(EVT, Align &) constllvm::TargetLoweringBaseinlinevirtual
hasStackProbeSymbol(MachineFunction &MF) const overridellvm::X86TargetLoweringvirtual
hasStandaloneRem(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) constllvm::TargetLoweringBaseinline
hasVectorBlend() const overridellvm::X86TargetLoweringinlinevirtual
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) constllvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
insertSSPDeclarations(Module &M) const overridellvm::X86TargetLoweringvirtual
InstructionOpcodeToISD(unsigned Opcode) constllvm::TargetLoweringBase
isBinOp(unsigned Opcode) const overridellvm::X86TargetLoweringvirtual
isCheapToSpeculateCtlz() const overridellvm::X86TargetLoweringvirtual
isCheapToSpeculateCttz() const overridellvm::X86TargetLoweringvirtual
isCommutativeBinOp(unsigned Opcode) const overridellvm::X86TargetLoweringvirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1, LLT Ty2) constllvm::TargetLoweringBaseinlinevirtual
isConstFalseVal(const SDNode *N) constllvm::TargetLowering
isConstTrueVal(const SDNode *N) constllvm::TargetLowering
isCtlzFast() const overridellvm::X86TargetLoweringvirtual
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) constllvm::TargetLoweringinlinevirtual
IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const overridellvm::X86TargetLoweringvirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) constllvm::TargetLoweringinlinevirtual
isEqualityCmpFoldedWithSignedCmp() constllvm::TargetLoweringBaseinlinevirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) constllvm::TargetLowering
isExtFree(const Instruction *I) constllvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) constllvm::TargetLoweringBaseinlineprotectedvirtual
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const overridellvm::X86TargetLoweringvirtual
isExtractVecEltCheap(EVT VT, unsigned Index) const overridellvm::X86TargetLoweringinlinevirtual
isFAbsFree(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isFMADLegal(const MachineInstr &MI, LLT Ty) constllvm::TargetLoweringBaseinlinevirtual
isFMADLegal(const SelectionDAG &DAG, const SDNode *N) constllvm::TargetLoweringBaseinlinevirtual
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const overridellvm::X86TargetLoweringvirtual
llvm::TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) constllvm::TargetLoweringBaseinlinevirtual
llvm::TargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F, Type *) constllvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const overridellvm::X86TargetLoweringvirtual
isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) constllvm::TargetLoweringBasevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) constllvm::TargetLoweringvirtual
isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) constllvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) constllvm::TargetLoweringinlinevirtual
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) constllvm::TargetLowering
isIntDivCheap(EVT VT, AttributeList Attr) const overridellvm::X86TargetLoweringvirtual
isJumpExpensive() constllvm::TargetLoweringBaseinline
isJumpTableRelative() constllvm::TargetLoweringBasevirtual
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) constllvm::TargetLoweringvirtual
isLegalAddImmediate(int64_t Imm) const overridellvm::X86TargetLoweringvirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const overridellvm::X86TargetLoweringvirtual
isLegalICmpImmediate(int64_t Imm) const overridellvm::X86TargetLoweringvirtual
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) constllvm::TargetLoweringBaseprotected
isLegalStoreImmediate(int64_t Imm) const overridellvm::X86TargetLoweringvirtual
isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const overridellvm::X86TargetLoweringvirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const overridellvm::X86TargetLoweringvirtual
isMulAddWithConstProfitable(const SDValue &AddNode, const SDValue &ConstNode) constllvm::TargetLoweringBaseinlinevirtual
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const overridellvm::X86TargetLoweringinlinevirtual
isNarrowingProfitable(EVT VT1, EVT VT2) const overridellvm::X86TargetLoweringvirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) constllvm::TargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isPositionIndependent() constllvm::TargetLowering
isPredictableSelectExpensive() constllvm::TargetLoweringBaseinline
isProfitableToCombineMinNumMaxNum(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isProfitableToHoist(Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
isSafeMemOpType(MVT VT) const overridellvm::X86TargetLoweringvirtual
isScalarFPTypeInSSEReg(EVT VT) constllvm::X86TargetLoweringinline
isSDNodeAlwaysUniform(const SDNode *N) constllvm::TargetLoweringinlinevirtual
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) constllvm::TargetLoweringinlinevirtual
isSelectSupported(SelectSupportKind) constllvm::TargetLoweringBaseinlinevirtual
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const overridellvm::X86TargetLoweringvirtual
isSlowDivBypassed() constllvm::TargetLoweringBaseinline
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) constllvm::TargetLoweringBaseinlinevirtual
IsStrictFPEnabledllvm::TargetLoweringBaseprotected
isStrictFPEnabled() constllvm::TargetLoweringBaseinline
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) constllvm::TargetLoweringBasevirtual
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinlinevirtual
isTruncateFree(Type *Ty1, Type *Ty2) const overridellvm::X86TargetLoweringvirtual
isTruncateFree(EVT VT1, EVT VT2) const overridellvm::X86TargetLoweringvirtual
llvm::TargetLowering::isTruncateFree(LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned Opc, EVT VT) const overridellvm::X86TargetLoweringvirtual
isTypeLegal(EVT VT) constllvm::TargetLoweringBaseinline
isVectorClearMaskLegal(ArrayRef< int > Mask, EVT VT) const overridellvm::X86TargetLoweringvirtual
isVectorLoadExtDesirable(SDValue) const overridellvm::X86TargetLoweringvirtual
isVectorShiftByScalarCheap(Type *Ty) const overridellvm::X86TargetLoweringvirtual
isZExtFree(Type *Ty1, Type *Ty2) const overridellvm::X86TargetLoweringvirtual
isZExtFree(EVT VT1, EVT VT2) const overridellvm::X86TargetLoweringvirtual
isZExtFree(SDValue Val, EVT VT2) const overridellvm::X86TargetLoweringvirtual
llvm::TargetLowering::isZExtFree(LLT FromTy, LLT ToTy, const DataLayout &DL, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, const SDLoc &DL, const AsmOperandInfo &Constraint, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
LowerCallTo(CallLoweringInfo &CLI) constllvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const overridellvm::X86TargetLoweringvirtual
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const overridellvm::X86TargetLoweringvirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const overridellvm::X86TargetLoweringvirtual
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerXConstraint(EVT ConstraintVT) const overridellvm::X86TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) constllvm::TargetLowering
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const overridellvm::X86TargetLoweringvirtual
MaxGluedStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mergeStoresAfterLegalization(EVT MemVT) const overridellvm::X86TargetLoweringinlinevirtual
MulExpansionKind enum namellvm::TargetLoweringBase
needsFixedCatchObjects() const overridellvm::X86TargetLoweringvirtual
NegatibleCost enum namellvm::TargetLoweringBase
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) constllvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) constllvm::TargetLoweringvirtual
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::X86TargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
preferIncOfAddToSubOfNot(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
preferZeroCompareBranch() constllvm::TargetLoweringBaseinlinevirtual
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
ReciprocalEstimate enum namellvm::TargetLoweringBase
reduceSelectOfFPConstantLoads(EVT CmpOpVT) const overridellvm::X86TargetLoweringvirtual
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
requiresUniformRegister(MachineFunction &MF, const Value *) constllvm::TargetLoweringBaseinlinevirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(Register R)llvm::TargetLoweringBaseinlineprotected
setSupportsUnalignedAtomics(bool UnalignedSupported)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) constllvm::TargetLoweringBaseinlinevirtual
shouldAvoidTransformToShift(EVT VT, unsigned Amount) constllvm::TargetLoweringBaseinlinevirtual
shouldConsiderGEPOffsetSplit() constllvm::TargetLoweringBaseinlinevirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const overridellvm::X86TargetLoweringvirtual
shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const overridellvm::X86TargetLoweringinlinevirtual
shouldConvertPhiType(Type *From, Type *To) const overridellvm::X86TargetLoweringvirtual
shouldConvertSplatType(ShuffleVectorInst *SVI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandShift(SelectionDAG &DAG, SDNode *N) const overridellvm::X86TargetLoweringvirtual
shouldExtendGSIndex(EVT VT, EVT &EltTy) constllvm::TargetLoweringBaseinlinevirtual
shouldExtendTypeInLibCall(EVT Type) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const overridellvm::X86TargetLoweringvirtual
shouldFoldMaskToVariableShiftPair(SDValue Y) const overridellvm::X86TargetLoweringvirtual
shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const overridellvm::X86TargetLoweringvirtual
shouldInsertFencesForAtomic(const Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
shouldKeepZExtForFP16Conv() constllvm::TargetLoweringBaseinlinevirtual
shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) constllvm::TargetLoweringBasevirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const overridellvm::X86TargetLoweringvirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const overridellvm::X86TargetLoweringvirtual
shouldRemoveExtendFromGSIndex(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldScalarizeBinop(SDValue) const overridellvm::X86TargetLoweringvirtual
ShouldShrinkFPConstant(EVT VT) const overridellvm::X86TargetLoweringinlinevirtual
shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const overridellvm::X86TargetLoweringvirtual
shouldSplatInsEltVarIndex(EVT VT) const overridellvm::X86TargetLoweringvirtual
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const overridellvm::X86TargetLoweringinlinevirtual
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const overridellvm::X86TargetLoweringvirtual
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const overridellvm::X86TargetLoweringvirtual
SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op, const APInt &DemandedElts, unsigned MaskIndex, TargetLoweringOpt &TLO, unsigned Depth) constllvm::X86TargetLowering
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) constllvm::TargetLowering
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const overridellvm::X86TargetLoweringvirtual
SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
softPromoteHalfType() const overridellvm::X86TargetLoweringinlinevirtual
splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const overridellvm::X86TargetLoweringinlinevirtual
supportsUnalignedAtomics() constllvm::TargetLoweringBaseinline
supportSwiftError() const overridellvm::X86TargetLoweringvirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const overridellvm::X86TargetLoweringvirtual
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeScalableVector enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSoftPromoteHalf enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
unwrapAddress(SDValue N) const overridellvm::X86TargetLoweringvirtual
useLoadStackGuardNode() const overridellvm::X86TargetLoweringvirtual
useSoftFloat() const overridellvm::X86TargetLoweringvirtual
useStackGuardXorFP() const overridellvm::X86TargetLoweringvirtual
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)llvm::X86TargetLoweringexplicit
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual