LLVM  14.0.0git
Enumerations
llvm::PPCISD Namespace Reference

Enumerations

enum  NodeType : unsigned {
  FIRST_NUMBER = ISD::BUILTIN_OP_END, FSEL, XSMAXCDP, XSMINCDP,
  FCFID, FCFIDU, FCFIDS, FCFIDUS,
  FCTIDZ, FCTIWZ, FCTIDUZ, FCTIWUZ,
  FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR, VEXTS, FRE,
  FRSQRTE, FTSQRT, FSQRT, VPERM,
  XXSPLT, XXSPLTI_SP_TO_DP, XXSPLTI32DX, VECINSERT,
  VECSHL, XXPERMDI, CMPB, Hi,
  Lo, DYNALLOC, DYNAREAOFFSET, PROBED_ALLOCA,
  GlobalBaseReg, SRL, SRA, SHL,
  FNMSUB, EXTSWSLI, SRA_ADDZE, CALL,
  CALL_NOP, CALL_NOTOC, MTCTR, BCTRL,
  BCTRL_LOAD_TOC, RET_FLAG, MFOCRF, MFVSR,
  MTVSRA, MTVSRZ, BUILD_FP128, BUILD_SPE64,
  EXTRACT_SPE, SINT_VEC_TO_FP, UINT_VEC_TO_FP, SCALAR_TO_VECTOR_PERMUTED,
  ANDI_rec_1_EQ_BIT, ANDI_rec_1_GT_BIT, READ_TIME_BASE, EH_SJLJ_SETJMP,
  EH_SJLJ_LONGJMP, VCMP, VCMP_rec, COND_BRANCH,
  BDNZ, BDZ, FADDRTZ, MFFS,
  TC_RETURN, CR6SET, CR6UNSET, PPC32_GOT,
  PPC32_PICGOT, ADDIS_GOT_TPREL_HA, LD_GOT_TPREL_L, ADD_TLS,
  ADDIS_TLSGD_HA, ADDI_TLSGD_L, GET_TLS_ADDR, ADDI_TLSGD_L_ADDR,
  TLSGD_AIX, ADDIS_TLSLD_HA, ADDI_TLSLD_L, GET_TLSLD_ADDR,
  ADDI_TLSLD_L_ADDR, ADDIS_DTPREL_HA, ADDI_DTPREL_L, PADDI_DTPREL,
  VADD_SPLAT, SC, CLRBHRB, MFBHRBE,
  RFEBB, XXSWAPD, SWAP_NO_CHAIN, VABSD,
  FP_EXTEND_HALF, MAT_PCREL_ADDR, TLS_DYNAMIC_MAT_PCREL_ADDR, TLS_LOCAL_EXEC_MAT_ADDR,
  ACC_BUILD, PAIR_BUILD, EXTRACT_VSX_REG, XXMFACC,
  STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, STRICT_FCTIWZ, STRICT_FCTIDUZ, STRICT_FCTIWUZ,
  STRICT_FCFID, STRICT_FCFIDU, STRICT_FCFIDS, STRICT_FCFIDUS,
  STRICT_FADDRTZ, STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, LBRX, STFIWX,
  LFIWAX, LFIWZX, LXSIZX, STXSIX,
  LXVD2X, LXVRZX, LOAD_VEC_BE, LD_VSX_LH,
  LD_SPLAT, STXVD2X, STORE_VEC_BE, ST_VSR_SCAL_INT,
  ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16, TOC_ENTRY
}
 

Enumeration Type Documentation

◆ NodeType

enum llvm::PPCISD::NodeType : unsigned
Enumerator
FIRST_NUMBER 
FSEL 

FSEL - Traditional three-operand fsel node.

XSMAXCDP 

XSMAXCDP, XSMINCDP - C-type min/max instructions.

XSMINCDP 
FCFID 

FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP representation of the integer that was temporarily in the f64 operand.

FCFIDU 

Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-precision outputs.

FCFIDS 
FCFIDUS 
FCTIDZ 

FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value containing the integer representation of that FP value.

FCTIWZ 
FCTIDUZ 

Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round toward zero.

FCTIWUZ 
FP_TO_UINT_IN_VSR 

Floating-point-to-interger conversion instructions.

FP_TO_SINT_IN_VSR 
VEXTS 

VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from ByteWidth to a 64-byte integer.

FRE 

Reciprocal estimate instructions (unary FP ops).

FRSQRTE 
FTSQRT 

Test instruction for software square root.

FSQRT 

Square root instruction.

VPERM 

VPERM - The PPC VPERM Instruction.

XXSPLT 

XXSPLT - The PPC VSX splat instructions.

XXSPLTI_SP_TO_DP 

XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single precision numbers to double precision vector or scalar.

XXSPLTI32DX 

XXSPLTI32DX - The PPC XXSPLTI32DX instruction.

VECINSERT 

VECINSERT - The PPC vector insert instruction.

VECSHL 

VECSHL - The PPC vector shift left instruction.

XXPERMDI 

XXPERMDI - The PPC XXPERMDI instruction.

CMPB 

The CMPB instruction (takes two operands of i32 or i64).

Hi 

Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.

These nodes have two operands, the first of which must be a TargetGlobalAddress, and the second of which must be a Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', though these are usually folded into other nodes.

Lo 
DYNALLOC 

The following two target-specific nodes are used for calls through function pointers in the 64-bit SVR4 ABI.

OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an allocation on the stack.

DYNAREAOFFSET 

This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native SP to the address of the most recent dynamic alloca.

PROBED_ALLOCA 

To avoid stack clash, allocation is performed by block and each block is probed.

GlobalBaseReg 

The result of the mflr at function entry, used for PIC code.

SRL 

These nodes represent PPC shifts.

For scalar types, only the last `n + 1` bits of the shift amounts
are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
for exact behaviors.

For vector types, only the last n bits are used. See vsld. 
SRA 
SHL 
FNMSUB 

FNMSUB - Negated multiply-subtract instruction.

EXTSWSLI 

EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.

SRA_ADDZE 

The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.

The first operand is the dividend, and the second is the constant shift amount (representing the divisor).

CALL 

CALL - A direct function call.

CALL_NOP is a call with the special NOP which follows 64-bit CALL_NOTOC the caller does not use the TOC. SVR4 calls and 32-bit/64-bit AIX calls.

CALL_NOP 
CALL_NOTOC 
MTCTR 

CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.

BCTRL 

CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.

BCTRL_LOAD_TOC 

CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload required on 64-bit ELF, 32-bit AIX and 64-bit AIX.

RET_FLAG 

Return with a flag operand, matched by 'blr'.

MFOCRF 

R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.

This copies the bits corresponding to the specified CRREG into the resultant GPR. Bits corresponding to other CR regs are undefined.

MFVSR 

Direct move from a VSX register to a GPR.

MTVSRA 

Direct move from a GPR to a VSX register (algebraic)

MTVSRZ 

Direct move from a GPR to a VSX register (zero)

BUILD_FP128 

Direct move of 2 consecutive GPR to a VSX register.

BUILD_SPE64 

BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is unsupported for this target.

Merge 2 GPRs to a single SPE register.

EXTRACT_SPE 

Extract SPE register component, second argument is high or low.

SINT_VEC_TO_FP 

Extract a subvector from signed integer vector and convert to FP.

It is primarily used to convert a (widened) illegal integer vector type to a legal floating point vector type. For example v2i32 -> widened to v4i32 -> v2f64

UINT_VEC_TO_FP 

Extract a subvector from unsigned integer vector and convert to FP.

As with SINT_VEC_TO_FP, used for converting illegal types.

SCALAR_TO_VECTOR_PERMUTED 

PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least significant element of the most significant doubleword in the vector.

This is not element zero for anything smaller than a doubleword on either endianness. This node has the same semantics as SCALAR_TO_VECTOR except that the value remains in the aforementioned location in the vector register.

ANDI_rec_1_EQ_BIT 

i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after executing andi.

x, 1. This is used to implement truncation of i32 or i64 to i1.

ANDI_rec_1_GT_BIT 
READ_TIME_BASE 
EH_SJLJ_SETJMP 
EH_SJLJ_LONGJMP 
VCMP 

RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.

For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.

VCMP_rec 

RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.

For lack of better number, we use the opcode number encoding for the OPC field to identify the compare. For example, 838 is VCMPGTSH.

COND_BRANCH 

CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo instruction.

CRRC is the condition register to branch on, OPC is the branch opcode to use (e.g. PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is an optional input flag argument.

BDNZ 

CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.

BDZ 
FADDRTZ 

F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.

Used only as part of the long double-to-int conversion sequence.

MFFS 

F8RC = MFFS - This moves the FPSCR (not modeled) into the register.

TC_RETURN 

TC_RETURN - A tail call return.

operand #0 chain operand #1 callee (register or absolute) operand #2 stack adjustment operand #3 optional in flag

CR6SET 

ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls

CR6UNSET 
PPC32_GOT 

GPRC = address of GLOBAL_OFFSET_TABLE.

Used by initial-exec TLS for non-position independent code on PPC32.

PPC32_PICGOT 

GPRC = address of GLOBAL_OFFSET_TABLE.

Used by general dynamic and local dynamic TLS and position indendepent code on PPC32.

ADDIS_GOT_TPREL_HA 

G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruction that adds the GOT base to sym@got@tprel@ha.

LD_GOT_TPREL_L 

G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction with base register G8RReg and offset sym@got@tprel@l.

This completes the addition that finds the offset of "sym" relative to the thread pointer.

ADD_TLS 

G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that adds the contents of G8RReg to the thread pointer.

Symbol contains a relocation sym@tls which is to be replaced by the thread pointer and identifies to the linker that the instruction is part of a TLS sequence.

ADDIS_TLSGD_HA 

G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction that adds the GOT base register to sym@got@tlsgd@ha.

ADDI_TLSGD_L 

x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@tlsgd@l and stores the result in X3.

Hidden by ADDIS_TLSGD_L_ADDR until after register assignment.

GET_TLS_ADDR 

x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(sym@tlsgd).

Hidden by ADDIS_TLSGD_L_ADDR until after register assignment.

ADDI_TLSGD_L_ADDR 

G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following register assignment.

TLSGD_AIX 

GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two register copies of TOC entries (region handle into R3 and variable offset into R4) followed by a GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr.

This node is used in 64-bit mode as well (in which case the result is G8RC and inputs are X3/X4).

ADDIS_TLSLD_HA 

G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction that adds the GOT base register to sym@got@tlsld@ha.

ADDI_TLSLD_L 

x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@tlsld@l and stores the result in X3.

Hidden by ADDIS_TLSLD_L_ADDR until after register assignment.

GET_TLSLD_ADDR 

x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(sym@tlsld).

Hidden by ADDIS_TLSLD_L_ADDR until after register assignment.

ADDI_TLSLD_L_ADDR 

G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion following register assignment.

ADDIS_DTPREL_HA 

G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction that adds X3 to sym@dtprel@ha.

ADDI_DTPREL_L 

G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction that adds G8RReg to sym@got@dtprel@l.

PADDI_DTPREL 

G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 instruction that adds X3 to sym@dtprel.

VADD_SPLAT 

VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimize a BUILD_VECTOR into operations on splats.

This is necessary to avoid losing these optimizations due to constant folding.

SC 

CHAIN = SC CHAIN, Imm128 - System call.

The 7-bit unsigned operand identifies the operating system entry point.

CLRBHRB 

CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.

MFBHRBE 

GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.

RFEBB 

CHAIN = RFEBB CHAIN, State - Return from event-based branch.

XXSWAPD 

VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.

Maps to an xxswapd instruction that corrects an lxvd2x or stxvd2x instruction. The chain is necessary because the sequence replaces a load and needs to provide the same number of outputs.

SWAP_NO_CHAIN 

An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.

VABSD 

An SDNode for Power9 vector absolute value difference.

operand #0 vector operand #1 vector operand #2 constant i32 0 or 1, to indicate whether needs to patch the most significant bit for signed i32

Power9 VABSD* instructions are designed to support unsigned integer vectors (byte/halfword/word), if we want to make use of them for signed integer vectors, we have to flip their sign bits first. To flip sign bit for byte/halfword integer vector would become inefficient, but for word integer vector, we can leverage XVNEGSP to make it efficiently. eg: abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) => VABSDUW((XVNEGSP a), (XVNEGSP b))

FP_EXTEND_HALF 

FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f64.

MAT_PCREL_ADDR 

MAT_PCREL_ADDR = Materialize a PC Relative address.

This can be done either through an add like PADDI or through a PC Relative load like PLD.

TLS_DYNAMIC_MAT_PCREL_ADDR 

TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dynamic access models.

This can be done through an add like PADDI.

TLS_LOCAL_EXEC_MAT_ADDR 

TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access models, and when prefixed instructions are available.

This is used with ADD_TLS to produce an add like PADDI.

ACC_BUILD 

ACC_BUILD = Build an accumulator register from 4 VSX registers.

PAIR_BUILD 

PAIR_BUILD = Build a vector pair register from 2 VSX registers.

EXTRACT_VSX_REG 

EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.

This node is needed because EXTRACT_SUBVECTOR expects the input and output vectors to have the same element type.

XXMFACC 

XXMFACC = This corresponds to the xxmfacc instruction.

STRICT_FCTIDZ 
STRICT_FCTIWZ 
STRICT_FCTIDUZ 
STRICT_FCTIWUZ 
STRICT_FCFID 

Constrained integer-to-floating-point conversion instructions.

STRICT_FCFIDU 
STRICT_FCFIDS 
STRICT_FCFIDUS 
STRICT_FADDRTZ 

Constrained floating point add in round-to-zero mode.

STBRX 

CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.

It byte-swaps the low "Type" bits of the GPRC input, then stores it through Ptr. Type can be either i16 or i32.

LBRX 

GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.

It loads "Type" bits, byte swaps it, then puts it in the bottom bits of the GPRC. TYPE can be either i16 or i32.

STFIWX 

STFIWX - The STFIWX instruction.

The first operand is an input token chain, then an f64 value to store, then an address to store it to.

LFIWAX 

GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit integer value into the destination 64-bit register.

LFIWZX 

GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit integer value into the destination 64-bit register.

LXSIZX 

GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into a VSR.

The integer is zero-extended. This can be used for converting loaded integers to floating point.

STXSIX 

STXSIX - The STXSI[bh]X instruction.

The first operand is an input chain, then an f64 value to store, then an address to store it to, followed by a byte-width for the store.

LXVD2X 

VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.

Maps directly to an lxvd2x instruction that will be followed by an xxswapd.

LXVRZX 

LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero extending load instruction from <byte, halfword, word, or doubleword> to i128.

Allows utilization of the Load VSX Vector Rightmost Instructions.

LOAD_VEC_BE 

VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.

Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on the vector type to load vector in big-endian element order.

LD_VSX_LH 

VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower half of a VSR register.

LD_SPLAT 

VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX, LXVWSX.

STXVD2X 

CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.

Maps directly to an stxvd2x instruction that will be preceded by an xxswapd.

STORE_VEC_BE 

CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.

Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on the vector type to store vector in big-endian element order.

ST_VSR_SCAL_INT 

Store scalar integers from VSR.

ATOMIC_CMP_SWAP_8 

ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare input is zero-extended for sub-word versions because the atomic loads zero-extend.

ATOMIC_CMP_SWAP_16 
TOC_ENTRY 

GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last operand.

Definition at line 46 of file PPCISelLowering.h.