LLVM  10.0.0svn
WebAssemblyTargetTransformInfo.cpp
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1 //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific TargetTransformInfo
11 /// implementation.
12 ///
13 //===----------------------------------------------------------------------===//
14 
16 #include "llvm/CodeGen/CostTable.h"
17 #include "llvm/Support/Debug.h"
18 using namespace llvm;
19 
20 #define DEBUG_TYPE "wasmtti"
21 
23 WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
24  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
26 }
27 
29  unsigned Result = BaseT::getNumberOfRegisters(Vector);
30 
31  // For SIMD, use at least 16 registers, as a rough guess.
32  if (Vector)
33  Result = std::max(Result, 16u);
34 
35  return Result;
36 }
37 
38 unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
39  if (Vector && getST()->hasSIMD128())
40  return 128;
41 
42  return 64;
43 }
44 
46  unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
49 
51  Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
52 
53  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
54  switch (Opcode) {
55  case Instruction::LShr:
56  case Instruction::AShr:
57  case Instruction::Shl:
58  // SIMD128's shifts currently only accept a scalar shift count. For each
59  // element, we'll need to extract, op, insert. The following is a rough
60  // approxmation.
61  if (Opd2Info != TTI::OK_UniformValue &&
62  Opd2Info != TTI::OK_UniformConstantValue)
63  Cost = VTy->getNumElements() *
65  getArithmeticInstrCost(Opcode, VTy->getElementType()) +
67  break;
68  }
69  }
70  return Cost;
71 }
72 
73 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
74  unsigned Index) {
75  unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
76 
77  // SIMD128's insert/extract currently only take constant indices.
78  if (Index == -1u)
79  return Cost + 25 * TargetTransformInfo::TCC_Expensive;
80 
81  return Cost;
82 }
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
Definition: BasicTTIImpl.h:589
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Cost tables and simple lookup functions.
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
This file a TargetTransformInfo::Concept conforming object specific to the WebAssembly target machine...
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const
PopcntSupportKind
Flags indicating the kind of support for population count.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
OperandValueProperties
Additional properties of an operand&#39;s values.
unsigned getRegisterBitWidth(bool Vector) const
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:833
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical &#39;add&#39; instruction.
OperandValueKind
Additional information about an operand&#39;s possible values.
The cost of a &#39;div&#39; instruction on x86.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.