LLVM  9.0.0svn
TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
52 #include "llvm/Support/Casting.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <climits>
59 #include <cstdint>
60 #include <iterator>
61 #include <map>
62 #include <string>
63 #include <utility>
64 #include <vector>
65 
66 namespace llvm {
67 
68 class BranchProbability;
69 class CCState;
70 class CCValAssign;
71 class Constant;
72 class FastISel;
73 class FunctionLoweringInfo;
74 class GlobalValue;
75 class IntrinsicInst;
76 struct KnownBits;
77 class LLVMContext;
78 class MachineBasicBlock;
79 class MachineFunction;
80 class MachineInstr;
81 class MachineJumpTableInfo;
82 class MachineLoop;
83 class MachineRegisterInfo;
84 class MCContext;
85 class MCExpr;
86 class Module;
87 class TargetRegisterClass;
88 class TargetLibraryInfo;
89 class TargetRegisterInfo;
90 class Value;
91 
92 namespace Sched {
93 
94  enum Preference {
95  None, // No preference
96  Source, // Follow source order.
97  RegPressure, // Scheduling for lowest register pressure.
98  Hybrid, // Scheduling for both latency and register pressure.
99  ILP, // Scheduling for ILP in low register pressure mode.
100  VLIW // Scheduling for VLIW targets.
101  };
102 
103 } // end namespace Sched
104 
105 /// This base class for TargetLowering contains the SelectionDAG-independent
106 /// parts that can be used from the rest of CodeGen.
108 public:
109  /// This enum indicates whether operations are valid for a target, and if not,
110  /// what action should be used to make them valid.
111  enum LegalizeAction : uint8_t {
112  Legal, // The target natively supports this operation.
113  Promote, // This operation should be executed in a larger type.
114  Expand, // Try to expand this to other ops, otherwise use a libcall.
115  LibCall, // Don't try to expand this to other ops, always use a libcall.
116  Custom // Use the LowerOperation hook to implement custom lowering.
117  };
118 
119  /// This enum indicates whether a types are legal for a target, and if not,
120  /// what action should be used to make them valid.
121  enum LegalizeTypeAction : uint8_t {
122  TypeLegal, // The target natively supports this type.
123  TypePromoteInteger, // Replace this integer with a larger one.
124  TypeExpandInteger, // Split this integer into two of half the size.
125  TypeSoftenFloat, // Convert this float to a same size integer type,
126  // if an operation is not supported in target HW.
127  TypeExpandFloat, // Split this float into two of half the size.
128  TypeScalarizeVector, // Replace this one-element vector with its element.
129  TypeSplitVector, // Split this vector into two of half the size.
130  TypeWidenVector, // This vector should be widened into a larger vector.
131  TypePromoteFloat // Replace this float with a larger one.
132  };
133 
134  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135  /// in order to type-legalize it.
136  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 
138  /// Enum that describes how the target represents true/false values.
140  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143  };
144 
145  /// Enum that describes what type of support for selects the target has.
147  ScalarValSelect, // The target supports scalar selects (ex: cmov).
148  ScalarCondVectorVal, // The target supports selects with a scalar condition
149  // and vector values (ex: cmov).
150  VectorMaskSelect // The target supports vector selects with a vector
151  // mask (ex: x86 blends).
152  };
153 
154  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155  /// to, if at all. Exists because different targets have different levels of
156  /// support for these atomic instructions, and also have different options
157  /// w.r.t. what they should expand to.
158  enum class AtomicExpansionKind {
159  None, // Don't expand the instruction.
160  LLSC, // Expand the instruction into loadlinked/storeconditional; used
161  // by ARM/AArch64.
162  LLOnly, // Expand the (load) instruction into just a load-linked, which has
163  // greater atomic guarantees than a normal load.
164  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(const CallBase *Call, unsigned ArgIdx);
198 
199  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
200  return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
201  }
202  };
203  using ArgListTy = std::vector<ArgListEntry>;
204 
205  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
206  ArgListTy &Args) const {};
207 
209  switch (Content) {
210  case UndefinedBooleanContent:
211  // Extend by adding rubbish bits.
212  return ISD::ANY_EXTEND;
213  case ZeroOrOneBooleanContent:
214  // Extend by adding zero bits.
215  return ISD::ZERO_EXTEND;
216  case ZeroOrNegativeOneBooleanContent:
217  // Extend by copying the sign bit.
218  return ISD::SIGN_EXTEND;
219  }
220  llvm_unreachable("Invalid content kind");
221  }
222 
223  /// NOTE: The TargetMachine owns TLOF.
224  explicit TargetLoweringBase(const TargetMachine &TM);
225  TargetLoweringBase(const TargetLoweringBase &) = delete;
226  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
227  virtual ~TargetLoweringBase() = default;
228 
229 protected:
230  /// Initialize all of the actions to default values.
231  void initActions();
232 
233 public:
234  const TargetMachine &getTargetMachine() const { return TM; }
235 
236  virtual bool useSoftFloat() const { return false; }
237 
238  /// Return the pointer type for the given address space, defaults to
239  /// the pointer type from the data layout.
240  /// FIXME: The default needs to be removed once all the code is updated.
241  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
243  }
244 
245  /// Return the type for frame index, which is determined by
246  /// the alloca address space specified through the data layout.
247  MVT getFrameIndexTy(const DataLayout &DL) const {
248  return getPointerTy(DL, DL.getAllocaAddrSpace());
249  }
250 
251  /// Return the type for operands of fence.
252  /// TODO: Let fence operands be of i32 type and remove this.
253  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
254  return getPointerTy(DL);
255  }
256 
257  /// EVT is not used in-tree, but is used by out-of-tree target.
258  /// A documentation for this function would be nice...
259  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
260 
261  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
262  bool LegalTypes = true) const;
263 
264  /// Returns the type to be used for the index operand of:
265  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
266  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
267  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
268  return getPointerTy(DL);
269  }
270 
271  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
272  return true;
273  }
274 
275  /// Return true if it is profitable to convert a select of FP constants into
276  /// a constant pool load whose address depends on the select condition. The
277  /// parameter may be used to differentiate a select with FP compare from
278  /// integer compare.
279  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
280  return true;
281  }
282 
283  /// Return true if multiple condition registers are available.
285  return HasMultipleConditionRegisters;
286  }
287 
288  /// Return true if the target has BitExtract instructions.
289  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
290 
291  /// Return the preferred vector type legalization action.
294  // The default action for one element vectors is to scalarize
295  if (VT.getVectorNumElements() == 1)
296  return TypeScalarizeVector;
297  // The default action for an odd-width vector is to widen.
298  if (!VT.isPow2VectorType())
299  return TypeWidenVector;
300  // The default action for other vectors is to promote
301  return TypePromoteInteger;
302  }
303 
304  // There are two general methods for expanding a BUILD_VECTOR node:
305  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
306  // them together.
307  // 2. Build the vector on the stack and then load it.
308  // If this function returns true, then method (1) will be used, subject to
309  // the constraint that all of the necessary shuffles are legal (as determined
310  // by isShuffleMaskLegal). If this function returns false, then method (2) is
311  // always used. The vector type, and the number of defined values, are
312  // provided.
313  virtual bool
315  unsigned DefinedValues) const {
316  return DefinedValues < 3;
317  }
318 
319  /// Return true if integer divide is usually cheaper than a sequence of
320  /// several shifts, adds, and multiplies for this target.
321  /// The definition of "cheaper" may depend on whether we're optimizing
322  /// for speed or for size.
323  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
324 
325  /// Return true if the target can handle a standalone remainder operation.
326  virtual bool hasStandaloneRem(EVT VT) const {
327  return true;
328  }
329 
330  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
331  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
332  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
333  return false;
334  }
335 
336  /// Reciprocal estimate status values used by the functions below.
337  enum ReciprocalEstimate : int {
338  Unspecified = -1,
339  Disabled = 0,
341  };
342 
343  /// Return a ReciprocalEstimate enum value for a square root of the given type
344  /// based on the function's attributes. If the operation is not overridden by
345  /// the function's attributes, "Unspecified" is returned and target defaults
346  /// are expected to be used for instruction selection.
347  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
348 
349  /// Return a ReciprocalEstimate enum value for a division of the given type
350  /// based on the function's attributes. If the operation is not overridden by
351  /// the function's attributes, "Unspecified" is returned and target defaults
352  /// are expected to be used for instruction selection.
353  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
354 
355  /// Return the refinement step count for a square root of the given type based
356  /// on the function's attributes. If the operation is not overridden by
357  /// the function's attributes, "Unspecified" is returned and target defaults
358  /// are expected to be used for instruction selection.
359  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
360 
361  /// Return the refinement step count for a division of the given type based
362  /// on the function's attributes. If the operation is not overridden by
363  /// the function's attributes, "Unspecified" is returned and target defaults
364  /// are expected to be used for instruction selection.
365  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
366 
367  /// Returns true if target has indicated at least one type should be bypassed.
368  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
369 
370  /// Returns map of slow types for division or remainder with corresponding
371  /// fast types
373  return BypassSlowDivWidths;
374  }
375 
376  /// Return true if Flow Control is an expensive operation that should be
377  /// avoided.
378  bool isJumpExpensive() const { return JumpIsExpensive; }
379 
380  /// Return true if selects are only cheaper than branches if the branch is
381  /// unlikely to be predicted right.
383  return PredictableSelectIsExpensive;
384  }
385 
386  /// If a branch or a select condition is skewed in one direction by more than
387  /// this factor, it is very likely to be predicted correctly.
388  virtual BranchProbability getPredictableBranchThreshold() const;
389 
390  /// Return true if the following transform is beneficial:
391  /// fold (conv (load x)) -> (load (conv*)x)
392  /// On architectures that don't natively support some vector loads
393  /// efficiently, casting the load to a smaller vector of larger types and
394  /// loading is more efficient, however, this can be undone by optimizations in
395  /// dag combiner.
396  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
397  EVT BitcastVT) const {
398  // Don't do if we could do an indexed load on the original type, but not on
399  // the new one.
400  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
401  return true;
402 
403  MVT LoadMVT = LoadVT.getSimpleVT();
404 
405  // Don't bother doing this if it's just going to be promoted again later, as
406  // doing so might interfere with other combines.
407  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
408  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
409  return false;
410 
411  return true;
412  }
413 
414  /// Return true if the following transform is beneficial:
415  /// (store (y (conv x)), y*)) -> (store x, (x*))
416  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
417  // Default to the same logic as loads.
418  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
419  }
420 
421  /// Return true if it is expected to be cheaper to do a store of a non-zero
422  /// vector constant with the given size and type for the address space than to
423  /// store the individual scalar element constants.
424  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
425  unsigned NumElem,
426  unsigned AddrSpace) const {
427  return false;
428  }
429 
430  /// Allow store merging after legalization in addition to before legalization.
431  /// This may catch stores that do not exist earlier (eg, stores created from
432  /// intrinsics).
433  virtual bool mergeStoresAfterLegalization() const { return true; }
434 
435  /// Returns if it's reasonable to merge stores to MemVT size.
436  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
437  const SelectionDAG &DAG) const {
438  return true;
439  }
440 
441  /// Return true if it is cheap to speculate a call to intrinsic cttz.
442  virtual bool isCheapToSpeculateCttz() const {
443  return false;
444  }
445 
446  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
447  virtual bool isCheapToSpeculateCtlz() const {
448  return false;
449  }
450 
451  /// Return true if ctlz instruction is fast.
452  virtual bool isCtlzFast() const {
453  return false;
454  }
455 
456  /// Return true if it is safe to transform an integer-domain bitwise operation
457  /// into the equivalent floating-point operation. This should be set to true
458  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
459  /// type.
460  virtual bool hasBitPreservingFPLogic(EVT VT) const {
461  return false;
462  }
463 
464  /// Return true if it is cheaper to split the store of a merged int val
465  /// from a pair of smaller values into multiple stores.
466  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
467  return false;
468  }
469 
470  /// Return if the target supports combining a
471  /// chain like:
472  /// \code
473  /// %andResult = and %val1, #mask
474  /// %icmpResult = icmp %andResult, 0
475  /// \endcode
476  /// into a single machine instruction of a form like:
477  /// \code
478  /// cc = test %register, #mask
479  /// \endcode
480  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
481  return false;
482  }
483 
484  /// Use bitwise logic to make pairs of compares more efficient. For example:
485  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
486  /// This should be true when it takes more than one instruction to lower
487  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
488  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
489  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
490  return false;
491  }
492 
493  /// Return the preferred operand type if the target has a quick way to compare
494  /// integer values of the given size. Assume that any legal integer type can
495  /// be compared efficiently. Targets may override this to allow illegal wide
496  /// types to return a vector type if there is support to compare that type.
497  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
498  MVT VT = MVT::getIntegerVT(NumBits);
499  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
500  }
501 
502  /// Return true if the target should transform:
503  /// (X & Y) == Y ---> (~X & Y) == 0
504  /// (X & Y) != Y ---> (~X & Y) != 0
505  ///
506  /// This may be profitable if the target has a bitwise and-not operation that
507  /// sets comparison flags. A target may want to limit the transformation based
508  /// on the type of Y or if Y is a constant.
509  ///
510  /// Note that the transform will not occur if Y is known to be a power-of-2
511  /// because a mask and compare of a single bit can be handled by inverting the
512  /// predicate, for example:
513  /// (X & 8) == 8 ---> (X & 8) != 0
514  virtual bool hasAndNotCompare(SDValue Y) const {
515  return false;
516  }
517 
518  /// Return true if the target has a bitwise and-not operation:
519  /// X = ~A & B
520  /// This can be used to simplify select or other instructions.
521  virtual bool hasAndNot(SDValue X) const {
522  // If the target has the more complex version of this operation, assume that
523  // it has this operation too.
524  return hasAndNotCompare(X);
525  }
526 
527  /// There are two ways to clear extreme bits (either low or high):
528  /// Mask: x & (-1 << y) (the instcombine canonical form)
529  /// Shifts: x >> y << y
530  /// Return true if the variant with 2 variable shifts is preferred.
531  /// Return false if there is no preference.
533  // By default, let's assume that no one prefers shifts.
534  return false;
535  }
536 
537  /// Return true if it is profitable to fold a pair of shifts into a mask.
538  /// This is usually true on most targets. But some targets, like Thumb1,
539  /// have immediate shift instructions, but no immediate "and" instruction;
540  /// this makes the fold unprofitable.
542  CombineLevel Level) const {
543  return true;
544  }
545 
546  /// Should we tranform the IR-optimal check for whether given truncation
547  /// down into KeptBits would be truncating or not:
548  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
549  /// Into it's more traditional form:
550  /// ((%x << C) a>> C) dstcond %x
551  /// Return true if we should transform.
552  /// Return false if there is no preference.
554  unsigned KeptBits) const {
555  // By default, let's assume that no one prefers shifts.
556  return false;
557  }
558 
559  /// Return true if the target wants to use the optimization that
560  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
561  /// promotedInst1(...(promotedInstN(ext(load)))).
562  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
563 
564  /// Return true if the target can combine store(extractelement VectorTy,
565  /// Idx).
566  /// \p Cost[out] gives the cost of that transformation when this is true.
567  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
568  unsigned &Cost) const {
569  return false;
570  }
571 
572  /// Return true if inserting a scalar into a variable element of an undef
573  /// vector is more efficiently handled by splatting the scalar instead.
574  virtual bool shouldSplatInsEltVarIndex(EVT) const {
575  return false;
576  }
577 
578  /// Return true if target supports floating point exceptions.
580  return HasFloatingPointExceptions;
581  }
582 
583  /// Return true if target always beneficiates from combining into FMA for a
584  /// given value type. This must typically return false on targets where FMA
585  /// takes more cycles to execute than FADD.
586  virtual bool enableAggressiveFMAFusion(EVT VT) const {
587  return false;
588  }
589 
590  /// Return the ValueType of the result of SETCC operations.
591  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
592  EVT VT) const;
593 
594  /// Return the ValueType for comparison libcalls. Comparions libcalls include
595  /// floating point comparion calls, and Ordered/Unordered check calls on
596  /// floating point numbers.
597  virtual
598  MVT::SimpleValueType getCmpLibcallReturnType() const;
599 
600  /// For targets without i1 registers, this gives the nature of the high-bits
601  /// of boolean values held in types wider than i1.
602  ///
603  /// "Boolean values" are special true/false values produced by nodes like
604  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
605  /// Not to be confused with general values promoted from i1. Some cpus
606  /// distinguish between vectors of boolean and scalars; the isVec parameter
607  /// selects between the two kinds. For example on X86 a scalar boolean should
608  /// be zero extended from i1, while the elements of a vector of booleans
609  /// should be sign extended from i1.
610  ///
611  /// Some cpus also treat floating point types the same way as they treat
612  /// vectors instead of the way they treat scalars.
613  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
614  if (isVec)
615  return BooleanVectorContents;
616  return isFloat ? BooleanFloatContents : BooleanContents;
617  }
618 
620  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
621  }
622 
623  /// Return target scheduling preference.
625  return SchedPreferenceInfo;
626  }
627 
628  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
629  /// for different nodes. This function returns the preference (or none) for
630  /// the given node.
632  return Sched::None;
633  }
634 
635  /// Return the register class that should be used for the specified value
636  /// type.
637  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
638  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
639  assert(RC && "This value type is not natively supported!");
640  return RC;
641  }
642 
643  /// Return the 'representative' register class for the specified value
644  /// type.
645  ///
646  /// The 'representative' register class is the largest legal super-reg
647  /// register class for the register class of the value type. For example, on
648  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
649  /// register class is GR64 on x86_64.
650  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
651  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
652  return RC;
653  }
654 
655  /// Return the cost of the 'representative' register class for the specified
656  /// value type.
657  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
658  return RepRegClassCostForVT[VT.SimpleTy];
659  }
660 
661  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
662  /// instructions, and false if a library call is preferred (e.g for code-size
663  /// reasons).
664  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
665  return true;
666  }
667 
668  /// Return true if the target has native support for the specified value type.
669  /// This means that it has a register that directly holds it without
670  /// promotions or expansions.
671  bool isTypeLegal(EVT VT) const {
672  assert(!VT.isSimple() ||
673  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
674  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
675  }
676 
678  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
679  /// that indicates how instruction selection should deal with the type.
680  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
681 
682  public:
684  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
685  TypeLegal);
686  }
687 
689  return ValueTypeActions[VT.SimpleTy];
690  }
691 
693  ValueTypeActions[VT.SimpleTy] = Action;
694  }
695  };
696 
698  return ValueTypeActions;
699  }
700 
701  /// Return how we should legalize values of this type, either it is already
702  /// legal (return 'Legal') or we need to promote it to a larger type (return
703  /// 'Promote'), or we need to expand it into multiple registers of smaller
704  /// integer type (return 'Expand'). 'Custom' is not an option.
706  return getTypeConversion(Context, VT).first;
707  }
709  return ValueTypeActions.getTypeAction(VT);
710  }
711 
712  /// For types supported by the target, this is an identity function. For
713  /// types that must be promoted to larger types, this returns the larger type
714  /// to promote to. For integer types that are larger than the largest integer
715  /// register, this contains one step in the expansion to get to the smaller
716  /// register. For illegal floating point types, this returns the integer type
717  /// to transform to.
718  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
719  return getTypeConversion(Context, VT).second;
720  }
721 
722  /// For types supported by the target, this is an identity function. For
723  /// types that must be expanded (i.e. integer types that are larger than the
724  /// largest integer register or illegal floating point types), this returns
725  /// the largest legal type it will be expanded to.
726  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
727  assert(!VT.isVector());
728  while (true) {
729  switch (getTypeAction(Context, VT)) {
730  case TypeLegal:
731  return VT;
732  case TypeExpandInteger:
733  VT = getTypeToTransformTo(Context, VT);
734  break;
735  default:
736  llvm_unreachable("Type is not legal nor is it to be expanded!");
737  }
738  }
739  }
740 
741  /// Vector types are broken down into some number of legal first class types.
742  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
743  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
744  /// turns into 4 EVT::i32 values with both PPC and X86.
745  ///
746  /// This method returns the number of registers needed, and the VT for each
747  /// register. It also returns the VT and quantity of the intermediate values
748  /// before they are promoted/expanded.
749  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
750  EVT &IntermediateVT,
751  unsigned &NumIntermediates,
752  MVT &RegisterVT) const;
753 
754  /// Certain targets such as MIPS require that some types such as vectors are
755  /// always broken down into scalars in some contexts. This occurs even if the
756  /// vector type is legal.
758  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
759  unsigned &NumIntermediates, MVT &RegisterVT) const {
760  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
761  RegisterVT);
762  }
763 
764  struct IntrinsicInfo {
765  unsigned opc = 0; // target opcode
766  EVT memVT; // memory VT
767 
768  // value representing memory location
770 
771  int offset = 0; // offset off of ptrVal
772  unsigned size = 0; // the size of the memory location
773  // (taken from memVT if zero)
774  unsigned align = 1; // alignment
775 
777  IntrinsicInfo() = default;
778  };
779 
780  /// Given an intrinsic, checks if on the target the intrinsic will need to map
781  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
782  /// true and store the intrinsic information into the IntrinsicInfo that was
783  /// passed to the function.
784  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
785  MachineFunction &,
786  unsigned /*Intrinsic*/) const {
787  return false;
788  }
789 
790  /// Returns true if the target can instruction select the specified FP
791  /// immediate natively. If false, the legalizer will materialize the FP
792  /// immediate as a load from a constant pool.
793  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/,
794  bool ForCodeSize = false) const {
795  return false;
796  }
797 
798  /// Targets can use this to indicate that they only support *some*
799  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
800  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
801  /// legal.
802  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
803  return true;
804  }
805 
806  /// Returns true if the operation can trap for the value type.
807  ///
808  /// VT must be a legal type. By default, we optimistically assume most
809  /// operations don't trap except for integer divide and remainder.
810  virtual bool canOpTrap(unsigned Op, EVT VT) const;
811 
812  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
813  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
814  /// constant pool entry.
815  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
816  EVT /*VT*/) const {
817  return false;
818  }
819 
820  /// Return how this operation should be treated: either it is legal, needs to
821  /// be promoted to a larger size, needs to be expanded to some other code
822  /// sequence, or the target has a custom expander for it.
823  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
824  if (VT.isExtended()) return Expand;
825  // If a target-specific SDNode requires legalization, require the target
826  // to provide custom legalization for it.
827  if (Op >= array_lengthof(OpActions[0])) return Custom;
828  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
829  }
830 
831  /// Custom method defined by each target to indicate if an operation which
832  /// may require a scale is supported natively by the target.
833  /// If not, the operation is illegal.
834  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
835  unsigned Scale) const {
836  return false;
837  }
838 
839  /// Some fixed point operations may be natively supported by the target but
840  /// only for specific scales. This method allows for checking
841  /// if the width is supported by the target for a given operation that may
842  /// depend on scale.
844  unsigned Scale) const {
845  auto Action = getOperationAction(Op, VT);
846  if (Action != Legal)
847  return Action;
848 
849  // This operation is supported in this type but may only work on specific
850  // scales.
851  bool Supported;
852  switch (Op) {
853  default:
854  llvm_unreachable("Unexpected fixed point operation.");
855  case ISD::SMULFIX:
856  case ISD::UMULFIX:
857  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
858  break;
859  }
860 
861  return Supported ? Action : Expand;
862  }
863 
865  unsigned EqOpc;
866  switch (Op) {
867  default: llvm_unreachable("Unexpected FP pseudo-opcode");
868  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
869  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
870  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
871  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
872  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
873  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
874  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
875  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
876  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
877  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
878  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
879  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
880  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
881  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
882  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
883  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
884  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
885  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
886  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
887  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
888  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
889  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
890  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
891  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
892  }
893 
894  auto Action = getOperationAction(EqOpc, VT);
895 
896  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
897  // For now, we just expand for those cases.
898  if (Action != Legal)
899  Action = Expand;
900 
901  return Action;
902  }
903 
904  /// Return true if the specified operation is legal on this target or can be
905  /// made legal with custom lowering. This is used to help guide high-level
906  /// lowering decisions.
907  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
908  return (VT == MVT::Other || isTypeLegal(VT)) &&
909  (getOperationAction(Op, VT) == Legal ||
910  getOperationAction(Op, VT) == Custom);
911  }
912 
913  /// Return true if the specified operation is legal on this target or can be
914  /// made legal using promotion. This is used to help guide high-level lowering
915  /// decisions.
916  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
917  return (VT == MVT::Other || isTypeLegal(VT)) &&
918  (getOperationAction(Op, VT) == Legal ||
919  getOperationAction(Op, VT) == Promote);
920  }
921 
922  /// Return true if the specified operation is legal on this target or can be
923  /// made legal with custom lowering or using promotion. This is used to help
924  /// guide high-level lowering decisions.
925  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
926  return (VT == MVT::Other || isTypeLegal(VT)) &&
927  (getOperationAction(Op, VT) == Legal ||
928  getOperationAction(Op, VT) == Custom ||
929  getOperationAction(Op, VT) == Promote);
930  }
931 
932  /// Return true if the operation uses custom lowering, regardless of whether
933  /// the type is legal or not.
934  bool isOperationCustom(unsigned Op, EVT VT) const {
935  return getOperationAction(Op, VT) == Custom;
936  }
937 
938  /// Return true if lowering to a jump table is allowed.
939  virtual bool areJTsAllowed(const Function *Fn) const {
940  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
941  return false;
942 
943  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
944  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
945  }
946 
947  /// Check whether the range [Low,High] fits in a machine word.
948  bool rangeFitsInWord(const APInt &Low, const APInt &High,
949  const DataLayout &DL) const {
950  // FIXME: Using the pointer type doesn't seem ideal.
951  uint64_t BW = DL.getIndexSizeInBits(0u);
952  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
953  return Range <= BW;
954  }
955 
956  /// Return true if lowering to a jump table is suitable for a set of case
957  /// clusters which may contain \p NumCases cases, \p Range range of values.
958  /// FIXME: This function check the maximum table size and density, but the
959  /// minimum size is not checked. It would be nice if the minimum size is
960  /// also combined within this function. Currently, the minimum size check is
961  /// performed in findJumpTable() in SelectionDAGBuiler and
962  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
963  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
964  uint64_t Range) const {
965  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
966  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
967  const unsigned MaxJumpTableSize =
968  OptForSize ? UINT_MAX : getMaximumJumpTableSize();
969  // Check whether a range of clusters is dense enough for a jump table.
970  if (Range <= MaxJumpTableSize &&
971  (NumCases * 100 >= Range * MinDensity)) {
972  return true;
973  }
974  return false;
975  }
976 
977  /// Return true if lowering to a bit test is suitable for a set of case
978  /// clusters which contains \p NumDests unique destinations, \p Low and
979  /// \p High as its lowest and highest case values, and expects \p NumCmps
980  /// case value comparisons. Check if the number of destinations, comparison
981  /// metric, and range are all suitable.
982  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
983  const APInt &Low, const APInt &High,
984  const DataLayout &DL) const {
985  // FIXME: I don't think NumCmps is the correct metric: a single case and a
986  // range of cases both require only one branch to lower. Just looking at the
987  // number of clusters and destinations should be enough to decide whether to
988  // build bit tests.
989 
990  // To lower a range with bit tests, the range must fit the bitwidth of a
991  // machine word.
992  if (!rangeFitsInWord(Low, High, DL))
993  return false;
994 
995  // Decide whether it's profitable to lower this range with bit tests. Each
996  // destination requires a bit test and branch, and there is an overall range
997  // check branch. For a small number of clusters, separate comparisons might
998  // be cheaper, and for many destinations, splitting the range might be
999  // better.
1000  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1001  (NumDests == 3 && NumCmps >= 6);
1002  }
1003 
1004  /// Return true if the specified operation is illegal on this target or
1005  /// unlikely to be made legal with custom lowering. This is used to help guide
1006  /// high-level lowering decisions.
1007  bool isOperationExpand(unsigned Op, EVT VT) const {
1008  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1009  }
1010 
1011  /// Return true if the specified operation is legal on this target.
1012  bool isOperationLegal(unsigned Op, EVT VT) const {
1013  return (VT == MVT::Other || isTypeLegal(VT)) &&
1014  getOperationAction(Op, VT) == Legal;
1015  }
1016 
1017  /// Return how this load with extension should be treated: either it is legal,
1018  /// needs to be promoted to a larger size, needs to be expanded to some other
1019  /// code sequence, or the target has a custom expander for it.
1021  EVT MemVT) const {
1022  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1023  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1024  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1025  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1026  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1027  unsigned Shift = 4 * ExtType;
1028  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1029  }
1030 
1031  /// Return true if the specified load with extension is legal on this target.
1032  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1033  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1034  }
1035 
1036  /// Return true if the specified load with extension is legal or custom
1037  /// on this target.
1038  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1039  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1040  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1041  }
1042 
1043  /// Return how this store with truncation should be treated: either it is
1044  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1045  /// other code sequence, or the target has a custom expander for it.
1047  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1048  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1049  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1050  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1051  "Table isn't big enough!");
1052  return TruncStoreActions[ValI][MemI];
1053  }
1054 
1055  /// Return true if the specified store with truncation is legal on this
1056  /// target.
1057  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1058  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1059  }
1060 
1061  /// Return true if the specified store with truncation has solution on this
1062  /// target.
1063  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1064  return isTypeLegal(ValVT) &&
1065  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1066  getTruncStoreAction(ValVT, MemVT) == Custom);
1067  }
1068 
1069  /// Return how the indexed load should be treated: either it is legal, needs
1070  /// to be promoted to a larger size, needs to be expanded to some other code
1071  /// sequence, or the target has a custom expander for it.
1073  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1074  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1075  "Table isn't big enough!");
1076  unsigned Ty = (unsigned)VT.SimpleTy;
1077  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1078  }
1079 
1080  /// Return true if the specified indexed load is legal on this target.
1081  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1082  return VT.isSimple() &&
1083  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1084  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1085  }
1086 
1087  /// Return how the indexed store should be treated: either it is legal, needs
1088  /// to be promoted to a larger size, needs to be expanded to some other code
1089  /// sequence, or the target has a custom expander for it.
1091  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1092  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1093  "Table isn't big enough!");
1094  unsigned Ty = (unsigned)VT.SimpleTy;
1095  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1096  }
1097 
1098  /// Return true if the specified indexed load is legal on this target.
1099  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1100  return VT.isSimple() &&
1101  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1102  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1103  }
1104 
1105  /// Return how the condition code should be treated: either it is legal, needs
1106  /// to be expanded to some other code sequence, or the target has a custom
1107  /// expander for it.
1110  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1111  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1112  "Table isn't big enough!");
1113  // See setCondCodeAction for how this is encoded.
1114  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1115  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1116  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1117  assert(Action != Promote && "Can't promote condition code!");
1118  return Action;
1119  }
1120 
1121  /// Return true if the specified condition code is legal on this target.
1122  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1123  return getCondCodeAction(CC, VT) == Legal;
1124  }
1125 
1126  /// Return true if the specified condition code is legal or custom on this
1127  /// target.
1129  return getCondCodeAction(CC, VT) == Legal ||
1130  getCondCodeAction(CC, VT) == Custom;
1131  }
1132 
1133  /// If the action for this operation is to promote, this method returns the
1134  /// ValueType to promote to.
1135  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1136  assert(getOperationAction(Op, VT) == Promote &&
1137  "This operation isn't promoted!");
1138 
1139  // See if this has an explicit type specified.
1140  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1142  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1143  if (PTTI != PromoteToType.end()) return PTTI->second;
1144 
1145  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1146  "Cannot autopromote this type, add it with AddPromotedToType.");
1147 
1148  MVT NVT = VT;
1149  do {
1150  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1151  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1152  "Didn't find type to promote to!");
1153  } while (!isTypeLegal(NVT) ||
1154  getOperationAction(Op, NVT) == Promote);
1155  return NVT;
1156  }
1157 
1158  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1159  /// operations except for the pointer size. If AllowUnknown is true, this
1160  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1161  /// otherwise it will assert.
1163  bool AllowUnknown = false) const {
1164  // Lower scalar pointers to native pointer types.
1165  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1166  return getPointerTy(DL, PTy->getAddressSpace());
1167 
1168  if (Ty->isVectorTy()) {
1169  VectorType *VTy = cast<VectorType>(Ty);
1170  Type *Elm = VTy->getElementType();
1171  // Lower vectors of pointers to native pointer types.
1172  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1173  EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1174  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1175  }
1176 
1177  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1178  VTy->getNumElements());
1179  }
1180  return EVT::getEVT(Ty, AllowUnknown);
1181  }
1182 
1183  /// Return the MVT corresponding to this LLVM type. See getValueType.
1185  bool AllowUnknown = false) const {
1186  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1187  }
1188 
1189  /// Return the desired alignment for ByVal or InAlloca aggregate function
1190  /// arguments in the caller parameter area. This is the actual alignment, not
1191  /// its logarithm.
1192  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1193 
1194  /// Return the type of registers that this ValueType will eventually require.
1196  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1197  return RegisterTypeForVT[VT.SimpleTy];
1198  }
1199 
1200  /// Return the type of registers that this ValueType will eventually require.
1201  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1202  if (VT.isSimple()) {
1203  assert((unsigned)VT.getSimpleVT().SimpleTy <
1204  array_lengthof(RegisterTypeForVT));
1205  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1206  }
1207  if (VT.isVector()) {
1208  EVT VT1;
1209  MVT RegisterVT;
1210  unsigned NumIntermediates;
1211  (void)getVectorTypeBreakdown(Context, VT, VT1,
1212  NumIntermediates, RegisterVT);
1213  return RegisterVT;
1214  }
1215  if (VT.isInteger()) {
1216  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1217  }
1218  llvm_unreachable("Unsupported extended type!");
1219  }
1220 
1221  /// Return the number of registers that this ValueType will eventually
1222  /// require.
1223  ///
1224  /// This is one for any types promoted to live in larger registers, but may be
1225  /// more than one for types (like i64) that are split into pieces. For types
1226  /// like i140, which are first promoted then expanded, it is the number of
1227  /// registers needed to hold all the bits of the original type. For an i140
1228  /// on a 32 bit machine this means 5 registers.
1229  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1230  if (VT.isSimple()) {
1231  assert((unsigned)VT.getSimpleVT().SimpleTy <
1232  array_lengthof(NumRegistersForVT));
1233  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1234  }
1235  if (VT.isVector()) {
1236  EVT VT1;
1237  MVT VT2;
1238  unsigned NumIntermediates;
1239  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1240  }
1241  if (VT.isInteger()) {
1242  unsigned BitWidth = VT.getSizeInBits();
1243  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1244  return (BitWidth + RegWidth - 1) / RegWidth;
1245  }
1246  llvm_unreachable("Unsupported extended type!");
1247  }
1248 
1249  /// Certain combinations of ABIs, Targets and features require that types
1250  /// are legal for some operations and not for other operations.
1251  /// For MIPS all vector types must be passed through the integer register set.
1253  CallingConv::ID CC, EVT VT) const {
1254  return getRegisterType(Context, VT);
1255  }
1256 
1257  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1258  /// this occurs when a vector type is used, as vector are passed through the
1259  /// integer register set.
1260  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1261  CallingConv::ID CC,
1262  EVT VT) const {
1263  return getNumRegisters(Context, VT);
1264  }
1265 
1266  /// Certain targets have context senstive alignment requirements, where one
1267  /// type has the alignment requirement of another type.
1268  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1269  DataLayout DL) const {
1270  return DL.getABITypeAlignment(ArgTy);
1271  }
1272 
1273  /// If true, then instruction selection should seek to shrink the FP constant
1274  /// of the specified type to a smaller type in order to save space and / or
1275  /// reduce runtime.
1276  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1277 
1278  /// Return true if it is profitable to reduce a load to a smaller type.
1279  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1281  EVT NewVT) const {
1282  // By default, assume that it is cheaper to extract a subvector from a wide
1283  // vector load rather than creating multiple narrow vector loads.
1284  if (NewVT.isVector() && !Load->hasOneUse())
1285  return false;
1286 
1287  return true;
1288  }
1289 
1290  /// When splitting a value of the specified type into parts, does the Lo
1291  /// or Hi part come first? This usually follows the endianness, except
1292  /// for ppcf128, where the Hi part always comes first.
1293  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1294  return DL.isBigEndian() || VT == MVT::ppcf128;
1295  }
1296 
1297  /// If true, the target has custom DAG combine transformations that it can
1298  /// perform for the specified node.
1300  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1301  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1302  }
1303 
1304  unsigned getGatherAllAliasesMaxDepth() const {
1305  return GatherAllAliasesMaxDepth;
1306  }
1307 
1308  /// Returns the size of the platform's va_list object.
1309  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1310  return getPointerTy(DL).getSizeInBits();
1311  }
1312 
1313  /// Get maximum # of store operations permitted for llvm.memset
1314  ///
1315  /// This function returns the maximum number of store operations permitted
1316  /// to replace a call to llvm.memset. The value is set by the target at the
1317  /// performance threshold for such a replacement. If OptSize is true,
1318  /// return the limit for functions that have OptSize attribute.
1319  unsigned getMaxStoresPerMemset(bool OptSize) const {
1320  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1321  }
1322 
1323  /// Get maximum # of store operations permitted for llvm.memcpy
1324  ///
1325  /// This function returns the maximum number of store operations permitted
1326  /// to replace a call to llvm.memcpy. The value is set by the target at the
1327  /// performance threshold for such a replacement. If OptSize is true,
1328  /// return the limit for functions that have OptSize attribute.
1329  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1330  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1331  }
1332 
1333  /// \brief Get maximum # of store operations to be glued together
1334  ///
1335  /// This function returns the maximum number of store operations permitted
1336  /// to glue together during lowering of llvm.memcpy. The value is set by
1337  // the target at the performance threshold for such a replacement.
1338  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1339  return MaxGluedStoresPerMemcpy;
1340  }
1341 
1342  /// Get maximum # of load operations permitted for memcmp
1343  ///
1344  /// This function returns the maximum number of load operations permitted
1345  /// to replace a call to memcmp. The value is set by the target at the
1346  /// performance threshold for such a replacement. If OptSize is true,
1347  /// return the limit for functions that have OptSize attribute.
1348  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1349  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1350  }
1351 
1352  /// For memcmp expansion when the memcmp result is only compared equal or
1353  /// not-equal to 0, allow up to this number of load pairs per block. As an
1354  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1355  /// a0 = load2bytes &a[0]
1356  /// b0 = load2bytes &b[0]
1357  /// a2 = load1byte &a[2]
1358  /// b2 = load1byte &b[2]
1359  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1360  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1361  return 1;
1362  }
1363 
1364  /// Get maximum # of store operations permitted for llvm.memmove
1365  ///
1366  /// This function returns the maximum number of store operations permitted
1367  /// to replace a call to llvm.memmove. The value is set by the target at the
1368  /// performance threshold for such a replacement. If OptSize is true,
1369  /// return the limit for functions that have OptSize attribute.
1370  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1371  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1372  }
1373 
1374  /// Determine if the target supports unaligned memory accesses.
1375  ///
1376  /// This function returns true if the target allows unaligned memory accesses
1377  /// of the specified type in the given address space. If true, it also returns
1378  /// whether the unaligned memory access is "fast" in the last argument by
1379  /// reference. This is used, for example, in situations where an array
1380  /// copy/move/set is converted to a sequence of store operations. Its use
1381  /// helps to ensure that such replacements don't generate code that causes an
1382  /// alignment error (trap) on the target machine.
1384  unsigned AddrSpace = 0,
1385  unsigned Align = 1,
1386  bool * /*Fast*/ = nullptr) const {
1387  return false;
1388  }
1389 
1390  /// Return true if the target supports a memory access of this type for the
1391  /// given address space and alignment. If the access is allowed, the optional
1392  /// final parameter returns if the access is also fast (as defined by the
1393  /// target).
1394  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1395  unsigned AddrSpace = 0, unsigned Alignment = 1,
1396  bool *Fast = nullptr) const;
1397 
1398  /// Returns the target specific optimal type for load and store operations as
1399  /// a result of memset, memcpy, and memmove lowering.
1400  ///
1401  /// If DstAlign is zero that means it's safe to destination alignment can
1402  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1403  /// a need to check it against alignment requirement, probably because the
1404  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1405  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1406  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1407  /// does not need to be loaded. It returns EVT::Other if the type should be
1408  /// determined using generic target-independent logic.
1409  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1410  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1411  bool /*IsMemset*/,
1412  bool /*ZeroMemset*/,
1413  bool /*MemcpyStrSrc*/,
1414  MachineFunction &/*MF*/) const {
1415  return MVT::Other;
1416  }
1417 
1418  /// Returns true if it's safe to use load / store of the specified type to
1419  /// expand memcpy / memset inline.
1420  ///
1421  /// This is mostly true for all types except for some special cases. For
1422  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1423  /// fstpl which also does type conversion. Note the specified type doesn't
1424  /// have to be legal as the hook is used before type legalization.
1425  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1426 
1427  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1428  bool usesUnderscoreSetJmp() const {
1429  return UseUnderscoreSetJmp;
1430  }
1431 
1432  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1433  bool usesUnderscoreLongJmp() const {
1434  return UseUnderscoreLongJmp;
1435  }
1436 
1437  /// Return lower limit for number of blocks in a jump table.
1438  virtual unsigned getMinimumJumpTableEntries() const;
1439 
1440  /// Return lower limit of the density in a jump table.
1441  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1442 
1443  /// Return upper limit for number of entries in a jump table.
1444  /// Zero if no limit.
1445  unsigned getMaximumJumpTableSize() const;
1446 
1447  virtual bool isJumpTableRelative() const {
1448  return TM.isPositionIndependent();
1449  }
1450 
1451  /// If a physical register, this specifies the register that
1452  /// llvm.savestack/llvm.restorestack should save and restore.
1454  return StackPointerRegisterToSaveRestore;
1455  }
1456 
1457  /// If a physical register, this returns the register that receives the
1458  /// exception address on entry to an EH pad.
1459  virtual unsigned
1460  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1461  // 0 is guaranteed to be the NoRegister value on all targets
1462  return 0;
1463  }
1464 
1465  /// If a physical register, this returns the register that receives the
1466  /// exception typeid on entry to a landing pad.
1467  virtual unsigned
1468  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1469  // 0 is guaranteed to be the NoRegister value on all targets
1470  return 0;
1471  }
1472 
1473  virtual bool needsFixedCatchObjects() const {
1474  report_fatal_error("Funclet EH is not implemented for this target");
1475  }
1476 
1477  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1478  /// 200)
1479  unsigned getJumpBufSize() const {
1480  return JumpBufSize;
1481  }
1482 
1483  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1484  /// is 0)
1485  unsigned getJumpBufAlignment() const {
1486  return JumpBufAlignment;
1487  }
1488 
1489  /// Return the minimum stack alignment of an argument.
1490  unsigned getMinStackArgumentAlignment() const {
1491  return MinStackArgumentAlignment;
1492  }
1493 
1494  /// Return the minimum function alignment.
1495  unsigned getMinFunctionAlignment() const {
1496  return MinFunctionAlignment;
1497  }
1498 
1499  /// Return the preferred function alignment.
1500  unsigned getPrefFunctionAlignment() const {
1501  return PrefFunctionAlignment;
1502  }
1503 
1504  /// Return the preferred loop alignment.
1505  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1506  return PrefLoopAlignment;
1507  }
1508 
1509  /// Should loops be aligned even when the function is marked OptSize (but not
1510  /// MinSize).
1511  virtual bool alignLoopsWithOptSize() const {
1512  return false;
1513  }
1514 
1515  /// If the target has a standard location for the stack protector guard,
1516  /// returns the address of that location. Otherwise, returns nullptr.
1517  /// DEPRECATED: please override useLoadStackGuardNode and customize
1518  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1519  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1520 
1521  /// Inserts necessary declarations for SSP (stack protection) purpose.
1522  /// Should be used only when getIRStackGuard returns nullptr.
1523  virtual void insertSSPDeclarations(Module &M) const;
1524 
1525  /// Return the variable that's previously inserted by insertSSPDeclarations,
1526  /// if any, otherwise return nullptr. Should be used only when
1527  /// getIRStackGuard returns nullptr.
1528  virtual Value *getSDagStackGuard(const Module &M) const;
1529 
1530  /// If this function returns true, stack protection checks should XOR the
1531  /// frame pointer (or whichever pointer is used to address locals) into the
1532  /// stack guard value before checking it. getIRStackGuard must return nullptr
1533  /// if this returns true.
1534  virtual bool useStackGuardXorFP() const { return false; }
1535 
1536  /// If the target has a standard stack protection check function that
1537  /// performs validation and error handling, returns the function. Otherwise,
1538  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1539  /// Should be used only when getIRStackGuard returns nullptr.
1540  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1541 
1542 protected:
1543  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1544  bool UseTLS) const;
1545 
1546 public:
1547  /// Returns the target-specific address of the unsafe stack pointer.
1548  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1549 
1550  /// Returns the name of the symbol used to emit stack probes or the empty
1551  /// string if not applicable.
1553  return "";
1554  }
1555 
1556  /// Returns true if a cast between SrcAS and DestAS is a noop.
1557  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1558  return false;
1559  }
1560 
1561  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1562  /// are happy to sink it into basic blocks.
1563  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1564  return isNoopAddrSpaceCast(SrcAS, DestAS);
1565  }
1566 
1567  /// Return true if the pointer arguments to CI should be aligned by aligning
1568  /// the object whose address is being passed. If so then MinSize is set to the
1569  /// minimum size the object must be to be aligned and PrefAlign is set to the
1570  /// preferred alignment.
1571  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1572  unsigned & /*PrefAlign*/) const {
1573  return false;
1574  }
1575 
1576  //===--------------------------------------------------------------------===//
1577  /// \name Helpers for TargetTransformInfo implementations
1578  /// @{
1579 
1580  /// Get the ISD node that corresponds to the Instruction class opcode.
1581  int InstructionOpcodeToISD(unsigned Opcode) const;
1582 
1583  /// Estimate the cost of type-legalization and the legalized type.
1584  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1585  Type *Ty) const;
1586 
1587  /// @}
1588 
1589  //===--------------------------------------------------------------------===//
1590  /// \name Helpers for atomic expansion.
1591  /// @{
1592 
1593  /// Returns the maximum atomic operation size (in bits) supported by
1594  /// the backend. Atomic operations greater than this size (as well
1595  /// as ones that are not naturally aligned), will be expanded by
1596  /// AtomicExpandPass into an __atomic_* library call.
1598  return MaxAtomicSizeInBitsSupported;
1599  }
1600 
1601  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1602  /// the backend supports. Any smaller operations are widened in
1603  /// AtomicExpandPass.
1604  ///
1605  /// Note that *unlike* operations above the maximum size, atomic ops
1606  /// are still natively supported below the minimum; they just
1607  /// require a more complex expansion.
1608  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1609 
1610  /// Whether the target supports unaligned atomic operations.
1611  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1612 
1613  /// Whether AtomicExpandPass should automatically insert fences and reduce
1614  /// ordering for this atomic. This should be true for most architectures with
1615  /// weak memory ordering. Defaults to false.
1616  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1617  return false;
1618  }
1619 
1620  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1621  /// corresponding pointee type. This may entail some non-trivial operations to
1622  /// truncate or reconstruct types that will be illegal in the backend. See
1623  /// ARMISelLowering for an example implementation.
1624  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1625  AtomicOrdering Ord) const {
1626  llvm_unreachable("Load linked unimplemented on this target");
1627  }
1628 
1629  /// Perform a store-conditional operation to Addr. Return the status of the
1630  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1631  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1632  Value *Addr, AtomicOrdering Ord) const {
1633  llvm_unreachable("Store conditional unimplemented on this target");
1634  }
1635 
1636  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1637  /// represents the core LL/SC loop which will be lowered at a late stage by
1638  /// the backend.
1640  AtomicRMWInst *AI,
1641  Value *AlignedAddr, Value *Incr,
1642  Value *Mask, Value *ShiftAmt,
1643  AtomicOrdering Ord) const {
1644  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1645  }
1646 
1647  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1648  /// represents the core LL/SC loop which will be lowered at a late stage by
1649  /// the backend.
1651  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1652  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1653  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1654  }
1655 
1656  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1657  /// It is called by AtomicExpandPass before expanding an
1658  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1659  /// if shouldInsertFencesForAtomic returns true.
1660  ///
1661  /// Inst is the original atomic instruction, prior to other expansions that
1662  /// may be performed.
1663  ///
1664  /// This function should either return a nullptr, or a pointer to an IR-level
1665  /// Instruction*. Even complex fence sequences can be represented by a
1666  /// single Instruction* through an intrinsic to be lowered later.
1667  /// Backends should override this method to produce target-specific intrinsic
1668  /// for their fences.
1669  /// FIXME: Please note that the default implementation here in terms of
1670  /// IR-level fences exists for historical/compatibility reasons and is
1671  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1672  /// consistency. For example, consider the following example:
1673  /// atomic<int> x = y = 0;
1674  /// int r1, r2, r3, r4;
1675  /// Thread 0:
1676  /// x.store(1);
1677  /// Thread 1:
1678  /// y.store(1);
1679  /// Thread 2:
1680  /// r1 = x.load();
1681  /// r2 = y.load();
1682  /// Thread 3:
1683  /// r3 = y.load();
1684  /// r4 = x.load();
1685  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1686  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1687  /// IR-level fences can prevent it.
1688  /// @{
1690  AtomicOrdering Ord) const {
1691  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1692  return Builder.CreateFence(Ord);
1693  else
1694  return nullptr;
1695  }
1696 
1698  Instruction *Inst,
1699  AtomicOrdering Ord) const {
1700  if (isAcquireOrStronger(Ord))
1701  return Builder.CreateFence(Ord);
1702  else
1703  return nullptr;
1704  }
1705  /// @}
1706 
1707  // Emits code that executes when the comparison result in the ll/sc
1708  // expansion of a cmpxchg instruction is such that the store-conditional will
1709  // not execute. This makes it possible to balance out the load-linked with
1710  // a dedicated instruction, if desired.
1711  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1712  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1713  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1714 
1715  /// Returns true if the given (atomic) store should be expanded by the
1716  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1718  return false;
1719  }
1720 
1721  /// Returns true if arguments should be sign-extended in lib calls.
1722  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1723  return IsSigned;
1724  }
1725 
1726  /// Returns how the given (atomic) load should be expanded by the
1727  /// IR-level AtomicExpand pass.
1730  }
1731 
1732  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1733  /// AtomicExpand pass.
1734  virtual AtomicExpansionKind
1737  }
1738 
1739  /// Returns how the IR-level AtomicExpand pass should expand the given
1740  /// AtomicRMW, if at all. Default is to never expand.
1742  return RMW->isFloatingPointOperation() ?
1743  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1744  }
1745 
1746  /// On some platforms, an AtomicRMW that never actually modifies the value
1747  /// (such as fetch_add of 0) can be turned into a fence followed by an
1748  /// atomic load. This may sound useless, but it makes it possible for the
1749  /// processor to keep the cacheline shared, dramatically improving
1750  /// performance. And such idempotent RMWs are useful for implementing some
1751  /// kinds of locks, see for example (justification + benchmarks):
1752  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1753  /// This method tries doing that transformation, returning the atomic load if
1754  /// it succeeds, and nullptr otherwise.
1755  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1756  /// another round of expansion.
1757  virtual LoadInst *
1759  return nullptr;
1760  }
1761 
1762  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1763  /// SIGN_EXTEND, or ANY_EXTEND).
1765  return ISD::ZERO_EXTEND;
1766  }
1767 
1768  /// @}
1769 
1770  /// Returns true if we should normalize
1771  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1772  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1773  /// that it saves us from materializing N0 and N1 in an integer register.
1774  /// Targets that are able to perform and/or on flags should return false here.
1776  EVT VT) const {
1777  // If a target has multiple condition registers, then it likely has logical
1778  // operations on those registers.
1779  if (hasMultipleConditionRegisters())
1780  return false;
1781  // Only do the transform if the value won't be split into multiple
1782  // registers.
1783  LegalizeTypeAction Action = getTypeAction(Context, VT);
1784  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1785  Action != TypeSplitVector;
1786  }
1787 
1788  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1789 
1790  /// Return true if a select of constants (select Cond, C1, C2) should be
1791  /// transformed into simple math ops with the condition value. For example:
1792  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1793  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1794  return false;
1795  }
1796 
1797  /// Return true if it is profitable to transform an integer
1798  /// multiplication-by-constant into simpler operations like shifts and adds.
1799  /// This may be true if the target does not directly support the
1800  /// multiplication operation for the specified type or the sequence of simpler
1801  /// ops is faster than the multiply.
1802  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1803  return false;
1804  }
1805 
1806  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1807  /// conversion operations - canonicalizing the FP source value instead of
1808  /// converting all cases and then selecting based on value.
1809  /// This may be true if the target throws exceptions for out of bounds
1810  /// conversions or has fast FP CMOV.
1811  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1812  bool IsSigned) const {
1813  return false;
1814  }
1815 
1816  //===--------------------------------------------------------------------===//
1817  // TargetLowering Configuration Methods - These methods should be invoked by
1818  // the derived class constructor to configure this object for the target.
1819  //
1820 protected:
1821  /// Specify how the target extends the result of integer and floating point
1822  /// boolean values from i1 to a wider type. See getBooleanContents.
1824  BooleanContents = Ty;
1825  BooleanFloatContents = Ty;
1826  }
1827 
1828  /// Specify how the target extends the result of integer and floating point
1829  /// boolean values from i1 to a wider type. See getBooleanContents.
1831  BooleanContents = IntTy;
1832  BooleanFloatContents = FloatTy;
1833  }
1834 
1835  /// Specify how the target extends the result of a vector boolean value from a
1836  /// vector of i1 to a wider type. See getBooleanContents.
1838  BooleanVectorContents = Ty;
1839  }
1840 
1841  /// Specify the target scheduling preference.
1843  SchedPreferenceInfo = Pref;
1844  }
1845 
1846  /// Indicate whether this target prefers to use _setjmp to implement
1847  /// llvm.setjmp or the version without _. Defaults to false.
1848  void setUseUnderscoreSetJmp(bool Val) {
1849  UseUnderscoreSetJmp = Val;
1850  }
1851 
1852  /// Indicate whether this target prefers to use _longjmp to implement
1853  /// llvm.longjmp or the version without _. Defaults to false.
1854  void setUseUnderscoreLongJmp(bool Val) {
1855  UseUnderscoreLongJmp = Val;
1856  }
1857 
1858  /// Indicate the minimum number of blocks to generate jump tables.
1859  void setMinimumJumpTableEntries(unsigned Val);
1860 
1861  /// Indicate the maximum number of entries in jump tables.
1862  /// Set to zero to generate unlimited jump tables.
1863  void setMaximumJumpTableSize(unsigned);
1864 
1865  /// If set to a physical register, this specifies the register that
1866  /// llvm.savestack/llvm.restorestack should save and restore.
1868  StackPointerRegisterToSaveRestore = R;
1869  }
1870 
1871  /// Tells the code generator that the target has multiple (allocatable)
1872  /// condition registers that can be used to store the results of comparisons
1873  /// for use by selects and conditional branches. With multiple condition
1874  /// registers, the code generator will not aggressively sink comparisons into
1875  /// the blocks of their users.
1876  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1877  HasMultipleConditionRegisters = hasManyRegs;
1878  }
1879 
1880  /// Tells the code generator that the target has BitExtract instructions.
1881  /// The code generator will aggressively sink "shift"s into the blocks of
1882  /// their users if the users will generate "and" instructions which can be
1883  /// combined with "shift" to BitExtract instructions.
1884  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1885  HasExtractBitsInsn = hasExtractInsn;
1886  }
1887 
1888  /// Tells the code generator not to expand logic operations on comparison
1889  /// predicates into separate sequences that increase the amount of flow
1890  /// control.
1891  void setJumpIsExpensive(bool isExpensive = true);
1892 
1893  /// Tells the code generator that this target supports floating point
1894  /// exceptions and cares about preserving floating point exception behavior.
1895  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1896  HasFloatingPointExceptions = FPExceptions;
1897  }
1898 
1899  /// Tells the code generator which bitwidths to bypass.
1900  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1901  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1902  }
1903 
1904  /// Add the specified register class as an available regclass for the
1905  /// specified value type. This indicates the selector can handle values of
1906  /// that class natively.
1908  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1909  RegClassForVT[VT.SimpleTy] = RC;
1910  }
1911 
1912  /// Return the largest legal super-reg register class of the register class
1913  /// for the specified type and its associated "cost".
1914  virtual std::pair<const TargetRegisterClass *, uint8_t>
1915  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1916 
1917  /// Once all of the register classes are added, this allows us to compute
1918  /// derived properties we expose.
1919  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1920 
1921  /// Indicate that the specified operation does not work with the specified
1922  /// type and indicate what to do about it. Note that VT may refer to either
1923  /// the type of a result or that of an operand of Op.
1924  void setOperationAction(unsigned Op, MVT VT,
1925  LegalizeAction Action) {
1926  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1927  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1928  }
1929 
1930  /// Indicate that the specified load with extension does not work with the
1931  /// specified type and indicate what to do about it.
1932  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1933  LegalizeAction Action) {
1934  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1935  MemVT.isValid() && "Table isn't big enough!");
1936  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1937  unsigned Shift = 4 * ExtType;
1938  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1939  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1940  }
1941 
1942  /// Indicate that the specified truncating store does not work with the
1943  /// specified type and indicate what to do about it.
1944  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1945  LegalizeAction Action) {
1946  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1947  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1948  }
1949 
1950  /// Indicate that the specified indexed load does or does not work with the
1951  /// specified type and indicate what to do abort it.
1952  ///
1953  /// NOTE: All indexed mode loads are initialized to Expand in
1954  /// TargetLowering.cpp
1955  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1956  LegalizeAction Action) {
1957  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1958  (unsigned)Action < 0xf && "Table isn't big enough!");
1959  // Load action are kept in the upper half.
1960  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1961  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1962  }
1963 
1964  /// Indicate that the specified indexed store does or does not work with the
1965  /// specified type and indicate what to do about it.
1966  ///
1967  /// NOTE: All indexed mode stores are initialized to Expand in
1968  /// TargetLowering.cpp
1969  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1970  LegalizeAction Action) {
1971  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1972  (unsigned)Action < 0xf && "Table isn't big enough!");
1973  // Store action are kept in the lower half.
1974  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1975  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1976  }
1977 
1978  /// Indicate that the specified condition code is or isn't supported on the
1979  /// target and indicate what to do about it.
1981  LegalizeAction Action) {
1982  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1983  "Table isn't big enough!");
1984  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1985  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1986  /// value and the upper 29 bits index into the second dimension of the array
1987  /// to select what 32-bit value to use.
1988  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1989  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1990  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1991  }
1992 
1993  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1994  /// to trying a larger integer/fp until it can find one that works. If that
1995  /// default is insufficient, this method can be used by the target to override
1996  /// the default.
1997  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1998  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1999  }
2000 
2001  /// Convenience method to set an operation to Promote and specify the type
2002  /// in a single call.
2003  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2004  setOperationAction(Opc, OrigVT, Promote);
2005  AddPromotedToType(Opc, OrigVT, DestVT);
2006  }
2007 
2008  /// Targets should invoke this method for each target independent node that
2009  /// they want to provide a custom DAG combiner for by implementing the
2010  /// PerformDAGCombine virtual method.
2012  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2013  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2014  }
2015 
2016  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
2017  void setJumpBufSize(unsigned Size) {
2018  JumpBufSize = Size;
2019  }
2020 
2021  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
2022  /// 0
2023  void setJumpBufAlignment(unsigned Align) {
2024  JumpBufAlignment = Align;
2025  }
2026 
2027  /// Set the target's minimum function alignment (in log2(bytes))
2029  MinFunctionAlignment = Align;
2030  }
2031 
2032  /// Set the target's preferred function alignment. This should be set if
2033  /// there is a performance benefit to higher-than-minimum alignment (in
2034  /// log2(bytes))
2036  PrefFunctionAlignment = Align;
2037  }
2038 
2039  /// Set the target's preferred loop alignment. Default alignment is zero, it
2040  /// means the target does not care about loop alignment. The alignment is
2041  /// specified in log2(bytes). The target may also override
2042  /// getPrefLoopAlignment to provide per-loop values.
2043  void setPrefLoopAlignment(unsigned Align) {
2044  PrefLoopAlignment = Align;
2045  }
2046 
2047  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2049  MinStackArgumentAlignment = Align;
2050  }
2051 
2052  /// Set the maximum atomic operation size supported by the
2053  /// backend. Atomic operations greater than this size (as well as
2054  /// ones that are not naturally aligned), will be expanded by
2055  /// AtomicExpandPass into an __atomic_* library call.
2056  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2057  MaxAtomicSizeInBitsSupported = SizeInBits;
2058  }
2059 
2060  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2061  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2062  MinCmpXchgSizeInBits = SizeInBits;
2063  }
2064 
2065  /// Sets whether unaligned atomic operations are supported.
2066  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2067  SupportsUnalignedAtomics = UnalignedSupported;
2068  }
2069 
2070 public:
2071  //===--------------------------------------------------------------------===//
2072  // Addressing mode description hooks (used by LSR etc).
2073  //
2074 
2075  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2076  /// instructions reading the address. This allows as much computation as
2077  /// possible to be done in the address mode for that operand. This hook lets
2078  /// targets also pass back when this should be done on intrinsics which
2079  /// load/store.
2080  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2081  SmallVectorImpl<Value*> &/*Ops*/,
2082  Type *&/*AccessTy*/) const {
2083  return false;
2084  }
2085 
2086  /// This represents an addressing mode of:
2087  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2088  /// If BaseGV is null, there is no BaseGV.
2089  /// If BaseOffs is zero, there is no base offset.
2090  /// If HasBaseReg is false, there is no base register.
2091  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2092  /// no scale.
2093  struct AddrMode {
2094  GlobalValue *BaseGV = nullptr;
2095  int64_t BaseOffs = 0;
2096  bool HasBaseReg = false;
2097  int64_t Scale = 0;
2098  AddrMode() = default;
2099  };
2100 
2101  /// Return true if the addressing mode represented by AM is legal for this
2102  /// target, for a load/store of the specified type.
2103  ///
2104  /// The type may be VoidTy, in which case only return true if the addressing
2105  /// mode is legal for a load/store of any legal type. TODO: Handle
2106  /// pre/postinc as well.
2107  ///
2108  /// If the address space cannot be determined, it will be -1.
2109  ///
2110  /// TODO: Remove default argument
2111  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2112  Type *Ty, unsigned AddrSpace,
2113  Instruction *I = nullptr) const;
2114 
2115  /// Return the cost of the scaling factor used in the addressing mode
2116  /// represented by AM for this target, for a load/store of the specified type.
2117  ///
2118  /// If the AM is supported, the return value must be >= 0.
2119  /// If the AM is not supported, it returns a negative value.
2120  /// TODO: Handle pre/postinc as well.
2121  /// TODO: Remove default argument
2122  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2123  Type *Ty, unsigned AS = 0) const {
2124  // Default: assume that any scaling factor used in a legal AM is free.
2125  if (isLegalAddressingMode(DL, AM, Ty, AS))
2126  return 0;
2127  return -1;
2128  }
2129 
2130  /// Return true if the specified immediate is legal icmp immediate, that is
2131  /// the target has icmp instructions which can compare a register against the
2132  /// immediate without having to materialize the immediate into a register.
2133  virtual bool isLegalICmpImmediate(int64_t) const {
2134  return true;
2135  }
2136 
2137  /// Return true if the specified immediate is legal add immediate, that is the
2138  /// target has add instructions which can add a register with the immediate
2139  /// without having to materialize the immediate into a register.
2140  virtual bool isLegalAddImmediate(int64_t) const {
2141  return true;
2142  }
2143 
2144  /// Return true if the specified immediate is legal for the value input of a
2145  /// store instruction.
2146  virtual bool isLegalStoreImmediate(int64_t Value) const {
2147  // Default implementation assumes that at least 0 works since it is likely
2148  // that a zero register exists or a zero immediate is allowed.
2149  return Value == 0;
2150  }
2151 
2152  /// Return true if it's significantly cheaper to shift a vector by a uniform
2153  /// scalar than by an amount which will vary across each lane. On x86, for
2154  /// example, there is a "psllw" instruction for the former case, but no simple
2155  /// instruction for a general "a << b" operation on vectors.
2156  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2157  return false;
2158  }
2159 
2160  /// Returns true if the opcode is a commutative binary operation.
2161  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2162  // FIXME: This should get its info from the td file.
2163  switch (Opcode) {
2164  case ISD::ADD:
2165  case ISD::SMIN:
2166  case ISD::SMAX:
2167  case ISD::UMIN:
2168  case ISD::UMAX:
2169  case ISD::MUL:
2170  case ISD::MULHU:
2171  case ISD::MULHS:
2172  case ISD::SMUL_LOHI:
2173  case ISD::UMUL_LOHI:
2174  case ISD::FADD:
2175  case ISD::FMUL:
2176  case ISD::AND:
2177  case ISD::OR:
2178  case ISD::XOR:
2179  case ISD::SADDO:
2180  case ISD::UADDO:
2181  case ISD::ADDC:
2182  case ISD::ADDE:
2183  case ISD::SADDSAT:
2184  case ISD::UADDSAT:
2185  case ISD::FMINNUM:
2186  case ISD::FMAXNUM:
2187  case ISD::FMINIMUM:
2188  case ISD::FMAXIMUM:
2189  return true;
2190  default: return false;
2191  }
2192  }
2193 
2194  /// Return true if it's free to truncate a value of type FromTy to type
2195  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2196  /// by referencing its sub-register AX.
2197  /// Targets must return false when FromTy <= ToTy.
2198  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2199  return false;
2200  }
2201 
2202  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2203  /// whether a call is in tail position. Typically this means that both results
2204  /// would be assigned to the same register or stack slot, but it could mean
2205  /// the target performs adequate checks of its own before proceeding with the
2206  /// tail call. Targets must return false when FromTy <= ToTy.
2207  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2208  return false;
2209  }
2210 
2211  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2212  return false;
2213  }
2214 
2215  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2216 
2217  /// Return true if the extension represented by \p I is free.
2218  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2219  /// this method can use the context provided by \p I to decide
2220  /// whether or not \p I is free.
2221  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2222  /// In other words, if is[Z|FP]Free returns true, then this method
2223  /// returns true as well. The converse is not true.
2224  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2225  /// \pre \p I must be a sign, zero, or fp extension.
2226  bool isExtFree(const Instruction *I) const {
2227  switch (I->getOpcode()) {
2228  case Instruction::FPExt:
2229  if (isFPExtFree(EVT::getEVT(I->getType()),
2230  EVT::getEVT(I->getOperand(0)->getType())))
2231  return true;
2232  break;
2233  case Instruction::ZExt:
2234  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2235  return true;
2236  break;
2237  case Instruction::SExt:
2238  break;
2239  default:
2240  llvm_unreachable("Instruction is not an extension");
2241  }
2242  return isExtFreeImpl(I);
2243  }
2244 
2245  /// Return true if \p Load and \p Ext can form an ExtLoad.
2246  /// For example, in AArch64
2247  /// %L = load i8, i8* %ptr
2248  /// %E = zext i8 %L to i32
2249  /// can be lowered into one load instruction
2250  /// ldrb w0, [x0]
2251  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2252  const DataLayout &DL) const {
2253  EVT VT = getValueType(DL, Ext->getType());
2254  EVT LoadVT = getValueType(DL, Load->getType());
2255 
2256  // If the load has other users and the truncate is not free, the ext
2257  // probably isn't free.
2258  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2259  !isTruncateFree(Ext->getType(), Load->getType()))
2260  return false;
2261 
2262  // Check whether the target supports casts folded into loads.
2263  unsigned LType;
2264  if (isa<ZExtInst>(Ext))
2265  LType = ISD::ZEXTLOAD;
2266  else {
2267  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2268  LType = ISD::SEXTLOAD;
2269  }
2270 
2271  return isLoadExtLegal(LType, VT, LoadVT);
2272  }
2273 
2274  /// Return true if any actual instruction that defines a value of type FromTy
2275  /// implicitly zero-extends the value to ToTy in the result register.
2276  ///
2277  /// The function should return true when it is likely that the truncate can
2278  /// be freely folded with an instruction defining a value of FromTy. If
2279  /// the defining instruction is unknown (because you're looking at a
2280  /// function argument, PHI, etc.) then the target may require an
2281  /// explicit truncate, which is not necessarily free, but this function
2282  /// does not deal with those cases.
2283  /// Targets must return false when FromTy >= ToTy.
2284  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2285  return false;
2286  }
2287 
2288  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2289  return false;
2290  }
2291 
2292  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2293  /// zero-extension.
2294  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2295  return false;
2296  }
2297 
2298  /// Return true if sinking I's operands to the same basic block as I is
2299  /// profitable, e.g. because the operands can be folded into a target
2300  /// instruction during instruction selection. After calling the function
2301  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2302  /// come first).
2304  SmallVectorImpl<Use *> &Ops) const {
2305  return false;
2306  }
2307 
2308  /// Return true if the target supplies and combines to a paired load
2309  /// two loaded values of type LoadedType next to each other in memory.
2310  /// RequiredAlignment gives the minimal alignment constraints that must be met
2311  /// to be able to select this paired load.
2312  ///
2313  /// This information is *not* used to generate actual paired loads, but it is
2314  /// used to generate a sequence of loads that is easier to combine into a
2315  /// paired load.
2316  /// For instance, something like this:
2317  /// a = load i64* addr
2318  /// b = trunc i64 a to i32
2319  /// c = lshr i64 a, 32
2320  /// d = trunc i64 c to i32
2321  /// will be optimized into:
2322  /// b = load i32* addr1
2323  /// d = load i32* addr2
2324  /// Where addr1 = addr2 +/- sizeof(i32).
2325  ///
2326  /// In other words, unless the target performs a post-isel load combining,
2327  /// this information should not be provided because it will generate more
2328  /// loads.
2329  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2330  unsigned & /*RequiredAlignment*/) const {
2331  return false;
2332  }
2333 
2334  /// Return true if the target has a vector blend instruction.
2335  virtual bool hasVectorBlend() const { return false; }
2336 
2337  /// Get the maximum supported factor for interleaved memory accesses.
2338  /// Default to be the minimum interleave factor: 2.
2339  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2340 
2341  /// Lower an interleaved load to target specific intrinsics. Return
2342  /// true on success.
2343  ///
2344  /// \p LI is the vector load instruction.
2345  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2346  /// \p Indices is the corresponding indices for each shufflevector.
2347  /// \p Factor is the interleave factor.
2348  virtual bool lowerInterleavedLoad(LoadInst *LI,
2350  ArrayRef<unsigned> Indices,
2351  unsigned Factor) const {
2352  return false;
2353  }
2354 
2355  /// Lower an interleaved store to target specific intrinsics. Return
2356  /// true on success.
2357  ///
2358  /// \p SI is the vector store instruction.
2359  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2360  /// \p Factor is the interleave factor.
2362  unsigned Factor) const {
2363  return false;
2364  }
2365 
2366  /// Return true if zero-extending the specific node Val to type VT2 is free
2367  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2368  /// because it's folded such as X86 zero-extending loads).
2369  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2370  return isZExtFree(Val.getValueType(), VT2);
2371  }
2372 
2373  /// Return true if an fpext operation is free (for instance, because
2374  /// single-precision floating-point numbers are implicitly extended to
2375  /// double-precision).
2376  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2377  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2378  "invalid fpext types");
2379  return false;
2380  }
2381 
2382  /// Return true if an fpext operation input to an \p Opcode operation is free
2383  /// (for instance, because half-precision floating-point numbers are
2384  /// implicitly extended to float-precision) for an FMA instruction.
2385  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2386  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2387  "invalid fpext types");
2388  return isFPExtFree(DestVT, SrcVT);
2389  }
2390 
2391  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2392  /// extend node) is profitable.
2393  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2394 
2395  /// Return true if an fneg operation is free to the point where it is never
2396  /// worthwhile to replace it with a bitwise operation.
2397  virtual bool isFNegFree(EVT VT) const {
2398  assert(VT.isFloatingPoint());
2399  return false;
2400  }
2401 
2402  /// Return true if an fabs operation is free to the point where it is never
2403  /// worthwhile to replace it with a bitwise operation.
2404  virtual bool isFAbsFree(EVT VT) const {
2405  assert(VT.isFloatingPoint());
2406  return false;
2407  }
2408 
2409  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2410  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2411  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2412  ///
2413  /// NOTE: This may be called before legalization on types for which FMAs are
2414  /// not legal, but should return true if those types will eventually legalize
2415  /// to types that support FMAs. After legalization, it will only be called on
2416  /// types that support FMAs (via Legal or Custom actions)
2417  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2418  return false;
2419  }
2420 
2421  /// Return true if it's profitable to narrow operations of type VT1 to
2422  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2423  /// i32 to i16.
2424  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2425  return false;
2426  }
2427 
2428  /// Return true if it is beneficial to convert a load of a constant to
2429  /// just the constant itself.
2430  /// On some targets it might be more efficient to use a combination of
2431  /// arithmetic instructions to materialize the constant instead of loading it
2432  /// from a constant pool.
2433  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2434  Type *Ty) const {
2435  return false;
2436  }
2437 
2438  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2439  /// from this source type with this index. This is needed because
2440  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2441  /// the first element, and only the target knows which lowering is cheap.
2442  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2443  unsigned Index) const {
2444  return false;
2445  }
2446 
2447  /// Try to convert an extract element of a vector binary operation into an
2448  /// extract element followed by a scalar operation.
2449  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2450  return false;
2451  }
2452 
2453  /// Return true if extraction of a scalar element from the given vector type
2454  /// at the given index is cheap. For example, if scalar operations occur on
2455  /// the same register file as vector operations, then an extract element may
2456  /// be a sub-register rename rather than an actual instruction.
2457  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2458  return false;
2459  }
2460 
2461  /// Try to convert math with an overflow comparison into the corresponding DAG
2462  /// node operation. Targets may want to override this independently of whether
2463  /// the operation is legal/custom for the given type because it may obscure
2464  /// matching of other patterns.
2465  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2466  // TODO: The default logic is inherited from code in CodeGenPrepare.
2467  // The opcode should not make a difference by default?
2468  if (Opcode != ISD::UADDO)
2469  return false;
2470 
2471  // Allow the transform as long as we have an integer type that is not
2472  // obviously illegal and unsupported.
2473  if (VT.isVector())
2474  return false;
2475  return VT.isSimple() || !isOperationExpand(Opcode, VT);
2476  }
2477 
2478  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2479  // even if the vector itself has multiple uses.
2480  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2481  return false;
2482  }
2483 
2484  // Return true if CodeGenPrepare should consider splitting large offset of a
2485  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2486  // same blocks of its users.
2487  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2488 
2489  //===--------------------------------------------------------------------===//
2490  // Runtime Library hooks
2491  //
2492 
2493  /// Rename the default libcall routine name for the specified libcall.
2494  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2495  LibcallRoutineNames[Call] = Name;
2496  }
2497 
2498  /// Get the libcall routine name for the specified libcall.
2499  const char *getLibcallName(RTLIB::Libcall Call) const {
2500  return LibcallRoutineNames[Call];
2501  }
2502 
2503  /// Override the default CondCode to be used to test the result of the
2504  /// comparison libcall against zero.
2506  CmpLibcallCCs[Call] = CC;
2507  }
2508 
2509  /// Get the CondCode that's to be used to test the result of the comparison
2510  /// libcall against zero.
2512  return CmpLibcallCCs[Call];
2513  }
2514 
2515  /// Set the CallingConv that should be used for the specified libcall.
2517  LibcallCallingConvs[Call] = CC;
2518  }
2519 
2520  /// Get the CallingConv that should be used for the specified libcall.
2522  return LibcallCallingConvs[Call];
2523  }
2524 
2525  /// Execute target specific actions to finalize target lowering.
2526  /// This is used to set extra flags in MachineFrameInformation and freezing
2527  /// the set of reserved registers.
2528  /// The default implementation just freezes the set of reserved registers.
2529  virtual void finalizeLowering(MachineFunction &MF) const;
2530 
2531 private:
2532  const TargetMachine &TM;
2533 
2534  /// Tells the code generator that the target has multiple (allocatable)
2535  /// condition registers that can be used to store the results of comparisons
2536  /// for use by selects and conditional branches. With multiple condition
2537  /// registers, the code generator will not aggressively sink comparisons into
2538  /// the blocks of their users.
2539  bool HasMultipleConditionRegisters;
2540 
2541  /// Tells the code generator that the target has BitExtract instructions.
2542  /// The code generator will aggressively sink "shift"s into the blocks of
2543  /// their users if the users will generate "and" instructions which can be
2544  /// combined with "shift" to BitExtract instructions.
2545  bool HasExtractBitsInsn;
2546 
2547  /// Tells the code generator to bypass slow divide or remainder
2548  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2549  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2550  /// div/rem when the operands are positive and less than 256.
2551  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2552 
2553  /// Tells the code generator that it shouldn't generate extra flow control
2554  /// instructions and should attempt to combine flow control instructions via
2555  /// predication.
2556  bool JumpIsExpensive;
2557 
2558  /// Whether the target supports or cares about preserving floating point
2559  /// exception behavior.
2560  bool HasFloatingPointExceptions;
2561 
2562  /// This target prefers to use _setjmp to implement llvm.setjmp.
2563  ///
2564  /// Defaults to false.
2565  bool UseUnderscoreSetJmp;
2566 
2567  /// This target prefers to use _longjmp to implement llvm.longjmp.
2568  ///
2569  /// Defaults to false.
2570  bool UseUnderscoreLongJmp;
2571 
2572  /// Information about the contents of the high-bits in boolean values held in
2573  /// a type wider than i1. See getBooleanContents.
2574  BooleanContent BooleanContents;
2575 
2576  /// Information about the contents of the high-bits in boolean values held in
2577  /// a type wider than i1. See getBooleanContents.
2578  BooleanContent BooleanFloatContents;
2579 
2580  /// Information about the contents of the high-bits in boolean vector values
2581  /// when the element type is wider than i1. See getBooleanContents.
2582  BooleanContent BooleanVectorContents;
2583 
2584  /// The target scheduling preference: shortest possible total cycles or lowest
2585  /// register usage.
2586  Sched::Preference SchedPreferenceInfo;
2587 
2588  /// The size, in bytes, of the target's jmp_buf buffers
2589  unsigned JumpBufSize;
2590 
2591  /// The alignment, in bytes, of the target's jmp_buf buffers
2592  unsigned JumpBufAlignment;
2593 
2594  /// The minimum alignment that any argument on the stack needs to have.
2595  unsigned MinStackArgumentAlignment;
2596 
2597  /// The minimum function alignment (used when optimizing for size, and to
2598  /// prevent explicitly provided alignment from leading to incorrect code).
2599  unsigned MinFunctionAlignment;
2600 
2601  /// The preferred function alignment (used when alignment unspecified and
2602  /// optimizing for speed).
2603  unsigned PrefFunctionAlignment;
2604 
2605  /// The preferred loop alignment.
2606  unsigned PrefLoopAlignment;
2607 
2608  /// Size in bits of the maximum atomics size the backend supports.
2609  /// Accesses larger than this will be expanded by AtomicExpandPass.
2610  unsigned MaxAtomicSizeInBitsSupported;
2611 
2612  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2613  /// backend supports.
2614  unsigned MinCmpXchgSizeInBits;
2615 
2616  /// This indicates if the target supports unaligned atomic operations.
2617  bool SupportsUnalignedAtomics;
2618 
2619  /// If set to a physical register, this specifies the register that
2620  /// llvm.savestack/llvm.restorestack should save and restore.
2621  unsigned StackPointerRegisterToSaveRestore;
2622 
2623  /// This indicates the default register class to use for each ValueType the
2624  /// target supports natively.
2625  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2626  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2627  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2628 
2629  /// This indicates the "representative" register class to use for each
2630  /// ValueType the target supports natively. This information is used by the
2631  /// scheduler to track register pressure. By default, the representative
2632  /// register class is the largest legal super-reg register class of the
2633  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2634  /// representative class would be GR32.
2635  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2636 
2637  /// This indicates the "cost" of the "representative" register class for each
2638  /// ValueType. The cost is used by the scheduler to approximate register
2639  /// pressure.
2640  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2641 
2642  /// For any value types we are promoting or expanding, this contains the value
2643  /// type that we are changing to. For Expanded types, this contains one step
2644  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2645  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2646  /// the same type (e.g. i32 -> i32).
2647  MVT TransformToType[MVT::LAST_VALUETYPE];
2648 
2649  /// For each operation and each value type, keep a LegalizeAction that
2650  /// indicates how instruction selection should deal with the operation. Most
2651  /// operations are Legal (aka, supported natively by the target), but
2652  /// operations that are not should be described. Note that operations on
2653  /// non-legal value types are not described here.
2655 
2656  /// For each load extension type and each value type, keep a LegalizeAction
2657  /// that indicates how instruction selection should deal with a load of a
2658  /// specific value type and extension type. Uses 4-bits to store the action
2659  /// for each of the 4 load ext types.
2660  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2661 
2662  /// For each value type pair keep a LegalizeAction that indicates whether a
2663  /// truncating store of a specific value type and truncating type is legal.
2665 
2666  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2667  /// that indicates how instruction selection should deal with the load /
2668  /// store.
2669  ///
2670  /// The first dimension is the value_type for the reference. The second
2671  /// dimension represents the various modes for load store.
2672  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2673 
2674  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2675  /// indicates how instruction selection should deal with the condition code.
2676  ///
2677  /// Because each CC action takes up 4 bits, we need to have the array size be
2678  /// large enough to fit all of the value types. This can be done by rounding
2679  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2680  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2681 
2682 protected:
2684 
2685 private:
2686  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2687 
2688  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2689  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2690  /// array.
2691  unsigned char
2692  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2693 
2694  /// For operations that must be promoted to a specific type, this holds the
2695  /// destination type. This map should be sparse, so don't hold it as an
2696  /// array.
2697  ///
2698  /// Targets add entries to this map with AddPromotedToType(..), clients access
2699  /// this with getTypeToPromoteTo(..).
2700  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2701  PromoteToType;
2702 
2703  /// Stores the name each libcall.
2704  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2705 
2706  /// The ISD::CondCode that should be used to test the result of each of the
2707  /// comparison libcall against zero.
2708  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2709 
2710  /// Stores the CallingConv that should be used for each libcall.
2711  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2712 
2713  /// Set default libcall names and calling conventions.
2714  void InitLibcalls(const Triple &TT);
2715 
2716 protected:
2717  /// Return true if the extension represented by \p I is free.
2718  /// \pre \p I is a sign, zero, or fp extension and
2719  /// is[Z|FP]ExtFree of the related types is not true.
2720  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2721 
2722  /// Depth that GatherAllAliases should should continue looking for chain
2723  /// dependencies when trying to find a more preferable chain. As an
2724  /// approximation, this should be more than the number of consecutive stores
2725  /// expected to be merged.
2727 
2728  /// Specify maximum number of store instructions per memset call.
2729  ///
2730  /// When lowering \@llvm.memset this field specifies the maximum number of
2731  /// store operations that may be substituted for the call to memset. Targets
2732  /// must set this value based on the cost threshold for that target. Targets
2733  /// should assume that the memset will be done using as many of the largest
2734  /// store operations first, followed by smaller ones, if necessary, per
2735  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2736  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2737  /// store. This only applies to setting a constant array of a constant size.
2739 
2740  /// Maximum number of stores operations that may be substituted for the call
2741  /// to memset, used for functions with OptSize attribute.
2743 
2744  /// Specify maximum bytes of store instructions per memcpy call.
2745  ///
2746  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2747  /// store operations that may be substituted for a call to memcpy. Targets
2748  /// must set this value based on the cost threshold for that target. Targets
2749  /// should assume that the memcpy will be done using as many of the largest
2750  /// store operations first, followed by smaller ones, if necessary, per
2751  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2752  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2753  /// and one 1-byte store. This only applies to copying a constant array of
2754  /// constant size.
2756 
2757 
2758  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2759  ///
2760  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2761  /// of store instructions to keep together. This helps in pairing and
2762  // vectorization later on.
2763  unsigned MaxGluedStoresPerMemcpy = 0;
2764 
2765  /// Maximum number of store operations that may be substituted for a call to
2766  /// memcpy, used for functions with OptSize attribute.
2770 
2771  /// Specify maximum bytes of store instructions per memmove call.
2772  ///
2773  /// When lowering \@llvm.memmove this field specifies the maximum number of
2774  /// store instructions that may be substituted for a call to memmove. Targets
2775  /// must set this value based on the cost threshold for that target. Targets
2776  /// should assume that the memmove will be done using as many of the largest
2777  /// store operations first, followed by smaller ones, if necessary, per
2778  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2779  /// with 8-bit alignment would result in nine 1-byte stores. This only
2780  /// applies to copying a constant array of constant size.
2782 
2783  /// Maximum number of store instructions that may be substituted for a call to
2784  /// memmove, used for functions with OptSize attribute.
2786 
2787  /// Tells the code generator that select is more expensive than a branch if
2788  /// the branch is usually predicted right.
2790 
2791  /// \see enableExtLdPromotion.
2793 
2794  /// Return true if the value types that can be represented by the specified
2795  /// register class are all legal.
2796  bool isLegalRC(const TargetRegisterInfo &TRI,
2797  const TargetRegisterClass &RC) const;
2798 
2799  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2800  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2801  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2802  MachineBasicBlock *MBB) const;
2803 
2804  /// Replace/modify the XRay custom event operands with target-dependent
2805  /// details.
2806  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2807  MachineBasicBlock *MBB) const;
2808 
2809  /// Replace/modify the XRay typed event operands with target-dependent
2810  /// details.
2811  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2812  MachineBasicBlock *MBB) const;
2813 };
2814 
2815 /// This class defines information used to lower LLVM code to legal SelectionDAG
2816 /// operators that the target instruction selector can accept natively.
2817 ///
2818 /// This class also defines callbacks that targets must implement to lower
2819 /// target-specific constructs to SelectionDAG operators.
2821 public:
2822  struct DAGCombinerInfo;
2823 
2824  TargetLowering(const TargetLowering &) = delete;
2825  TargetLowering &operator=(const TargetLowering &) = delete;
2826 
2827  /// NOTE: The TargetMachine owns TLOF.
2828  explicit TargetLowering(const TargetMachine &TM);
2829 
2830  bool isPositionIndependent() const;
2831 
2832  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2833  FunctionLoweringInfo *FLI,
2834  LegacyDivergenceAnalysis *DA) const {
2835  return false;
2836  }
2837 
2838  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2839  return false;
2840  }
2841 
2842  /// Returns true by value, base pointer and offset pointer and addressing mode
2843  /// by reference if the node's address can be legally represented as
2844  /// pre-indexed load / store address.
2845  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2846  SDValue &/*Offset*/,
2847  ISD::MemIndexedMode &/*AM*/,
2848  SelectionDAG &/*DAG*/) const {
2849  return false;
2850  }
2851 
2852  /// Returns true by value, base pointer and offset pointer and addressing mode
2853  /// by reference if this node can be combined with a load / store to form a
2854  /// post-indexed load / store.
2855  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2856  SDValue &/*Base*/,
2857  SDValue &/*Offset*/,
2858  ISD::MemIndexedMode &/*AM*/,
2859  SelectionDAG &/*DAG*/) const {
2860  return false;
2861  }
2862 
2863  /// Return the entry encoding for a jump table in the current function. The
2864  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2865  virtual unsigned getJumpTableEncoding() const;
2866 
2867  virtual const MCExpr *
2869  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2870  MCContext &/*Ctx*/) const {
2871  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2872  }
2873 
2874  /// Returns relocation base for the given PIC jumptable.
2875  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2876  SelectionDAG &DAG) const;
2877 
2878  /// This returns the relocation base for the given PIC jumptable, the same as
2879  /// getPICJumpTableRelocBase, but as an MCExpr.
2880  virtual const MCExpr *
2881  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2882  unsigned JTI, MCContext &Ctx) const;
2883 
2884  /// Return true if folding a constant offset with the given GlobalAddress is
2885  /// legal. It is frequently not legal in PIC relocation models.
2886  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2887 
2889  SDValue &Chain) const;
2890 
2891  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2892  SDValue &NewRHS, ISD::CondCode &CCCode,
2893  const SDLoc &DL) const;
2894 
2895  /// Returns a pair of (return value, chain).
2896  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2897  std::pair<SDValue, SDValue> makeLibCall(
2898  SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops,
2899  bool isSigned, const SDLoc &dl, bool doesNotReturn = false,
2900  bool isReturnValueUsed = true, bool isPostTypeLegalization = false) const;
2901 
2902  /// Check whether parameters to a call that are passed in callee saved
2903  /// registers are the same as from the calling function. This needs to be
2904  /// checked for tail call eligibility.
2905  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2906  const uint32_t *CallerPreservedMask,
2907  const SmallVectorImpl<CCValAssign> &ArgLocs,
2908  const SmallVectorImpl<SDValue> &OutVals) const;
2909 
2910  //===--------------------------------------------------------------------===//
2911  // TargetLowering Optimization Methods
2912  //
2913 
2914  /// A convenience struct that encapsulates a DAG, and two SDValues for
2915  /// returning information from TargetLowering to its clients that want to
2916  /// combine.
2919  bool LegalTys;
2920  bool LegalOps;
2923 
2925  bool LT, bool LO) :
2926  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2927 
2928  bool LegalTypes() const { return LegalTys; }
2929  bool LegalOperations() const { return LegalOps; }
2930 
2932  Old = O;
2933  New = N;
2934  return true;
2935  }
2936  };
2937 
2938  /// Check to see if the specified operand of the specified instruction is a
2939  /// constant integer. If so, check to see if there are any bits set in the
2940  /// constant that are not demanded. If so, shrink the constant and return
2941  /// true.
2942  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2943  TargetLoweringOpt &TLO) const;
2944 
2945  // Target hook to do target-specific const optimization, which is called by
2946  // ShrinkDemandedConstant. This function should return true if the target
2947  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2948  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2949  TargetLoweringOpt &TLO) const {
2950  return false;
2951  }
2952 
2953  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2954  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2955  /// generalized for targets with other types of implicit widening casts.
2956  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2957  TargetLoweringOpt &TLO) const;
2958 
2959  /// Look at Op. At this point, we know that only the DemandedBits bits of the
2960  /// result of Op are ever used downstream. If we can use this information to
2961  /// simplify Op, create a new simplified DAG node and return true, returning
2962  /// the original and new nodes in Old and New. Otherwise, analyze the
2963  /// expression and return a mask of KnownOne and KnownZero bits for the
2964  /// expression (used to simplify the caller). The KnownZero/One bits may only
2965  /// be accurate for those bits in the Demanded masks.
2966  /// \p AssumeSingleUse When this parameter is true, this function will
2967  /// attempt to simplify \p Op even if there are multiple uses.
2968  /// Callers are responsible for correctly updating the DAG based on the
2969  /// results of this function, because simply replacing replacing TLO.Old
2970  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2971  /// has multiple uses.
2972  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2973  const APInt &DemandedElts, KnownBits &Known,
2974  TargetLoweringOpt &TLO, unsigned Depth = 0,
2975  bool AssumeSingleUse = false) const;
2976 
2977  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
2978  /// Adds Op back to the worklist upon success.
2979  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2980  KnownBits &Known, TargetLoweringOpt &TLO,
2981  unsigned Depth = 0,
2982  bool AssumeSingleUse = false) const;
2983 
2984  /// Helper wrapper around SimplifyDemandedBits.
2985  /// Adds Op back to the worklist upon success.
2986  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2987  DAGCombinerInfo &DCI) const;
2988 
2989  /// Look at Vector Op. At this point, we know that only the DemandedElts
2990  /// elements of the result of Op are ever used downstream. If we can use
2991  /// this information to simplify Op, create a new simplified DAG node and
2992  /// return true, storing the original and new nodes in TLO.
2993  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2994  /// KnownZero elements for the expression (used to simplify the caller).
2995  /// The KnownUndef/Zero elements may only be accurate for those bits
2996  /// in the DemandedMask.
2997  /// \p AssumeSingleUse When this parameter is true, this function will
2998  /// attempt to simplify \p Op even if there are multiple uses.
2999  /// Callers are responsible for correctly updating the DAG based on the
3000  /// results of this function, because simply replacing replacing TLO.Old
3001  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3002  /// has multiple uses.
3003  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3004  APInt &KnownUndef, APInt &KnownZero,
3005  TargetLoweringOpt &TLO, unsigned Depth = 0,
3006  bool AssumeSingleUse = false) const;
3007 
3008  /// Helper wrapper around SimplifyDemandedVectorElts.
3009  /// Adds Op back to the worklist upon success.
3010  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3011  APInt &KnownUndef, APInt &KnownZero,
3012  DAGCombinerInfo &DCI) const;
3013 
3014  /// Determine which of the bits specified in Mask are known to be either zero
3015  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3016  /// argument allows us to only collect the known bits that are shared by the
3017  /// requested vector elements.
3018  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3019  KnownBits &Known,
3020  const APInt &DemandedElts,
3021  const SelectionDAG &DAG,
3022  unsigned Depth = 0) const;
3023 
3024  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3025  /// Default implementation computes low bits based on alignment
3026  /// information. This should preserve known bits passed into it.
3027  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3028  KnownBits &Known,
3029  const APInt &DemandedElts,
3030  const SelectionDAG &DAG,
3031  unsigned Depth = 0) const;
3032 
3033  /// This method can be implemented by targets that want to expose additional
3034  /// information about sign bits to the DAG Combiner. The DemandedElts
3035  /// argument allows us to only collect the minimum sign bits that are shared
3036  /// by the requested vector elements.
3037  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3038  const APInt &DemandedElts,
3039  const SelectionDAG &DAG,
3040  unsigned Depth = 0) const;
3041 
3042  /// Attempt to simplify any target nodes based on the demanded vector
3043  /// elements, returning true on success. Otherwise, analyze the expression and
3044  /// return a mask of KnownUndef and KnownZero elements for the expression
3045  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3046  /// accurate for those bits in the DemandedMask.
3047  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3048  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3049  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3050 
3051  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3052  /// returning true on success. Otherwise, analyze the
3053  /// expression and return a mask of KnownOne and KnownZero bits for the
3054  /// expression (used to simplify the caller). The KnownZero/One bits may only
3055  /// be accurate for those bits in the Demanded masks.
3056  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3057  const APInt &DemandedBits,
3058  const APInt &DemandedElts,
3059  KnownBits &Known,
3060  TargetLoweringOpt &TLO,
3061  unsigned Depth = 0) const;
3062 
3063  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3064  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3065  /// NaN.
3066  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3067  const SelectionDAG &DAG,
3068  bool SNaN = false,
3069  unsigned Depth = 0) const;
3071  void *DC; // The DAG Combiner object.
3074 
3075  public:
3077 
3078  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3079  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3080 
3081  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3082  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3083  bool isAfterLegalizeDAG() const {
3084  return Level == AfterLegalizeDAG;
3085  }
3087  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3088 
3089  void AddToWorklist(SDNode *N);
3090  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3091  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3092  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3093 
3094  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3095  };
3096 
3097  /// Return if the N is a constant or constant vector equal to the true value
3098  /// from getBooleanContents().
3099  bool isConstTrueVal(const SDNode *N) const;
3100 
3101  /// Return if the N is a constant or constant vector equal to the false value
3102  /// from getBooleanContents().
3103  bool isConstFalseVal(const SDNode *N) const;
3104 
3105  /// Return if \p N is a True value when extended to \p VT.
3106  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3107 
3108  /// Try to simplify a setcc built with the specified operands and cc. If it is
3109  /// unable to simplify it, return a null SDValue.
3110  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3111  bool foldBooleans, DAGCombinerInfo &DCI,
3112  const SDLoc &dl) const;
3113 
3114  // For targets which wrap address, unwrap for analysis.
3115  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3116 
3117  /// Returns true (and the GlobalValue and the offset) if the node is a
3118  /// GlobalAddress + offset.
3119  virtual bool
3120  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3121 
3122  /// This method will be invoked for all target nodes and for any
3123  /// target-independent nodes that the target has registered with invoke it
3124  /// for.
3125  ///
3126  /// The semantics are as follows:
3127  /// Return Value:
3128  /// SDValue.Val == 0 - No change was made
3129  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3130  /// otherwise - N should be replaced by the returned Operand.
3131  ///
3132  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3133  /// more complex transformations.
3134  ///
3135  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3136 
3137  /// Return true if it is profitable to move this shift by a constant amount
3138  /// though its operand, adjusting any immediate operands as necessary to
3139  /// preserve semantics. This transformation may not be desirable if it
3140  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3141  /// extraction in AArch64). By default, it returns true.
3142  ///
3143  /// @param N the shift node
3144  /// @param Level the current DAGCombine legalization level.
3145  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3146  CombineLevel Level) const {
3147  return true;
3148  }
3149 
3150  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3151  // to a shuffle and a truncate.
3152  // Example of such a combine:
3153  // v4i32 build_vector((extract_elt V, 1),
3154  // (extract_elt V, 3),
3155  // (extract_elt V, 5),
3156  // (extract_elt V, 7))
3157  // -->
3158  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3160  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3161  return false;
3162  }
3163 
3164  /// Return true if the target has native support for the specified value type
3165  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3166  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3167  /// and some i16 instructions are slow.
3168  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3169  // By default, assume all legal types are desirable.
3170  return isTypeLegal(VT);
3171  }
3172 
3173  /// Return true if it is profitable for dag combiner to transform a floating
3174  /// point op of specified opcode to a equivalent op of an integer
3175  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3176  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3177  EVT /*VT*/) const {
3178  return false;
3179  }
3180 
3181  /// This method query the target whether it is beneficial for dag combiner to
3182  /// promote the specified node. If true, it should return the desired
3183  /// promotion type by reference.
3184  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3185  return false;
3186  }
3187 
3188  /// Return true if the target supports swifterror attribute. It optimizes
3189  /// loads and stores to reading and writing a specific register.
3190  virtual bool supportSwiftError() const {
3191  return false;
3192  }
3193 
3194  /// Return true if the target supports that a subset of CSRs for the given
3195  /// machine function is handled explicitly via copies.
3196  virtual bool supportSplitCSR(MachineFunction *MF) const {
3197  return false;
3198  }
3199 
3200  /// Perform necessary initialization to handle a subset of CSRs explicitly
3201  /// via copies. This function is called at the beginning of instruction
3202  /// selection.
3204  llvm_unreachable("Not Implemented");
3205  }
3206 
3207  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3208  /// CSRs to virtual registers in the entry block, and copy them back to
3209  /// physical registers in the exit blocks. This function is called at the end
3210  /// of instruction selection.
3211  virtual void insertCopiesSplitCSR(
3213  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3214  llvm_unreachable("Not Implemented");
3215  }
3216 
3217  //===--------------------------------------------------------------------===//
3218  // Lowering methods - These methods must be implemented by targets so that
3219  // the SelectionDAGBuilder code knows how to lower these.
3220  //
3221 
3222  /// This hook must be implemented to lower the incoming (formal) arguments,
3223  /// described by the Ins array, into the specified DAG. The implementation
3224  /// should fill in the InVals array with legal-type argument values, and
3225  /// return the resulting token chain value.
3227  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3228  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3229  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3230  llvm_unreachable("Not Implemented");
3231  }
3232 
3233  /// This structure contains all information that is necessary for lowering
3234  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3235  /// needs to lower a call, and targets will see this struct in their LowerCall
3236  /// implementation.
3239  Type *RetTy = nullptr;
3240  bool RetSExt : 1;
3241  bool RetZExt : 1;
3242  bool IsVarArg : 1;
3243  bool IsInReg : 1;
3244  bool DoesNotReturn : 1;
3246  bool IsConvergent : 1;
3247  bool IsPatchPoint : 1;
3248 
3249  // IsTailCall should be modified by implementations of
3250  // TargetLowering::LowerCall that perform tail call conversions.
3251  bool IsTailCall = false;
3252 
3253  // Is Call lowering done post SelectionDAG type legalization.
3254  bool IsPostTypeLegalization = false;
3255 
3256  unsigned NumFixedArgs = -1;
3259  ArgListTy Args;
3267 
3269  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3270  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3271  IsPatchPoint(false), DAG(DAG) {}
3272 
3274  DL = dl;
3275  return *this;
3276  }
3277 
3279  Chain = InChain;
3280  return *this;
3281  }
3282 
3283  // setCallee with target/module-specific attributes
3285  SDValue Target, ArgListTy &&ArgsList) {
3286  RetTy = ResultType;
3287  Callee = Target;
3288  CallConv = CC;
3289  NumFixedArgs = ArgsList.size();
3290  Args = std::move(ArgsList);
3291 
3293  &(DAG.getMachineFunction()), CC, Args);
3294  return *this;
3295  }
3296 
3298  SDValue Target, ArgListTy &&ArgsList) {
3299  RetTy = ResultType;
3300  Callee = Target;
3301  CallConv = CC;
3302  NumFixedArgs = ArgsList.size();
3303  Args = std::move(ArgsList);
3304  return *this;
3305  }
3306 
3308  SDValue Target, ArgListTy &&ArgsList,
3309  ImmutableCallSite Call) {
3310  RetTy = ResultType;
3311 
3312  IsInReg = Call.hasRetAttr(Attribute::InReg);
3313  DoesNotReturn =
3314  Call.doesNotReturn() ||
3315  (!Call.isInvoke() &&
3316  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3317  IsVarArg = FTy->isVarArg();
3318  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3319  RetSExt = Call.hasRetAttr(Attribute::SExt);
3320  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3321 
3322  Callee = Target;
3323 
3324  CallConv = Call.getCallingConv();
3325  NumFixedArgs = FTy->getNumParams();
3326  Args = std::move(ArgsList);
3327 
3328  CS = Call;
3329 
3330  return *this;
3331  }
3332 
3334  IsInReg = Value;
3335  return *this;
3336  }
3337 
3339  DoesNotReturn = Value;
3340  return *this;
3341  }
3342 
3344  IsVarArg = Value;
3345  return *this;
3346  }
3347 
3349  IsTailCall = Value;
3350  return *this;
3351  }
3352 
3354  IsReturnValueUsed = !Value;
3355  return *this;
3356  }
3357 
3359  IsConvergent = Value;
3360  return *this;
3361  }
3362 
3364  RetSExt = Value;
3365  return *this;
3366  }
3367 
3369  RetZExt = Value;
3370  return *this;
3371  }
3372 
3374  IsPatchPoint = Value;
3375  return *this;
3376  }
3377 
3379  IsPostTypeLegalization = Value;
3380  return *this;
3381  }
3382 
3383  ArgListTy &getArgs() {
3384  return Args;
3385  }
3386  };
3387 
3388  /// This function lowers an abstract call to a function into an actual call.
3389  /// This returns a pair of operands. The first element is the return value
3390  /// for the function (if RetTy is not VoidTy). The second element is the
3391  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3392  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3393 
3394  /// This hook must be implemented to lower calls into the specified
3395  /// DAG. The outgoing arguments to the call are described by the Outs array,
3396  /// and the values to be returned by the call are described by the Ins
3397  /// array. The implementation should fill in the InVals array with legal-type
3398  /// return values from the call, and return the resulting token chain value.
3399  virtual SDValue
3401  SmallVectorImpl<SDValue> &/*InVals*/) const {
3402  llvm_unreachable("Not Implemented");
3403  }
3404 
3405  /// Target-specific cleanup for formal ByVal parameters.
3406  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3407 
3408  /// This hook should be implemented to check whether the return values
3409  /// described by the Outs array can fit into the return registers. If false
3410  /// is returned, an sret-demotion is performed.
3411  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3412  MachineFunction &/*MF*/, bool /*isVarArg*/,
3413  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3414  LLVMContext &/*Context*/) const
3415  {
3416  // Return true by default to get preexisting behavior.
3417  return true;
3418  }
3419 
3420  /// This hook must be implemented to lower outgoing return values, described
3421  /// by the Outs array, into the specified DAG. The implementation should
3422  /// return the resulting token chain value.
3423  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3424  bool /*isVarArg*/,
3425  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3426  const SmallVectorImpl<SDValue> & /*OutVals*/,
3427  const SDLoc & /*dl*/,
3428  SelectionDAG & /*DAG*/) const {
3429  llvm_unreachable("Not Implemented");
3430  }
3431 
3432  /// Return true if result of the specified node is used by a return node
3433  /// only. It also compute and return the input chain for the tail call.
3434  ///
3435  /// This is used to determine whether it is possible to codegen a libcall as
3436  /// tail call at legalization time.
3437  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3438  return false;
3439  }
3440 
3441  /// Return true if the target may be able emit the call instruction as a tail
3442  /// call. This is used by optimization passes to determine if it's profitable
3443  /// to duplicate return instructions to enable tailcall optimization.
3444  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3445  return false;
3446  }
3447 
3448  /// Return the builtin name for the __builtin___clear_cache intrinsic
3449  /// Default is to invoke the clear cache library call
3450  virtual const char * getClearCacheBuiltinName() const {
3451  return "__clear_cache";
3452  }
3453 
3454  /// Return the register ID of the name passed in. Used by named register
3455  /// global variables extension. There is no target-independent behaviour
3456  /// so the default action is to bail.
3457  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3458  SelectionDAG &DAG) const {
3459  report_fatal_error("Named registers not implemented for this target");
3460  }
3461 
3462  /// Return the type that should be used to zero or sign extend a
3463  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3464  /// require the return type to be promoted, but this is not true all the time,
3465  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3466  /// conventions. The frontend should handle this and include all of the
3467  /// necessary information.
3469  ISD::NodeType /*ExtendKind*/) const {
3470  EVT MinVT = getRegisterType(Context, MVT::i32);
3471  return VT.bitsLT(MinVT) ? MinVT : VT;
3472  }
3473 
3474  /// For some targets, an LLVM struct type must be broken down into multiple
3475  /// simple types, but the calling convention specifies that the entire struct
3476  /// must be passed in a block of consecutive registers.
3477  virtual bool
3479  bool isVarArg) const {
3480  return false;
3481  }
3482 
3483  /// Returns a 0 terminated array of registers that can be safely used as
3484  /// scratch registers.
3485  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3486  return nullptr;
3487  }
3488 
3489  /// This callback is used to prepare for a volatile or atomic load.
3490  /// It takes a chain node as input and returns the chain for the load itself.
3491  ///
3492  /// Having a callback like this is necessary for targets like SystemZ,
3493  /// which allows a CPU to reuse the result of a previous load indefinitely,
3494  /// even if a cache-coherent store is performed by another CPU. The default
3495  /// implementation does nothing.
3497  SelectionDAG &DAG) const {
3498  return Chain;
3499  }
3500 
3501  /// This callback is used to inspect load/store instructions and add
3502  /// target-specific MachineMemOperand flags to them. The default
3503  /// implementation does nothing.
3506  }
3507 
3508  /// This callback is invoked by the type legalizer to legalize nodes with an
3509  /// illegal operand type but legal result types. It replaces the
3510  /// LowerOperation callback in the type Legalizer. The reason we can not do
3511  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3512  /// use this callback.
3513  ///
3514  /// TODO: Consider merging with ReplaceNodeResults.
3515  ///
3516  /// The target places new result values for the node in Results (their number
3517  /// and types must exactly match those of the original return values of
3518  /// the node), or leaves Results empty, which indicates that the node is not
3519  /// to be custom lowered after all.
3520  /// The default implementation calls LowerOperation.
3521  virtual void LowerOperationWrapper(SDNode *N,
3523  SelectionDAG &DAG) const;
3524 
3525  /// This callback is invoked for operations that are unsupported by the
3526  /// target, which are registered to use 'custom' lowering, and whose defined
3527  /// values are all legal. If the target has no operations that require custom
3528  /// lowering, it need not implement this. The default implementation of this
3529  /// aborts.
3530  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3531 
3532  /// This callback is invoked when a node result type is illegal for the
3533  /// target, and the operation was registered to use 'custom' lowering for that
3534  /// result type. The target places new result values for the node in Results
3535  /// (their number and types must exactly match those of the original return
3536  /// values of the node), or leaves Results empty, which indicates that the
3537  /// node is not to be custom lowered after all.
3538  ///
3539  /// If the target has no operations that require custom lowering, it need not
3540  /// implement this. The default implementation aborts.
3541  virtual void ReplaceNodeResults(SDNode * /*N*/,
3542  SmallVectorImpl<SDValue> &/*Results*/,
3543  SelectionDAG &/*DAG*/) const {
3544  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3545  }
3546 
3547  /// This method returns the name of a target specific DAG node.
3548  virtual const char *getTargetNodeName(unsigned Opcode) const;
3549 
3550  /// This method returns a target specific FastISel object, or null if the
3551  /// target does not support "fast" ISel.
3553  const TargetLibraryInfo *) const {
3554  return nullptr;
3555  }
3556 
3557  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3558  SelectionDAG &DAG) const;
3559 
3560  //===--------------------------------------------------------------------===//
3561  // Inline Asm Support hooks
3562  //
3563 
3564  /// This hook allows the target to expand an inline asm call to be explicit
3565  /// llvm code if it wants to. This is useful for turning simple inline asms
3566  /// into LLVM intrinsics, which gives the compiler more information about the
3567  /// behavior of the code.
3568  virtual bool ExpandInlineAsm(CallInst *) const {
3569  return false;
3570  }
3571 
3573  C_Register, // Constraint represents specific register(s).
3574  C_RegisterClass, // Constraint represents any of register(s) in class.
3575  C_Memory, // Memory constraint.
3576  C_Other, // Something else.
3577  C_Unknown // Unsupported constraint.
3578  };
3579 
3581  // Generic weights.
3582  CW_Invalid = -1, // No match.
3583  CW_Okay = 0, // Acceptable.
3584  CW_Good = 1, // Good weight.
3585  CW_Better = 2, // Better weight.
3586  CW_Best = 3, // Best weight.
3587 
3588  // Well-known weights.
3589  CW_SpecificReg = CW_Okay, // Specific register operands.
3590  CW_Register = CW_Good, // Register operands.
3591  CW_Memory = CW_Better, // Memory operands.
3592  CW_Constant = CW_Best, // Constant operand.
3593  CW_Default = CW_Okay // Default or don't know type.
3594  };
3595 
3596  /// This contains information for each constraint that we are lowering.
3598  /// This contains the actual string for the code, like "m". TargetLowering
3599  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3600  /// matches the operand.
3601  std::string ConstraintCode;
3602 
3603  /// Information about the constraint code, e.g. Register, RegisterClass,
3604  /// Memory, Other, Unknown.
3606 
3607  /// If this is the result output operand or a clobber, this is null,
3608  /// otherwise it is the incoming operand to the CallInst. This gets
3609  /// modified as the asm is processed.
3610  Value *CallOperandVal = nullptr;
3611 
3612  /// The ValueType for the operand value.
3613  MVT ConstraintVT = MVT::Other;
3614 
3615  /// Copy constructor for copying from a ConstraintInfo.
3617  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3618 
3619  /// Return true of this is an input operand that is a matching constraint
3620  /// like "4".
3621  bool isMatchingInputConstraint() const;
3622 
3623  /// If this is an input matching constraint, this method returns the output
3624  /// operand it matches.
3625  unsigned getMatchedOperand() const;
3626  };
3627 
3628  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3629 
3630  /// Split up the constraint string from the inline assembly value into the
3631  /// specific constraints and their prefixes, and also tie in the associated
3632  /// operand values. If this returns an empty vector, and if the constraint
3633  /// string itself isn't empty, there was an error parsing.
3634  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3635  const TargetRegisterInfo *TRI,
3636  ImmutableCallSite CS) const;
3637 
3638  /// Examine constraint type and operand type and determine a weight value.
3639  /// The operand object must already have been set up with the operand type.
3640  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3641  AsmOperandInfo &info, int maIndex) const;
3642 
3643  /// Examine constraint string and operand type and determine a weight value.
3644  /// The operand object must already have been set up with the operand type.
3645  virtual ConstraintWeight getSingleConstraintMatchWeight(
3646  AsmOperandInfo &info, const char *constraint) const;
3647 
3648  /// Determines the constraint code and constraint type to use for the specific
3649  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3650  /// If the actual operand being passed in is available, it can be passed in as
3651  /// Op, otherwise an empty SDValue can be passed.
3652  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3653  SDValue Op,
3654  SelectionDAG *DAG = nullptr) const;
3655 
3656  /// Given a constraint, return the type of constraint it is for this target.
3657  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3658 
3659  /// Given a physical register constraint (e.g. {edx}), return the register
3660  /// number and the register class for the register.
3661  ///
3662  /// Given a register class constraint, like 'r', if this corresponds directly
3663  /// to an LLVM register class, return a register of 0 and the register class
3664  /// pointer.
3665  ///
3666  /// This should only be used for C_Register constraints. On error, this
3667  /// returns a register number of 0 and a null register class pointer.
3668  virtual std::pair<unsigned, const TargetRegisterClass *>
3669  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3670  StringRef Constraint, MVT VT) const;
3671 
3672  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3673  if (ConstraintCode == "i")
3674  return InlineAsm::Constraint_i;
3675  else if (ConstraintCode == "m")
3676  return InlineAsm::Constraint_m;
3678  }
3679 
3680  /// Try to replace an X constraint, which matches anything, with another that
3681  /// has more specific requirements based on the type of the corresponding
3682  /// operand. This returns null if there is no replacement to make.
3683  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3684 
3685  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3686  /// add anything to Ops.
3687  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3688  std::vector<SDValue> &Ops,
3689  SelectionDAG &DAG) const;
3690 
3691  // Lower custom output constraints. If invalid, return SDValue().
3692  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3693  SDLoc DL,
3694  const AsmOperandInfo &OpInfo,
3695  SelectionDAG &DAG) const;
3696 
3697  //===--------------------------------------------------------------------===//
3698  // Div utility functions
3699  //
3700  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3701  SmallVectorImpl<SDNode *> &Created) const;
3702  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3703  SmallVectorImpl<SDNode *> &Created) const;
3704 
3705  /// Targets may override this function to provide custom SDIV lowering for
3706  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3707  /// assumes SDIV is expensive and replaces it with a series of other integer
3708  /// operations.
3709  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3710  SelectionDAG &DAG,
3711  SmallVectorImpl<SDNode *> &Created) const;
3712 
3713  /// Indicate whether this target prefers to combine FDIVs with the same
3714  /// divisor. If the transform should never be done, return zero. If the
3715  /// transform should be done, return the minimum number of divisor uses
3716  /// that must exist.
3717  virtual unsigned combineRepeatedFPDivisors() const {
3718  return 0;
3719  }
3720 
3721  /// Hooks for building estimates in place of slower divisions and square
3722  /// roots.
3723 
3724  /// Return either a square root or its reciprocal estimate value for the input
3725  /// operand.
3726  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3727  /// 'Enabled' as set by a potential default override attribute.
3728  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3729  /// refinement iterations required to generate a sufficient (though not
3730  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3731  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3732  /// algorithm implementation that uses either one or two constants.
3733  /// The boolean Reciprocal is used to select whether the estimate is for the
3734  /// square root of the input operand or the reciprocal of its square root.
3735  /// A target may choose to implement its own refinement within this function.
3736  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3737  /// any further refinement of the estimate.
3738  /// An empty SDValue return means no estimate sequence can be created.
3740  int Enabled, int &RefinementSteps,
3741  bool &UseOneConstNR, bool Reciprocal) const {
3742  return SDValue();
3743  }
3744 
3745  /// Return a reciprocal estimate value for the input operand.
3746  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3747  /// 'Enabled' as set by a potential default override attribute.
3748  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3749  /// refinement iterations required to generate a sufficient (though not
3750  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3751  /// A target may choose to implement its own refinement within this function.
3752  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3753  /// any further refinement of the estimate.
3754  /// An empty SDValue return means no estimate sequence can be created.
3756  int Enabled, int &RefinementSteps) const {
3757  return SDValue();
3758  }
3759 
3760  //===--------------------------------------------------------------------===//
3761  // Legalization utility functions
3762  //
3763 
3764  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3765  /// respectively, each computing an n/2-bit part of the result.
3766  /// \param Result A vector that will be filled with the parts of the result
3767  /// in little-endian order.
3768  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3769  /// if you want to control how low bits are extracted from the LHS.
3770  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3771  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3772  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3773  /// \returns true if the node has been expanded, false if it has not
3774  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3775  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3777  SDValue LL = SDValue(), SDValue LH = SDValue(),
3778  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3779 
3780  /// Expand a MUL into two nodes. One that computes the high bits of
3781  /// the result and one that computes the low bits.
3782  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3783  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3784  /// if you want to control how low bits are extracted from the LHS.
3785  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3786  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3787  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3788  /// \returns true if the node has been expanded. false if it has not
3789  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3790  SelectionDAG &DAG, MulExpansionKind Kind,
3791  SDValue LL = SDValue(), SDValue LH = SDValue(),
3792  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3793 
3794  /// Expand funnel shift.
3795  /// \param N Node to expand
3796  /// \param Result output after conversion
3797  /// \returns True, if the expansion was successful, false otherwise
3798  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3799 
3800  /// Expand rotations.
3801  /// \param N Node to expand
3802  /// \param Result output after conversion
3803  /// \returns True, if the expansion was successful, false otherwise
3804  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3805 
3806  /// Expand float(f32) to SINT(i64) conversion
3807  /// \param N Node to expand
3808  /// \param Result output after conversion
3809  /// \returns True, if the expansion was successful, false otherwise
3810  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3811 
3812  /// Expand float to UINT conversion
3813  /// \param N Node to expand
3814  /// \param Result output after conversion
3815  /// \returns True, if the expansion was successful, false otherwise
3816  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3817 
3818  /// Expand UINT(i64) to double(f64) conversion
3819  /// \param N Node to expand
3820  /// \param Result output after conversion
3821  /// \returns True, if the expansion was successful, false otherwise
3822  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3823 
3824  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3825  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3826 
3827  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3828  /// vector nodes can only succeed if all operations are legal/custom.
3829  /// \param N Node to expand
3830  /// \param Result output after conversion
3831  /// \returns True, if the expansion was successful, false otherwise
3832  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3833 
3834  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3835  /// vector nodes can only succeed if all operations are legal/custom.
3836  /// \param N Node to expand
3837  /// \param Result output after conversion
3838  /// \returns True, if the expansion was successful, false otherwise
3839  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3840 
3841  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3842  /// vector nodes can only succeed if all operations are legal/custom.
3843  /// \param N Node to expand
3844  /// \param Result output after conversion
3845  /// \returns True, if the expansion was successful, false otherwise
3846  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3847 
3848  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
3849  /// vector nodes can only succeed if all operations are legal/custom.
3850  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
3851  /// \param N Node to expand
3852  /// \param Result output after conversion
3853  /// \returns True, if the expansion was successful, false otherwise
3854  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3855 
3856  /// Turn load of vector type into a load of the individual elements.
3857  /// \param LD load to expand
3858  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3859  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3860 
3861  // Turn a store of a vector type into stores of the individual elements.
3862  /// \param ST Store with a vector value type
3863  /// \returns MERGE_VALUs of the individual store chains.
3864  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3865 
3866  /// Expands an unaligned load to 2 half-size loads for an integer, and
3867  /// possibly more for vectors.
3868  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3869  SelectionDAG &DAG) const;
3870 
3871  /// Expands an unaligned store to 2 half-size stores for integer values, and
3872  /// possibly more for vectors.
3873  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3874 
3875  /// Increments memory address \p Addr according to the type of the value
3876  /// \p DataVT that should be stored. If the data is stored in compressed
3877  /// form, the memory address should be incremented according to the number of
3878  /// the stored elements. This number is equal to the number of '1's bits
3879  /// in the \p Mask.
3880  /// \p DataVT is a vector type. \p Mask is a vector value.
3881  /// \p DataVT and \p Mask have the same number of vector elements.
3882  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3883  EVT DataVT, SelectionDAG &DAG,
3884  bool IsCompressedMemory) const;
3885 
3886  /// Get a pointer to vector element \p Idx located in memory for a vector of
3887  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3888  /// bounds the returned pointer is unspecified, but will be within the vector
3889  /// bounds.
3890  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3891  SDValue Index) const;
3892 
3893  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3894  /// method accepts integers as its arguments.
3895  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
3896 
3897  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
3898  /// integers as its arguments.
3899  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
3900 
3901  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
3902  /// expansion was successful and populates the Result and Overflow arguments.
3903  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3904  SelectionDAG &DAG) const;
3905 
3906  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
3907  /// only the first Count elements of the vector are used.
3908  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
3909 
3910  //===--------------------------------------------------------------------===//
3911  // Instruction Emitting Hooks
3912  //
3913 
3914  /// This method should be implemented by targets that mark instructions with
3915  /// the 'usesCustomInserter' flag. These instructions are special in various
3916  /// ways, which require special support to insert. The specified MachineInstr
3917  /// is created but not inserted into any basic blocks, and this method is
3918  /// called to expand it into a sequence of instructions, potentially also
3919  /// creating new basic blocks and control flow.
3920  /// As long as the returned basic block is different (i.e., we created a new
3921  /// one), the custom inserter is free to modify the rest of \p MBB.
3922  virtual MachineBasicBlock *
3923  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3924 
3925  /// This method should be implemented by targets that mark instructions with
3926  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3927  /// instruction selection by target hooks. e.g. To fill in optional defs for
3928  /// ARM 's' setting instructions.
3929  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3930  SDNode *Node) const;
3931 
3932  /// If this function returns true, SelectionDAGBuilder emits a
3933  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3934  virtual bool useLoadStackGuardNode() const {
3935  return false;
3936  }
3937 
3939  const SDLoc &DL) const {
3940  llvm_unreachable("not implemented for this target");
3941  }
3942 
3943  /// Lower TLS global address SDNode for target independent emulated TLS model.
3944  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3945  SelectionDAG &DAG) const;
3946 
3947  /// Expands target specific indirect branch for the case of JumpTable
3948  /// expanasion.
3950  SelectionDAG &DAG) const {
3951  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3952  }
3953 
3954  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3955  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3956  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3957  // combiner can fold the new nodes.
3958  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3959 
3960 private:
3961  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3962  const SDLoc &DL, DAGCombinerInfo &DCI) const;
3963  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3964  const SDLoc &DL, DAGCombinerInfo &DCI) const;
3965 
3966  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3967  SDValue N1, ISD::CondCode Cond,
3968  DAGCombinerInfo &DCI,
3969  const SDLoc &DL) const;
3970 };
3971 
3972 /// Given an LLVM IR type and return type attributes, compute the return value
3973 /// EVTs and flags, and optionally also the offsets, if the return value is
3974 /// being lowered to memory.
3977  const TargetLowering &TLI, const DataLayout &DL);
3978 
3979 } // end namespace llvm
3980 
3981 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:886
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:398
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:606
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:600
virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:380
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1014
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:269
void * PointerTy
Definition: GenericValue.h:21
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: BitVector.h:937
virtual bool decomposeMulByConstant(EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
uint64_t getNumElements() const
Definition: DerivedTypes.h:390
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:62
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
InstrTy * getInstruction() const
Definition: CallSite.h:96
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:102
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
static cl::opt< unsigned > MaxLoadsPerMemcmpOptSize("max-loads-per-memcmp-opt-size", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz"))
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const
Return true if sinking I&#39;s operands to the same basic block as I is profitable, e.g.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:122
SmallVector< ISD::OutputArg, 32 > Outs
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
An instruction for storing to memory.
Definition: Instructions.h:320
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:968
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:498
This class is used to represent ISD::STORE nodes.
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx)
static cl::opt< unsigned > MaxLoadsPerMemcmp("max-loads-per-memcmp", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp"))
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:41
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isFloatingPointOperation() const
Definition: Instructions.h:823
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:943
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:15
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
virtual bool isProfitableToHoist(Instruction *I) const
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information that is necessary for lowering calls.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
bool isExtFree(const Instruction *I) const
Return true if the extension represented by I is free.
const TargetMachine & getTargetMachine() const
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
void setUseUnderscoreLongJmp(bool Val)
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AsmOperandInfo(InlineAsm::ConstraintInfo Info)
Copy constructor for copying from a ConstraintInfo.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getMaxAtomicSizeInBitsSupported() const
Returns the maximum atomic operation size (in bits) supported by the backend.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:500
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
virtual bool shouldScalarizeBinop(SDValue VecOp) const
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
virtual bool isExtFreeImpl(const Instruction *I) const
Return true if the extension represented by I is free.
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
bool isReleaseOrStronger(AtomicOrdering ao)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
virtual bool IsDesirableToPromoteOp(SDValue, EVT &) const
This method query the target whether it is beneficial for dag combiner to promote the specified node...
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:406
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.