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TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Alignment.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class GISelKnownBits;
77 class IntrinsicInst;
78 struct KnownBits;
79 class LLVMContext;
80 class MachineBasicBlock;
81 class MachineFunction;
82 class MachineInstr;
83 class MachineJumpTableInfo;
84 class MachineLoop;
85 class MachineRegisterInfo;
86 class MCContext;
87 class MCExpr;
88 class Module;
89 class TargetRegisterClass;
90 class TargetLibraryInfo;
91 class TargetRegisterInfo;
92 class Value;
93 
94 namespace Sched {
95 
96  enum Preference {
97  None, // No preference
98  Source, // Follow source order.
99  RegPressure, // Scheduling for lowest register pressure.
100  Hybrid, // Scheduling for both latency and register pressure.
101  ILP, // Scheduling for ILP in low register pressure mode.
102  VLIW // Scheduling for VLIW targets.
103  };
104 
105 } // end namespace Sched
106 
107 /// This base class for TargetLowering contains the SelectionDAG-independent
108 /// parts that can be used from the rest of CodeGen.
110 public:
111  /// This enum indicates whether operations are valid for a target, and if not,
112  /// what action should be used to make them valid.
113  enum LegalizeAction : uint8_t {
114  Legal, // The target natively supports this operation.
115  Promote, // This operation should be executed in a larger type.
116  Expand, // Try to expand this to other ops, otherwise use a libcall.
117  LibCall, // Don't try to expand this to other ops, always use a libcall.
118  Custom // Use the LowerOperation hook to implement custom lowering.
119  };
120 
121  /// This enum indicates whether a types are legal for a target, and if not,
122  /// what action should be used to make them valid.
123  enum LegalizeTypeAction : uint8_t {
124  TypeLegal, // The target natively supports this type.
125  TypePromoteInteger, // Replace this integer with a larger one.
126  TypeExpandInteger, // Split this integer into two of half the size.
127  TypeSoftenFloat, // Convert this float to a same size integer type.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167  };
168 
169  /// Enum that specifies when a multiplication should be expanded.
170  enum class MulExpansionKind {
171  Always, // Always expand the instruction.
172  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173  // or custom.
174  };
175 
176  class ArgListEntry {
177  public:
178  Value *Val = nullptr;
180  Type *Ty = nullptr;
181  bool IsSExt : 1;
182  bool IsZExt : 1;
183  bool IsInReg : 1;
184  bool IsSRet : 1;
185  bool IsNest : 1;
186  bool IsByVal : 1;
187  bool IsInAlloca : 1;
188  bool IsReturned : 1;
189  bool IsSwiftSelf : 1;
190  bool IsSwiftError : 1;
191  uint16_t Alignment = 0;
192  Type *ByValType = nullptr;
193 
195  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
196  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
197  IsSwiftSelf(false), IsSwiftError(false) {}
198 
199  void setAttributes(const CallBase *Call, unsigned ArgIdx);
200 
201  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
202  return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
203  }
204  };
205  using ArgListTy = std::vector<ArgListEntry>;
206 
207  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
208  ArgListTy &Args) const {};
209 
211  switch (Content) {
212  case UndefinedBooleanContent:
213  // Extend by adding rubbish bits.
214  return ISD::ANY_EXTEND;
215  case ZeroOrOneBooleanContent:
216  // Extend by adding zero bits.
217  return ISD::ZERO_EXTEND;
218  case ZeroOrNegativeOneBooleanContent:
219  // Extend by copying the sign bit.
220  return ISD::SIGN_EXTEND;
221  }
222  llvm_unreachable("Invalid content kind");
223  }
224 
225  /// NOTE: The TargetMachine owns TLOF.
226  explicit TargetLoweringBase(const TargetMachine &TM);
227  TargetLoweringBase(const TargetLoweringBase &) = delete;
228  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
229  virtual ~TargetLoweringBase() = default;
230 
231 protected:
232  /// Initialize all of the actions to default values.
233  void initActions();
234 
235 public:
236  const TargetMachine &getTargetMachine() const { return TM; }
237 
238  virtual bool useSoftFloat() const { return false; }
239 
240  /// Return the pointer type for the given address space, defaults to
241  /// the pointer type from the data layout.
242  /// FIXME: The default needs to be removed once all the code is updated.
243  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
245  }
246 
247  /// Return the in-memory pointer type for the given address space, defaults to
248  /// the pointer type from the data layout. FIXME: The default needs to be
249  /// removed once all the code is updated.
250  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
252  }
253 
254  /// Return the type for frame index, which is determined by
255  /// the alloca address space specified through the data layout.
256  MVT getFrameIndexTy(const DataLayout &DL) const {
257  return getPointerTy(DL, DL.getAllocaAddrSpace());
258  }
259 
260  /// Return the type for operands of fence.
261  /// TODO: Let fence operands be of i32 type and remove this.
262  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
263  return getPointerTy(DL);
264  }
265 
266  /// EVT is not used in-tree, but is used by out-of-tree target.
267  /// A documentation for this function would be nice...
268  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
269 
270  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
271  bool LegalTypes = true) const;
272 
273  /// Returns the type to be used for the index operand of:
274  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
275  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
276  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
277  return getPointerTy(DL);
278  }
279 
280  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
281  return true;
282  }
283 
284  /// Return true if it is profitable to convert a select of FP constants into
285  /// a constant pool load whose address depends on the select condition. The
286  /// parameter may be used to differentiate a select with FP compare from
287  /// integer compare.
288  virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
289  return true;
290  }
291 
292  /// Return true if multiple condition registers are available.
294  return HasMultipleConditionRegisters;
295  }
296 
297  /// Return true if the target has BitExtract instructions.
298  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
299 
300  /// Return the preferred vector type legalization action.
303  // The default action for one element vectors is to scalarize
304  if (VT.getVectorNumElements() == 1)
305  return TypeScalarizeVector;
306  // The default action for an odd-width vector is to widen.
307  if (!VT.isPow2VectorType())
308  return TypeWidenVector;
309  // The default action for other vectors is to promote
310  return TypePromoteInteger;
311  }
312 
313  // There are two general methods for expanding a BUILD_VECTOR node:
314  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
315  // them together.
316  // 2. Build the vector on the stack and then load it.
317  // If this function returns true, then method (1) will be used, subject to
318  // the constraint that all of the necessary shuffles are legal (as determined
319  // by isShuffleMaskLegal). If this function returns false, then method (2) is
320  // always used. The vector type, and the number of defined values, are
321  // provided.
322  virtual bool
324  unsigned DefinedValues) const {
325  return DefinedValues < 3;
326  }
327 
328  /// Return true if integer divide is usually cheaper than a sequence of
329  /// several shifts, adds, and multiplies for this target.
330  /// The definition of "cheaper" may depend on whether we're optimizing
331  /// for speed or for size.
332  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
333 
334  /// Return true if the target can handle a standalone remainder operation.
335  virtual bool hasStandaloneRem(EVT VT) const {
336  return true;
337  }
338 
339  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
340  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
341  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
342  return false;
343  }
344 
345  /// Reciprocal estimate status values used by the functions below.
346  enum ReciprocalEstimate : int {
347  Unspecified = -1,
348  Disabled = 0,
350  };
351 
352  /// Return a ReciprocalEstimate enum value for a square root of the given type
353  /// based on the function's attributes. If the operation is not overridden by
354  /// the function's attributes, "Unspecified" is returned and target defaults
355  /// are expected to be used for instruction selection.
356  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
357 
358  /// Return a ReciprocalEstimate enum value for a division of the given type
359  /// based on the function's attributes. If the operation is not overridden by
360  /// the function's attributes, "Unspecified" is returned and target defaults
361  /// are expected to be used for instruction selection.
362  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
363 
364  /// Return the refinement step count for a square root of the given type based
365  /// on the function's attributes. If the operation is not overridden by
366  /// the function's attributes, "Unspecified" is returned and target defaults
367  /// are expected to be used for instruction selection.
368  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
369 
370  /// Return the refinement step count for a division of the given type based
371  /// on the function's attributes. If the operation is not overridden by
372  /// the function's attributes, "Unspecified" is returned and target defaults
373  /// are expected to be used for instruction selection.
374  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
375 
376  /// Returns true if target has indicated at least one type should be bypassed.
377  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
378 
379  /// Returns map of slow types for division or remainder with corresponding
380  /// fast types
382  return BypassSlowDivWidths;
383  }
384 
385  /// Return true if Flow Control is an expensive operation that should be
386  /// avoided.
387  bool isJumpExpensive() const { return JumpIsExpensive; }
388 
389  /// Return true if selects are only cheaper than branches if the branch is
390  /// unlikely to be predicted right.
392  return PredictableSelectIsExpensive;
393  }
394 
395  /// If a branch or a select condition is skewed in one direction by more than
396  /// this factor, it is very likely to be predicted correctly.
397  virtual BranchProbability getPredictableBranchThreshold() const;
398 
399  /// Return true if the following transform is beneficial:
400  /// fold (conv (load x)) -> (load (conv*)x)
401  /// On architectures that don't natively support some vector loads
402  /// efficiently, casting the load to a smaller vector of larger types and
403  /// loading is more efficient, however, this can be undone by optimizations in
404  /// dag combiner.
405  virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
406  const SelectionDAG &DAG,
407  const MachineMemOperand &MMO) const {
408  // Don't do if we could do an indexed load on the original type, but not on
409  // the new one.
410  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
411  return true;
412 
413  MVT LoadMVT = LoadVT.getSimpleVT();
414 
415  // Don't bother doing this if it's just going to be promoted again later, as
416  // doing so might interfere with other combines.
417  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
418  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
419  return false;
420 
421  bool Fast = false;
422  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
423  MMO, &Fast) && Fast;
424  }
425 
426  /// Return true if the following transform is beneficial:
427  /// (store (y (conv x)), y*)) -> (store x, (x*))
428  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
429  const SelectionDAG &DAG,
430  const MachineMemOperand &MMO) const {
431  // Default to the same logic as loads.
432  return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
433  }
434 
435  /// Return true if it is expected to be cheaper to do a store of a non-zero
436  /// vector constant with the given size and type for the address space than to
437  /// store the individual scalar element constants.
438  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
439  unsigned NumElem,
440  unsigned AddrSpace) const {
441  return false;
442  }
443 
444  /// Allow store merging for the specified type after legalization in addition
445  /// to before legalization. This may transform stores that do not exist
446  /// earlier (for example, stores created from intrinsics).
447  virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
448  return true;
449  }
450 
451  /// Returns if it's reasonable to merge stores to MemVT size.
452  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
453  const SelectionDAG &DAG) const {
454  return true;
455  }
456 
457  /// Return true if it is cheap to speculate a call to intrinsic cttz.
458  virtual bool isCheapToSpeculateCttz() const {
459  return false;
460  }
461 
462  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
463  virtual bool isCheapToSpeculateCtlz() const {
464  return false;
465  }
466 
467  /// Return true if ctlz instruction is fast.
468  virtual bool isCtlzFast() const {
469  return false;
470  }
471 
472  /// Return true if it is safe to transform an integer-domain bitwise operation
473  /// into the equivalent floating-point operation. This should be set to true
474  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
475  /// type.
476  virtual bool hasBitPreservingFPLogic(EVT VT) const {
477  return false;
478  }
479 
480  /// Return true if it is cheaper to split the store of a merged int val
481  /// from a pair of smaller values into multiple stores.
482  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
483  return false;
484  }
485 
486  /// Return if the target supports combining a
487  /// chain like:
488  /// \code
489  /// %andResult = and %val1, #mask
490  /// %icmpResult = icmp %andResult, 0
491  /// \endcode
492  /// into a single machine instruction of a form like:
493  /// \code
494  /// cc = test %register, #mask
495  /// \endcode
496  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
497  return false;
498  }
499 
500  /// Use bitwise logic to make pairs of compares more efficient. For example:
501  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
502  /// This should be true when it takes more than one instruction to lower
503  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
504  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
505  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
506  return false;
507  }
508 
509  /// Return the preferred operand type if the target has a quick way to compare
510  /// integer values of the given size. Assume that any legal integer type can
511  /// be compared efficiently. Targets may override this to allow illegal wide
512  /// types to return a vector type if there is support to compare that type.
513  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
514  MVT VT = MVT::getIntegerVT(NumBits);
515  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
516  }
517 
518  /// Return true if the target should transform:
519  /// (X & Y) == Y ---> (~X & Y) == 0
520  /// (X & Y) != Y ---> (~X & Y) != 0
521  ///
522  /// This may be profitable if the target has a bitwise and-not operation that
523  /// sets comparison flags. A target may want to limit the transformation based
524  /// on the type of Y or if Y is a constant.
525  ///
526  /// Note that the transform will not occur if Y is known to be a power-of-2
527  /// because a mask and compare of a single bit can be handled by inverting the
528  /// predicate, for example:
529  /// (X & 8) == 8 ---> (X & 8) != 0
530  virtual bool hasAndNotCompare(SDValue Y) const {
531  return false;
532  }
533 
534  /// Return true if the target has a bitwise and-not operation:
535  /// X = ~A & B
536  /// This can be used to simplify select or other instructions.
537  virtual bool hasAndNot(SDValue X) const {
538  // If the target has the more complex version of this operation, assume that
539  // it has this operation too.
540  return hasAndNotCompare(X);
541  }
542 
543  /// Return true if the target has a bit-test instruction:
544  /// (X & (1 << Y)) ==/!= 0
545  /// This knowledge can be used to prevent breaking the pattern,
546  /// or creating it if it could be recognized.
547  virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
548 
549  /// There are two ways to clear extreme bits (either low or high):
550  /// Mask: x & (-1 << y) (the instcombine canonical form)
551  /// Shifts: x >> y << y
552  /// Return true if the variant with 2 variable shifts is preferred.
553  /// Return false if there is no preference.
555  // By default, let's assume that no one prefers shifts.
556  return false;
557  }
558 
559  /// Return true if it is profitable to fold a pair of shifts into a mask.
560  /// This is usually true on most targets. But some targets, like Thumb1,
561  /// have immediate shift instructions, but no immediate "and" instruction;
562  /// this makes the fold unprofitable.
564  CombineLevel Level) const {
565  return true;
566  }
567 
568  /// Should we tranform the IR-optimal check for whether given truncation
569  /// down into KeptBits would be truncating or not:
570  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
571  /// Into it's more traditional form:
572  /// ((%x << C) a>> C) dstcond %x
573  /// Return true if we should transform.
574  /// Return false if there is no preference.
576  unsigned KeptBits) const {
577  // By default, let's assume that no one prefers shifts.
578  return false;
579  }
580 
581  /// Given the pattern
582  /// (X & (C l>>/<< Y)) ==/!= 0
583  /// return true if it should be transformed into:
584  /// ((X <</l>> Y) & C) ==/!= 0
585  /// WARNING: if 'X' is a constant, the fold may deadlock!
586  /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
587  /// here because it can end up being not linked in.
590  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
591  SelectionDAG &DAG) const {
592  if (hasBitTest(X, Y)) {
593  // One interesting pattern that we'd want to form is 'bit test':
594  // ((1 << Y) & C) ==/!= 0
595  // But we also need to be careful not to try to reverse that fold.
596 
597  // Is this '1 << Y' ?
598  if (OldShiftOpcode == ISD::SHL && CC->isOne())
599  return false; // Keep the 'bit test' pattern.
600 
601  // Will it be '1 << Y' after the transform ?
602  if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
603  return true; // Do form the 'bit test' pattern.
604  }
605 
606  // If 'X' is a constant, and we transform, then we will immediately
607  // try to undo the fold, thus causing endless combine loop.
608  // So by default, let's assume everyone prefers the fold
609  // iff 'X' is not a constant.
610  return !XC;
611  }
612 
613  /// These two forms are equivalent:
614  /// sub %y, (xor %x, -1)
615  /// add (add %x, 1), %y
616  /// The variant with two add's is IR-canonical.
617  /// Some targets may prefer one to the other.
618  virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
619  // By default, let's assume that everyone prefers the form with two add's.
620  return true;
621  }
622 
623  /// Return true if the target wants to use the optimization that
624  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
625  /// promotedInst1(...(promotedInstN(ext(load)))).
626  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
627 
628  /// Return true if the target can combine store(extractelement VectorTy,
629  /// Idx).
630  /// \p Cost[out] gives the cost of that transformation when this is true.
631  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
632  unsigned &Cost) const {
633  return false;
634  }
635 
636  /// Return true if inserting a scalar into a variable element of an undef
637  /// vector is more efficiently handled by splatting the scalar instead.
638  virtual bool shouldSplatInsEltVarIndex(EVT) const {
639  return false;
640  }
641 
642  /// Return true if target always beneficiates from combining into FMA for a
643  /// given value type. This must typically return false on targets where FMA
644  /// takes more cycles to execute than FADD.
645  virtual bool enableAggressiveFMAFusion(EVT VT) const {
646  return false;
647  }
648 
649  /// Return the ValueType of the result of SETCC operations.
650  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
651  EVT VT) const;
652 
653  /// Return the ValueType for comparison libcalls. Comparions libcalls include
654  /// floating point comparion calls, and Ordered/Unordered check calls on
655  /// floating point numbers.
656  virtual
657  MVT::SimpleValueType getCmpLibcallReturnType() const;
658 
659  /// For targets without i1 registers, this gives the nature of the high-bits
660  /// of boolean values held in types wider than i1.
661  ///
662  /// "Boolean values" are special true/false values produced by nodes like
663  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
664  /// Not to be confused with general values promoted from i1. Some cpus
665  /// distinguish between vectors of boolean and scalars; the isVec parameter
666  /// selects between the two kinds. For example on X86 a scalar boolean should
667  /// be zero extended from i1, while the elements of a vector of booleans
668  /// should be sign extended from i1.
669  ///
670  /// Some cpus also treat floating point types the same way as they treat
671  /// vectors instead of the way they treat scalars.
672  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
673  if (isVec)
674  return BooleanVectorContents;
675  return isFloat ? BooleanFloatContents : BooleanContents;
676  }
677 
679  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
680  }
681 
682  /// Return target scheduling preference.
684  return SchedPreferenceInfo;
685  }
686 
687  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
688  /// for different nodes. This function returns the preference (or none) for
689  /// the given node.
691  return Sched::None;
692  }
693 
694  /// Return the register class that should be used for the specified value
695  /// type.
696  virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
697  (void)isDivergent;
698  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
699  assert(RC && "This value type is not natively supported!");
700  return RC;
701  }
702 
703  /// Allows target to decide about the register class of the
704  /// specific value that is live outside the defining block.
705  /// Returns true if the value needs uniform register class.
707  const Value *) const {
708  return false;
709  }
710 
711  /// Return the 'representative' register class for the specified value
712  /// type.
713  ///
714  /// The 'representative' register class is the largest legal super-reg
715  /// register class for the register class of the value type. For example, on
716  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
717  /// register class is GR64 on x86_64.
718  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
719  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
720  return RC;
721  }
722 
723  /// Return the cost of the 'representative' register class for the specified
724  /// value type.
725  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
726  return RepRegClassCostForVT[VT.SimpleTy];
727  }
728 
729  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
730  /// instructions, and false if a library call is preferred (e.g for code-size
731  /// reasons).
732  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
733  return true;
734  }
735 
736  /// Return true if the target has native support for the specified value type.
737  /// This means that it has a register that directly holds it without
738  /// promotions or expansions.
739  bool isTypeLegal(EVT VT) const {
740  assert(!VT.isSimple() ||
741  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
742  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
743  }
744 
746  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
747  /// that indicates how instruction selection should deal with the type.
748  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
749 
750  public:
752  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
753  TypeLegal);
754  }
755 
757  return ValueTypeActions[VT.SimpleTy];
758  }
759 
761  ValueTypeActions[VT.SimpleTy] = Action;
762  }
763  };
764 
766  return ValueTypeActions;
767  }
768 
769  /// Return how we should legalize values of this type, either it is already
770  /// legal (return 'Legal') or we need to promote it to a larger type (return
771  /// 'Promote'), or we need to expand it into multiple registers of smaller
772  /// integer type (return 'Expand'). 'Custom' is not an option.
774  return getTypeConversion(Context, VT).first;
775  }
777  return ValueTypeActions.getTypeAction(VT);
778  }
779 
780  /// For types supported by the target, this is an identity function. For
781  /// types that must be promoted to larger types, this returns the larger type
782  /// to promote to. For integer types that are larger than the largest integer
783  /// register, this contains one step in the expansion to get to the smaller
784  /// register. For illegal floating point types, this returns the integer type
785  /// to transform to.
786  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
787  return getTypeConversion(Context, VT).second;
788  }
789 
790  /// For types supported by the target, this is an identity function. For
791  /// types that must be expanded (i.e. integer types that are larger than the
792  /// largest integer register or illegal floating point types), this returns
793  /// the largest legal type it will be expanded to.
794  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
795  assert(!VT.isVector());
796  while (true) {
797  switch (getTypeAction(Context, VT)) {
798  case TypeLegal:
799  return VT;
800  case TypeExpandInteger:
801  VT = getTypeToTransformTo(Context, VT);
802  break;
803  default:
804  llvm_unreachable("Type is not legal nor is it to be expanded!");
805  }
806  }
807  }
808 
809  /// Vector types are broken down into some number of legal first class types.
810  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
811  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
812  /// turns into 4 EVT::i32 values with both PPC and X86.
813  ///
814  /// This method returns the number of registers needed, and the VT for each
815  /// register. It also returns the VT and quantity of the intermediate values
816  /// before they are promoted/expanded.
817  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
818  EVT &IntermediateVT,
819  unsigned &NumIntermediates,
820  MVT &RegisterVT) const;
821 
822  /// Certain targets such as MIPS require that some types such as vectors are
823  /// always broken down into scalars in some contexts. This occurs even if the
824  /// vector type is legal.
826  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
827  unsigned &NumIntermediates, MVT &RegisterVT) const {
828  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
829  RegisterVT);
830  }
831 
832  struct IntrinsicInfo {
833  unsigned opc = 0; // target opcode
834  EVT memVT; // memory VT
835 
836  // value representing memory location
838 
839  int offset = 0; // offset off of ptrVal
840  uint64_t size = 0; // the size of the memory location
841  // (taken from memVT if zero)
842  MaybeAlign align = Align::None(); // alignment
843 
845  IntrinsicInfo() = default;
846  };
847 
848  /// Given an intrinsic, checks if on the target the intrinsic will need to map
849  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
850  /// true and store the intrinsic information into the IntrinsicInfo that was
851  /// passed to the function.
852  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
853  MachineFunction &,
854  unsigned /*Intrinsic*/) const {
855  return false;
856  }
857 
858  /// Returns true if the target can instruction select the specified FP
859  /// immediate natively. If false, the legalizer will materialize the FP
860  /// immediate as a load from a constant pool.
861  virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
862  bool ForCodeSize = false) const {
863  return false;
864  }
865 
866  /// Targets can use this to indicate that they only support *some*
867  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
868  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
869  /// legal.
870  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
871  return true;
872  }
873 
874  /// Returns true if the operation can trap for the value type.
875  ///
876  /// VT must be a legal type. By default, we optimistically assume most
877  /// operations don't trap except for integer divide and remainder.
878  virtual bool canOpTrap(unsigned Op, EVT VT) const;
879 
880  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
881  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
882  /// constant pool entry.
883  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
884  EVT /*VT*/) const {
885  return false;
886  }
887 
888  /// Return how this operation should be treated: either it is legal, needs to
889  /// be promoted to a larger size, needs to be expanded to some other code
890  /// sequence, or the target has a custom expander for it.
891  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
892  if (VT.isExtended()) return Expand;
893  // If a target-specific SDNode requires legalization, require the target
894  // to provide custom legalization for it.
895  if (Op >= array_lengthof(OpActions[0])) return Custom;
896  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
897  }
898 
899  /// Custom method defined by each target to indicate if an operation which
900  /// may require a scale is supported natively by the target.
901  /// If not, the operation is illegal.
902  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
903  unsigned Scale) const {
904  return false;
905  }
906 
907  /// Some fixed point operations may be natively supported by the target but
908  /// only for specific scales. This method allows for checking
909  /// if the width is supported by the target for a given operation that may
910  /// depend on scale.
912  unsigned Scale) const {
913  auto Action = getOperationAction(Op, VT);
914  if (Action != Legal)
915  return Action;
916 
917  // This operation is supported in this type but may only work on specific
918  // scales.
919  bool Supported;
920  switch (Op) {
921  default:
922  llvm_unreachable("Unexpected fixed point operation.");
923  case ISD::SMULFIX:
924  case ISD::SMULFIXSAT:
925  case ISD::UMULFIX:
926  case ISD::UMULFIXSAT:
927  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
928  break;
929  }
930 
931  return Supported ? Action : Expand;
932  }
933 
934  // If Op is a strict floating-point operation, return the result
935  // of getOperationAction for the equivalent non-strict operation.
937  unsigned EqOpc;
938  switch (Op) {
939  default: llvm_unreachable("Unexpected FP pseudo-opcode");
940  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
941  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
942  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
943  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
944  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
945  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
946  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
947  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
948  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
949  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
950  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
951  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
952  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
953  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
954  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
955  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
956  case ISD::STRICT_LRINT: EqOpc = ISD::LRINT; break;
957  case ISD::STRICT_LLRINT: EqOpc = ISD::LLRINT; break;
958  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
959  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
960  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
961  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
962  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
963  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
964  case ISD::STRICT_LROUND: EqOpc = ISD::LROUND; break;
965  case ISD::STRICT_LLROUND: EqOpc = ISD::LLROUND; break;
966  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
967  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
968  case ISD::STRICT_FP_TO_SINT: EqOpc = ISD::FP_TO_SINT; break;
969  case ISD::STRICT_FP_TO_UINT: EqOpc = ISD::FP_TO_UINT; break;
970  case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
971  case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
972  }
973 
974  return getOperationAction(EqOpc, VT);
975  }
976 
977  /// Return true if the specified operation is legal on this target or can be
978  /// made legal with custom lowering. This is used to help guide high-level
979  /// lowering decisions.
980  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
981  return (VT == MVT::Other || isTypeLegal(VT)) &&
982  (getOperationAction(Op, VT) == Legal ||
983  getOperationAction(Op, VT) == Custom);
984  }
985 
986  /// Return true if the specified operation is legal on this target or can be
987  /// made legal using promotion. This is used to help guide high-level lowering
988  /// decisions.
989  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
990  return (VT == MVT::Other || isTypeLegal(VT)) &&
991  (getOperationAction(Op, VT) == Legal ||
992  getOperationAction(Op, VT) == Promote);
993  }
994 
995  /// Return true if the specified operation is legal on this target or can be
996  /// made legal with custom lowering or using promotion. This is used to help
997  /// guide high-level lowering decisions.
998  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
999  return (VT == MVT::Other || isTypeLegal(VT)) &&
1000  (getOperationAction(Op, VT) == Legal ||
1001  getOperationAction(Op, VT) == Custom ||
1002  getOperationAction(Op, VT) == Promote);
1003  }
1004 
1005  /// Return true if the operation uses custom lowering, regardless of whether
1006  /// the type is legal or not.
1007  bool isOperationCustom(unsigned Op, EVT VT) const {
1008  return getOperationAction(Op, VT) == Custom;
1009  }
1010 
1011  /// Return true if lowering to a jump table is allowed.
1012  virtual bool areJTsAllowed(const Function *Fn) const {
1013  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1014  return false;
1015 
1016  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1017  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
1018  }
1019 
1020  /// Check whether the range [Low,High] fits in a machine word.
1021  bool rangeFitsInWord(const APInt &Low, const APInt &High,
1022  const DataLayout &DL) const {
1023  // FIXME: Using the pointer type doesn't seem ideal.
1024  uint64_t BW = DL.getIndexSizeInBits(0u);
1025  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
1026  return Range <= BW;
1027  }
1028 
1029  /// Return true if lowering to a jump table is suitable for a set of case
1030  /// clusters which may contain \p NumCases cases, \p Range range of values.
1031  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1032  uint64_t Range) const {
1033  // FIXME: This function check the maximum table size and density, but the
1034  // minimum size is not checked. It would be nice if the minimum size is
1035  // also combined within this function. Currently, the minimum size check is
1036  // performed in findJumpTable() in SelectionDAGBuiler and
1037  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1038  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
1039  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1040  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1041 
1042  // Check whether the number of cases is small enough and
1043  // the range is dense enough for a jump table.
1044  if ((OptForSize || Range <= MaxJumpTableSize) &&
1045  (NumCases * 100 >= Range * MinDensity)) {
1046  return true;
1047  }
1048  return false;
1049  }
1050 
1051  /// Return true if lowering to a bit test is suitable for a set of case
1052  /// clusters which contains \p NumDests unique destinations, \p Low and
1053  /// \p High as its lowest and highest case values, and expects \p NumCmps
1054  /// case value comparisons. Check if the number of destinations, comparison
1055  /// metric, and range are all suitable.
1056  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1057  const APInt &Low, const APInt &High,
1058  const DataLayout &DL) const {
1059  // FIXME: I don't think NumCmps is the correct metric: a single case and a
1060  // range of cases both require only one branch to lower. Just looking at the
1061  // number of clusters and destinations should be enough to decide whether to
1062  // build bit tests.
1063 
1064  // To lower a range with bit tests, the range must fit the bitwidth of a
1065  // machine word.
1066  if (!rangeFitsInWord(Low, High, DL))
1067  return false;
1068 
1069  // Decide whether it's profitable to lower this range with bit tests. Each
1070  // destination requires a bit test and branch, and there is an overall range
1071  // check branch. For a small number of clusters, separate comparisons might
1072  // be cheaper, and for many destinations, splitting the range might be
1073  // better.
1074  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1075  (NumDests == 3 && NumCmps >= 6);
1076  }
1077 
1078  /// Return true if the specified operation is illegal on this target or
1079  /// unlikely to be made legal with custom lowering. This is used to help guide
1080  /// high-level lowering decisions.
1081  bool isOperationExpand(unsigned Op, EVT VT) const {
1082  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1083  }
1084 
1085  /// Return true if the specified operation is legal on this target.
1086  bool isOperationLegal(unsigned Op, EVT VT) const {
1087  return (VT == MVT::Other || isTypeLegal(VT)) &&
1088  getOperationAction(Op, VT) == Legal;
1089  }
1090 
1091  /// Return how this load with extension should be treated: either it is legal,
1092  /// needs to be promoted to a larger size, needs to be expanded to some other
1093  /// code sequence, or the target has a custom expander for it.
1095  EVT MemVT) const {
1096  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1097  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1098  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1099  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1100  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1101  unsigned Shift = 4 * ExtType;
1102  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1103  }
1104 
1105  /// Return true if the specified load with extension is legal on this target.
1106  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1107  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1108  }
1109 
1110  /// Return true if the specified load with extension is legal or custom
1111  /// on this target.
1112  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1113  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1114  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1115  }
1116 
1117  /// Return how this store with truncation should be treated: either it is
1118  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1119  /// other code sequence, or the target has a custom expander for it.
1121  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1122  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1123  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1124  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1125  "Table isn't big enough!");
1126  return TruncStoreActions[ValI][MemI];
1127  }
1128 
1129  /// Return true if the specified store with truncation is legal on this
1130  /// target.
1131  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1132  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1133  }
1134 
1135  /// Return true if the specified store with truncation has solution on this
1136  /// target.
1137  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1138  return isTypeLegal(ValVT) &&
1139  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1140  getTruncStoreAction(ValVT, MemVT) == Custom);
1141  }
1142 
1143  /// Return how the indexed load should be treated: either it is legal, needs
1144  /// to be promoted to a larger size, needs to be expanded to some other code
1145  /// sequence, or the target has a custom expander for it.
1147  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1148  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1149  "Table isn't big enough!");
1150  unsigned Ty = (unsigned)VT.SimpleTy;
1151  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1152  }
1153 
1154  /// Return true if the specified indexed load is legal on this target.
1155  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1156  return VT.isSimple() &&
1157  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1158  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1159  }
1160 
1161  /// Return how the indexed store should be treated: either it is legal, needs
1162  /// to be promoted to a larger size, needs to be expanded to some other code
1163  /// sequence, or the target has a custom expander for it.
1165  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1166  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1167  "Table isn't big enough!");
1168  unsigned Ty = (unsigned)VT.SimpleTy;
1169  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1170  }
1171 
1172  /// Return true if the specified indexed load is legal on this target.
1173  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1174  return VT.isSimple() &&
1175  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1176  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1177  }
1178 
1179  /// Return how the condition code should be treated: either it is legal, needs
1180  /// to be expanded to some other code sequence, or the target has a custom
1181  /// expander for it.
1184  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1185  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1186  "Table isn't big enough!");
1187  // See setCondCodeAction for how this is encoded.
1188  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1189  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1190  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1191  assert(Action != Promote && "Can't promote condition code!");
1192  return Action;
1193  }
1194 
1195  /// Return true if the specified condition code is legal on this target.
1196  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1197  return getCondCodeAction(CC, VT) == Legal;
1198  }
1199 
1200  /// Return true if the specified condition code is legal or custom on this
1201  /// target.
1203  return getCondCodeAction(CC, VT) == Legal ||
1204  getCondCodeAction(CC, VT) == Custom;
1205  }
1206 
1207  /// If the action for this operation is to promote, this method returns the
1208  /// ValueType to promote to.
1209  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1210  assert(getOperationAction(Op, VT) == Promote &&
1211  "This operation isn't promoted!");
1212 
1213  // See if this has an explicit type specified.
1214  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1216  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1217  if (PTTI != PromoteToType.end()) return PTTI->second;
1218 
1219  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1220  "Cannot autopromote this type, add it with AddPromotedToType.");
1221 
1222  MVT NVT = VT;
1223  do {
1224  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1225  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1226  "Didn't find type to promote to!");
1227  } while (!isTypeLegal(NVT) ||
1228  getOperationAction(Op, NVT) == Promote);
1229  return NVT;
1230  }
1231 
1232  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1233  /// operations except for the pointer size. If AllowUnknown is true, this
1234  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1235  /// otherwise it will assert.
1237  bool AllowUnknown = false) const {
1238  // Lower scalar pointers to native pointer types.
1239  if (auto *PTy = dyn_cast<PointerType>(Ty))
1240  return getPointerTy(DL, PTy->getAddressSpace());
1241 
1242  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1243  Type *EltTy = VTy->getElementType();
1244  // Lower vectors of pointers to native pointer types.
1245  if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1246  EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1247  EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1248  }
1249  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1250  VTy->getElementCount());
1251  }
1252 
1253  return EVT::getEVT(Ty, AllowUnknown);
1254  }
1255 
1257  bool AllowUnknown = false) const {
1258  // Lower scalar pointers to native pointer types.
1259  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1260  return getPointerMemTy(DL, PTy->getAddressSpace());
1261  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262  Type *Elm = VTy->getElementType();
1263  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1264  EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1265  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1266  }
1267  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1268  VTy->getNumElements());
1269  }
1270 
1271  return getValueType(DL, Ty, AllowUnknown);
1272  }
1273 
1274 
1275  /// Return the MVT corresponding to this LLVM type. See getValueType.
1277  bool AllowUnknown = false) const {
1278  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1279  }
1280 
1281  /// Return the desired alignment for ByVal or InAlloca aggregate function
1282  /// arguments in the caller parameter area. This is the actual alignment, not
1283  /// its logarithm.
1284  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1285 
1286  /// Return the type of registers that this ValueType will eventually require.
1288  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1289  return RegisterTypeForVT[VT.SimpleTy];
1290  }
1291 
1292  /// Return the type of registers that this ValueType will eventually require.
1293  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1294  if (VT.isSimple()) {
1295  assert((unsigned)VT.getSimpleVT().SimpleTy <
1296  array_lengthof(RegisterTypeForVT));
1297  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1298  }
1299  if (VT.isVector()) {
1300  EVT VT1;
1301  MVT RegisterVT;
1302  unsigned NumIntermediates;
1303  (void)getVectorTypeBreakdown(Context, VT, VT1,
1304  NumIntermediates, RegisterVT);
1305  return RegisterVT;
1306  }
1307  if (VT.isInteger()) {
1308  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1309  }
1310  llvm_unreachable("Unsupported extended type!");
1311  }
1312 
1313  /// Return the number of registers that this ValueType will eventually
1314  /// require.
1315  ///
1316  /// This is one for any types promoted to live in larger registers, but may be
1317  /// more than one for types (like i64) that are split into pieces. For types
1318  /// like i140, which are first promoted then expanded, it is the number of
1319  /// registers needed to hold all the bits of the original type. For an i140
1320  /// on a 32 bit machine this means 5 registers.
1321  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1322  if (VT.isSimple()) {
1323  assert((unsigned)VT.getSimpleVT().SimpleTy <
1324  array_lengthof(NumRegistersForVT));
1325  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1326  }
1327  if (VT.isVector()) {
1328  EVT VT1;
1329  MVT VT2;
1330  unsigned NumIntermediates;
1331  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1332  }
1333  if (VT.isInteger()) {
1334  unsigned BitWidth = VT.getSizeInBits();
1335  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1336  return (BitWidth + RegWidth - 1) / RegWidth;
1337  }
1338  llvm_unreachable("Unsupported extended type!");
1339  }
1340 
1341  /// Certain combinations of ABIs, Targets and features require that types
1342  /// are legal for some operations and not for other operations.
1343  /// For MIPS all vector types must be passed through the integer register set.
1345  CallingConv::ID CC, EVT VT) const {
1346  return getRegisterType(Context, VT);
1347  }
1348 
1349  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1350  /// this occurs when a vector type is used, as vector are passed through the
1351  /// integer register set.
1352  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1353  CallingConv::ID CC,
1354  EVT VT) const {
1355  return getNumRegisters(Context, VT);
1356  }
1357 
1358  /// Certain targets have context senstive alignment requirements, where one
1359  /// type has the alignment requirement of another type.
1360  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1361  DataLayout DL) const {
1362  return DL.getABITypeAlignment(ArgTy);
1363  }
1364 
1365  /// If true, then instruction selection should seek to shrink the FP constant
1366  /// of the specified type to a smaller type in order to save space and / or
1367  /// reduce runtime.
1368  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1369 
1370  /// Return true if it is profitable to reduce a load to a smaller type.
1371  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1373  EVT NewVT) const {
1374  // By default, assume that it is cheaper to extract a subvector from a wide
1375  // vector load rather than creating multiple narrow vector loads.
1376  if (NewVT.isVector() && !Load->hasOneUse())
1377  return false;
1378 
1379  return true;
1380  }
1381 
1382  /// When splitting a value of the specified type into parts, does the Lo
1383  /// or Hi part come first? This usually follows the endianness, except
1384  /// for ppcf128, where the Hi part always comes first.
1385  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1386  return DL.isBigEndian() || VT == MVT::ppcf128;
1387  }
1388 
1389  /// If true, the target has custom DAG combine transformations that it can
1390  /// perform for the specified node.
1392  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1393  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1394  }
1395 
1396  unsigned getGatherAllAliasesMaxDepth() const {
1397  return GatherAllAliasesMaxDepth;
1398  }
1399 
1400  /// Returns the size of the platform's va_list object.
1401  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1402  return getPointerTy(DL).getSizeInBits();
1403  }
1404 
1405  /// Get maximum # of store operations permitted for llvm.memset
1406  ///
1407  /// This function returns the maximum number of store operations permitted
1408  /// to replace a call to llvm.memset. The value is set by the target at the
1409  /// performance threshold for such a replacement. If OptSize is true,
1410  /// return the limit for functions that have OptSize attribute.
1411  unsigned getMaxStoresPerMemset(bool OptSize) const {
1412  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1413  }
1414 
1415  /// Get maximum # of store operations permitted for llvm.memcpy
1416  ///
1417  /// This function returns the maximum number of store operations permitted
1418  /// to replace a call to llvm.memcpy. The value is set by the target at the
1419  /// performance threshold for such a replacement. If OptSize is true,
1420  /// return the limit for functions that have OptSize attribute.
1421  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1422  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1423  }
1424 
1425  /// \brief Get maximum # of store operations to be glued together
1426  ///
1427  /// This function returns the maximum number of store operations permitted
1428  /// to glue together during lowering of llvm.memcpy. The value is set by
1429  // the target at the performance threshold for such a replacement.
1430  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1431  return MaxGluedStoresPerMemcpy;
1432  }
1433 
1434  /// Get maximum # of load operations permitted for memcmp
1435  ///
1436  /// This function returns the maximum number of load operations permitted
1437  /// to replace a call to memcmp. The value is set by the target at the
1438  /// performance threshold for such a replacement. If OptSize is true,
1439  /// return the limit for functions that have OptSize attribute.
1440  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1441  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1442  }
1443 
1444  /// Get maximum # of store operations permitted for llvm.memmove
1445  ///
1446  /// This function returns the maximum number of store operations permitted
1447  /// to replace a call to llvm.memmove. The value is set by the target at the
1448  /// performance threshold for such a replacement. If OptSize is true,
1449  /// return the limit for functions that have OptSize attribute.
1450  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1451  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1452  }
1453 
1454  /// Determine if the target supports unaligned memory accesses.
1455  ///
1456  /// This function returns true if the target allows unaligned memory accesses
1457  /// of the specified type in the given address space. If true, it also returns
1458  /// whether the unaligned memory access is "fast" in the last argument by
1459  /// reference. This is used, for example, in situations where an array
1460  /// copy/move/set is converted to a sequence of store operations. Its use
1461  /// helps to ensure that such replacements don't generate code that causes an
1462  /// alignment error (trap) on the target machine.
1464  EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1466  bool * /*Fast*/ = nullptr) const {
1467  return false;
1468  }
1469 
1470  /// LLT handling variant.
1472  LLT, unsigned AddrSpace = 0, unsigned Align = 1,
1474  bool * /*Fast*/ = nullptr) const {
1475  return false;
1476  }
1477 
1478  /// This function returns true if the memory access is aligned or if the
1479  /// target allows this specific unaligned memory access. If the access is
1480  /// allowed, the optional final parameter returns if the access is also fast
1481  /// (as defined by the target).
1482  bool allowsMemoryAccessForAlignment(
1483  LLVMContext &Context, const DataLayout &DL, EVT VT,
1484  unsigned AddrSpace = 0, unsigned Alignment = 1,
1486  bool *Fast = nullptr) const;
1487 
1488  /// Return true if the memory access of this type is aligned or if the target
1489  /// allows this specific unaligned access for the given MachineMemOperand.
1490  /// If the access is allowed, the optional final parameter returns if the
1491  /// access is also fast (as defined by the target).
1492  bool allowsMemoryAccessForAlignment(LLVMContext &Context,
1493  const DataLayout &DL, EVT VT,
1494  const MachineMemOperand &MMO,
1495  bool *Fast = nullptr) const;
1496 
1497  /// Return true if the target supports a memory access of this type for the
1498  /// given address space and alignment. If the access is allowed, the optional
1499  /// final parameter returns if the access is also fast (as defined by the
1500  /// target).
1501  virtual bool
1502  allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1503  unsigned AddrSpace = 0, unsigned Alignment = 1,
1505  bool *Fast = nullptr) const;
1506 
1507  /// Return true if the target supports a memory access of this type for the
1508  /// given MachineMemOperand. If the access is allowed, the optional
1509  /// final parameter returns if the access is also fast (as defined by the
1510  /// target).
1511  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1512  const MachineMemOperand &MMO,
1513  bool *Fast = nullptr) const;
1514 
1515  /// Returns the target specific optimal type for load and store operations as
1516  /// a result of memset, memcpy, and memmove lowering.
1517  ///
1518  /// If DstAlign is zero that means it's safe to destination alignment can
1519  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1520  /// a need to check it against alignment requirement, probably because the
1521  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1522  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1523  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1524  /// does not need to be loaded. It returns EVT::Other if the type should be
1525  /// determined using generic target-independent logic.
1526  virtual EVT
1527  getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1528  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1529  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1530  const AttributeList & /*FuncAttributes*/) const {
1531  return MVT::Other;
1532  }
1533 
1534 
1535  /// LLT returning variant.
1536  virtual LLT
1537  getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1538  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1539  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1540  const AttributeList & /*FuncAttributes*/) const {
1541  return LLT();
1542  }
1543 
1544  /// Returns true if it's safe to use load / store of the specified type to
1545  /// expand memcpy / memset inline.
1546  ///
1547  /// This is mostly true for all types except for some special cases. For
1548  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1549  /// fstpl which also does type conversion. Note the specified type doesn't
1550  /// have to be legal as the hook is used before type legalization.
1551  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1552 
1553  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1554  bool usesUnderscoreSetJmp() const {
1555  return UseUnderscoreSetJmp;
1556  }
1557 
1558  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1559  bool usesUnderscoreLongJmp() const {
1560  return UseUnderscoreLongJmp;
1561  }
1562 
1563  /// Return lower limit for number of blocks in a jump table.
1564  virtual unsigned getMinimumJumpTableEntries() const;
1565 
1566  /// Return lower limit of the density in a jump table.
1567  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1568 
1569  /// Return upper limit for number of entries in a jump table.
1570  /// Zero if no limit.
1571  unsigned getMaximumJumpTableSize() const;
1572 
1573  virtual bool isJumpTableRelative() const {
1574  return TM.isPositionIndependent();
1575  }
1576 
1577  /// If a physical register, this specifies the register that
1578  /// llvm.savestack/llvm.restorestack should save and restore.
1580  return StackPointerRegisterToSaveRestore;
1581  }
1582 
1583  /// If a physical register, this returns the register that receives the
1584  /// exception address on entry to an EH pad.
1585  virtual unsigned
1586  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1587  // 0 is guaranteed to be the NoRegister value on all targets
1588  return 0;
1589  }
1590 
1591  /// If a physical register, this returns the register that receives the
1592  /// exception typeid on entry to a landing pad.
1593  virtual unsigned
1594  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1595  // 0 is guaranteed to be the NoRegister value on all targets
1596  return 0;
1597  }
1598 
1599  virtual bool needsFixedCatchObjects() const {
1600  report_fatal_error("Funclet EH is not implemented for this target");
1601  }
1602 
1603  /// Return the minimum stack alignment of an argument.
1605  return MinStackArgumentAlignment;
1606  }
1607 
1608  /// Return the minimum function alignment.
1609  Align getMinFunctionAlignment() const { return MinFunctionAlignment; }
1610 
1611  /// Return the preferred function alignment.
1612  Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
1613 
1614  /// Return the preferred loop alignment.
1615  virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1616  return PrefLoopAlignment;
1617  }
1618 
1619  /// Should loops be aligned even when the function is marked OptSize (but not
1620  /// MinSize).
1621  virtual bool alignLoopsWithOptSize() const {
1622  return false;
1623  }
1624 
1625  /// If the target has a standard location for the stack protector guard,
1626  /// returns the address of that location. Otherwise, returns nullptr.
1627  /// DEPRECATED: please override useLoadStackGuardNode and customize
1628  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1629  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1630 
1631  /// Inserts necessary declarations for SSP (stack protection) purpose.
1632  /// Should be used only when getIRStackGuard returns nullptr.
1633  virtual void insertSSPDeclarations(Module &M) const;
1634 
1635  /// Return the variable that's previously inserted by insertSSPDeclarations,
1636  /// if any, otherwise return nullptr. Should be used only when
1637  /// getIRStackGuard returns nullptr.
1638  virtual Value *getSDagStackGuard(const Module &M) const;
1639 
1640  /// If this function returns true, stack protection checks should XOR the
1641  /// frame pointer (or whichever pointer is used to address locals) into the
1642  /// stack guard value before checking it. getIRStackGuard must return nullptr
1643  /// if this returns true.
1644  virtual bool useStackGuardXorFP() const { return false; }
1645 
1646  /// If the target has a standard stack protection check function that
1647  /// performs validation and error handling, returns the function. Otherwise,
1648  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1649  /// Should be used only when getIRStackGuard returns nullptr.
1650  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1651 
1652 protected:
1653  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1654  bool UseTLS) const;
1655 
1656 public:
1657  /// Returns the target-specific address of the unsafe stack pointer.
1658  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1659 
1660  /// Returns the name of the symbol used to emit stack probes or the empty
1661  /// string if not applicable.
1663  return "";
1664  }
1665 
1666  /// Returns true if a cast between SrcAS and DestAS is a noop.
1667  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1668  return false;
1669  }
1670 
1671  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1672  /// are happy to sink it into basic blocks. A cast may be free, but not
1673  /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1674  virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1675  return isNoopAddrSpaceCast(SrcAS, DestAS);
1676  }
1677 
1678  /// Return true if the pointer arguments to CI should be aligned by aligning
1679  /// the object whose address is being passed. If so then MinSize is set to the
1680  /// minimum size the object must be to be aligned and PrefAlign is set to the
1681  /// preferred alignment.
1682  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1683  unsigned & /*PrefAlign*/) const {
1684  return false;
1685  }
1686 
1687  //===--------------------------------------------------------------------===//
1688  /// \name Helpers for TargetTransformInfo implementations
1689  /// @{
1690 
1691  /// Get the ISD node that corresponds to the Instruction class opcode.
1692  int InstructionOpcodeToISD(unsigned Opcode) const;
1693 
1694  /// Estimate the cost of type-legalization and the legalized type.
1695  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1696  Type *Ty) const;
1697 
1698  /// @}
1699 
1700  //===--------------------------------------------------------------------===//
1701  /// \name Helpers for atomic expansion.
1702  /// @{
1703 
1704  /// Returns the maximum atomic operation size (in bits) supported by
1705  /// the backend. Atomic operations greater than this size (as well
1706  /// as ones that are not naturally aligned), will be expanded by
1707  /// AtomicExpandPass into an __atomic_* library call.
1709  return MaxAtomicSizeInBitsSupported;
1710  }
1711 
1712  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1713  /// the backend supports. Any smaller operations are widened in
1714  /// AtomicExpandPass.
1715  ///
1716  /// Note that *unlike* operations above the maximum size, atomic ops
1717  /// are still natively supported below the minimum; they just
1718  /// require a more complex expansion.
1719  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1720 
1721  /// Whether the target supports unaligned atomic operations.
1722  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1723 
1724  /// Whether AtomicExpandPass should automatically insert fences and reduce
1725  /// ordering for this atomic. This should be true for most architectures with
1726  /// weak memory ordering. Defaults to false.
1727  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1728  return false;
1729  }
1730 
1731  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1732  /// corresponding pointee type. This may entail some non-trivial operations to
1733  /// truncate or reconstruct types that will be illegal in the backend. See
1734  /// ARMISelLowering for an example implementation.
1735  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1736  AtomicOrdering Ord) const {
1737  llvm_unreachable("Load linked unimplemented on this target");
1738  }
1739 
1740  /// Perform a store-conditional operation to Addr. Return the status of the
1741  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1742  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1743  Value *Addr, AtomicOrdering Ord) const {
1744  llvm_unreachable("Store conditional unimplemented on this target");
1745  }
1746 
1747  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1748  /// represents the core LL/SC loop which will be lowered at a late stage by
1749  /// the backend.
1751  AtomicRMWInst *AI,
1752  Value *AlignedAddr, Value *Incr,
1753  Value *Mask, Value *ShiftAmt,
1754  AtomicOrdering Ord) const {
1755  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1756  }
1757 
1758  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1759  /// represents the core LL/SC loop which will be lowered at a late stage by
1760  /// the backend.
1762  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1763  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1764  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1765  }
1766 
1767  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1768  /// It is called by AtomicExpandPass before expanding an
1769  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1770  /// if shouldInsertFencesForAtomic returns true.
1771  ///
1772  /// Inst is the original atomic instruction, prior to other expansions that
1773  /// may be performed.
1774  ///
1775  /// This function should either return a nullptr, or a pointer to an IR-level
1776  /// Instruction*. Even complex fence sequences can be represented by a
1777  /// single Instruction* through an intrinsic to be lowered later.
1778  /// Backends should override this method to produce target-specific intrinsic
1779  /// for their fences.
1780  /// FIXME: Please note that the default implementation here in terms of
1781  /// IR-level fences exists for historical/compatibility reasons and is
1782  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1783  /// consistency. For example, consider the following example:
1784  /// atomic<int> x = y = 0;
1785  /// int r1, r2, r3, r4;
1786  /// Thread 0:
1787  /// x.store(1);
1788  /// Thread 1:
1789  /// y.store(1);
1790  /// Thread 2:
1791  /// r1 = x.load();
1792  /// r2 = y.load();
1793  /// Thread 3:
1794  /// r3 = y.load();
1795  /// r4 = x.load();
1796  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1797  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1798  /// IR-level fences can prevent it.
1799  /// @{
1801  AtomicOrdering Ord) const {
1802  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1803  return Builder.CreateFence(Ord);
1804  else
1805  return nullptr;
1806  }
1807 
1809  Instruction *Inst,
1810  AtomicOrdering Ord) const {
1811  if (isAcquireOrStronger(Ord))
1812  return Builder.CreateFence(Ord);
1813  else
1814  return nullptr;
1815  }
1816  /// @}
1817 
1818  // Emits code that executes when the comparison result in the ll/sc
1819  // expansion of a cmpxchg instruction is such that the store-conditional will
1820  // not execute. This makes it possible to balance out the load-linked with
1821  // a dedicated instruction, if desired.
1822  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1823  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1824  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1825 
1826  /// Returns true if the given (atomic) store should be expanded by the
1827  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1829  return false;
1830  }
1831 
1832  /// Returns true if arguments should be sign-extended in lib calls.
1833  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1834  return IsSigned;
1835  }
1836 
1837  /// Returns true if arguments should be extended in lib calls.
1838  virtual bool shouldExtendTypeInLibCall(EVT Type) const {
1839  return true;
1840  }
1841 
1842  /// Returns how the given (atomic) load should be expanded by the
1843  /// IR-level AtomicExpand pass.
1846  }
1847 
1848  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1849  /// AtomicExpand pass.
1850  virtual AtomicExpansionKind
1853  }
1854 
1855  /// Returns how the IR-level AtomicExpand pass should expand the given
1856  /// AtomicRMW, if at all. Default is to never expand.
1858  return RMW->isFloatingPointOperation() ?
1859  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1860  }
1861 
1862  /// On some platforms, an AtomicRMW that never actually modifies the value
1863  /// (such as fetch_add of 0) can be turned into a fence followed by an
1864  /// atomic load. This may sound useless, but it makes it possible for the
1865  /// processor to keep the cacheline shared, dramatically improving
1866  /// performance. And such idempotent RMWs are useful for implementing some
1867  /// kinds of locks, see for example (justification + benchmarks):
1868  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1869  /// This method tries doing that transformation, returning the atomic load if
1870  /// it succeeds, and nullptr otherwise.
1871  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1872  /// another round of expansion.
1873  virtual LoadInst *
1875  return nullptr;
1876  }
1877 
1878  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1879  /// SIGN_EXTEND, or ANY_EXTEND).
1881  return ISD::ZERO_EXTEND;
1882  }
1883 
1884  /// @}
1885 
1886  /// Returns true if we should normalize
1887  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1888  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1889  /// that it saves us from materializing N0 and N1 in an integer register.
1890  /// Targets that are able to perform and/or on flags should return false here.
1892  EVT VT) const {
1893  // If a target has multiple condition registers, then it likely has logical
1894  // operations on those registers.
1895  if (hasMultipleConditionRegisters())
1896  return false;
1897  // Only do the transform if the value won't be split into multiple
1898  // registers.
1899  LegalizeTypeAction Action = getTypeAction(Context, VT);
1900  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1901  Action != TypeSplitVector;
1902  }
1903 
1904  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1905 
1906  /// Return true if a select of constants (select Cond, C1, C2) should be
1907  /// transformed into simple math ops with the condition value. For example:
1908  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1909  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1910  return false;
1911  }
1912 
1913  /// Return true if it is profitable to transform an integer
1914  /// multiplication-by-constant into simpler operations like shifts and adds.
1915  /// This may be true if the target does not directly support the
1916  /// multiplication operation for the specified type or the sequence of simpler
1917  /// ops is faster than the multiply.
1918  virtual bool decomposeMulByConstant(LLVMContext &Context,
1919  EVT VT, SDValue C) const {
1920  return false;
1921  }
1922 
1923  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1924  /// conversion operations - canonicalizing the FP source value instead of
1925  /// converting all cases and then selecting based on value.
1926  /// This may be true if the target throws exceptions for out of bounds
1927  /// conversions or has fast FP CMOV.
1928  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1929  bool IsSigned) const {
1930  return false;
1931  }
1932 
1933  //===--------------------------------------------------------------------===//
1934  // TargetLowering Configuration Methods - These methods should be invoked by
1935  // the derived class constructor to configure this object for the target.
1936  //
1937 protected:
1938  /// Specify how the target extends the result of integer and floating point
1939  /// boolean values from i1 to a wider type. See getBooleanContents.
1941  BooleanContents = Ty;
1942  BooleanFloatContents = Ty;
1943  }
1944 
1945  /// Specify how the target extends the result of integer and floating point
1946  /// boolean values from i1 to a wider type. See getBooleanContents.
1948  BooleanContents = IntTy;
1949  BooleanFloatContents = FloatTy;
1950  }
1951 
1952  /// Specify how the target extends the result of a vector boolean value from a
1953  /// vector of i1 to a wider type. See getBooleanContents.
1955  BooleanVectorContents = Ty;
1956  }
1957 
1958  /// Specify the target scheduling preference.
1960  SchedPreferenceInfo = Pref;
1961  }
1962 
1963  /// Indicate whether this target prefers to use _setjmp to implement
1964  /// llvm.setjmp or the version without _. Defaults to false.
1965  void setUseUnderscoreSetJmp(bool Val) {
1966  UseUnderscoreSetJmp = Val;
1967  }
1968 
1969  /// Indicate whether this target prefers to use _longjmp to implement
1970  /// llvm.longjmp or the version without _. Defaults to false.
1971  void setUseUnderscoreLongJmp(bool Val) {
1972  UseUnderscoreLongJmp = Val;
1973  }
1974 
1975  /// Indicate the minimum number of blocks to generate jump tables.
1976  void setMinimumJumpTableEntries(unsigned Val);
1977 
1978  /// Indicate the maximum number of entries in jump tables.
1979  /// Set to zero to generate unlimited jump tables.
1980  void setMaximumJumpTableSize(unsigned);
1981 
1982  /// If set to a physical register, this specifies the register that
1983  /// llvm.savestack/llvm.restorestack should save and restore.
1985  StackPointerRegisterToSaveRestore = R;
1986  }
1987 
1988  /// Tells the code generator that the target has multiple (allocatable)
1989  /// condition registers that can be used to store the results of comparisons
1990  /// for use by selects and conditional branches. With multiple condition
1991  /// registers, the code generator will not aggressively sink comparisons into
1992  /// the blocks of their users.
1993  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1994  HasMultipleConditionRegisters = hasManyRegs;
1995  }
1996 
1997  /// Tells the code generator that the target has BitExtract instructions.
1998  /// The code generator will aggressively sink "shift"s into the blocks of
1999  /// their users if the users will generate "and" instructions which can be
2000  /// combined with "shift" to BitExtract instructions.
2001  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
2002  HasExtractBitsInsn = hasExtractInsn;
2003  }
2004 
2005  /// Tells the code generator not to expand logic operations on comparison
2006  /// predicates into separate sequences that increase the amount of flow
2007  /// control.
2008  void setJumpIsExpensive(bool isExpensive = true);
2009 
2010  /// Tells the code generator which bitwidths to bypass.
2011  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
2012  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2013  }
2014 
2015  /// Add the specified register class as an available regclass for the
2016  /// specified value type. This indicates the selector can handle values of
2017  /// that class natively.
2019  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
2020  RegClassForVT[VT.SimpleTy] = RC;
2021  }
2022 
2023  /// Return the largest legal super-reg register class of the register class
2024  /// for the specified type and its associated "cost".
2025  virtual std::pair<const TargetRegisterClass *, uint8_t>
2026  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
2027 
2028  /// Once all of the register classes are added, this allows us to compute
2029  /// derived properties we expose.
2030  void computeRegisterProperties(const TargetRegisterInfo *TRI);
2031 
2032  /// Indicate that the specified operation does not work with the specified
2033  /// type and indicate what to do about it. Note that VT may refer to either
2034  /// the type of a result or that of an operand of Op.
2035  void setOperationAction(unsigned Op, MVT VT,
2036  LegalizeAction Action) {
2037  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
2038  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
2039  }
2040 
2041  /// Indicate that the specified load with extension does not work with the
2042  /// specified type and indicate what to do about it.
2043  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
2044  LegalizeAction Action) {
2045  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
2046  MemVT.isValid() && "Table isn't big enough!");
2047  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2048  unsigned Shift = 4 * ExtType;
2049  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
2050  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
2051  }
2052 
2053  /// Indicate that the specified truncating store does not work with the
2054  /// specified type and indicate what to do about it.
2055  void setTruncStoreAction(MVT ValVT, MVT MemVT,
2056  LegalizeAction Action) {
2057  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
2058  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
2059  }
2060 
2061  /// Indicate that the specified indexed load does or does not work with the
2062  /// specified type and indicate what to do abort it.
2063  ///
2064  /// NOTE: All indexed mode loads are initialized to Expand in
2065  /// TargetLowering.cpp
2066  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
2067  LegalizeAction Action) {
2068  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2069  (unsigned)Action < 0xf && "Table isn't big enough!");
2070  // Load action are kept in the upper half.
2071  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
2072  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
2073  }
2074 
2075  /// Indicate that the specified indexed store does or does not work with the
2076  /// specified type and indicate what to do about it.
2077  ///
2078  /// NOTE: All indexed mode stores are initialized to Expand in
2079  /// TargetLowering.cpp
2080  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
2081  LegalizeAction Action) {
2082  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2083  (unsigned)Action < 0xf && "Table isn't big enough!");
2084  // Store action are kept in the lower half.
2085  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
2086  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
2087  }
2088 
2089  /// Indicate that the specified condition code is or isn't supported on the
2090  /// target and indicate what to do about it.
2092  LegalizeAction Action) {
2093  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
2094  "Table isn't big enough!");
2095  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2096  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2097  /// value and the upper 29 bits index into the second dimension of the array
2098  /// to select what 32-bit value to use.
2099  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2100  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2101  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2102  }
2103 
2104  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2105  /// to trying a larger integer/fp until it can find one that works. If that
2106  /// default is insufficient, this method can be used by the target to override
2107  /// the default.
2108  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2109  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2110  }
2111 
2112  /// Convenience method to set an operation to Promote and specify the type
2113  /// in a single call.
2114  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2115  setOperationAction(Opc, OrigVT, Promote);
2116  AddPromotedToType(Opc, OrigVT, DestVT);
2117  }
2118 
2119  /// Targets should invoke this method for each target independent node that
2120  /// they want to provide a custom DAG combiner for by implementing the
2121  /// PerformDAGCombine virtual method.
2123  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2124  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2125  }
2126 
2127  /// Set the target's minimum function alignment.
2128  void setMinFunctionAlignment(Align Alignment) {
2129  MinFunctionAlignment = Alignment;
2130  }
2131 
2132  /// Set the target's preferred function alignment. This should be set if
2133  /// there is a performance benefit to higher-than-minimum alignment
2135  PrefFunctionAlignment = Alignment;
2136  }
2137 
2138  /// Set the target's preferred loop alignment. Default alignment is one, it
2139  /// means the target does not care about loop alignment. The target may also
2140  /// override getPrefLoopAlignment to provide per-loop values.
2141  void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }
2142 
2143  /// Set the minimum stack alignment of an argument.
2145  MinStackArgumentAlignment = Alignment;
2146  }
2147 
2148  /// Set the maximum atomic operation size supported by the
2149  /// backend. Atomic operations greater than this size (as well as
2150  /// ones that are not naturally aligned), will be expanded by
2151  /// AtomicExpandPass into an __atomic_* library call.
2152  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2153  MaxAtomicSizeInBitsSupported = SizeInBits;
2154  }
2155 
2156  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2157  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2158  MinCmpXchgSizeInBits = SizeInBits;
2159  }
2160 
2161  /// Sets whether unaligned atomic operations are supported.
2162  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2163  SupportsUnalignedAtomics = UnalignedSupported;
2164  }
2165 
2166 public:
2167  //===--------------------------------------------------------------------===//
2168  // Addressing mode description hooks (used by LSR etc).
2169  //
2170 
2171  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2172  /// instructions reading the address. This allows as much computation as
2173  /// possible to be done in the address mode for that operand. This hook lets
2174  /// targets also pass back when this should be done on intrinsics which
2175  /// load/store.
2176  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2177  SmallVectorImpl<Value*> &/*Ops*/,
2178  Type *&/*AccessTy*/) const {
2179  return false;
2180  }
2181 
2182  /// This represents an addressing mode of:
2183  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2184  /// If BaseGV is null, there is no BaseGV.
2185  /// If BaseOffs is zero, there is no base offset.
2186  /// If HasBaseReg is false, there is no base register.
2187  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2188  /// no scale.
2189  struct AddrMode {
2190  GlobalValue *BaseGV = nullptr;
2191  int64_t BaseOffs = 0;
2192  bool HasBaseReg = false;
2193  int64_t Scale = 0;
2194  AddrMode() = default;
2195  };
2196 
2197  /// Return true if the addressing mode represented by AM is legal for this
2198  /// target, for a load/store of the specified type.
2199  ///
2200  /// The type may be VoidTy, in which case only return true if the addressing
2201  /// mode is legal for a load/store of any legal type. TODO: Handle
2202  /// pre/postinc as well.
2203  ///
2204  /// If the address space cannot be determined, it will be -1.
2205  ///
2206  /// TODO: Remove default argument
2207  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2208  Type *Ty, unsigned AddrSpace,
2209  Instruction *I = nullptr) const;
2210 
2211  /// Return the cost of the scaling factor used in the addressing mode
2212  /// represented by AM for this target, for a load/store of the specified type.
2213  ///
2214  /// If the AM is supported, the return value must be >= 0.
2215  /// If the AM is not supported, it returns a negative value.
2216  /// TODO: Handle pre/postinc as well.
2217  /// TODO: Remove default argument
2218  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2219  Type *Ty, unsigned AS = 0) const {
2220  // Default: assume that any scaling factor used in a legal AM is free.
2221  if (isLegalAddressingMode(DL, AM, Ty, AS))
2222  return 0;
2223  return -1;
2224  }
2225 
2226  /// Return true if the specified immediate is legal icmp immediate, that is
2227  /// the target has icmp instructions which can compare a register against the
2228  /// immediate without having to materialize the immediate into a register.
2229  virtual bool isLegalICmpImmediate(int64_t) const {
2230  return true;
2231  }
2232 
2233  /// Return true if the specified immediate is legal add immediate, that is the
2234  /// target has add instructions which can add a register with the immediate
2235  /// without having to materialize the immediate into a register.
2236  virtual bool isLegalAddImmediate(int64_t) const {
2237  return true;
2238  }
2239 
2240  /// Return true if the specified immediate is legal for the value input of a
2241  /// store instruction.
2242  virtual bool isLegalStoreImmediate(int64_t Value) const {
2243  // Default implementation assumes that at least 0 works since it is likely
2244  // that a zero register exists or a zero immediate is allowed.
2245  return Value == 0;
2246  }
2247 
2248  /// Return true if it's significantly cheaper to shift a vector by a uniform
2249  /// scalar than by an amount which will vary across each lane. On x86, for
2250  /// example, there is a "psllw" instruction for the former case, but no simple
2251  /// instruction for a general "a << b" operation on vectors.
2252  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2253  return false;
2254  }
2255 
2256  /// Returns true if the opcode is a commutative binary operation.
2257  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2258  // FIXME: This should get its info from the td file.
2259  switch (Opcode) {
2260  case ISD::ADD:
2261  case ISD::SMIN:
2262  case ISD::SMAX:
2263  case ISD::UMIN:
2264  case ISD::UMAX:
2265  case ISD::MUL:
2266  case ISD::MULHU:
2267  case ISD::MULHS:
2268  case ISD::SMUL_LOHI:
2269  case ISD::UMUL_LOHI:
2270  case ISD::FADD:
2271  case ISD::FMUL:
2272  case ISD::AND:
2273  case ISD::OR:
2274  case ISD::XOR:
2275  case ISD::SADDO:
2276  case ISD::UADDO:
2277  case ISD::ADDC:
2278  case ISD::ADDE:
2279  case ISD::SADDSAT:
2280  case ISD::UADDSAT:
2281  case ISD::FMINNUM:
2282  case ISD::FMAXNUM:
2283  case ISD::FMINNUM_IEEE:
2284  case ISD::FMAXNUM_IEEE:
2285  case ISD::FMINIMUM:
2286  case ISD::FMAXIMUM:
2287  return true;
2288  default: return false;
2289  }
2290  }
2291 
2292  /// Return true if the node is a math/logic binary operator.
2293  virtual bool isBinOp(unsigned Opcode) const {
2294  // A commutative binop must be a binop.
2295  if (isCommutativeBinOp(Opcode))
2296  return true;
2297  // These are non-commutative binops.
2298  switch (Opcode) {
2299  case ISD::SUB:
2300  case ISD::SHL:
2301  case ISD::SRL:
2302  case ISD::SRA:
2303  case ISD::SDIV:
2304  case ISD::UDIV:
2305  case ISD::SREM:
2306  case ISD::UREM:
2307  case ISD::FSUB:
2308  case ISD::FDIV:
2309  case ISD::FREM:
2310  return true;
2311  default:
2312  return false;
2313  }
2314  }
2315 
2316  /// Return true if it's free to truncate a value of type FromTy to type
2317  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2318  /// by referencing its sub-register AX.
2319  /// Targets must return false when FromTy <= ToTy.
2320  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2321  return false;
2322  }
2323 
2324  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2325  /// whether a call is in tail position. Typically this means that both results
2326  /// would be assigned to the same register or stack slot, but it could mean
2327  /// the target performs adequate checks of its own before proceeding with the
2328  /// tail call. Targets must return false when FromTy <= ToTy.
2329  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2330  return false;
2331  }
2332 
2333  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2334  return false;
2335  }
2336 
2337  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2338 
2339  /// Return true if the extension represented by \p I is free.
2340  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2341  /// this method can use the context provided by \p I to decide
2342  /// whether or not \p I is free.
2343  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2344  /// In other words, if is[Z|FP]Free returns true, then this method
2345  /// returns true as well. The converse is not true.
2346  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2347  /// \pre \p I must be a sign, zero, or fp extension.
2348  bool isExtFree(const Instruction *I) const {
2349  switch (I->getOpcode()) {
2350  case Instruction::FPExt:
2351  if (isFPExtFree(EVT::getEVT(I->getType()),
2352  EVT::getEVT(I->getOperand(0)->getType())))
2353  return true;
2354  break;
2355  case Instruction::ZExt:
2356  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2357  return true;
2358  break;
2359  case Instruction::SExt:
2360  break;
2361  default:
2362  llvm_unreachable("Instruction is not an extension");
2363  }
2364  return isExtFreeImpl(I);
2365  }
2366 
2367  /// Return true if \p Load and \p Ext can form an ExtLoad.
2368  /// For example, in AArch64
2369  /// %L = load i8, i8* %ptr
2370  /// %E = zext i8 %L to i32
2371  /// can be lowered into one load instruction
2372  /// ldrb w0, [x0]
2373  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2374  const DataLayout &DL) const {
2375  EVT VT = getValueType(DL, Ext->getType());
2376  EVT LoadVT = getValueType(DL, Load->getType());
2377 
2378  // If the load has other users and the truncate is not free, the ext
2379  // probably isn't free.
2380  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2381  !isTruncateFree(Ext->getType(), Load->getType()))
2382  return false;
2383 
2384  // Check whether the target supports casts folded into loads.
2385  unsigned LType;
2386  if (isa<ZExtInst>(Ext))
2387  LType = ISD::ZEXTLOAD;
2388  else {
2389  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2390  LType = ISD::SEXTLOAD;
2391  }
2392 
2393  return isLoadExtLegal(LType, VT, LoadVT);
2394  }
2395 
2396  /// Return true if any actual instruction that defines a value of type FromTy
2397  /// implicitly zero-extends the value to ToTy in the result register.
2398  ///
2399  /// The function should return true when it is likely that the truncate can
2400  /// be freely folded with an instruction defining a value of FromTy. If
2401  /// the defining instruction is unknown (because you're looking at a
2402  /// function argument, PHI, etc.) then the target may require an
2403  /// explicit truncate, which is not necessarily free, but this function
2404  /// does not deal with those cases.
2405  /// Targets must return false when FromTy >= ToTy.
2406  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2407  return false;
2408  }
2409 
2410  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2411  return false;
2412  }
2413 
2414  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2415  /// zero-extension.
2416  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2417  return false;
2418  }
2419 
2420  /// Return true if sinking I's operands to the same basic block as I is
2421  /// profitable, e.g. because the operands can be folded into a target
2422  /// instruction during instruction selection. After calling the function
2423  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2424  /// come first).
2426  SmallVectorImpl<Use *> &Ops) const {
2427  return false;
2428  }
2429 
2430  /// Return true if the target supplies and combines to a paired load
2431  /// two loaded values of type LoadedType next to each other in memory.
2432  /// RequiredAlignment gives the minimal alignment constraints that must be met
2433  /// to be able to select this paired load.
2434  ///
2435  /// This information is *not* used to generate actual paired loads, but it is
2436  /// used to generate a sequence of loads that is easier to combine into a
2437  /// paired load.
2438  /// For instance, something like this:
2439  /// a = load i64* addr
2440  /// b = trunc i64 a to i32
2441  /// c = lshr i64 a, 32
2442  /// d = trunc i64 c to i32
2443  /// will be optimized into:
2444  /// b = load i32* addr1
2445  /// d = load i32* addr2
2446  /// Where addr1 = addr2 +/- sizeof(i32).
2447  ///
2448  /// In other words, unless the target performs a post-isel load combining,
2449  /// this information should not be provided because it will generate more
2450  /// loads.
2451  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2452  unsigned & /*RequiredAlignment*/) const {
2453  return false;
2454  }
2455 
2456  /// Return true if the target has a vector blend instruction.
2457  virtual bool hasVectorBlend() const { return false; }
2458 
2459  /// Get the maximum supported factor for interleaved memory accesses.
2460  /// Default to be the minimum interleave factor: 2.
2461  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2462 
2463  /// Lower an interleaved load to target specific intrinsics. Return
2464  /// true on success.
2465  ///
2466  /// \p LI is the vector load instruction.
2467  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2468  /// \p Indices is the corresponding indices for each shufflevector.
2469  /// \p Factor is the interleave factor.
2470  virtual bool lowerInterleavedLoad(LoadInst *LI,
2472  ArrayRef<unsigned> Indices,
2473  unsigned Factor) const {
2474  return false;
2475  }
2476 
2477  /// Lower an interleaved store to target specific intrinsics. Return
2478  /// true on success.
2479  ///
2480  /// \p SI is the vector store instruction.
2481  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2482  /// \p Factor is the interleave factor.
2484  unsigned Factor) const {
2485  return false;
2486  }
2487 
2488  /// Return true if zero-extending the specific node Val to type VT2 is free
2489  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2490  /// because it's folded such as X86 zero-extending loads).
2491  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2492  return isZExtFree(Val.getValueType(), VT2);
2493  }
2494 
2495  /// Return true if an fpext operation is free (for instance, because
2496  /// single-precision floating-point numbers are implicitly extended to
2497  /// double-precision).
2498  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2499  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2500  "invalid fpext types");
2501  return false;
2502  }
2503 
2504  /// Return true if an fpext operation input to an \p Opcode operation is free
2505  /// (for instance, because half-precision floating-point numbers are
2506  /// implicitly extended to float-precision) for an FMA instruction.
2507  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2508  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2509  "invalid fpext types");
2510  return isFPExtFree(DestVT, SrcVT);
2511  }
2512 
2513  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2514  /// extend node) is profitable.
2515  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2516 
2517  /// Return true if an fneg operation is free to the point where it is never
2518  /// worthwhile to replace it with a bitwise operation.
2519  virtual bool isFNegFree(EVT VT) const {
2520  assert(VT.isFloatingPoint());
2521  return false;
2522  }
2523 
2524  /// Return true if an fabs operation is free to the point where it is never
2525  /// worthwhile to replace it with a bitwise operation.
2526  virtual bool isFAbsFree(EVT VT) const {
2527  assert(VT.isFloatingPoint());
2528  return false;
2529  }
2530 
2531  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2532  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2533  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2534  ///
2535  /// NOTE: This may be called before legalization on types for which FMAs are
2536  /// not legal, but should return true if those types will eventually legalize
2537  /// to types that support FMAs. After legalization, it will only be called on
2538  /// types that support FMAs (via Legal or Custom actions)
2539  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2540  return false;
2541  }
2542 
2543  /// Return true if it's profitable to narrow operations of type VT1 to
2544  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2545  /// i32 to i16.
2546  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2547  return false;
2548  }
2549 
2550  /// Return true if it is beneficial to convert a load of a constant to
2551  /// just the constant itself.
2552  /// On some targets it might be more efficient to use a combination of
2553  /// arithmetic instructions to materialize the constant instead of loading it
2554  /// from a constant pool.
2555  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2556  Type *Ty) const {
2557  return false;
2558  }
2559 
2560  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2561  /// from this source type with this index. This is needed because
2562  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2563  /// the first element, and only the target knows which lowering is cheap.
2564  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2565  unsigned Index) const {
2566  return false;
2567  }
2568 
2569  /// Try to convert an extract element of a vector binary operation into an
2570  /// extract element followed by a scalar operation.
2571  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2572  return false;
2573  }
2574 
2575  /// Return true if extraction of a scalar element from the given vector type
2576  /// at the given index is cheap. For example, if scalar operations occur on
2577  /// the same register file as vector operations, then an extract element may
2578  /// be a sub-register rename rather than an actual instruction.
2579  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2580  return false;
2581  }
2582 
2583  /// Try to convert math with an overflow comparison into the corresponding DAG
2584  /// node operation. Targets may want to override this independently of whether
2585  /// the operation is legal/custom for the given type because it may obscure
2586  /// matching of other patterns.
2587  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2588  // TODO: The default logic is inherited from code in CodeGenPrepare.
2589  // The opcode should not make a difference by default?
2590  if (Opcode != ISD::UADDO)
2591  return false;
2592 
2593  // Allow the transform as long as we have an integer type that is not
2594  // obviously illegal and unsupported.
2595  if (VT.isVector())
2596  return false;
2597  return VT.isSimple() || !isOperationExpand(Opcode, VT);
2598  }
2599 
2600  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2601  // even if the vector itself has multiple uses.
2602  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2603  return false;
2604  }
2605 
2606  // Return true if CodeGenPrepare should consider splitting large offset of a
2607  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2608  // same blocks of its users.
2609  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2610 
2611  //===--------------------------------------------------------------------===//
2612  // Runtime Library hooks
2613  //
2614 
2615  /// Rename the default libcall routine name for the specified libcall.
2616  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2617  LibcallRoutineNames[Call] = Name;
2618  }
2619 
2620  /// Get the libcall routine name for the specified libcall.
2621  const char *getLibcallName(RTLIB::Libcall Call) const {
2622  return LibcallRoutineNames[Call];
2623  }
2624 
2625  /// Override the default CondCode to be used to test the result of the
2626  /// comparison libcall against zero.
2628  CmpLibcallCCs[Call] = CC;
2629  }
2630 
2631  /// Get the CondCode that's to be used to test the result of the comparison
2632  /// libcall against zero.
2634  return CmpLibcallCCs[Call];
2635  }
2636 
2637  /// Set the CallingConv that should be used for the specified libcall.
2639  LibcallCallingConvs[Call] = CC;
2640  }
2641 
2642  /// Get the CallingConv that should be used for the specified libcall.
2644  return LibcallCallingConvs[Call];
2645  }
2646 
2647  /// Execute target specific actions to finalize target lowering.
2648  /// This is used to set extra flags in MachineFrameInformation and freezing
2649  /// the set of reserved registers.
2650  /// The default implementation just freezes the set of reserved registers.
2651  virtual void finalizeLowering(MachineFunction &MF) const;
2652 
2653 private:
2654  const TargetMachine &TM;
2655 
2656  /// Tells the code generator that the target has multiple (allocatable)
2657  /// condition registers that can be used to store the results of comparisons
2658  /// for use by selects and conditional branches. With multiple condition
2659  /// registers, the code generator will not aggressively sink comparisons into
2660  /// the blocks of their users.
2661  bool HasMultipleConditionRegisters;
2662 
2663  /// Tells the code generator that the target has BitExtract instructions.
2664  /// The code generator will aggressively sink "shift"s into the blocks of
2665  /// their users if the users will generate "and" instructions which can be
2666  /// combined with "shift" to BitExtract instructions.
2667  bool HasExtractBitsInsn;
2668 
2669  /// Tells the code generator to bypass slow divide or remainder
2670  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2671  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2672  /// div/rem when the operands are positive and less than 256.
2673  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2674 
2675  /// Tells the code generator that it shouldn't generate extra flow control
2676  /// instructions and should attempt to combine flow control instructions via
2677  /// predication.
2678  bool JumpIsExpensive;
2679 
2680  /// This target prefers to use _setjmp to implement llvm.setjmp.
2681  ///
2682  /// Defaults to false.
2683  bool UseUnderscoreSetJmp;
2684 
2685  /// This target prefers to use _longjmp to implement llvm.longjmp.
2686  ///
2687  /// Defaults to false.
2688  bool UseUnderscoreLongJmp;
2689 
2690  /// Information about the contents of the high-bits in boolean values held in
2691  /// a type wider than i1. See getBooleanContents.
2692  BooleanContent BooleanContents;
2693 
2694  /// Information about the contents of the high-bits in boolean values held in
2695  /// a type wider than i1. See getBooleanContents.
2696  BooleanContent BooleanFloatContents;
2697 
2698  /// Information about the contents of the high-bits in boolean vector values
2699  /// when the element type is wider than i1. See getBooleanContents.
2700  BooleanContent BooleanVectorContents;
2701 
2702  /// The target scheduling preference: shortest possible total cycles or lowest
2703  /// register usage.
2704  Sched::Preference SchedPreferenceInfo;
2705 
2706  /// The minimum alignment that any argument on the stack needs to have.
2707  Align MinStackArgumentAlignment;
2708 
2709  /// The minimum function alignment (used when optimizing for size, and to
2710  /// prevent explicitly provided alignment from leading to incorrect code).
2711  Align MinFunctionAlignment;
2712 
2713  /// The preferred function alignment (used when alignment unspecified and
2714  /// optimizing for speed).
2715  Align PrefFunctionAlignment;
2716 
2717  /// The preferred loop alignment (in log2 bot in bytes).
2718  Align PrefLoopAlignment;
2719 
2720  /// Size in bits of the maximum atomics size the backend supports.
2721  /// Accesses larger than this will be expanded by AtomicExpandPass.
2722  unsigned MaxAtomicSizeInBitsSupported;
2723 
2724  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2725  /// backend supports.
2726  unsigned MinCmpXchgSizeInBits;
2727 
2728  /// This indicates if the target supports unaligned atomic operations.
2729  bool SupportsUnalignedAtomics;
2730 
2731  /// If set to a physical register, this specifies the register that
2732  /// llvm.savestack/llvm.restorestack should save and restore.
2733  unsigned StackPointerRegisterToSaveRestore;
2734 
2735  /// This indicates the default register class to use for each ValueType the
2736  /// target supports natively.
2737  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2738  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2739  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2740 
2741  /// This indicates the "representative" register class to use for each
2742  /// ValueType the target supports natively. This information is used by the
2743  /// scheduler to track register pressure. By default, the representative
2744  /// register class is the largest legal super-reg register class of the
2745  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2746  /// representative class would be GR32.
2747  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2748 
2749  /// This indicates the "cost" of the "representative" register class for each
2750  /// ValueType. The cost is used by the scheduler to approximate register
2751  /// pressure.
2752  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2753 
2754  /// For any value types we are promoting or expanding, this contains the value
2755  /// type that we are changing to. For Expanded types, this contains one step
2756  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2757  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2758  /// the same type (e.g. i32 -> i32).
2759  MVT TransformToType[MVT::LAST_VALUETYPE];
2760 
2761  /// For each operation and each value type, keep a LegalizeAction that
2762  /// indicates how instruction selection should deal with the operation. Most
2763  /// operations are Legal (aka, supported natively by the target), but
2764  /// operations that are not should be described. Note that operations on
2765  /// non-legal value types are not described here.
2767 
2768  /// For each load extension type and each value type, keep a LegalizeAction
2769  /// that indicates how instruction selection should deal with a load of a
2770  /// specific value type and extension type. Uses 4-bits to store the action
2771  /// for each of the 4 load ext types.
2772  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2773 
2774  /// For each value type pair keep a LegalizeAction that indicates whether a
2775  /// truncating store of a specific value type and truncating type is legal.
2777 
2778  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2779  /// that indicates how instruction selection should deal with the load /
2780  /// store.
2781  ///
2782  /// The first dimension is the value_type for the reference. The second
2783  /// dimension represents the various modes for load store.
2784  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2785 
2786  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2787  /// indicates how instruction selection should deal with the condition code.
2788  ///
2789  /// Because each CC action takes up 4 bits, we need to have the array size be
2790  /// large enough to fit all of the value types. This can be done by rounding
2791  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2792  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2793 
2794  ValueTypeActionImpl ValueTypeActions;
2795 
2796 private:
2797  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2798 
2799  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2800  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2801  /// array.
2802  unsigned char
2803  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2804 
2805  /// For operations that must be promoted to a specific type, this holds the
2806  /// destination type. This map should be sparse, so don't hold it as an
2807  /// array.
2808  ///
2809  /// Targets add entries to this map with AddPromotedToType(..), clients access
2810  /// this with getTypeToPromoteTo(..).
2811  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2812  PromoteToType;
2813 
2814  /// Stores the name each libcall.
2815  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2816 
2817  /// The ISD::CondCode that should be used to test the result of each of the
2818  /// comparison libcall against zero.
2819  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2820 
2821  /// Stores the CallingConv that should be used for each libcall.
2822  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2823 
2824  /// Set default libcall names and calling conventions.
2825  void InitLibcalls(const Triple &TT);
2826 
2827 protected:
2828  /// Return true if the extension represented by \p I is free.
2829  /// \pre \p I is a sign, zero, or fp extension and
2830  /// is[Z|FP]ExtFree of the related types is not true.
2831  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2832 
2833  /// Depth that GatherAllAliases should should continue looking for chain
2834  /// dependencies when trying to find a more preferable chain. As an
2835  /// approximation, this should be more than the number of consecutive stores
2836  /// expected to be merged.
2838 
2839  /// \brief Specify maximum number of store instructions per memset call.
2840  ///
2841  /// When lowering \@llvm.memset this field specifies the maximum number of
2842  /// store operations that may be substituted for the call to memset. Targets
2843  /// must set this value based on the cost threshold for that target. Targets
2844  /// should assume that the memset will be done using as many of the largest
2845  /// store operations first, followed by smaller ones, if necessary, per
2846  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2847  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2848  /// store. This only applies to setting a constant array of a constant size.
2850  /// Likewise for functions with the OptSize attribute.
2852 
2853  /// \brief Specify maximum number of store instructions per memcpy call.
2854  ///
2855  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2856  /// store operations that may be substituted for a call to memcpy. Targets
2857  /// must set this value based on the cost threshold for that target. Targets
2858  /// should assume that the memcpy will be done using as many of the largest
2859  /// store operations first, followed by smaller ones, if necessary, per
2860  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2861  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2862  /// and one 1-byte store. This only applies to copying a constant array of
2863  /// constant size.
2865  /// Likewise for functions with the OptSize attribute.
2867  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2868  ///
2869  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2870  /// of store instructions to keep together. This helps in pairing and
2871  // vectorization later on.
2872  unsigned MaxGluedStoresPerMemcpy = 0;
2873 
2874  /// \brief Specify maximum number of load instructions per memcmp call.
2875  ///
2876  /// When lowering \@llvm.memcmp this field specifies the maximum number of
2877  /// pairs of load operations that may be substituted for a call to memcmp.
2878  /// Targets must set this value based on the cost threshold for that target.
2879  /// Targets should assume that the memcmp will be done using as many of the
2880  /// largest load operations first, followed by smaller ones, if necessary, per
2881  /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2882  /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2883  /// and one 1-byte load. This only applies to copying a constant array of
2884  /// constant size.
2886  /// Likewise for functions with the OptSize attribute.
2888 
2889  /// \brief Specify maximum number of store instructions per memmove call.
2890  ///
2891  /// When lowering \@llvm.memmove this field specifies the maximum number of
2892  /// store instructions that may be substituted for a call to memmove. Targets
2893  /// must set this value based on the cost threshold for that target. Targets
2894  /// should assume that the memmove will be done using as many of the largest
2895  /// store operations first, followed by smaller ones, if necessary, per
2896  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2897  /// with 8-bit alignment would result in nine 1-byte stores. This only
2898  /// applies to copying a constant array of constant size.
2900  /// Likewise for functions with the OptSize attribute.
2902 
2903  /// Tells the code generator that select is more expensive than a branch if
2904  /// the branch is usually predicted right.
2906 
2907  /// \see enableExtLdPromotion.
2909 
2910  /// Return true if the value types that can be represented by the specified
2911  /// register class are all legal.
2912  bool isLegalRC(const TargetRegisterInfo &TRI,
2913  const TargetRegisterClass &RC) const;
2914 
2915  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2916  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2917  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2918  MachineBasicBlock *MBB) const;
2919 
2920  /// Replace/modify the XRay custom event operands with target-dependent
2921  /// details.
2922  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2923  MachineBasicBlock *MBB) const;
2924 
2925  /// Replace/modify the XRay typed event operands with target-dependent
2926  /// details.
2927  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2928  MachineBasicBlock *MBB) const;
2929 };
2930 
2931 /// This class defines information used to lower LLVM code to legal SelectionDAG
2932 /// operators that the target instruction selector can accept natively.
2933 ///
2934 /// This class also defines callbacks that targets must implement to lower
2935 /// target-specific constructs to SelectionDAG operators.
2937 public:
2938  struct DAGCombinerInfo;
2939  struct MakeLibCallOptions;
2940 
2941  TargetLowering(const TargetLowering &) = delete;
2942  TargetLowering &operator=(const TargetLowering &) = delete;
2943 
2944  /// NOTE: The TargetMachine owns TLOF.
2945  explicit TargetLowering(const TargetMachine &TM);
2946 
2947  bool isPositionIndependent() const;
2948 
2949  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2950  FunctionLoweringInfo *FLI,
2951  LegacyDivergenceAnalysis *DA) const {
2952  return false;
2953  }
2954 
2955  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2956  return false;
2957  }
2958 
2959  /// Returns true by value, base pointer and offset pointer and addressing mode
2960  /// by reference if the node's address can be legally represented as
2961  /// pre-indexed load / store address.
2962  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2963  SDValue &/*Offset*/,
2964  ISD::MemIndexedMode &/*AM*/,
2965  SelectionDAG &/*DAG*/) const {
2966  return false;
2967  }
2968 
2969  /// Returns true by value, base pointer and offset pointer and addressing mode
2970  /// by reference if this node can be combined with a load / store to form a
2971  /// post-indexed load / store.
2972  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2973  SDValue &/*Base*/,
2974  SDValue &/*Offset*/,
2975  ISD::MemIndexedMode &/*AM*/,
2976  SelectionDAG &/*DAG*/) const {
2977  return false;
2978  }
2979 
2980  /// Returns true if the specified base+offset is a legal indexed addressing
2981  /// mode for this target. \p MI is the load or store instruction that is being
2982  /// considered for transformation.
2984  bool IsPre, MachineRegisterInfo &MRI) const {
2985  return false;
2986  }
2987 
2988  /// Return the entry encoding for a jump table in the current function. The
2989  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2990  virtual unsigned getJumpTableEncoding() const;
2991 
2992  virtual const MCExpr *
2994  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2995  MCContext &/*Ctx*/) const {
2996  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2997  }
2998 
2999  /// Returns relocation base for the given PIC jumptable.
3000  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
3001  SelectionDAG &DAG) const;
3002 
3003  /// This returns the relocation base for the given PIC jumptable, the same as
3004  /// getPICJumpTableRelocBase, but as an MCExpr.
3005  virtual const MCExpr *
3006  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3007  unsigned JTI, MCContext &Ctx) const;
3008 
3009  /// Return true if folding a constant offset with the given GlobalAddress is
3010  /// legal. It is frequently not legal in PIC relocation models.
3011  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
3012 
3014  SDValue &Chain) const;
3015 
3016  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3017  SDValue &NewRHS, ISD::CondCode &CCCode,
3018  const SDLoc &DL, const SDValue OldLHS,
3019  const SDValue OldRHS) const;
3020 
3021  /// Returns a pair of (return value, chain).
3022  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
3023  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
3024  EVT RetVT, ArrayRef<SDValue> Ops,
3025  MakeLibCallOptions CallOptions,
3026  const SDLoc &dl) const;
3027 
3028  /// Check whether parameters to a call that are passed in callee saved
3029  /// registers are the same as from the calling function. This needs to be
3030  /// checked for tail call eligibility.
3031  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
3032  const uint32_t *CallerPreservedMask,
3033  const SmallVectorImpl<CCValAssign> &ArgLocs,
3034  const SmallVectorImpl<SDValue> &OutVals) const;
3035 
3036  //===--------------------------------------------------------------------===//
3037  // TargetLowering Optimization Methods
3038  //
3039 
3040  /// A convenience struct that encapsulates a DAG, and two SDValues for
3041  /// returning information from TargetLowering to its clients that want to
3042  /// combine.
3045  bool LegalTys;
3046  bool LegalOps;
3049 
3051  bool LT, bool LO) :
3052  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
3053 
3054  bool LegalTypes() const { return LegalTys; }
3055  bool LegalOperations() const { return LegalOps; }
3056 
3058  Old = O;
3059  New = N;
3060  return true;
3061  }
3062  };
3063 
3064  /// Determines the optimal series of memory ops to replace the memset / memcpy.
3065  /// Return true if the number of memory ops is below the threshold (Limit).
3066  /// It returns the types of the sequence of memory ops to perform
3067  /// memset / memcpy by reference.
3068  bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
3069  unsigned Limit, uint64_t Size,
3070  unsigned DstAlign, unsigned SrcAlign,
3071  bool IsMemset,
3072  bool ZeroMemset,
3073  bool MemcpyStrSrc,
3074  bool AllowOverlap,
3075  unsigned DstAS, unsigned SrcAS,
3076  const AttributeList &FuncAttributes) const;
3077 
3078  /// Check to see if the specified operand of the specified instruction is a
3079  /// constant integer. If so, check to see if there are any bits set in the
3080  /// constant that are not demanded. If so, shrink the constant and return
3081  /// true.
3082  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3083  TargetLoweringOpt &TLO) const;
3084 
3085  // Target hook to do target-specific const optimization, which is called by
3086  // ShrinkDemandedConstant. This function should return true if the target
3087  // doesn't want ShrinkDemandedConstant to further optimize the constant.
3088  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3089  TargetLoweringOpt &TLO) const {
3090  return false;
3091  }
3092 
3093  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3094  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3095  /// generalized for targets with other types of implicit widening casts.
3096  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3097  TargetLoweringOpt &TLO) const;
3098 
3099  /// Look at Op. At this point, we know that only the DemandedBits bits of the
3100  /// result of Op are ever used downstream. If we can use this information to
3101  /// simplify Op, create a new simplified DAG node and return true, returning
3102  /// the original and new nodes in Old and New. Otherwise, analyze the
3103  /// expression and return a mask of KnownOne and KnownZero bits for the
3104  /// expression (used to simplify the caller). The KnownZero/One bits may only
3105  /// be accurate for those bits in the Demanded masks.
3106  /// \p AssumeSingleUse When this parameter is true, this function will
3107  /// attempt to simplify \p Op even if there are multiple uses.
3108  /// Callers are responsible for correctly updating the DAG based on the
3109  /// results of this function, because simply replacing replacing TLO.Old
3110  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3111  /// has multiple uses.
3112  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3113  const APInt &DemandedElts, KnownBits &Known,
3114  TargetLoweringOpt &TLO, unsigned Depth = 0,
3115  bool AssumeSingleUse = false) const;
3116 
3117  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3118  /// Adds Op back to the worklist upon success.
3119  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3120  KnownBits &Known, TargetLoweringOpt &TLO,
3121  unsigned Depth = 0,
3122  bool AssumeSingleUse = false) const;
3123 
3124  /// Helper wrapper around SimplifyDemandedBits.
3125  /// Adds Op back to the worklist upon success.
3126  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
3127  DAGCombinerInfo &DCI) const;
3128 
3129  /// More limited version of SimplifyDemandedBits that can be used to "look
3130  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3131  /// bitwise ops etc.
3132  SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3133  const APInt &DemandedElts,
3134  SelectionDAG &DAG,
3135  unsigned Depth) const;
3136 
3137  /// Look at Vector Op. At this point, we know that only the DemandedElts
3138  /// elements of the result of Op are ever used downstream. If we can use
3139  /// this information to simplify Op, create a new simplified DAG node and
3140  /// return true, storing the original and new nodes in TLO.
3141  /// Otherwise, analyze the expression and return a mask of KnownUndef and
3142  /// KnownZero elements for the expression (used to simplify the caller).
3143  /// The KnownUndef/Zero elements may only be accurate for those bits
3144  /// in the DemandedMask.
3145  /// \p AssumeSingleUse When this parameter is true, this function will
3146  /// attempt to simplify \p Op even if there are multiple uses.
3147  /// Callers are responsible for correctly updating the DAG based on the
3148  /// results of this function, because simply replacing replacing TLO.Old
3149  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3150  /// has multiple uses.
3151  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3152  APInt &KnownUndef, APInt &KnownZero,
3153  TargetLoweringOpt &TLO, unsigned Depth = 0,
3154  bool AssumeSingleUse = false) const;
3155 
3156  /// Helper wrapper around SimplifyDemandedVectorElts.
3157  /// Adds Op back to the worklist upon success.
3158  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3159  APInt &KnownUndef, APInt &KnownZero,
3160  DAGCombinerInfo &DCI) const;
3161 
3162  /// Determine which of the bits specified in Mask are known to be either zero
3163  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3164  /// argument allows us to only collect the known bits that are shared by the
3165  /// requested vector elements.
3166  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3167  KnownBits &Known,
3168  const APInt &DemandedElts,
3169  const SelectionDAG &DAG,
3170  unsigned Depth = 0) const;
3171  /// Determine which of the bits specified in Mask are known to be either zero
3172  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3173  /// argument allows us to only collect the known bits that are shared by the
3174  /// requested vector elements. This is for GISel.
3175  virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis,
3176  Register R, KnownBits &Known,
3177  const APInt &DemandedElts,
3178  const MachineRegisterInfo &MRI,
3179  unsigned Depth = 0) const;
3180 
3181  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3182  /// Default implementation computes low bits based on alignment
3183  /// information. This should preserve known bits passed into it.
3184  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3185  KnownBits &Known,
3186  const APInt &DemandedElts,
3187  const SelectionDAG &DAG,
3188  unsigned Depth = 0) const;
3189 
3190  /// This method can be implemented by targets that want to expose additional
3191  /// information about sign bits to the DAG Combiner. The DemandedElts
3192  /// argument allows us to only collect the minimum sign bits that are shared
3193  /// by the requested vector elements.
3194  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3195  const APInt &DemandedElts,
3196  const SelectionDAG &DAG,
3197  unsigned Depth = 0) const;
3198 
3199  /// Attempt to simplify any target nodes based on the demanded vector
3200  /// elements, returning true on success. Otherwise, analyze the expression and
3201  /// return a mask of KnownUndef and KnownZero elements for the expression
3202  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3203  /// accurate for those bits in the DemandedMask.
3204  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3205  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3206  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3207 
3208  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3209  /// returning true on success. Otherwise, analyze the
3210  /// expression and return a mask of KnownOne and KnownZero bits for the
3211  /// expression (used to simplify the caller). The KnownZero/One bits may only
3212  /// be accurate for those bits in the Demanded masks.
3213  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3214  const APInt &DemandedBits,
3215  const APInt &DemandedElts,
3216  KnownBits &Known,
3217  TargetLoweringOpt &TLO,
3218  unsigned Depth = 0) const;
3219 
3220  /// More limited version of SimplifyDemandedBits that can be used to "look
3221  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3222  /// bitwise ops etc.
3223  virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
3224  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3225  SelectionDAG &DAG, unsigned Depth) const;
3226 
3227  /// Tries to build a legal vector shuffle using the provided parameters
3228  /// or equivalent variations. The Mask argument maybe be modified as the
3229  /// function tries different variations.
3230  /// Returns an empty SDValue if the operation fails.
3231  SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
3233  SelectionDAG &DAG) const;
3234 
3235  /// This method returns the constant pool value that will be loaded by LD.
3236  /// NOTE: You must check for implicit extensions of the constant by LD.
3237  virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
3238 
3239  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3240  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3241  /// NaN.
3242  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3243  const SelectionDAG &DAG,
3244  bool SNaN = false,
3245  unsigned Depth = 0) const;
3247  void *DC; // The DAG Combiner object.
3250 
3251  public:
3253 
3254  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3255  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3256 
3257  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3258  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3259  bool isAfterLegalizeDAG() const {
3260  return Level == AfterLegalizeDAG;
3261  }
3263  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3264 
3265  void AddToWorklist(SDNode *N);
3266  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3267  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3268  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3269 
3270  bool recursivelyDeleteUnusedNodes(SDNode *N);
3271 
3272  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3273  };
3274 
3275  /// Return if the N is a constant or constant vector equal to the true value
3276  /// from getBooleanContents().
3277  bool isConstTrueVal(const SDNode *N) const;
3278 
3279  /// Return if the N is a constant or constant vector equal to the false value
3280  /// from getBooleanContents().
3281  bool isConstFalseVal(const SDNode *N) const;
3282 
3283  /// Return if \p N is a True value when extended to \p VT.
3284  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3285 
3286  /// Try to simplify a setcc built with the specified operands and cc. If it is
3287  /// unable to simplify it, return a null SDValue.
3288  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3289  bool foldBooleans, DAGCombinerInfo &DCI,
3290  const SDLoc &dl) const;
3291 
3292  // For targets which wrap address, unwrap for analysis.
3293  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3294 
3295  /// Returns true (and the GlobalValue and the offset) if the node is a
3296  /// GlobalAddress + offset.
3297  virtual bool
3298  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3299 
3300  /// This method will be invoked for all target nodes and for any
3301  /// target-independent nodes that the target has registered with invoke it
3302  /// for.
3303  ///
3304  /// The semantics are as follows:
3305  /// Return Value:
3306  /// SDValue.Val == 0 - No change was made
3307  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3308  /// otherwise - N should be replaced by the returned Operand.
3309  ///
3310  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3311  /// more complex transformations.
3312  ///
3313  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3314 
3315  /// Return true if it is profitable to move this shift by a constant amount
3316  /// though its operand, adjusting any immediate operands as necessary to
3317  /// preserve semantics. This transformation may not be desirable if it
3318  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3319  /// extraction in AArch64). By default, it returns true.
3320  ///
3321  /// @param N the shift node
3322  /// @param Level the current DAGCombine legalization level.
3323  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3324  CombineLevel Level) const {
3325  return true;
3326  }
3327 
3328  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3329  // to a shuffle and a truncate.
3330  // Example of such a combine:
3331  // v4i32 build_vector((extract_elt V, 1),
3332  // (extract_elt V, 3),
3333  // (extract_elt V, 5),
3334  // (extract_elt V, 7))
3335  // -->
3336  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3338  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3339  return false;
3340  }
3341 
3342  /// Return true if the target has native support for the specified value type
3343  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3344  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3345  /// and some i16 instructions are slow.
3346  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3347  // By default, assume all legal types are desirable.
3348  return isTypeLegal(VT);
3349  }
3350 
3351  /// Return true if it is profitable for dag combiner to transform a floating
3352  /// point op of specified opcode to a equivalent op of an integer
3353  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3354  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3355  EVT /*VT*/) const {
3356  return false;
3357  }
3358 
3359  /// This method query the target whether it is beneficial for dag combiner to
3360  /// promote the specified node. If true, it should return the desired
3361  /// promotion type by reference.
3362  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3363  return false;
3364  }
3365 
3366  /// Return true if the target supports swifterror attribute. It optimizes
3367  /// loads and stores to reading and writing a specific register.
3368  virtual bool supportSwiftError() const {
3369  return false;
3370  }
3371 
3372  /// Return true if the target supports that a subset of CSRs for the given
3373  /// machine function is handled explicitly via copies.
3374  virtual bool supportSplitCSR(MachineFunction *MF) const {
3375  return false;
3376  }
3377 
3378  /// Perform necessary initialization to handle a subset of CSRs explicitly
3379  /// via copies. This function is called at the beginning of instruction
3380  /// selection.
3382  llvm_unreachable("Not Implemented");
3383  }
3384 
3385  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3386  /// CSRs to virtual registers in the entry block, and copy them back to
3387  /// physical registers in the exit blocks. This function is called at the end
3388  /// of instruction selection.
3389  virtual void insertCopiesSplitCSR(
3391  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3392  llvm_unreachable("Not Implemented");
3393  }
3394 
3395  /// Return 1 if we can compute the negated form of the specified expression
3396  /// for the same cost as the expression itself, or 2 if we can compute the
3397  /// negated form more cheaply than the expression itself. Else return 0.
3398  virtual char isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
3399  bool LegalOperations, bool ForCodeSize,
3400  unsigned Depth = 0) const;
3401 
3402  /// If isNegatibleForFree returns true, return the newly negated expression.
3403  virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
3404  bool LegalOperations, bool ForCodeSize,
3405  unsigned Depth = 0) const;
3406 
3407  //===--------------------------------------------------------------------===//
3408  // Lowering methods - These methods must be implemented by targets so that
3409  // the SelectionDAGBuilder code knows how to lower these.
3410  //
3411 
3412  /// This hook must be implemented to lower the incoming (formal) arguments,
3413  /// described by the Ins array, into the specified DAG. The implementation
3414  /// should fill in the InVals array with legal-type argument values, and
3415  /// return the resulting token chain value.
3417  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3418  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3419  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3420  llvm_unreachable("Not Implemented");
3421  }
3422 
3423  /// This structure contains all information that is necessary for lowering
3424  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3425  /// needs to lower a call, and targets will see this struct in their LowerCall
3426  /// implementation.
3429  Type *RetTy = nullptr;
3430  bool RetSExt : 1;
3431  bool RetZExt : 1;
3432  bool IsVarArg : 1;
3433  bool IsInReg : 1;
3434  bool DoesNotReturn : 1;
3436  bool IsConvergent : 1;
3437  bool IsPatchPoint : 1;
3438 
3439  // IsTailCall should be modified by implementations of
3440  // TargetLowering::LowerCall that perform tail call conversions.
3441  bool IsTailCall = false;
3442 
3443  // Is Call lowering done post SelectionDAG type legalization.
3444  bool IsPostTypeLegalization = false;
3445 
3446  unsigned NumFixedArgs = -1;
3449  ArgListTy Args;
3457 
3459  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3460  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3461  IsPatchPoint(false), DAG(DAG) {}
3462 
3464  DL = dl;
3465  return *this;
3466  }
3467 
3469  Chain = InChain;
3470  return *this;
3471  }
3472 
3473  // setCallee with target/module-specific attributes
3475  SDValue Target, ArgListTy &&ArgsList) {
3476  RetTy = ResultType;
3477  Callee = Target;
3478  CallConv = CC;
3479  NumFixedArgs = ArgsList.size();
3480  Args = std::move(ArgsList);
3481 
3483  &(DAG.getMachineFunction()), CC, Args);
3484  return *this;
3485  }
3486 
3488  SDValue Target, ArgListTy &&ArgsList) {
3489  RetTy = ResultType;
3490  Callee = Target;
3491  CallConv = CC;
3492  NumFixedArgs = ArgsList.size();
3493  Args = std::move(ArgsList);
3494  return *this;
3495  }
3496 
3498  SDValue Target, ArgListTy &&ArgsList,
3499  ImmutableCallSite Call) {
3500  RetTy = ResultType;
3501 
3502  IsInReg = Call.hasRetAttr(Attribute::InReg);
3503  DoesNotReturn =
3504  Call.doesNotReturn() ||
3505  (!Call.isInvoke() &&
3506  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3507  IsVarArg = FTy->isVarArg();
3508  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3509  RetSExt = Call.hasRetAttr(Attribute::SExt);
3510  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3511 
3512  Callee = Target;
3513 
3514  CallConv = Call.getCallingConv();
3515  NumFixedArgs = FTy->getNumParams();
3516  Args = std::move(ArgsList);
3517 
3518  CS = Call;
3519 
3520  return *this;
3521  }
3522 
3524  IsInReg = Value;
3525  return *this;
3526  }
3527 
3529  DoesNotReturn = Value;
3530  return *this;
3531  }
3532 
3534  IsVarArg = Value;
3535  return *this;
3536  }
3537 
3539  IsTailCall = Value;
3540  return *this;
3541  }
3542 
3544  IsReturnValueUsed = !Value;
3545  return *this;
3546  }
3547 
3549  IsConvergent = Value;
3550  return *this;
3551  }
3552 
3554  RetSExt = Value;
3555  return *this;
3556  }
3557 
3559  RetZExt = Value;
3560  return *this;
3561  }
3562 
3564  IsPatchPoint = Value;
3565  return *this;
3566  }
3567 
3569  IsPostTypeLegalization = Value;
3570  return *this;
3571  }
3572 
3573  ArgListTy &getArgs() {
3574  return Args;
3575  }
3576  };
3577 
3578  /// This structure is used to pass arguments to makeLibCall function.
3580  // By passing type list before soften to makeLibCall, the target hook
3581  // shouldExtendTypeInLibCall can get the original type before soften.
3584  bool IsSExt : 1;
3585  bool DoesNotReturn : 1;
3588  bool IsSoften : 1;
3589 
3591  : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
3592  IsPostTypeLegalization(false), IsSoften(false) {}
3593 
3595  IsSExt = Value;
3596  return *this;
3597  }
3598 
3600  DoesNotReturn = Value;
3601  return *this;
3602  }
3603 
3605  IsReturnValueUsed = !Value;
3606  return *this;
3607  }
3608 
3610  IsPostTypeLegalization = Value;
3611  return *this;
3612  }
3613 
3615  bool Value = true) {
3616  OpsVTBeforeSoften = OpsVT;
3617  RetVTBeforeSoften = RetVT;
3618  IsSoften = Value;
3619  return *this;
3620  }
3621  };
3622 
3623  /// This function lowers an abstract call to a function into an actual call.
3624  /// This returns a pair of operands. The first element is the return value
3625  /// for the function (if RetTy is not VoidTy). The second element is the
3626  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3627  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3628 
3629  /// This hook must be implemented to lower calls into the specified
3630  /// DAG. The outgoing arguments to the call are described by the Outs array,
3631  /// and the values to be returned by the call are described by the Ins
3632  /// array. The implementation should fill in the InVals array with legal-type
3633  /// return values from the call, and return the resulting token chain value.
3634  virtual SDValue
3636  SmallVectorImpl<SDValue> &/*InVals*/) const {
3637  llvm_unreachable("Not Implemented");
3638  }
3639 
3640  /// Target-specific cleanup for formal ByVal parameters.
3641  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3642 
3643  /// This hook should be implemented to check whether the return values
3644  /// described by the Outs array can fit into the return registers. If false
3645  /// is returned, an sret-demotion is performed.
3646  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3647  MachineFunction &/*MF*/, bool /*isVarArg*/,
3648  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3649  LLVMContext &/*Context*/) const
3650  {
3651  // Return true by default to get preexisting behavior.
3652  return true;
3653  }
3654 
3655  /// This hook must be implemented to lower outgoing return values, described
3656  /// by the Outs array, into the specified DAG. The implementation should
3657  /// return the resulting token chain value.
3658  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3659  bool /*isVarArg*/,
3660  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3661  const SmallVectorImpl<SDValue> & /*OutVals*/,
3662  const SDLoc & /*dl*/,
3663  SelectionDAG & /*DAG*/) const {
3664  llvm_unreachable("Not Implemented");
3665  }
3666 
3667  /// Return true if result of the specified node is used by a return node
3668  /// only. It also compute and return the input chain for the tail call.
3669  ///
3670  /// This is used to determine whether it is possible to codegen a libcall as
3671  /// tail call at legalization time.
3672  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3673  return false;
3674  }
3675 
3676  /// Return true if the target may be able emit the call instruction as a tail
3677  /// call. This is used by optimization passes to determine if it's profitable
3678  /// to duplicate return instructions to enable tailcall optimization.
3679  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3680  return false;
3681  }
3682 
3683  /// Return the builtin name for the __builtin___clear_cache intrinsic
3684  /// Default is to invoke the clear cache library call
3685  virtual const char * getClearCacheBuiltinName() const {
3686  return "__clear_cache";
3687  }
3688 
3689  /// Return the register ID of the name passed in. Used by named register
3690  /// global variables extension. There is no target-independent behaviour
3691  /// so the default action is to bail.
3692  virtual Register getRegisterByName(const char* RegName, EVT VT,
3693  const MachineFunction &MF) const {
3694  report_fatal_error("Named registers not implemented for this target");
3695  }
3696 
3697  /// Return the type that should be used to zero or sign extend a
3698  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3699  /// require the return type to be promoted, but this is not true all the time,
3700  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3701  /// conventions. The frontend should handle this and include all of the
3702  /// necessary information.
3704  ISD::NodeType /*ExtendKind*/) const {
3705  EVT MinVT = getRegisterType(Context, MVT::i32);
3706  return VT.bitsLT(MinVT) ? MinVT : VT;
3707  }
3708 
3709  /// For some targets, an LLVM struct type must be broken down into multiple
3710  /// simple types, but the calling convention specifies that the entire struct
3711  /// must be passed in a block of consecutive registers.
3712  virtual bool
3714  bool isVarArg) const {
3715  return false;
3716  }
3717 
3718  /// For most targets, an LLVM type must be broken down into multiple
3719  /// smaller types. Usually the halves are ordered according to the endianness
3720  /// but for some platform that would break. So this method will default to
3721  /// matching the endianness but can be overridden.
3722  virtual bool
3724  return DL.isLittleEndian();
3725  }
3726 
3727  /// Returns a 0 terminated array of registers that can be safely used as
3728  /// scratch registers.
3729  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3730  return nullptr;
3731  }
3732 
3733  /// This callback is used to prepare for a volatile or atomic load.
3734  /// It takes a chain node as input and returns the chain for the load itself.
3735  ///
3736  /// Having a callback like this is necessary for targets like SystemZ,
3737  /// which allows a CPU to reuse the result of a previous load indefinitely,
3738  /// even if a cache-coherent store is performed by another CPU. The default
3739  /// implementation does nothing.
3741  SelectionDAG &DAG) const {
3742  return Chain;
3743  }
3744 
3745  /// This callback is used to inspect load/store instructions and add
3746  /// target-specific MachineMemOperand flags to them. The default
3747  /// implementation does nothing.
3750  }
3751 
3752  /// Should SelectionDAG lower an atomic store of the given kind as a normal
3753  /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3754  /// eventually migrate all targets to the using StoreSDNodes, but porting is
3755  /// being done target at a time.
3756  virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const {
3757  assert(SI.isAtomic() && "violated precondition");
3758  return false;
3759  }
3760 
3761  /// Should SelectionDAG lower an atomic load of the given kind as a normal
3762  /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3763  /// eventually migrate all targets to the using LoadSDNodes, but porting is
3764  /// being done target at a time.
3765  virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const {
3766  assert(LI.isAtomic() && "violated precondition");
3767  return false;
3768  }
3769 
3770 
3771  /// This callback is invoked by the type legalizer to legalize nodes with an
3772  /// illegal operand type but legal result types. It replaces the
3773  /// LowerOperation callback in the type Legalizer. The reason we can not do
3774  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3775  /// use this callback.
3776  ///
3777  /// TODO: Consider merging with ReplaceNodeResults.
3778  ///
3779  /// The target places new result values for the node in Results (their number
3780  /// and types must exactly match those of the original return values of
3781  /// the node), or leaves Results empty, which indicates that the node is not
3782  /// to be custom lowered after all.
3783  /// The default implementation calls LowerOperation.
3784  virtual void LowerOperationWrapper(SDNode *N,
3786  SelectionDAG &DAG) const;
3787 
3788  /// This callback is invoked for operations that are unsupported by the
3789  /// target, which are registered to use 'custom' lowering, and whose defined
3790  /// values are all legal. If the target has no operations that require custom
3791  /// lowering, it need not implement this. The default implementation of this
3792  /// aborts.
3793  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3794 
3795  /// This callback is invoked when a node result type is illegal for the
3796  /// target, and the operation was registered to use 'custom' lowering for that
3797  /// result type. The target places new result values for the node in Results
3798  /// (their number and types must exactly match those of the original return
3799  /// values of the node), or leaves Results empty, which indicates that the
3800  /// node is not to be custom lowered after all.
3801  ///
3802  /// If the target has no operations that require custom lowering, it need not
3803  /// implement this. The default implementation aborts.
3804  virtual void ReplaceNodeResults(SDNode * /*N*/,
3805  SmallVectorImpl<SDValue> &/*Results*/,
3806  SelectionDAG &/*DAG*/) const {
3807  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3808  }
3809 
3810  /// This method returns the name of a target specific DAG node.
3811  virtual const char *getTargetNodeName(unsigned Opcode) const;
3812 
3813  /// This method returns a target specific FastISel object, or null if the
3814  /// target does not support "fast" ISel.
3816  const TargetLibraryInfo *) const {
3817  return nullptr;
3818  }
3819 
3820  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3821  SelectionDAG &DAG) const;
3822 
3823  //===--------------------------------------------------------------------===//
3824  // Inline Asm Support hooks
3825  //
3826 
3827  /// This hook allows the target to expand an inline asm call to be explicit
3828  /// llvm code if it wants to. This is useful for turning simple inline asms
3829  /// into LLVM intrinsics, which gives the compiler more information about the
3830  /// behavior of the code.
3831  virtual bool ExpandInlineAsm(CallInst *) const {
3832  return false;
3833  }
3834 
3836  C_Register, // Constraint represents specific register(s).
3837  C_RegisterClass, // Constraint represents any of register(s) in class.
3838  C_Memory, // Memory constraint.
3839  C_Immediate, // Requires an immediate.
3840  C_Other, // Something else.
3841  C_Unknown // Unsupported constraint.
3842  };
3843 
3845  // Generic weights.
3846  CW_Invalid = -1, // No match.
3847  CW_Okay = 0, // Acceptable.
3848  CW_Good = 1, // Good weight.
3849  CW_Better = 2, // Better weight.
3850  CW_Best = 3, // Best weight.
3851 
3852  // Well-known weights.
3853  CW_SpecificReg = CW_Okay, // Specific register operands.
3854  CW_Register = CW_Good, // Register operands.
3855  CW_Memory = CW_Better, // Memory operands.
3856  CW_Constant = CW_Best, // Constant operand.
3857  CW_Default = CW_Okay // Default or don't know type.
3858  };
3859 
3860  /// This contains information for each constraint that we are lowering.
3862  /// This contains the actual string for the code, like "m". TargetLowering
3863  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3864  /// matches the operand.
3865  std::string ConstraintCode;
3866 
3867  /// Information about the constraint code, e.g. Register, RegisterClass,
3868  /// Memory, Other, Unknown.
3870 
3871  /// If this is the result output operand or a clobber, this is null,
3872  /// otherwise it is the incoming operand to the CallInst. This gets
3873  /// modified as the asm is processed.
3874  Value *CallOperandVal = nullptr;
3875 
3876  /// The ValueType for the operand value.
3877  MVT ConstraintVT = MVT::Other;
3878 
3879  /// Copy constructor for copying from a ConstraintInfo.
3881  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3882 
3883  /// Return true of this is an input operand that is a matching constraint
3884  /// like "4".
3885  bool isMatchingInputConstraint() const;
3886 
3887  /// If this is an input matching constraint, this method returns the output
3888  /// operand it matches.
3889  unsigned getMatchedOperand() const;
3890  };
3891 
3892  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3893 
3894  /// Split up the constraint string from the inline assembly value into the
3895  /// specific constraints and their prefixes, and also tie in the associated
3896  /// operand values. If this returns an empty vector, and if the constraint
3897  /// string itself isn't empty, there was an error parsing.
3898  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3899  const TargetRegisterInfo *TRI,
3900  ImmutableCallSite CS) const;
3901 
3902  /// Examine constraint type and operand type and determine a weight value.
3903  /// The operand object must already have been set up with the operand type.
3904  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3905  AsmOperandInfo &info, int maIndex) const;
3906 
3907  /// Examine constraint string and operand type and determine a weight value.
3908  /// The operand object must already have been set up with the operand type.
3909  virtual ConstraintWeight getSingleConstraintMatchWeight(
3910  AsmOperandInfo &info, const char *constraint) const;
3911 
3912  /// Determines the constraint code and constraint type to use for the specific
3913  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3914  /// If the actual operand being passed in is available, it can be passed in as
3915  /// Op, otherwise an empty SDValue can be passed.
3916  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3917  SDValue Op,
3918  SelectionDAG *DAG = nullptr) const;
3919 
3920  /// Given a constraint, return the type of constraint it is for this target.
3921  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3922 
3923  /// Given a physical register constraint (e.g. {edx}), return the register
3924  /// number and the register class for the register.
3925  ///
3926  /// Given a register class constraint, like 'r', if this corresponds directly
3927  /// to an LLVM register class, return a register of 0 and the register class
3928  /// pointer.
3929  ///
3930  /// This should only be used for C_Register constraints. On error, this
3931  /// returns a register number of 0 and a null register class pointer.
3932  virtual std::pair<unsigned, const TargetRegisterClass *>
3933  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3934  StringRef Constraint, MVT VT) const;
3935 
3936  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3937  if (ConstraintCode == "i")
3938  return InlineAsm::Constraint_i;
3939  else if (ConstraintCode == "m")
3940  return InlineAsm::Constraint_m;
3942  }
3943 
3944  /// Try to replace an X constraint, which matches anything, with another that
3945  /// has more specific requirements based on the type of the corresponding
3946  /// operand. This returns null if there is no replacement to make.
3947  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3948 
3949  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3950  /// add anything to Ops.
3951  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3952  std::vector<SDValue> &Ops,
3953  SelectionDAG &DAG) const;
3954 
3955  // Lower custom output constraints. If invalid, return SDValue().
3956  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3957  SDLoc DL,
3958  const AsmOperandInfo &OpInfo,
3959  SelectionDAG &DAG) const;
3960 
3961  //===--------------------------------------------------------------------===//
3962  // Div utility functions
3963  //
3964  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3965  SmallVectorImpl<SDNode *> &Created) const;
3966  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3967  SmallVectorImpl<SDNode *> &Created) const;
3968 
3969  /// Targets may override this function to provide custom SDIV lowering for
3970  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3971  /// assumes SDIV is expensive and replaces it with a series of other integer
3972  /// operations.
3973  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3974  SelectionDAG &DAG,
3975  SmallVectorImpl<SDNode *> &Created) const;
3976 
3977  /// Indicate whether this target prefers to combine FDIVs with the same
3978  /// divisor. If the transform should never be done, return zero. If the
3979  /// transform should be done, return the minimum number of divisor uses
3980  /// that must exist.
3981  virtual unsigned combineRepeatedFPDivisors() const {
3982  return 0;
3983  }
3984 
3985  /// Hooks for building estimates in place of slower divisions and square
3986  /// roots.
3987 
3988  /// Return either a square root or its reciprocal estimate value for the input
3989  /// operand.
3990  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3991  /// 'Enabled' as set by a potential default override attribute.
3992  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3993  /// refinement iterations required to generate a sufficient (though not
3994  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3995  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3996  /// algorithm implementation that uses either one or two constants.
3997  /// The boolean Reciprocal is used to select whether the estimate is for the
3998  /// square root of the input operand or the reciprocal of its square root.
3999  /// A target may choose to implement its own refinement within this function.
4000  /// If that's true, then return '0' as the number of RefinementSteps to avoid
4001  /// any further refinement of the estimate.
4002  /// An empty SDValue return means no estimate sequence can be created.
4004  int Enabled, int &RefinementSteps,
4005  bool &UseOneConstNR, bool Reciprocal) const {
4006  return SDValue();
4007  }
4008 
4009  /// Return a reciprocal estimate value for the input operand.
4010  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
4011  /// 'Enabled' as set by a potential default override attribute.
4012  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
4013  /// refinement iterations required to generate a sufficient (though not
4014  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
4015  /// A target may choose to implement its own refinement within this function.
4016  /// If that's true, then return '0' as the number of RefinementSteps to avoid
4017  /// any further refinement of the estimate.
4018  /// An empty SDValue return means no estimate sequence can be created.
4020  int Enabled, int &RefinementSteps) const {
4021  return SDValue();
4022  }
4023 
4024  //===--------------------------------------------------------------------===//
4025  // Legalization utility functions
4026  //
4027 
4028  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
4029  /// respectively, each computing an n/2-bit part of the result.
4030  /// \param Result A vector that will be filled with the parts of the result
4031  /// in little-endian order.
4032  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4033  /// if you want to control how low bits are extracted from the LHS.
4034  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4035  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4036  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4037  /// \returns true if the node has been expanded, false if it has not
4038  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
4039  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
4041  SDValue LL = SDValue(), SDValue LH = SDValue(),
4042  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4043 
4044  /// Expand a MUL into two nodes. One that computes the high bits of
4045  /// the result and one that computes the low bits.
4046  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
4047  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4048  /// if you want to control how low bits are extracted from the LHS.
4049  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4050  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4051  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4052  /// \returns true if the node has been expanded. false if it has not
4053  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
4054  SelectionDAG &DAG, MulExpansionKind Kind,
4055  SDValue LL = SDValue(), SDValue LH = SDValue(),
4056  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4057 
4058  /// Expand funnel shift.
4059  /// \param N Node to expand
4060  /// \param Result output after conversion
4061  /// \returns True, if the expansion was successful, false otherwise
4062  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4063 
4064  /// Expand rotations.
4065  /// \param N Node to expand
4066  /// \param Result output after conversion
4067  /// \returns True, if the expansion was successful, false otherwise
4068  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4069 
4070  /// Expand float(f32) to SINT(i64) conversion
4071  /// \param N Node to expand
4072  /// \param Result output after conversion
4073  /// \returns True, if the expansion was successful, false otherwise
4074  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4075 
4076  /// Expand float to UINT conversion
4077  /// \param N Node to expand
4078  /// \param Result output after conversion
4079  /// \returns True, if the expansion was successful, false otherwise
4080  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const;
4081 
4082  /// Expand UINT(i64) to double(f64) conversion
4083  /// \param N Node to expand
4084  /// \param Result output after conversion
4085  /// \returns True, if the expansion was successful, false otherwise
4086  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4087 
4088  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
4089  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
4090 
4091  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4092  /// vector nodes can only succeed if all operations are legal/custom.
4093  /// \param N Node to expand
4094  /// \param Result output after conversion
4095  /// \returns True, if the expansion was successful, false otherwise
4096  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4097 
4098  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4099  /// vector nodes can only succeed if all operations are legal/custom.
4100  /// \param N Node to expand
4101  /// \param Result output after conversion
4102  /// \returns True, if the expansion was successful, false otherwise
4103  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4104 
4105  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4106  /// vector nodes can only succeed if all operations are legal/custom.
4107  /// \param N Node to expand
4108  /// \param Result output after conversion
4109  /// \returns True, if the expansion was successful, false otherwise
4110  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4111 
4112  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4113  /// vector nodes can only succeed if all operations are legal/custom.
4114  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4115  /// \param N Node to expand
4116  /// \param Result output after conversion
4117  /// \returns True, if the expansion was successful, false otherwise
4118  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4119 
4120  /// Turn load of vector type into a load of the individual elements.
4121  /// \param LD load to expand
4122  /// \returns MERGE_VALUEs of the scalar loads with their chains.
4123  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
4124 
4125  // Turn a store of a vector type into stores of the individual elements.
4126  /// \param ST Store with a vector value type
4127  /// \returns MERGE_VALUs of the individual store chains.
4129 
4130  /// Expands an unaligned load to 2 half-size loads for an integer, and
4131  /// possibly more for vectors.
4132  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
4133  SelectionDAG &DAG) const;
4134 
4135  /// Expands an unaligned store to 2 half-size stores for integer values, and
4136  /// possibly more for vectors.
4137  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
4138 
4139  /// Increments memory address \p Addr according to the type of the value
4140  /// \p DataVT that should be stored. If the data is stored in compressed
4141  /// form, the memory address should be incremented according to the number of
4142  /// the stored elements. This number is equal to the number of '1's bits
4143  /// in the \p Mask.
4144  /// \p DataVT is a vector type. \p Mask is a vector value.
4145  /// \p DataVT and \p Mask have the same number of vector elements.
4146  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
4147  EVT DataVT, SelectionDAG &DAG,
4148  bool IsCompressedMemory) const;
4149 
4150  /// Get a pointer to vector element \p Idx located in memory for a vector of
4151  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4152  /// bounds the returned pointer is unspecified, but will be within the vector
4153  /// bounds.
4154  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4155  SDValue Index) const;
4156 
4157  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4158  /// method accepts integers as its arguments.
4159  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
4160 
4161  /// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This
4162  /// method accepts integers as its arguments.
4163  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
4164 
4165  /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4166  /// always suceeds and populates the Result and Overflow arguments.
4167  void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4168  SelectionDAG &DAG) const;
4169 
4170  /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4171  /// always suceeds and populates the Result and Overflow arguments.
4172  void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4173  SelectionDAG &DAG) const;
4174 
4175  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4176  /// expansion was successful and populates the Result and Overflow arguments.
4177  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4178  SelectionDAG &DAG) const;
4179 
4180  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4181  /// only the first Count elements of the vector are used.
4182  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
4183 
4184  //===--------------------------------------------------------------------===//
4185  // Instruction Emitting Hooks
4186  //
4187 
4188  /// This method should be implemented by targets that mark instructions with
4189  /// the 'usesCustomInserter' flag. These instructions are special in various
4190  /// ways, which require special support to insert. The specified MachineInstr
4191  /// is created but not inserted into any basic blocks, and this method is
4192  /// called to expand it into a sequence of instructions, potentially also
4193  /// creating new basic blocks and control flow.
4194  /// As long as the returned basic block is different (i.e., we created a new
4195  /// one), the custom inserter is free to modify the rest of \p MBB.
4196  virtual MachineBasicBlock *
4197  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4198 
4199  /// This method should be implemented by targets that mark instructions with
4200  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4201  /// instruction selection by target hooks. e.g. To fill in optional defs for
4202  /// ARM 's' setting instructions.
4203  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4204  SDNode *Node) const;
4205 
4206  /// If this function returns true, SelectionDAGBuilder emits a
4207  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4208  virtual bool useLoadStackGuardNode() const {
4209  return false;
4210  }
4211 
4213  const SDLoc &DL) const {
4214  llvm_unreachable("not implemented for this target");
4215  }
4216 
4217  /// Lower TLS global address SDNode for target independent emulated TLS model.
4218  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4219  SelectionDAG &DAG) const;
4220 
4221  /// Expands target specific indirect branch for the case of JumpTable
4222  /// expanasion.
4224  SelectionDAG &DAG) const {
4225  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4226  }
4227 
4228  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4229  // If we're comparing for equality to zero and isCtlzFast is true, expose the
4230  // fact that this can be implemented as a ctlz/srl pair, so that the dag
4231  // combiner can fold the new nodes.
4232  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4233 
4234 private:
4235  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4236  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4237  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4238  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4239 
4240  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4241  SDValue N1, ISD::CondCode Cond,
4242  DAGCombinerInfo &DCI,
4243  const SDLoc &DL) const;
4244 
4245  // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4246  SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
4247  EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
4248  DAGCombinerInfo &DCI, const SDLoc &DL) const;
4249 
4250  SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4251  SDValue CompTargetNode, ISD::CondCode Cond,
4252  DAGCombinerInfo &DCI, const SDLoc &DL,
4253  SmallVectorImpl<SDNode *> &Created) const;
4254  SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4255  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4256  const SDLoc &DL) const;
4257 
4258  SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
4259  SDValue CompTargetNode, ISD::CondCode Cond,
4260  DAGCombinerInfo &DCI, const SDLoc &DL,
4261  SmallVectorImpl<SDNode *> &Created) const;
4262  SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4263  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4264  const SDLoc &DL) const;
4265 };
4266 
4267 /// Given an LLVM IR type and return type attributes, compute the return value
4268 /// EVTs and flags, and optionally also the offsets, if the return value is
4269 /// being lowered to memory.
4272  const TargetLowering &TLI, const DataLayout &DL);
4273 
4274 } // end namespace llvm
4275 
4276 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:570
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:914
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:623
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:403
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT, bool Value=true)
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
bool isAtomic() const
Return true if this instruction has an AtomicOrdering of unordered or higher.
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:634
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:622
This structure is used to pass arguments to makeLibCall function.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:538
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
virtual bool shouldExtendTypeInLibCall(EVT Type) const
Returns true if arguments should be extended in lib calls.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
MakeLibCallOptions & setIsPostTypeLegalization(bool Value=true)
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:380
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
virtual Register getRegisterByName(const char *RegName, EVT VT, const MachineFunction &MF) const
Return the register ID of the name passed in.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:393
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1100
virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const
Should SelectionDAG lower an atomic load of the given kind as a normal LoadSDNode (as opposed to an A...
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:169
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:416
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:701
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
Align getMinFunctionAlignment() const
Return the minimum function alignment.
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const
Should SelectionDAG lower an atomic store of the given kind as a normal StoreSDNode (as opposed to an...
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:274
void * PointerTy
Definition: GenericValue.h:21
virtual LLT getOptimalMemOpLLT(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
LLT returning variant.
bool hasOneUse() const
Return true if there is exactly one use of this node.
A description of a memory reference used in the backend.
Definition: BitVector.h:937
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Shift and rotation operations.
Definition: ISDOpcodes.h:442
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
virtual bool mergeStoresAfterLegalization(EVT MemVT) const
Allow store merging for the specified type after legalization in addition to before legalization...
SimpleValueType SimpleTy
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:65
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
InstrTy * getInstruction() const
Definition: CallSite.h:96
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:108
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:414
static cl::opt< unsigned > MaxLoadsPerMemcmpOptSize("max-loads-per-memcmp-opt-size", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz"))
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const
Return true if sinking I&#39;s operands to the same basic block as I is profitable, e.g.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
void setMinFunctionAlignment(Align Alignment)
Set the target&#39;s minimum function alignment.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:128
SmallVector< ISD::OutputArg, 32 > Outs
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool hasBitTest(SDValue X, SDValue Y) const
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:233
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
An instruction for storing to memory.
Definition: Instructions.h:325
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.