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TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
52 #include "llvm/Support/Casting.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <climits>
59 #include <cstdint>
60 #include <iterator>
61 #include <map>
62 #include <string>
63 #include <utility>
64 #include <vector>
65 
66 namespace llvm {
67 
68 class BranchProbability;
69 class CCState;
70 class CCValAssign;
71 class Constant;
72 class FastISel;
73 class FunctionLoweringInfo;
74 class GlobalValue;
75 class IntrinsicInst;
76 struct KnownBits;
77 class LLVMContext;
78 class MachineBasicBlock;
79 class MachineFunction;
80 class MachineInstr;
81 class MachineJumpTableInfo;
82 class MachineLoop;
83 class MachineRegisterInfo;
84 class MCContext;
85 class MCExpr;
86 class Module;
87 class TargetRegisterClass;
88 class TargetLibraryInfo;
89 class TargetRegisterInfo;
90 class Value;
91 
92 namespace Sched {
93 
94  enum Preference {
95  None, // No preference
96  Source, // Follow source order.
97  RegPressure, // Scheduling for lowest register pressure.
98  Hybrid, // Scheduling for both latency and register pressure.
99  ILP, // Scheduling for ILP in low register pressure mode.
100  VLIW // Scheduling for VLIW targets.
101  };
102 
103 } // end namespace Sched
104 
105 /// This base class for TargetLowering contains the SelectionDAG-independent
106 /// parts that can be used from the rest of CodeGen.
108 public:
109  /// This enum indicates whether operations are valid for a target, and if not,
110  /// what action should be used to make them valid.
111  enum LegalizeAction : uint8_t {
112  Legal, // The target natively supports this operation.
113  Promote, // This operation should be executed in a larger type.
114  Expand, // Try to expand this to other ops, otherwise use a libcall.
115  LibCall, // Don't try to expand this to other ops, always use a libcall.
116  Custom // Use the LowerOperation hook to implement custom lowering.
117  };
118 
119  /// This enum indicates whether a types are legal for a target, and if not,
120  /// what action should be used to make them valid.
121  enum LegalizeTypeAction : uint8_t {
122  TypeLegal, // The target natively supports this type.
123  TypePromoteInteger, // Replace this integer with a larger one.
124  TypeExpandInteger, // Split this integer into two of half the size.
125  TypeSoftenFloat, // Convert this float to a same size integer type,
126  // if an operation is not supported in target HW.
127  TypeExpandFloat, // Split this float into two of half the size.
128  TypeScalarizeVector, // Replace this one-element vector with its element.
129  TypeSplitVector, // Split this vector into two of half the size.
130  TypeWidenVector, // This vector should be widened into a larger vector.
131  TypePromoteFloat // Replace this float with a larger one.
132  };
133 
134  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135  /// in order to type-legalize it.
136  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 
138  /// Enum that describes how the target represents true/false values.
140  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143  };
144 
145  /// Enum that describes what type of support for selects the target has.
147  ScalarValSelect, // The target supports scalar selects (ex: cmov).
148  ScalarCondVectorVal, // The target supports selects with a scalar condition
149  // and vector values (ex: cmov).
150  VectorMaskSelect // The target supports vector selects with a vector
151  // mask (ex: x86 blends).
152  };
153 
154  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155  /// to, if at all. Exists because different targets have different levels of
156  /// support for these atomic instructions, and also have different options
157  /// w.r.t. what they should expand to.
158  enum class AtomicExpansionKind {
159  None, // Don't expand the instruction.
160  LLSC, // Expand the instruction into loadlinked/storeconditional; used
161  // by ARM/AArch64.
162  LLOnly, // Expand the (load) instruction into just a load-linked, which has
163  // greater atomic guarantees than a normal load.
164  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191  Type *ByValType = nullptr;
192 
194  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196  IsSwiftSelf(false), IsSwiftError(false) {}
197 
198  void setAttributes(const CallBase *Call, unsigned ArgIdx);
199 
200  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
201  return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
202  }
203  };
204  using ArgListTy = std::vector<ArgListEntry>;
205 
206  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
207  ArgListTy &Args) const {};
208 
210  switch (Content) {
211  case UndefinedBooleanContent:
212  // Extend by adding rubbish bits.
213  return ISD::ANY_EXTEND;
214  case ZeroOrOneBooleanContent:
215  // Extend by adding zero bits.
216  return ISD::ZERO_EXTEND;
217  case ZeroOrNegativeOneBooleanContent:
218  // Extend by copying the sign bit.
219  return ISD::SIGN_EXTEND;
220  }
221  llvm_unreachable("Invalid content kind");
222  }
223 
224  /// NOTE: The TargetMachine owns TLOF.
225  explicit TargetLoweringBase(const TargetMachine &TM);
226  TargetLoweringBase(const TargetLoweringBase &) = delete;
227  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
228  virtual ~TargetLoweringBase() = default;
229 
230 protected:
231  /// Initialize all of the actions to default values.
232  void initActions();
233 
234 public:
235  const TargetMachine &getTargetMachine() const { return TM; }
236 
237  virtual bool useSoftFloat() const { return false; }
238 
239  /// Return the pointer type for the given address space, defaults to
240  /// the pointer type from the data layout.
241  /// FIXME: The default needs to be removed once all the code is updated.
242  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
244  }
245 
246  /// Return the in-memory pointer type for the given address space, defaults to
247  /// the pointer type from the data layout. FIXME: The default needs to be
248  /// removed once all the code is updated.
249  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
251  }
252 
253  /// Return the type for frame index, which is determined by
254  /// the alloca address space specified through the data layout.
255  MVT getFrameIndexTy(const DataLayout &DL) const {
256  return getPointerTy(DL, DL.getAllocaAddrSpace());
257  }
258 
259  /// Return the type for operands of fence.
260  /// TODO: Let fence operands be of i32 type and remove this.
261  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
262  return getPointerTy(DL);
263  }
264 
265  /// EVT is not used in-tree, but is used by out-of-tree target.
266  /// A documentation for this function would be nice...
267  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
268 
269  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
270  bool LegalTypes = true) const;
271 
272  /// Returns the type to be used for the index operand of:
273  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
274  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
275  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
276  return getPointerTy(DL);
277  }
278 
279  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
280  return true;
281  }
282 
283  /// Return true if it is profitable to convert a select of FP constants into
284  /// a constant pool load whose address depends on the select condition. The
285  /// parameter may be used to differentiate a select with FP compare from
286  /// integer compare.
287  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
288  return true;
289  }
290 
291  /// Return true if multiple condition registers are available.
293  return HasMultipleConditionRegisters;
294  }
295 
296  /// Return true if the target has BitExtract instructions.
297  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
298 
299  /// Return the preferred vector type legalization action.
302  // The default action for one element vectors is to scalarize
303  if (VT.getVectorNumElements() == 1)
304  return TypeScalarizeVector;
305  // The default action for an odd-width vector is to widen.
306  if (!VT.isPow2VectorType())
307  return TypeWidenVector;
308  // The default action for other vectors is to promote
309  return TypePromoteInteger;
310  }
311 
312  // There are two general methods for expanding a BUILD_VECTOR node:
313  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
314  // them together.
315  // 2. Build the vector on the stack and then load it.
316  // If this function returns true, then method (1) will be used, subject to
317  // the constraint that all of the necessary shuffles are legal (as determined
318  // by isShuffleMaskLegal). If this function returns false, then method (2) is
319  // always used. The vector type, and the number of defined values, are
320  // provided.
321  virtual bool
323  unsigned DefinedValues) const {
324  return DefinedValues < 3;
325  }
326 
327  /// Return true if integer divide is usually cheaper than a sequence of
328  /// several shifts, adds, and multiplies for this target.
329  /// The definition of "cheaper" may depend on whether we're optimizing
330  /// for speed or for size.
331  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
332 
333  /// Return true if the target can handle a standalone remainder operation.
334  virtual bool hasStandaloneRem(EVT VT) const {
335  return true;
336  }
337 
338  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
339  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
340  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
341  return false;
342  }
343 
344  /// Reciprocal estimate status values used by the functions below.
345  enum ReciprocalEstimate : int {
346  Unspecified = -1,
347  Disabled = 0,
349  };
350 
351  /// Return a ReciprocalEstimate enum value for a square root of the given type
352  /// based on the function's attributes. If the operation is not overridden by
353  /// the function's attributes, "Unspecified" is returned and target defaults
354  /// are expected to be used for instruction selection.
355  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
356 
357  /// Return a ReciprocalEstimate enum value for a division of the given type
358  /// based on the function's attributes. If the operation is not overridden by
359  /// the function's attributes, "Unspecified" is returned and target defaults
360  /// are expected to be used for instruction selection.
361  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
362 
363  /// Return the refinement step count for a square root of the given type based
364  /// on the function's attributes. If the operation is not overridden by
365  /// the function's attributes, "Unspecified" is returned and target defaults
366  /// are expected to be used for instruction selection.
367  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
368 
369  /// Return the refinement step count for a division of the given type based
370  /// on the function's attributes. If the operation is not overridden by
371  /// the function's attributes, "Unspecified" is returned and target defaults
372  /// are expected to be used for instruction selection.
373  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
374 
375  /// Returns true if target has indicated at least one type should be bypassed.
376  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
377 
378  /// Returns map of slow types for division or remainder with corresponding
379  /// fast types
381  return BypassSlowDivWidths;
382  }
383 
384  /// Return true if Flow Control is an expensive operation that should be
385  /// avoided.
386  bool isJumpExpensive() const { return JumpIsExpensive; }
387 
388  /// Return true if selects are only cheaper than branches if the branch is
389  /// unlikely to be predicted right.
391  return PredictableSelectIsExpensive;
392  }
393 
394  /// If a branch or a select condition is skewed in one direction by more than
395  /// this factor, it is very likely to be predicted correctly.
396  virtual BranchProbability getPredictableBranchThreshold() const;
397 
398  /// Return true if the following transform is beneficial:
399  /// fold (conv (load x)) -> (load (conv*)x)
400  /// On architectures that don't natively support some vector loads
401  /// efficiently, casting the load to a smaller vector of larger types and
402  /// loading is more efficient, however, this can be undone by optimizations in
403  /// dag combiner.
404  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
405  EVT BitcastVT) const {
406  // Don't do if we could do an indexed load on the original type, but not on
407  // the new one.
408  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
409  return true;
410 
411  MVT LoadMVT = LoadVT.getSimpleVT();
412 
413  // Don't bother doing this if it's just going to be promoted again later, as
414  // doing so might interfere with other combines.
415  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
416  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
417  return false;
418 
419  return true;
420  }
421 
422  /// Return true if the following transform is beneficial:
423  /// (store (y (conv x)), y*)) -> (store x, (x*))
424  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
425  // Default to the same logic as loads.
426  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
427  }
428 
429  /// Return true if it is expected to be cheaper to do a store of a non-zero
430  /// vector constant with the given size and type for the address space than to
431  /// store the individual scalar element constants.
432  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
433  unsigned NumElem,
434  unsigned AddrSpace) const {
435  return false;
436  }
437 
438  /// Allow store merging for the specified type after legalization in addition
439  /// to before legalization. This may transform stores that do not exist
440  /// earlier (for example, stores created from intrinsics).
441  virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
442  return true;
443  }
444 
445  /// Returns if it's reasonable to merge stores to MemVT size.
446  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
447  const SelectionDAG &DAG) const {
448  return true;
449  }
450 
451  /// Return true if it is cheap to speculate a call to intrinsic cttz.
452  virtual bool isCheapToSpeculateCttz() const {
453  return false;
454  }
455 
456  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
457  virtual bool isCheapToSpeculateCtlz() const {
458  return false;
459  }
460 
461  /// Return true if ctlz instruction is fast.
462  virtual bool isCtlzFast() const {
463  return false;
464  }
465 
466  /// Return true if it is safe to transform an integer-domain bitwise operation
467  /// into the equivalent floating-point operation. This should be set to true
468  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
469  /// type.
470  virtual bool hasBitPreservingFPLogic(EVT VT) const {
471  return false;
472  }
473 
474  /// Return true if it is cheaper to split the store of a merged int val
475  /// from a pair of smaller values into multiple stores.
476  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
477  return false;
478  }
479 
480  /// Return if the target supports combining a
481  /// chain like:
482  /// \code
483  /// %andResult = and %val1, #mask
484  /// %icmpResult = icmp %andResult, 0
485  /// \endcode
486  /// into a single machine instruction of a form like:
487  /// \code
488  /// cc = test %register, #mask
489  /// \endcode
490  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
491  return false;
492  }
493 
494  /// Use bitwise logic to make pairs of compares more efficient. For example:
495  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
496  /// This should be true when it takes more than one instruction to lower
497  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
498  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
499  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
500  return false;
501  }
502 
503  /// Return the preferred operand type if the target has a quick way to compare
504  /// integer values of the given size. Assume that any legal integer type can
505  /// be compared efficiently. Targets may override this to allow illegal wide
506  /// types to return a vector type if there is support to compare that type.
507  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
508  MVT VT = MVT::getIntegerVT(NumBits);
509  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
510  }
511 
512  /// Return true if the target should transform:
513  /// (X & Y) == Y ---> (~X & Y) == 0
514  /// (X & Y) != Y ---> (~X & Y) != 0
515  ///
516  /// This may be profitable if the target has a bitwise and-not operation that
517  /// sets comparison flags. A target may want to limit the transformation based
518  /// on the type of Y or if Y is a constant.
519  ///
520  /// Note that the transform will not occur if Y is known to be a power-of-2
521  /// because a mask and compare of a single bit can be handled by inverting the
522  /// predicate, for example:
523  /// (X & 8) == 8 ---> (X & 8) != 0
524  virtual bool hasAndNotCompare(SDValue Y) const {
525  return false;
526  }
527 
528  /// Return true if the target has a bitwise and-not operation:
529  /// X = ~A & B
530  /// This can be used to simplify select or other instructions.
531  virtual bool hasAndNot(SDValue X) const {
532  // If the target has the more complex version of this operation, assume that
533  // it has this operation too.
534  return hasAndNotCompare(X);
535  }
536 
537  /// There are two ways to clear extreme bits (either low or high):
538  /// Mask: x & (-1 << y) (the instcombine canonical form)
539  /// Shifts: x >> y << y
540  /// Return true if the variant with 2 variable shifts is preferred.
541  /// Return false if there is no preference.
543  // By default, let's assume that no one prefers shifts.
544  return false;
545  }
546 
547  /// Return true if it is profitable to fold a pair of shifts into a mask.
548  /// This is usually true on most targets. But some targets, like Thumb1,
549  /// have immediate shift instructions, but no immediate "and" instruction;
550  /// this makes the fold unprofitable.
552  CombineLevel Level) const {
553  return true;
554  }
555 
556  /// Should we tranform the IR-optimal check for whether given truncation
557  /// down into KeptBits would be truncating or not:
558  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
559  /// Into it's more traditional form:
560  /// ((%x << C) a>> C) dstcond %x
561  /// Return true if we should transform.
562  /// Return false if there is no preference.
564  unsigned KeptBits) const {
565  // By default, let's assume that no one prefers shifts.
566  return false;
567  }
568 
569  /// Return true if the target wants to use the optimization that
570  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
571  /// promotedInst1(...(promotedInstN(ext(load)))).
572  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
573 
574  /// Return true if the target can combine store(extractelement VectorTy,
575  /// Idx).
576  /// \p Cost[out] gives the cost of that transformation when this is true.
577  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
578  unsigned &Cost) const {
579  return false;
580  }
581 
582  /// Return true if inserting a scalar into a variable element of an undef
583  /// vector is more efficiently handled by splatting the scalar instead.
584  virtual bool shouldSplatInsEltVarIndex(EVT) const {
585  return false;
586  }
587 
588  /// Return true if target always beneficiates from combining into FMA for a
589  /// given value type. This must typically return false on targets where FMA
590  /// takes more cycles to execute than FADD.
591  virtual bool enableAggressiveFMAFusion(EVT VT) const {
592  return false;
593  }
594 
595  /// Return the ValueType of the result of SETCC operations.
596  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
597  EVT VT) const;
598 
599  /// Return the ValueType for comparison libcalls. Comparions libcalls include
600  /// floating point comparion calls, and Ordered/Unordered check calls on
601  /// floating point numbers.
602  virtual
603  MVT::SimpleValueType getCmpLibcallReturnType() const;
604 
605  /// For targets without i1 registers, this gives the nature of the high-bits
606  /// of boolean values held in types wider than i1.
607  ///
608  /// "Boolean values" are special true/false values produced by nodes like
609  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
610  /// Not to be confused with general values promoted from i1. Some cpus
611  /// distinguish between vectors of boolean and scalars; the isVec parameter
612  /// selects between the two kinds. For example on X86 a scalar boolean should
613  /// be zero extended from i1, while the elements of a vector of booleans
614  /// should be sign extended from i1.
615  ///
616  /// Some cpus also treat floating point types the same way as they treat
617  /// vectors instead of the way they treat scalars.
618  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
619  if (isVec)
620  return BooleanVectorContents;
621  return isFloat ? BooleanFloatContents : BooleanContents;
622  }
623 
625  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
626  }
627 
628  /// Return target scheduling preference.
630  return SchedPreferenceInfo;
631  }
632 
633  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
634  /// for different nodes. This function returns the preference (or none) for
635  /// the given node.
637  return Sched::None;
638  }
639 
640  /// Return the register class that should be used for the specified value
641  /// type.
642  virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
643  (void)isDivergent;
644  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
645  assert(RC && "This value type is not natively supported!");
646  return RC;
647  }
648 
649  /// Allows target to decide about the register class of the
650  /// specific value that is live outside the defining block.
651  /// Returns true if the value needs uniform register class.
653  const Value *) const {
654  return false;
655  }
656 
657  /// Return the 'representative' register class for the specified value
658  /// type.
659  ///
660  /// The 'representative' register class is the largest legal super-reg
661  /// register class for the register class of the value type. For example, on
662  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
663  /// register class is GR64 on x86_64.
664  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
665  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
666  return RC;
667  }
668 
669  /// Return the cost of the 'representative' register class for the specified
670  /// value type.
671  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
672  return RepRegClassCostForVT[VT.SimpleTy];
673  }
674 
675  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
676  /// instructions, and false if a library call is preferred (e.g for code-size
677  /// reasons).
678  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
679  return true;
680  }
681 
682  /// Return true if the target has native support for the specified value type.
683  /// This means that it has a register that directly holds it without
684  /// promotions or expansions.
685  bool isTypeLegal(EVT VT) const {
686  assert(!VT.isSimple() ||
687  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
688  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
689  }
690 
692  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
693  /// that indicates how instruction selection should deal with the type.
694  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
695 
696  public:
698  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
699  TypeLegal);
700  }
701 
703  return ValueTypeActions[VT.SimpleTy];
704  }
705 
707  ValueTypeActions[VT.SimpleTy] = Action;
708  }
709  };
710 
712  return ValueTypeActions;
713  }
714 
715  /// Return how we should legalize values of this type, either it is already
716  /// legal (return 'Legal') or we need to promote it to a larger type (return
717  /// 'Promote'), or we need to expand it into multiple registers of smaller
718  /// integer type (return 'Expand'). 'Custom' is not an option.
720  return getTypeConversion(Context, VT).first;
721  }
723  return ValueTypeActions.getTypeAction(VT);
724  }
725 
726  /// For types supported by the target, this is an identity function. For
727  /// types that must be promoted to larger types, this returns the larger type
728  /// to promote to. For integer types that are larger than the largest integer
729  /// register, this contains one step in the expansion to get to the smaller
730  /// register. For illegal floating point types, this returns the integer type
731  /// to transform to.
732  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
733  return getTypeConversion(Context, VT).second;
734  }
735 
736  /// For types supported by the target, this is an identity function. For
737  /// types that must be expanded (i.e. integer types that are larger than the
738  /// largest integer register or illegal floating point types), this returns
739  /// the largest legal type it will be expanded to.
740  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
741  assert(!VT.isVector());
742  while (true) {
743  switch (getTypeAction(Context, VT)) {
744  case TypeLegal:
745  return VT;
746  case TypeExpandInteger:
747  VT = getTypeToTransformTo(Context, VT);
748  break;
749  default:
750  llvm_unreachable("Type is not legal nor is it to be expanded!");
751  }
752  }
753  }
754 
755  /// Vector types are broken down into some number of legal first class types.
756  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
757  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
758  /// turns into 4 EVT::i32 values with both PPC and X86.
759  ///
760  /// This method returns the number of registers needed, and the VT for each
761  /// register. It also returns the VT and quantity of the intermediate values
762  /// before they are promoted/expanded.
763  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
764  EVT &IntermediateVT,
765  unsigned &NumIntermediates,
766  MVT &RegisterVT) const;
767 
768  /// Certain targets such as MIPS require that some types such as vectors are
769  /// always broken down into scalars in some contexts. This occurs even if the
770  /// vector type is legal.
772  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
773  unsigned &NumIntermediates, MVT &RegisterVT) const {
774  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
775  RegisterVT);
776  }
777 
778  struct IntrinsicInfo {
779  unsigned opc = 0; // target opcode
780  EVT memVT; // memory VT
781 
782  // value representing memory location
784 
785  int offset = 0; // offset off of ptrVal
786  unsigned size = 0; // the size of the memory location
787  // (taken from memVT if zero)
788  unsigned align = 1; // alignment
789 
791  IntrinsicInfo() = default;
792  };
793 
794  /// Given an intrinsic, checks if on the target the intrinsic will need to map
795  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
796  /// true and store the intrinsic information into the IntrinsicInfo that was
797  /// passed to the function.
798  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
799  MachineFunction &,
800  unsigned /*Intrinsic*/) const {
801  return false;
802  }
803 
804  /// Returns true if the target can instruction select the specified FP
805  /// immediate natively. If false, the legalizer will materialize the FP
806  /// immediate as a load from a constant pool.
807  virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
808  bool ForCodeSize = false) const {
809  return false;
810  }
811 
812  /// Targets can use this to indicate that they only support *some*
813  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
814  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
815  /// legal.
816  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
817  return true;
818  }
819 
820  /// Returns true if the operation can trap for the value type.
821  ///
822  /// VT must be a legal type. By default, we optimistically assume most
823  /// operations don't trap except for integer divide and remainder.
824  virtual bool canOpTrap(unsigned Op, EVT VT) const;
825 
826  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
827  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
828  /// constant pool entry.
829  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
830  EVT /*VT*/) const {
831  return false;
832  }
833 
834  /// Return how this operation should be treated: either it is legal, needs to
835  /// be promoted to a larger size, needs to be expanded to some other code
836  /// sequence, or the target has a custom expander for it.
837  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
838  if (VT.isExtended()) return Expand;
839  // If a target-specific SDNode requires legalization, require the target
840  // to provide custom legalization for it.
841  if (Op >= array_lengthof(OpActions[0])) return Custom;
842  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
843  }
844 
845  /// Custom method defined by each target to indicate if an operation which
846  /// may require a scale is supported natively by the target.
847  /// If not, the operation is illegal.
848  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
849  unsigned Scale) const {
850  return false;
851  }
852 
853  /// Some fixed point operations may be natively supported by the target but
854  /// only for specific scales. This method allows for checking
855  /// if the width is supported by the target for a given operation that may
856  /// depend on scale.
858  unsigned Scale) const {
859  auto Action = getOperationAction(Op, VT);
860  if (Action != Legal)
861  return Action;
862 
863  // This operation is supported in this type but may only work on specific
864  // scales.
865  bool Supported;
866  switch (Op) {
867  default:
868  llvm_unreachable("Unexpected fixed point operation.");
869  case ISD::SMULFIX:
870  case ISD::SMULFIXSAT:
871  case ISD::UMULFIX:
872  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
873  break;
874  }
875 
876  return Supported ? Action : Expand;
877  }
878 
880  unsigned EqOpc;
881  switch (Op) {
882  default: llvm_unreachable("Unexpected FP pseudo-opcode");
883  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
884  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
885  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
886  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
887  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
888  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
889  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
890  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
891  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
892  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
893  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
894  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
895  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
896  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
897  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
898  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
899  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
900  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
901  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
902  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
903  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
904  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
905  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
906  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
907  case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
908  case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
909  }
910 
911  auto Action = getOperationAction(EqOpc, VT);
912 
913  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
914  // For now, we just expand for those cases.
915  if (Action != Legal)
916  Action = Expand;
917 
918  return Action;
919  }
920 
921  /// Return true if the specified operation is legal on this target or can be
922  /// made legal with custom lowering. This is used to help guide high-level
923  /// lowering decisions.
924  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
925  return (VT == MVT::Other || isTypeLegal(VT)) &&
926  (getOperationAction(Op, VT) == Legal ||
927  getOperationAction(Op, VT) == Custom);
928  }
929 
930  /// Return true if the specified operation is legal on this target or can be
931  /// made legal using promotion. This is used to help guide high-level lowering
932  /// decisions.
933  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
934  return (VT == MVT::Other || isTypeLegal(VT)) &&
935  (getOperationAction(Op, VT) == Legal ||
936  getOperationAction(Op, VT) == Promote);
937  }
938 
939  /// Return true if the specified operation is legal on this target or can be
940  /// made legal with custom lowering or using promotion. This is used to help
941  /// guide high-level lowering decisions.
942  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
943  return (VT == MVT::Other || isTypeLegal(VT)) &&
944  (getOperationAction(Op, VT) == Legal ||
945  getOperationAction(Op, VT) == Custom ||
946  getOperationAction(Op, VT) == Promote);
947  }
948 
949  /// Return true if the operation uses custom lowering, regardless of whether
950  /// the type is legal or not.
951  bool isOperationCustom(unsigned Op, EVT VT) const {
952  return getOperationAction(Op, VT) == Custom;
953  }
954 
955  /// Return true if lowering to a jump table is allowed.
956  virtual bool areJTsAllowed(const Function *Fn) const {
957  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
958  return false;
959 
960  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
961  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
962  }
963 
964  /// Check whether the range [Low,High] fits in a machine word.
965  bool rangeFitsInWord(const APInt &Low, const APInt &High,
966  const DataLayout &DL) const {
967  // FIXME: Using the pointer type doesn't seem ideal.
968  uint64_t BW = DL.getIndexSizeInBits(0u);
969  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
970  return Range <= BW;
971  }
972 
973  /// Return true if lowering to a jump table is suitable for a set of case
974  /// clusters which may contain \p NumCases cases, \p Range range of values.
975  /// FIXME: This function check the maximum table size and density, but the
976  /// minimum size is not checked. It would be nice if the minimum size is
977  /// also combined within this function. Currently, the minimum size check is
978  /// performed in findJumpTable() in SelectionDAGBuiler and
979  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
980  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
981  uint64_t Range) const {
982  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
983  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
984  const unsigned MaxJumpTableSize =
985  OptForSize ? UINT_MAX : getMaximumJumpTableSize();
986  // Check whether a range of clusters is dense enough for a jump table.
987  if (Range <= MaxJumpTableSize &&
988  (NumCases * 100 >= Range * MinDensity)) {
989  return true;
990  }
991  return false;
992  }
993 
994  /// Return true if lowering to a bit test is suitable for a set of case
995  /// clusters which contains \p NumDests unique destinations, \p Low and
996  /// \p High as its lowest and highest case values, and expects \p NumCmps
997  /// case value comparisons. Check if the number of destinations, comparison
998  /// metric, and range are all suitable.
999  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1000  const APInt &Low, const APInt &High,
1001  const DataLayout &DL) const {
1002  // FIXME: I don't think NumCmps is the correct metric: a single case and a
1003  // range of cases both require only one branch to lower. Just looking at the
1004  // number of clusters and destinations should be enough to decide whether to
1005  // build bit tests.
1006 
1007  // To lower a range with bit tests, the range must fit the bitwidth of a
1008  // machine word.
1009  if (!rangeFitsInWord(Low, High, DL))
1010  return false;
1011 
1012  // Decide whether it's profitable to lower this range with bit tests. Each
1013  // destination requires a bit test and branch, and there is an overall range
1014  // check branch. For a small number of clusters, separate comparisons might
1015  // be cheaper, and for many destinations, splitting the range might be
1016  // better.
1017  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1018  (NumDests == 3 && NumCmps >= 6);
1019  }
1020 
1021  /// Return true if the specified operation is illegal on this target or
1022  /// unlikely to be made legal with custom lowering. This is used to help guide
1023  /// high-level lowering decisions.
1024  bool isOperationExpand(unsigned Op, EVT VT) const {
1025  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1026  }
1027 
1028  /// Return true if the specified operation is legal on this target.
1029  bool isOperationLegal(unsigned Op, EVT VT) const {
1030  return (VT == MVT::Other || isTypeLegal(VT)) &&
1031  getOperationAction(Op, VT) == Legal;
1032  }
1033 
1034  /// Return how this load with extension should be treated: either it is legal,
1035  /// needs to be promoted to a larger size, needs to be expanded to some other
1036  /// code sequence, or the target has a custom expander for it.
1038  EVT MemVT) const {
1039  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1040  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1041  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1042  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1043  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1044  unsigned Shift = 4 * ExtType;
1045  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1046  }
1047 
1048  /// Return true if the specified load with extension is legal on this target.
1049  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1050  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1051  }
1052 
1053  /// Return true if the specified load with extension is legal or custom
1054  /// on this target.
1055  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1056  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1057  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1058  }
1059 
1060  /// Return how this store with truncation should be treated: either it is
1061  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1062  /// other code sequence, or the target has a custom expander for it.
1064  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1065  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1066  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1067  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1068  "Table isn't big enough!");
1069  return TruncStoreActions[ValI][MemI];
1070  }
1071 
1072  /// Return true if the specified store with truncation is legal on this
1073  /// target.
1074  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1075  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1076  }
1077 
1078  /// Return true if the specified store with truncation has solution on this
1079  /// target.
1080  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1081  return isTypeLegal(ValVT) &&
1082  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1083  getTruncStoreAction(ValVT, MemVT) == Custom);
1084  }
1085 
1086  /// Return how the indexed load should be treated: either it is legal, needs
1087  /// to be promoted to a larger size, needs to be expanded to some other code
1088  /// sequence, or the target has a custom expander for it.
1090  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1091  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1092  "Table isn't big enough!");
1093  unsigned Ty = (unsigned)VT.SimpleTy;
1094  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1095  }
1096 
1097  /// Return true if the specified indexed load is legal on this target.
1098  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1099  return VT.isSimple() &&
1100  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1101  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1102  }
1103 
1104  /// Return how the indexed store should be treated: either it is legal, needs
1105  /// to be promoted to a larger size, needs to be expanded to some other code
1106  /// sequence, or the target has a custom expander for it.
1108  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1109  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1110  "Table isn't big enough!");
1111  unsigned Ty = (unsigned)VT.SimpleTy;
1112  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1113  }
1114 
1115  /// Return true if the specified indexed load is legal on this target.
1116  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1117  return VT.isSimple() &&
1118  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1119  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1120  }
1121 
1122  /// Return how the condition code should be treated: either it is legal, needs
1123  /// to be expanded to some other code sequence, or the target has a custom
1124  /// expander for it.
1127  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1128  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1129  "Table isn't big enough!");
1130  // See setCondCodeAction for how this is encoded.
1131  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1132  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1133  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1134  assert(Action != Promote && "Can't promote condition code!");
1135  return Action;
1136  }
1137 
1138  /// Return true if the specified condition code is legal on this target.
1139  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1140  return getCondCodeAction(CC, VT) == Legal;
1141  }
1142 
1143  /// Return true if the specified condition code is legal or custom on this
1144  /// target.
1146  return getCondCodeAction(CC, VT) == Legal ||
1147  getCondCodeAction(CC, VT) == Custom;
1148  }
1149 
1150  /// If the action for this operation is to promote, this method returns the
1151  /// ValueType to promote to.
1152  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1153  assert(getOperationAction(Op, VT) == Promote &&
1154  "This operation isn't promoted!");
1155 
1156  // See if this has an explicit type specified.
1157  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1159  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1160  if (PTTI != PromoteToType.end()) return PTTI->second;
1161 
1162  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1163  "Cannot autopromote this type, add it with AddPromotedToType.");
1164 
1165  MVT NVT = VT;
1166  do {
1167  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1168  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1169  "Didn't find type to promote to!");
1170  } while (!isTypeLegal(NVT) ||
1171  getOperationAction(Op, NVT) == Promote);
1172  return NVT;
1173  }
1174 
1175  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1176  /// operations except for the pointer size. If AllowUnknown is true, this
1177  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1178  /// otherwise it will assert.
1180  bool AllowUnknown = false) const {
1181  // Lower scalar pointers to native pointer types.
1182  if (auto *PTy = dyn_cast<PointerType>(Ty))
1183  return getPointerTy(DL, PTy->getAddressSpace());
1184 
1185  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1186  Type *EltTy = VTy->getElementType();
1187  // Lower vectors of pointers to native pointer types.
1188  if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1189  EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1190  EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1191  }
1192  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1193  VTy->getNumElements());
1194  }
1195 
1196  return EVT::getEVT(Ty, AllowUnknown);
1197  }
1198 
1200  bool AllowUnknown = false) const {
1201  // Lower scalar pointers to native pointer types.
1202  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1203  return getPointerMemTy(DL, PTy->getAddressSpace());
1204  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1205  Type *Elm = VTy->getElementType();
1206  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1207  EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1208  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1209  }
1210  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1211  VTy->getNumElements());
1212  }
1213 
1214  return getValueType(DL, Ty, AllowUnknown);
1215  }
1216 
1217 
1218  /// Return the MVT corresponding to this LLVM type. See getValueType.
1220  bool AllowUnknown = false) const {
1221  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1222  }
1223 
1224  /// Return the desired alignment for ByVal or InAlloca aggregate function
1225  /// arguments in the caller parameter area. This is the actual alignment, not
1226  /// its logarithm.
1227  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1228 
1229  /// Return the type of registers that this ValueType will eventually require.
1231  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1232  return RegisterTypeForVT[VT.SimpleTy];
1233  }
1234 
1235  /// Return the type of registers that this ValueType will eventually require.
1236  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1237  if (VT.isSimple()) {
1238  assert((unsigned)VT.getSimpleVT().SimpleTy <
1239  array_lengthof(RegisterTypeForVT));
1240  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1241  }
1242  if (VT.isVector()) {
1243  EVT VT1;
1244  MVT RegisterVT;
1245  unsigned NumIntermediates;
1246  (void)getVectorTypeBreakdown(Context, VT, VT1,
1247  NumIntermediates, RegisterVT);
1248  return RegisterVT;
1249  }
1250  if (VT.isInteger()) {
1251  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1252  }
1253  llvm_unreachable("Unsupported extended type!");
1254  }
1255 
1256  /// Return the number of registers that this ValueType will eventually
1257  /// require.
1258  ///
1259  /// This is one for any types promoted to live in larger registers, but may be
1260  /// more than one for types (like i64) that are split into pieces. For types
1261  /// like i140, which are first promoted then expanded, it is the number of
1262  /// registers needed to hold all the bits of the original type. For an i140
1263  /// on a 32 bit machine this means 5 registers.
1264  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1265  if (VT.isSimple()) {
1266  assert((unsigned)VT.getSimpleVT().SimpleTy <
1267  array_lengthof(NumRegistersForVT));
1268  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1269  }
1270  if (VT.isVector()) {
1271  EVT VT1;
1272  MVT VT2;
1273  unsigned NumIntermediates;
1274  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1275  }
1276  if (VT.isInteger()) {
1277  unsigned BitWidth = VT.getSizeInBits();
1278  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1279  return (BitWidth + RegWidth - 1) / RegWidth;
1280  }
1281  llvm_unreachable("Unsupported extended type!");
1282  }
1283 
1284  /// Certain combinations of ABIs, Targets and features require that types
1285  /// are legal for some operations and not for other operations.
1286  /// For MIPS all vector types must be passed through the integer register set.
1288  CallingConv::ID CC, EVT VT) const {
1289  return getRegisterType(Context, VT);
1290  }
1291 
1292  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1293  /// this occurs when a vector type is used, as vector are passed through the
1294  /// integer register set.
1295  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1296  CallingConv::ID CC,
1297  EVT VT) const {
1298  return getNumRegisters(Context, VT);
1299  }
1300 
1301  /// Certain targets have context senstive alignment requirements, where one
1302  /// type has the alignment requirement of another type.
1303  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1304  DataLayout DL) const {
1305  return DL.getABITypeAlignment(ArgTy);
1306  }
1307 
1308  /// If true, then instruction selection should seek to shrink the FP constant
1309  /// of the specified type to a smaller type in order to save space and / or
1310  /// reduce runtime.
1311  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1312 
1313  /// Return true if it is profitable to reduce a load to a smaller type.
1314  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1316  EVT NewVT) const {
1317  // By default, assume that it is cheaper to extract a subvector from a wide
1318  // vector load rather than creating multiple narrow vector loads.
1319  if (NewVT.isVector() && !Load->hasOneUse())
1320  return false;
1321 
1322  return true;
1323  }
1324 
1325  /// When splitting a value of the specified type into parts, does the Lo
1326  /// or Hi part come first? This usually follows the endianness, except
1327  /// for ppcf128, where the Hi part always comes first.
1328  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1329  return DL.isBigEndian() || VT == MVT::ppcf128;
1330  }
1331 
1332  /// If true, the target has custom DAG combine transformations that it can
1333  /// perform for the specified node.
1335  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1336  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1337  }
1338 
1339  unsigned getGatherAllAliasesMaxDepth() const {
1340  return GatherAllAliasesMaxDepth;
1341  }
1342 
1343  /// Returns the size of the platform's va_list object.
1344  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1345  return getPointerTy(DL).getSizeInBits();
1346  }
1347 
1348  /// Get maximum # of store operations permitted for llvm.memset
1349  ///
1350  /// This function returns the maximum number of store operations permitted
1351  /// to replace a call to llvm.memset. The value is set by the target at the
1352  /// performance threshold for such a replacement. If OptSize is true,
1353  /// return the limit for functions that have OptSize attribute.
1354  unsigned getMaxStoresPerMemset(bool OptSize) const {
1355  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1356  }
1357 
1358  /// Get maximum # of store operations permitted for llvm.memcpy
1359  ///
1360  /// This function returns the maximum number of store operations permitted
1361  /// to replace a call to llvm.memcpy. The value is set by the target at the
1362  /// performance threshold for such a replacement. If OptSize is true,
1363  /// return the limit for functions that have OptSize attribute.
1364  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1365  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1366  }
1367 
1368  /// \brief Get maximum # of store operations to be glued together
1369  ///
1370  /// This function returns the maximum number of store operations permitted
1371  /// to glue together during lowering of llvm.memcpy. The value is set by
1372  // the target at the performance threshold for such a replacement.
1373  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1374  return MaxGluedStoresPerMemcpy;
1375  }
1376 
1377  /// Get maximum # of load operations permitted for memcmp
1378  ///
1379  /// This function returns the maximum number of load operations permitted
1380  /// to replace a call to memcmp. The value is set by the target at the
1381  /// performance threshold for such a replacement. If OptSize is true,
1382  /// return the limit for functions that have OptSize attribute.
1383  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1384  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1385  }
1386 
1387  /// For memcmp expansion when the memcmp result is only compared equal or
1388  /// not-equal to 0, allow up to this number of load pairs per block. As an
1389  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1390  /// a0 = load2bytes &a[0]
1391  /// b0 = load2bytes &b[0]
1392  /// a2 = load1byte &a[2]
1393  /// b2 = load1byte &b[2]
1394  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1395  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1396  return 1;
1397  }
1398 
1399  /// Get maximum # of store operations permitted for llvm.memmove
1400  ///
1401  /// This function returns the maximum number of store operations permitted
1402  /// to replace a call to llvm.memmove. The value is set by the target at the
1403  /// performance threshold for such a replacement. If OptSize is true,
1404  /// return the limit for functions that have OptSize attribute.
1405  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1406  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1407  }
1408 
1409  /// Determine if the target supports unaligned memory accesses.
1410  ///
1411  /// This function returns true if the target allows unaligned memory accesses
1412  /// of the specified type in the given address space. If true, it also returns
1413  /// whether the unaligned memory access is "fast" in the last argument by
1414  /// reference. This is used, for example, in situations where an array
1415  /// copy/move/set is converted to a sequence of store operations. Its use
1416  /// helps to ensure that such replacements don't generate code that causes an
1417  /// alignment error (trap) on the target machine.
1419  EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1421  bool * /*Fast*/ = nullptr) const {
1422  return false;
1423  }
1424 
1425  /// Return true if the target supports a memory access of this type for the
1426  /// given address space and alignment. If the access is allowed, the optional
1427  /// final parameter returns if the access is also fast (as defined by the
1428  /// target).
1429  bool
1430  allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1431  unsigned AddrSpace = 0, unsigned Alignment = 1,
1433  bool *Fast = nullptr) const;
1434 
1435  /// Return true if the target supports a memory access of this type for the
1436  /// given MachineMemOperand. If the access is allowed, the optional
1437  /// final parameter returns if the access is also fast (as defined by the
1438  /// target).
1439  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1440  const MachineMemOperand &MMO,
1441  bool *Fast = nullptr) const;
1442 
1443  /// Returns the target specific optimal type for load and store operations as
1444  /// a result of memset, memcpy, and memmove lowering.
1445  ///
1446  /// If DstAlign is zero that means it's safe to destination alignment can
1447  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1448  /// a need to check it against alignment requirement, probably because the
1449  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1450  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1451  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1452  /// does not need to be loaded. It returns EVT::Other if the type should be
1453  /// determined using generic target-independent logic.
1454  virtual EVT
1455  getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1456  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1457  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1458  const AttributeList & /*FuncAttributes*/) const {
1459  return MVT::Other;
1460  }
1461 
1462  /// Returns true if it's safe to use load / store of the specified type to
1463  /// expand memcpy / memset inline.
1464  ///
1465  /// This is mostly true for all types except for some special cases. For
1466  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1467  /// fstpl which also does type conversion. Note the specified type doesn't
1468  /// have to be legal as the hook is used before type legalization.
1469  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1470 
1471  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1472  bool usesUnderscoreSetJmp() const {
1473  return UseUnderscoreSetJmp;
1474  }
1475 
1476  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1477  bool usesUnderscoreLongJmp() const {
1478  return UseUnderscoreLongJmp;
1479  }
1480 
1481  /// Return lower limit for number of blocks in a jump table.
1482  virtual unsigned getMinimumJumpTableEntries() const;
1483 
1484  /// Return lower limit of the density in a jump table.
1485  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1486 
1487  /// Return upper limit for number of entries in a jump table.
1488  /// Zero if no limit.
1489  unsigned getMaximumJumpTableSize() const;
1490 
1491  virtual bool isJumpTableRelative() const {
1492  return TM.isPositionIndependent();
1493  }
1494 
1495  /// If a physical register, this specifies the register that
1496  /// llvm.savestack/llvm.restorestack should save and restore.
1498  return StackPointerRegisterToSaveRestore;
1499  }
1500 
1501  /// If a physical register, this returns the register that receives the
1502  /// exception address on entry to an EH pad.
1503  virtual unsigned
1504  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1505  // 0 is guaranteed to be the NoRegister value on all targets
1506  return 0;
1507  }
1508 
1509  /// If a physical register, this returns the register that receives the
1510  /// exception typeid on entry to a landing pad.
1511  virtual unsigned
1512  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1513  // 0 is guaranteed to be the NoRegister value on all targets
1514  return 0;
1515  }
1516 
1517  virtual bool needsFixedCatchObjects() const {
1518  report_fatal_error("Funclet EH is not implemented for this target");
1519  }
1520 
1521  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1522  /// 200)
1523  unsigned getJumpBufSize() const {
1524  return JumpBufSize;
1525  }
1526 
1527  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1528  /// is 0)
1529  unsigned getJumpBufAlignment() const {
1530  return JumpBufAlignment;
1531  }
1532 
1533  /// Return the minimum stack alignment of an argument.
1534  unsigned getMinStackArgumentAlignment() const {
1535  return MinStackArgumentAlignment;
1536  }
1537 
1538  /// Return the minimum function alignment.
1539  unsigned getMinFunctionAlignment() const {
1540  return MinFunctionAlignment;
1541  }
1542 
1543  /// Return the preferred function alignment.
1544  unsigned getPrefFunctionAlignment() const {
1545  return PrefFunctionAlignment;
1546  }
1547 
1548  /// Return the preferred loop alignment.
1549  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1550  return PrefLoopAlignment;
1551  }
1552 
1553  /// Should loops be aligned even when the function is marked OptSize (but not
1554  /// MinSize).
1555  virtual bool alignLoopsWithOptSize() const {
1556  return false;
1557  }
1558 
1559  /// If the target has a standard location for the stack protector guard,
1560  /// returns the address of that location. Otherwise, returns nullptr.
1561  /// DEPRECATED: please override useLoadStackGuardNode and customize
1562  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1563  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1564 
1565  /// Inserts necessary declarations for SSP (stack protection) purpose.
1566  /// Should be used only when getIRStackGuard returns nullptr.
1567  virtual void insertSSPDeclarations(Module &M) const;
1568 
1569  /// Return the variable that's previously inserted by insertSSPDeclarations,
1570  /// if any, otherwise return nullptr. Should be used only when
1571  /// getIRStackGuard returns nullptr.
1572  virtual Value *getSDagStackGuard(const Module &M) const;
1573 
1574  /// If this function returns true, stack protection checks should XOR the
1575  /// frame pointer (or whichever pointer is used to address locals) into the
1576  /// stack guard value before checking it. getIRStackGuard must return nullptr
1577  /// if this returns true.
1578  virtual bool useStackGuardXorFP() const { return false; }
1579 
1580  /// If the target has a standard stack protection check function that
1581  /// performs validation and error handling, returns the function. Otherwise,
1582  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1583  /// Should be used only when getIRStackGuard returns nullptr.
1584  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1585 
1586 protected:
1587  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1588  bool UseTLS) const;
1589 
1590 public:
1591  /// Returns the target-specific address of the unsafe stack pointer.
1592  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1593 
1594  /// Returns the name of the symbol used to emit stack probes or the empty
1595  /// string if not applicable.
1597  return "";
1598  }
1599 
1600  /// Returns true if a cast between SrcAS and DestAS is a noop.
1601  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1602  return false;
1603  }
1604 
1605  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1606  /// are happy to sink it into basic blocks. A cast may be free, but not
1607  /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1608  virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1609  return isNoopAddrSpaceCast(SrcAS, DestAS);
1610  }
1611 
1612  /// Return true if the pointer arguments to CI should be aligned by aligning
1613  /// the object whose address is being passed. If so then MinSize is set to the
1614  /// minimum size the object must be to be aligned and PrefAlign is set to the
1615  /// preferred alignment.
1616  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1617  unsigned & /*PrefAlign*/) const {
1618  return false;
1619  }
1620 
1621  //===--------------------------------------------------------------------===//
1622  /// \name Helpers for TargetTransformInfo implementations
1623  /// @{
1624 
1625  /// Get the ISD node that corresponds to the Instruction class opcode.
1626  int InstructionOpcodeToISD(unsigned Opcode) const;
1627 
1628  /// Estimate the cost of type-legalization and the legalized type.
1629  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1630  Type *Ty) const;
1631 
1632  /// @}
1633 
1634  //===--------------------------------------------------------------------===//
1635  /// \name Helpers for atomic expansion.
1636  /// @{
1637 
1638  /// Returns the maximum atomic operation size (in bits) supported by
1639  /// the backend. Atomic operations greater than this size (as well
1640  /// as ones that are not naturally aligned), will be expanded by
1641  /// AtomicExpandPass into an __atomic_* library call.
1643  return MaxAtomicSizeInBitsSupported;
1644  }
1645 
1646  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1647  /// the backend supports. Any smaller operations are widened in
1648  /// AtomicExpandPass.
1649  ///
1650  /// Note that *unlike* operations above the maximum size, atomic ops
1651  /// are still natively supported below the minimum; they just
1652  /// require a more complex expansion.
1653  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1654 
1655  /// Whether the target supports unaligned atomic operations.
1656  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1657 
1658  /// Whether AtomicExpandPass should automatically insert fences and reduce
1659  /// ordering for this atomic. This should be true for most architectures with
1660  /// weak memory ordering. Defaults to false.
1661  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1662  return false;
1663  }
1664 
1665  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1666  /// corresponding pointee type. This may entail some non-trivial operations to
1667  /// truncate or reconstruct types that will be illegal in the backend. See
1668  /// ARMISelLowering for an example implementation.
1669  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1670  AtomicOrdering Ord) const {
1671  llvm_unreachable("Load linked unimplemented on this target");
1672  }
1673 
1674  /// Perform a store-conditional operation to Addr. Return the status of the
1675  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1676  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1677  Value *Addr, AtomicOrdering Ord) const {
1678  llvm_unreachable("Store conditional unimplemented on this target");
1679  }
1680 
1681  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1682  /// represents the core LL/SC loop which will be lowered at a late stage by
1683  /// the backend.
1685  AtomicRMWInst *AI,
1686  Value *AlignedAddr, Value *Incr,
1687  Value *Mask, Value *ShiftAmt,
1688  AtomicOrdering Ord) const {
1689  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1690  }
1691 
1692  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1693  /// represents the core LL/SC loop which will be lowered at a late stage by
1694  /// the backend.
1696  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1697  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1698  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1699  }
1700 
1701  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1702  /// It is called by AtomicExpandPass before expanding an
1703  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1704  /// if shouldInsertFencesForAtomic returns true.
1705  ///
1706  /// Inst is the original atomic instruction, prior to other expansions that
1707  /// may be performed.
1708  ///
1709  /// This function should either return a nullptr, or a pointer to an IR-level
1710  /// Instruction*. Even complex fence sequences can be represented by a
1711  /// single Instruction* through an intrinsic to be lowered later.
1712  /// Backends should override this method to produce target-specific intrinsic
1713  /// for their fences.
1714  /// FIXME: Please note that the default implementation here in terms of
1715  /// IR-level fences exists for historical/compatibility reasons and is
1716  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1717  /// consistency. For example, consider the following example:
1718  /// atomic<int> x = y = 0;
1719  /// int r1, r2, r3, r4;
1720  /// Thread 0:
1721  /// x.store(1);
1722  /// Thread 1:
1723  /// y.store(1);
1724  /// Thread 2:
1725  /// r1 = x.load();
1726  /// r2 = y.load();
1727  /// Thread 3:
1728  /// r3 = y.load();
1729  /// r4 = x.load();
1730  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1731  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1732  /// IR-level fences can prevent it.
1733  /// @{
1735  AtomicOrdering Ord) const {
1736  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1737  return Builder.CreateFence(Ord);
1738  else
1739  return nullptr;
1740  }
1741 
1743  Instruction *Inst,
1744  AtomicOrdering Ord) const {
1745  if (isAcquireOrStronger(Ord))
1746  return Builder.CreateFence(Ord);
1747  else
1748  return nullptr;
1749  }
1750  /// @}
1751 
1752  // Emits code that executes when the comparison result in the ll/sc
1753  // expansion of a cmpxchg instruction is such that the store-conditional will
1754  // not execute. This makes it possible to balance out the load-linked with
1755  // a dedicated instruction, if desired.
1756  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1757  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1758  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1759 
1760  /// Returns true if the given (atomic) store should be expanded by the
1761  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1763  return false;
1764  }
1765 
1766  /// Returns true if arguments should be sign-extended in lib calls.
1767  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1768  return IsSigned;
1769  }
1770 
1771  /// Returns how the given (atomic) load should be expanded by the
1772  /// IR-level AtomicExpand pass.
1775  }
1776 
1777  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1778  /// AtomicExpand pass.
1779  virtual AtomicExpansionKind
1782  }
1783 
1784  /// Returns how the IR-level AtomicExpand pass should expand the given
1785  /// AtomicRMW, if at all. Default is to never expand.
1787  return RMW->isFloatingPointOperation() ?
1788  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1789  }
1790 
1791  /// On some platforms, an AtomicRMW that never actually modifies the value
1792  /// (such as fetch_add of 0) can be turned into a fence followed by an
1793  /// atomic load. This may sound useless, but it makes it possible for the
1794  /// processor to keep the cacheline shared, dramatically improving
1795  /// performance. And such idempotent RMWs are useful for implementing some
1796  /// kinds of locks, see for example (justification + benchmarks):
1797  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1798  /// This method tries doing that transformation, returning the atomic load if
1799  /// it succeeds, and nullptr otherwise.
1800  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1801  /// another round of expansion.
1802  virtual LoadInst *
1804  return nullptr;
1805  }
1806 
1807  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1808  /// SIGN_EXTEND, or ANY_EXTEND).
1810  return ISD::ZERO_EXTEND;
1811  }
1812 
1813  /// @}
1814 
1815  /// Returns true if we should normalize
1816  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1817  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1818  /// that it saves us from materializing N0 and N1 in an integer register.
1819  /// Targets that are able to perform and/or on flags should return false here.
1821  EVT VT) const {
1822  // If a target has multiple condition registers, then it likely has logical
1823  // operations on those registers.
1824  if (hasMultipleConditionRegisters())
1825  return false;
1826  // Only do the transform if the value won't be split into multiple
1827  // registers.
1828  LegalizeTypeAction Action = getTypeAction(Context, VT);
1829  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1830  Action != TypeSplitVector;
1831  }
1832 
1833  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1834 
1835  /// Return true if a select of constants (select Cond, C1, C2) should be
1836  /// transformed into simple math ops with the condition value. For example:
1837  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1838  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1839  return false;
1840  }
1841 
1842  /// Return true if it is profitable to transform an integer
1843  /// multiplication-by-constant into simpler operations like shifts and adds.
1844  /// This may be true if the target does not directly support the
1845  /// multiplication operation for the specified type or the sequence of simpler
1846  /// ops is faster than the multiply.
1847  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1848  return false;
1849  }
1850 
1851  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1852  /// conversion operations - canonicalizing the FP source value instead of
1853  /// converting all cases and then selecting based on value.
1854  /// This may be true if the target throws exceptions for out of bounds
1855  /// conversions or has fast FP CMOV.
1856  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1857  bool IsSigned) const {
1858  return false;
1859  }
1860 
1861  //===--------------------------------------------------------------------===//
1862  // TargetLowering Configuration Methods - These methods should be invoked by
1863  // the derived class constructor to configure this object for the target.
1864  //
1865 protected:
1866  /// Specify how the target extends the result of integer and floating point
1867  /// boolean values from i1 to a wider type. See getBooleanContents.
1869  BooleanContents = Ty;
1870  BooleanFloatContents = Ty;
1871  }
1872 
1873  /// Specify how the target extends the result of integer and floating point
1874  /// boolean values from i1 to a wider type. See getBooleanContents.
1876  BooleanContents = IntTy;
1877  BooleanFloatContents = FloatTy;
1878  }
1879 
1880  /// Specify how the target extends the result of a vector boolean value from a
1881  /// vector of i1 to a wider type. See getBooleanContents.
1883  BooleanVectorContents = Ty;
1884  }
1885 
1886  /// Specify the target scheduling preference.
1888  SchedPreferenceInfo = Pref;
1889  }
1890 
1891  /// Indicate whether this target prefers to use _setjmp to implement
1892  /// llvm.setjmp or the version without _. Defaults to false.
1893  void setUseUnderscoreSetJmp(bool Val) {
1894  UseUnderscoreSetJmp = Val;
1895  }
1896 
1897  /// Indicate whether this target prefers to use _longjmp to implement
1898  /// llvm.longjmp or the version without _. Defaults to false.
1899  void setUseUnderscoreLongJmp(bool Val) {
1900  UseUnderscoreLongJmp = Val;
1901  }
1902 
1903  /// Indicate the minimum number of blocks to generate jump tables.
1904  void setMinimumJumpTableEntries(unsigned Val);
1905 
1906  /// Indicate the maximum number of entries in jump tables.
1907  /// Set to zero to generate unlimited jump tables.
1908  void setMaximumJumpTableSize(unsigned);
1909 
1910  /// If set to a physical register, this specifies the register that
1911  /// llvm.savestack/llvm.restorestack should save and restore.
1913  StackPointerRegisterToSaveRestore = R;
1914  }
1915 
1916  /// Tells the code generator that the target has multiple (allocatable)
1917  /// condition registers that can be used to store the results of comparisons
1918  /// for use by selects and conditional branches. With multiple condition
1919  /// registers, the code generator will not aggressively sink comparisons into
1920  /// the blocks of their users.
1921  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1922  HasMultipleConditionRegisters = hasManyRegs;
1923  }
1924 
1925  /// Tells the code generator that the target has BitExtract instructions.
1926  /// The code generator will aggressively sink "shift"s into the blocks of
1927  /// their users if the users will generate "and" instructions which can be
1928  /// combined with "shift" to BitExtract instructions.
1929  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1930  HasExtractBitsInsn = hasExtractInsn;
1931  }
1932 
1933  /// Tells the code generator not to expand logic operations on comparison
1934  /// predicates into separate sequences that increase the amount of flow
1935  /// control.
1936  void setJumpIsExpensive(bool isExpensive = true);
1937 
1938  /// Tells the code generator which bitwidths to bypass.
1939  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1940  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1941  }
1942 
1943  /// Add the specified register class as an available regclass for the
1944  /// specified value type. This indicates the selector can handle values of
1945  /// that class natively.
1947  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1948  RegClassForVT[VT.SimpleTy] = RC;
1949  }
1950 
1951  /// Return the largest legal super-reg register class of the register class
1952  /// for the specified type and its associated "cost".
1953  virtual std::pair<const TargetRegisterClass *, uint8_t>
1954  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1955 
1956  /// Once all of the register classes are added, this allows us to compute
1957  /// derived properties we expose.
1958  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1959 
1960  /// Indicate that the specified operation does not work with the specified
1961  /// type and indicate what to do about it. Note that VT may refer to either
1962  /// the type of a result or that of an operand of Op.
1963  void setOperationAction(unsigned Op, MVT VT,
1964  LegalizeAction Action) {
1965  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1966  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1967  }
1968 
1969  /// Indicate that the specified load with extension does not work with the
1970  /// specified type and indicate what to do about it.
1971  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1972  LegalizeAction Action) {
1973  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1974  MemVT.isValid() && "Table isn't big enough!");
1975  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1976  unsigned Shift = 4 * ExtType;
1977  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1978  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1979  }
1980 
1981  /// Indicate that the specified truncating store does not work with the
1982  /// specified type and indicate what to do about it.
1983  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1984  LegalizeAction Action) {
1985  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1986  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1987  }
1988 
1989  /// Indicate that the specified indexed load does or does not work with the
1990  /// specified type and indicate what to do abort it.
1991  ///
1992  /// NOTE: All indexed mode loads are initialized to Expand in
1993  /// TargetLowering.cpp
1994  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1995  LegalizeAction Action) {
1996  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1997  (unsigned)Action < 0xf && "Table isn't big enough!");
1998  // Load action are kept in the upper half.
1999  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
2000  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
2001  }
2002 
2003  /// Indicate that the specified indexed store does or does not work with the
2004  /// specified type and indicate what to do about it.
2005  ///
2006  /// NOTE: All indexed mode stores are initialized to Expand in
2007  /// TargetLowering.cpp
2008  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
2009  LegalizeAction Action) {
2010  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2011  (unsigned)Action < 0xf && "Table isn't big enough!");
2012  // Store action are kept in the lower half.
2013  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
2014  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
2015  }
2016 
2017  /// Indicate that the specified condition code is or isn't supported on the
2018  /// target and indicate what to do about it.
2020  LegalizeAction Action) {
2021  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
2022  "Table isn't big enough!");
2023  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2024  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2025  /// value and the upper 29 bits index into the second dimension of the array
2026  /// to select what 32-bit value to use.
2027  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2028  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2029  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2030  }
2031 
2032  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2033  /// to trying a larger integer/fp until it can find one that works. If that
2034  /// default is insufficient, this method can be used by the target to override
2035  /// the default.
2036  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2037  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2038  }
2039 
2040  /// Convenience method to set an operation to Promote and specify the type
2041  /// in a single call.
2042  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2043  setOperationAction(Opc, OrigVT, Promote);
2044  AddPromotedToType(Opc, OrigVT, DestVT);
2045  }
2046 
2047  /// Targets should invoke this method for each target independent node that
2048  /// they want to provide a custom DAG combiner for by implementing the
2049  /// PerformDAGCombine virtual method.
2051  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2052  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2053  }
2054 
2055  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
2056  void setJumpBufSize(unsigned Size) {
2057  JumpBufSize = Size;
2058  }
2059 
2060  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
2061  /// 0
2062  void setJumpBufAlignment(unsigned Align) {
2063  JumpBufAlignment = Align;
2064  }
2065 
2066  /// Set the target's minimum function alignment (in log2(bytes))
2068  MinFunctionAlignment = Align;
2069  }
2070 
2071  /// Set the target's preferred function alignment. This should be set if
2072  /// there is a performance benefit to higher-than-minimum alignment (in
2073  /// log2(bytes))
2075  PrefFunctionAlignment = Align;
2076  }
2077 
2078  /// Set the target's preferred loop alignment. Default alignment is zero, it
2079  /// means the target does not care about loop alignment. The alignment is
2080  /// specified in log2(bytes). The target may also override
2081  /// getPrefLoopAlignment to provide per-loop values.
2082  void setPrefLoopAlignment(unsigned Align) {
2083  PrefLoopAlignment = Align;
2084  }
2085 
2086  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2088  MinStackArgumentAlignment = Align;
2089  }
2090 
2091  /// Set the maximum atomic operation size supported by the
2092  /// backend. Atomic operations greater than this size (as well as
2093  /// ones that are not naturally aligned), will be expanded by
2094  /// AtomicExpandPass into an __atomic_* library call.
2095  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2096  MaxAtomicSizeInBitsSupported = SizeInBits;
2097  }
2098 
2099  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2100  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2101  MinCmpXchgSizeInBits = SizeInBits;
2102  }
2103 
2104  /// Sets whether unaligned atomic operations are supported.
2105  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2106  SupportsUnalignedAtomics = UnalignedSupported;
2107  }
2108 
2109 public:
2110  //===--------------------------------------------------------------------===//
2111  // Addressing mode description hooks (used by LSR etc).
2112  //
2113 
2114  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2115  /// instructions reading the address. This allows as much computation as
2116  /// possible to be done in the address mode for that operand. This hook lets
2117  /// targets also pass back when this should be done on intrinsics which
2118  /// load/store.
2119  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2120  SmallVectorImpl<Value*> &/*Ops*/,
2121  Type *&/*AccessTy*/) const {
2122  return false;
2123  }
2124 
2125  /// This represents an addressing mode of:
2126  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2127  /// If BaseGV is null, there is no BaseGV.
2128  /// If BaseOffs is zero, there is no base offset.
2129  /// If HasBaseReg is false, there is no base register.
2130  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2131  /// no scale.
2132  struct AddrMode {
2133  GlobalValue *BaseGV = nullptr;
2134  int64_t BaseOffs = 0;
2135  bool HasBaseReg = false;
2136  int64_t Scale = 0;
2137  AddrMode() = default;
2138  };
2139 
2140  /// Return true if the addressing mode represented by AM is legal for this
2141  /// target, for a load/store of the specified type.
2142  ///
2143  /// The type may be VoidTy, in which case only return true if the addressing
2144  /// mode is legal for a load/store of any legal type. TODO: Handle
2145  /// pre/postinc as well.
2146  ///
2147  /// If the address space cannot be determined, it will be -1.
2148  ///
2149  /// TODO: Remove default argument
2150  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2151  Type *Ty, unsigned AddrSpace,
2152  Instruction *I = nullptr) const;
2153 
2154  /// Return the cost of the scaling factor used in the addressing mode
2155  /// represented by AM for this target, for a load/store of the specified type.
2156  ///
2157  /// If the AM is supported, the return value must be >= 0.
2158  /// If the AM is not supported, it returns a negative value.
2159  /// TODO: Handle pre/postinc as well.
2160  /// TODO: Remove default argument
2161  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2162  Type *Ty, unsigned AS = 0) const {
2163  // Default: assume that any scaling factor used in a legal AM is free.
2164  if (isLegalAddressingMode(DL, AM, Ty, AS))
2165  return 0;
2166  return -1;
2167  }
2168 
2169  /// Return true if the specified immediate is legal icmp immediate, that is
2170  /// the target has icmp instructions which can compare a register against the
2171  /// immediate without having to materialize the immediate into a register.
2172  virtual bool isLegalICmpImmediate(int64_t) const {
2173  return true;
2174  }
2175 
2176  /// Return true if the specified immediate is legal add immediate, that is the
2177  /// target has add instructions which can add a register with the immediate
2178  /// without having to materialize the immediate into a register.
2179  virtual bool isLegalAddImmediate(int64_t) const {
2180  return true;
2181  }
2182 
2183  /// Return true if the specified immediate is legal for the value input of a
2184  /// store instruction.
2185  virtual bool isLegalStoreImmediate(int64_t Value) const {
2186  // Default implementation assumes that at least 0 works since it is likely
2187  // that a zero register exists or a zero immediate is allowed.
2188  return Value == 0;
2189  }
2190 
2191  /// Return true if it's significantly cheaper to shift a vector by a uniform
2192  /// scalar than by an amount which will vary across each lane. On x86, for
2193  /// example, there is a "psllw" instruction for the former case, but no simple
2194  /// instruction for a general "a << b" operation on vectors.
2195  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2196  return false;
2197  }
2198 
2199  /// Returns true if the opcode is a commutative binary operation.
2200  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2201  // FIXME: This should get its info from the td file.
2202  switch (Opcode) {
2203  case ISD::ADD:
2204  case ISD::SMIN:
2205  case ISD::SMAX:
2206  case ISD::UMIN:
2207  case ISD::UMAX:
2208  case ISD::MUL:
2209  case ISD::MULHU:
2210  case ISD::MULHS:
2211  case ISD::SMUL_LOHI:
2212  case ISD::UMUL_LOHI:
2213  case ISD::FADD:
2214  case ISD::FMUL:
2215  case ISD::AND:
2216  case ISD::OR:
2217  case ISD::XOR:
2218  case ISD::SADDO:
2219  case ISD::UADDO:
2220  case ISD::ADDC:
2221  case ISD::ADDE:
2222  case ISD::SADDSAT:
2223  case ISD::UADDSAT:
2224  case ISD::FMINNUM:
2225  case ISD::FMAXNUM:
2226  case ISD::FMINNUM_IEEE:
2227  case ISD::FMAXNUM_IEEE:
2228  case ISD::FMINIMUM:
2229  case ISD::FMAXIMUM:
2230  return true;
2231  default: return false;
2232  }
2233  }
2234 
2235  /// Return true if the node is a math/logic binary operator.
2236  virtual bool isBinOp(unsigned Opcode) const {
2237  // A commutative binop must be a binop.
2238  if (isCommutativeBinOp(Opcode))
2239  return true;
2240  // These are non-commutative binops.
2241  switch (Opcode) {
2242  case ISD::SUB:
2243  case ISD::SHL:
2244  case ISD::SRL:
2245  case ISD::SRA:
2246  case ISD::SDIV:
2247  case ISD::UDIV:
2248  case ISD::SREM:
2249  case ISD::UREM:
2250  case ISD::FSUB:
2251  case ISD::FDIV:
2252  case ISD::FREM:
2253  return true;
2254  default:
2255  return false;
2256  }
2257  }
2258 
2259  /// Return true if it's free to truncate a value of type FromTy to type
2260  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2261  /// by referencing its sub-register AX.
2262  /// Targets must return false when FromTy <= ToTy.
2263  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2264  return false;
2265  }
2266 
2267  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2268  /// whether a call is in tail position. Typically this means that both results
2269  /// would be assigned to the same register or stack slot, but it could mean
2270  /// the target performs adequate checks of its own before proceeding with the
2271  /// tail call. Targets must return false when FromTy <= ToTy.
2272  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2273  return false;
2274  }
2275 
2276  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2277  return false;
2278  }
2279 
2280  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2281 
2282  /// Return true if the extension represented by \p I is free.
2283  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2284  /// this method can use the context provided by \p I to decide
2285  /// whether or not \p I is free.
2286  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2287  /// In other words, if is[Z|FP]Free returns true, then this method
2288  /// returns true as well. The converse is not true.
2289  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2290  /// \pre \p I must be a sign, zero, or fp extension.
2291  bool isExtFree(const Instruction *I) const {
2292  switch (I->getOpcode()) {
2293  case Instruction::FPExt:
2294  if (isFPExtFree(EVT::getEVT(I->getType()),
2295  EVT::getEVT(I->getOperand(0)->getType())))
2296  return true;
2297  break;
2298  case Instruction::ZExt:
2299  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2300  return true;
2301  break;
2302  case Instruction::SExt:
2303  break;
2304  default:
2305  llvm_unreachable("Instruction is not an extension");
2306  }
2307  return isExtFreeImpl(I);
2308  }
2309 
2310  /// Return true if \p Load and \p Ext can form an ExtLoad.
2311  /// For example, in AArch64
2312  /// %L = load i8, i8* %ptr
2313  /// %E = zext i8 %L to i32
2314  /// can be lowered into one load instruction
2315  /// ldrb w0, [x0]
2316  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2317  const DataLayout &DL) const {
2318  EVT VT = getValueType(DL, Ext->getType());
2319  EVT LoadVT = getValueType(DL, Load->getType());
2320 
2321  // If the load has other users and the truncate is not free, the ext
2322  // probably isn't free.
2323  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2324  !isTruncateFree(Ext->getType(), Load->getType()))
2325  return false;
2326 
2327  // Check whether the target supports casts folded into loads.
2328  unsigned LType;
2329  if (isa<ZExtInst>(Ext))
2330  LType = ISD::ZEXTLOAD;
2331  else {
2332  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2333  LType = ISD::SEXTLOAD;
2334  }
2335 
2336  return isLoadExtLegal(LType, VT, LoadVT);
2337  }
2338 
2339  /// Return true if any actual instruction that defines a value of type FromTy
2340  /// implicitly zero-extends the value to ToTy in the result register.
2341  ///
2342  /// The function should return true when it is likely that the truncate can
2343  /// be freely folded with an instruction defining a value of FromTy. If
2344  /// the defining instruction is unknown (because you're looking at a
2345  /// function argument, PHI, etc.) then the target may require an
2346  /// explicit truncate, which is not necessarily free, but this function
2347  /// does not deal with those cases.
2348  /// Targets must return false when FromTy >= ToTy.
2349  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2350  return false;
2351  }
2352 
2353  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2354  return false;
2355  }
2356 
2357  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2358  /// zero-extension.
2359  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2360  return false;
2361  }
2362 
2363  /// Return true if sinking I's operands to the same basic block as I is
2364  /// profitable, e.g. because the operands can be folded into a target
2365  /// instruction during instruction selection. After calling the function
2366  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2367  /// come first).
2369  SmallVectorImpl<Use *> &Ops) const {
2370  return false;
2371  }
2372 
2373  /// Return true if the target supplies and combines to a paired load
2374  /// two loaded values of type LoadedType next to each other in memory.
2375  /// RequiredAlignment gives the minimal alignment constraints that must be met
2376  /// to be able to select this paired load.
2377  ///
2378  /// This information is *not* used to generate actual paired loads, but it is
2379  /// used to generate a sequence of loads that is easier to combine into a
2380  /// paired load.
2381  /// For instance, something like this:
2382  /// a = load i64* addr
2383  /// b = trunc i64 a to i32
2384  /// c = lshr i64 a, 32
2385  /// d = trunc i64 c to i32
2386  /// will be optimized into:
2387  /// b = load i32* addr1
2388  /// d = load i32* addr2
2389  /// Where addr1 = addr2 +/- sizeof(i32).
2390  ///
2391  /// In other words, unless the target performs a post-isel load combining,
2392  /// this information should not be provided because it will generate more
2393  /// loads.
2394  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2395  unsigned & /*RequiredAlignment*/) const {
2396  return false;
2397  }
2398 
2399  /// Return true if the target has a vector blend instruction.
2400  virtual bool hasVectorBlend() const { return false; }
2401 
2402  /// Get the maximum supported factor for interleaved memory accesses.
2403  /// Default to be the minimum interleave factor: 2.
2404  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2405 
2406  /// Lower an interleaved load to target specific intrinsics. Return
2407  /// true on success.
2408  ///
2409  /// \p LI is the vector load instruction.
2410  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2411  /// \p Indices is the corresponding indices for each shufflevector.
2412  /// \p Factor is the interleave factor.
2413  virtual bool lowerInterleavedLoad(LoadInst *LI,
2415  ArrayRef<unsigned> Indices,
2416  unsigned Factor) const {
2417  return false;
2418  }
2419 
2420  /// Lower an interleaved store to target specific intrinsics. Return
2421  /// true on success.
2422  ///
2423  /// \p SI is the vector store instruction.
2424  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2425  /// \p Factor is the interleave factor.
2427  unsigned Factor) const {
2428  return false;
2429  }
2430 
2431  /// Return true if zero-extending the specific node Val to type VT2 is free
2432  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2433  /// because it's folded such as X86 zero-extending loads).
2434  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2435  return isZExtFree(Val.getValueType(), VT2);
2436  }
2437 
2438  /// Return true if an fpext operation is free (for instance, because
2439  /// single-precision floating-point numbers are implicitly extended to
2440  /// double-precision).
2441  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2442  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2443  "invalid fpext types");
2444  return false;
2445  }
2446 
2447  /// Return true if an fpext operation input to an \p Opcode operation is free
2448  /// (for instance, because half-precision floating-point numbers are
2449  /// implicitly extended to float-precision) for an FMA instruction.
2450  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2451  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2452  "invalid fpext types");
2453  return isFPExtFree(DestVT, SrcVT);
2454  }
2455 
2456  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2457  /// extend node) is profitable.
2458  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2459 
2460  /// Return true if an fneg operation is free to the point where it is never
2461  /// worthwhile to replace it with a bitwise operation.
2462  virtual bool isFNegFree(EVT VT) const {
2463  assert(VT.isFloatingPoint());
2464  return false;
2465  }
2466 
2467  /// Return true if an fabs operation is free to the point where it is never
2468  /// worthwhile to replace it with a bitwise operation.
2469  virtual bool isFAbsFree(EVT VT) const {
2470  assert(VT.isFloatingPoint());
2471  return false;
2472  }
2473 
2474  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2475  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2476  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2477  ///
2478  /// NOTE: This may be called before legalization on types for which FMAs are
2479  /// not legal, but should return true if those types will eventually legalize
2480  /// to types that support FMAs. After legalization, it will only be called on
2481  /// types that support FMAs (via Legal or Custom actions)
2482  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2483  return false;
2484  }
2485 
2486  /// Return true if it's profitable to narrow operations of type VT1 to
2487  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2488  /// i32 to i16.
2489  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2490  return false;
2491  }
2492 
2493  /// Return true if it is beneficial to convert a load of a constant to
2494  /// just the constant itself.
2495  /// On some targets it might be more efficient to use a combination of
2496  /// arithmetic instructions to materialize the constant instead of loading it
2497  /// from a constant pool.
2498  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2499  Type *Ty) const {
2500  return false;
2501  }
2502 
2503  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2504  /// from this source type with this index. This is needed because
2505  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2506  /// the first element, and only the target knows which lowering is cheap.
2507  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2508  unsigned Index) const {
2509  return false;
2510  }
2511 
2512  /// Try to convert an extract element of a vector binary operation into an
2513  /// extract element followed by a scalar operation.
2514  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2515  return false;
2516  }
2517 
2518  /// Return true if extraction of a scalar element from the given vector type
2519  /// at the given index is cheap. For example, if scalar operations occur on
2520  /// the same register file as vector operations, then an extract element may
2521  /// be a sub-register rename rather than an actual instruction.
2522  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2523  return false;
2524  }
2525 
2526  /// Try to convert math with an overflow comparison into the corresponding DAG
2527  /// node operation. Targets may want to override this independently of whether
2528  /// the operation is legal/custom for the given type because it may obscure
2529  /// matching of other patterns.
2530  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2531  // TODO: The default logic is inherited from code in CodeGenPrepare.
2532  // The opcode should not make a difference by default?
2533  if (Opcode != ISD::UADDO)
2534  return false;
2535 
2536  // Allow the transform as long as we have an integer type that is not
2537  // obviously illegal and unsupported.
2538  if (VT.isVector())
2539  return false;
2540  return VT.isSimple() || !isOperationExpand(Opcode, VT);
2541  }
2542 
2543  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2544  // even if the vector itself has multiple uses.
2545  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2546  return false;
2547  }
2548 
2549  // Return true if CodeGenPrepare should consider splitting large offset of a
2550  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2551  // same blocks of its users.
2552  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2553 
2554  //===--------------------------------------------------------------------===//
2555  // Runtime Library hooks
2556  //
2557 
2558  /// Rename the default libcall routine name for the specified libcall.
2559  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2560  LibcallRoutineNames[Call] = Name;
2561  }
2562 
2563  /// Get the libcall routine name for the specified libcall.
2564  const char *getLibcallName(RTLIB::Libcall Call) const {
2565  return LibcallRoutineNames[Call];
2566  }
2567 
2568  /// Override the default CondCode to be used to test the result of the
2569  /// comparison libcall against zero.
2571  CmpLibcallCCs[Call] = CC;
2572  }
2573 
2574  /// Get the CondCode that's to be used to test the result of the comparison
2575  /// libcall against zero.
2577  return CmpLibcallCCs[Call];
2578  }
2579 
2580  /// Set the CallingConv that should be used for the specified libcall.
2582  LibcallCallingConvs[Call] = CC;
2583  }
2584 
2585  /// Get the CallingConv that should be used for the specified libcall.
2587  return LibcallCallingConvs[Call];
2588  }
2589 
2590  /// Execute target specific actions to finalize target lowering.
2591  /// This is used to set extra flags in MachineFrameInformation and freezing
2592  /// the set of reserved registers.
2593  /// The default implementation just freezes the set of reserved registers.
2594  virtual void finalizeLowering(MachineFunction &MF) const;
2595 
2596 private:
2597  const TargetMachine &TM;
2598 
2599  /// Tells the code generator that the target has multiple (allocatable)
2600  /// condition registers that can be used to store the results of comparisons
2601  /// for use by selects and conditional branches. With multiple condition
2602  /// registers, the code generator will not aggressively sink comparisons into
2603  /// the blocks of their users.
2604  bool HasMultipleConditionRegisters;
2605 
2606  /// Tells the code generator that the target has BitExtract instructions.
2607  /// The code generator will aggressively sink "shift"s into the blocks of
2608  /// their users if the users will generate "and" instructions which can be
2609  /// combined with "shift" to BitExtract instructions.
2610  bool HasExtractBitsInsn;
2611 
2612  /// Tells the code generator to bypass slow divide or remainder
2613  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2614  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2615  /// div/rem when the operands are positive and less than 256.
2616  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2617 
2618  /// Tells the code generator that it shouldn't generate extra flow control
2619  /// instructions and should attempt to combine flow control instructions via
2620  /// predication.
2621  bool JumpIsExpensive;
2622 
2623  /// This target prefers to use _setjmp to implement llvm.setjmp.
2624  ///
2625  /// Defaults to false.
2626  bool UseUnderscoreSetJmp;
2627 
2628  /// This target prefers to use _longjmp to implement llvm.longjmp.
2629  ///
2630  /// Defaults to false.
2631  bool UseUnderscoreLongJmp;
2632 
2633  /// Information about the contents of the high-bits in boolean values held in
2634  /// a type wider than i1. See getBooleanContents.
2635  BooleanContent BooleanContents;
2636 
2637  /// Information about the contents of the high-bits in boolean values held in
2638  /// a type wider than i1. See getBooleanContents.
2639  BooleanContent BooleanFloatContents;
2640 
2641  /// Information about the contents of the high-bits in boolean vector values
2642  /// when the element type is wider than i1. See getBooleanContents.
2643  BooleanContent BooleanVectorContents;
2644 
2645  /// The target scheduling preference: shortest possible total cycles or lowest
2646  /// register usage.
2647  Sched::Preference SchedPreferenceInfo;
2648 
2649  /// The size, in bytes, of the target's jmp_buf buffers
2650  unsigned JumpBufSize;
2651 
2652  /// The alignment, in bytes, of the target's jmp_buf buffers
2653  unsigned JumpBufAlignment;
2654 
2655  /// The minimum alignment that any argument on the stack needs to have.
2656  unsigned MinStackArgumentAlignment;
2657 
2658  /// The minimum function alignment (used when optimizing for size, and to
2659  /// prevent explicitly provided alignment from leading to incorrect code).
2660  unsigned MinFunctionAlignment;
2661 
2662  /// The preferred function alignment (used when alignment unspecified and
2663  /// optimizing for speed).
2664  unsigned PrefFunctionAlignment;
2665 
2666  /// The preferred loop alignment.
2667  unsigned PrefLoopAlignment;
2668 
2669  /// Size in bits of the maximum atomics size the backend supports.
2670  /// Accesses larger than this will be expanded by AtomicExpandPass.
2671  unsigned MaxAtomicSizeInBitsSupported;
2672 
2673  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2674  /// backend supports.
2675  unsigned MinCmpXchgSizeInBits;
2676 
2677  /// This indicates if the target supports unaligned atomic operations.
2678  bool SupportsUnalignedAtomics;
2679 
2680  /// If set to a physical register, this specifies the register that
2681  /// llvm.savestack/llvm.restorestack should save and restore.
2682  unsigned StackPointerRegisterToSaveRestore;
2683 
2684  /// This indicates the default register class to use for each ValueType the
2685  /// target supports natively.
2686  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2687  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2688  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2689 
2690  /// This indicates the "representative" register class to use for each
2691  /// ValueType the target supports natively. This information is used by the
2692  /// scheduler to track register pressure. By default, the representative
2693  /// register class is the largest legal super-reg register class of the
2694  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2695  /// representative class would be GR32.
2696  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2697 
2698  /// This indicates the "cost" of the "representative" register class for each
2699  /// ValueType. The cost is used by the scheduler to approximate register
2700  /// pressure.
2701  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2702 
2703  /// For any value types we are promoting or expanding, this contains the value
2704  /// type that we are changing to. For Expanded types, this contains one step
2705  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2706  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2707  /// the same type (e.g. i32 -> i32).
2708  MVT TransformToType[MVT::LAST_VALUETYPE];
2709 
2710  /// For each operation and each value type, keep a LegalizeAction that
2711  /// indicates how instruction selection should deal with the operation. Most
2712  /// operations are Legal (aka, supported natively by the target), but
2713  /// operations that are not should be described. Note that operations on
2714  /// non-legal value types are not described here.
2716 
2717  /// For each load extension type and each value type, keep a LegalizeAction
2718  /// that indicates how instruction selection should deal with a load of a
2719  /// specific value type and extension type. Uses 4-bits to store the action
2720  /// for each of the 4 load ext types.
2721  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2722 
2723  /// For each value type pair keep a LegalizeAction that indicates whether a
2724  /// truncating store of a specific value type and truncating type is legal.
2726 
2727  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2728  /// that indicates how instruction selection should deal with the load /
2729  /// store.
2730  ///
2731  /// The first dimension is the value_type for the reference. The second
2732  /// dimension represents the various modes for load store.
2733  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2734 
2735  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2736  /// indicates how instruction selection should deal with the condition code.
2737  ///
2738  /// Because each CC action takes up 4 bits, we need to have the array size be
2739  /// large enough to fit all of the value types. This can be done by rounding
2740  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2741  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2742 
2743 protected:
2745 
2746 private:
2747  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2748 
2749  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2750  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2751  /// array.
2752  unsigned char
2753  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2754 
2755  /// For operations that must be promoted to a specific type, this holds the
2756  /// destination type. This map should be sparse, so don't hold it as an
2757  /// array.
2758  ///
2759  /// Targets add entries to this map with AddPromotedToType(..), clients access
2760  /// this with getTypeToPromoteTo(..).
2761  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2762  PromoteToType;
2763 
2764  /// Stores the name each libcall.
2765  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2766 
2767  /// The ISD::CondCode that should be used to test the result of each of the
2768  /// comparison libcall against zero.
2769  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2770 
2771  /// Stores the CallingConv that should be used for each libcall.
2772  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2773 
2774  /// Set default libcall names and calling conventions.
2775  void InitLibcalls(const Triple &TT);
2776 
2777 protected:
2778  /// Return true if the extension represented by \p I is free.
2779  /// \pre \p I is a sign, zero, or fp extension and
2780  /// is[Z|FP]ExtFree of the related types is not true.
2781  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2782 
2783  /// Depth that GatherAllAliases should should continue looking for chain
2784  /// dependencies when trying to find a more preferable chain. As an
2785  /// approximation, this should be more than the number of consecutive stores
2786  /// expected to be merged.
2788 
2789  /// Specify maximum number of store instructions per memset call.
2790  ///
2791  /// When lowering \@llvm.memset this field specifies the maximum number of
2792  /// store operations that may be substituted for the call to memset. Targets
2793  /// must set this value based on the cost threshold for that target. Targets
2794  /// should assume that the memset will be done using as many of the largest
2795  /// store operations first, followed by smaller ones, if necessary, per
2796  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2797  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2798  /// store. This only applies to setting a constant array of a constant size.
2800 
2801  /// Maximum number of stores operations that may be substituted for the call
2802  /// to memset, used for functions with OptSize attribute.
2804 
2805  /// Specify maximum bytes of store instructions per memcpy call.
2806  ///
2807  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2808  /// store operations that may be substituted for a call to memcpy. Targets
2809  /// must set this value based on the cost threshold for that target. Targets
2810  /// should assume that the memcpy will be done using as many of the largest
2811  /// store operations first, followed by smaller ones, if necessary, per
2812  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2813  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2814  /// and one 1-byte store. This only applies to copying a constant array of
2815  /// constant size.
2817 
2818 
2819  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2820  ///
2821  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2822  /// of store instructions to keep together. This helps in pairing and
2823  // vectorization later on.
2824  unsigned MaxGluedStoresPerMemcpy = 0;
2825 
2826  /// Maximum number of store operations that may be substituted for a call to
2827  /// memcpy, used for functions with OptSize attribute.
2831 
2832  /// Specify maximum bytes of store instructions per memmove call.
2833  ///
2834  /// When lowering \@llvm.memmove this field specifies the maximum number of
2835  /// store instructions that may be substituted for a call to memmove. Targets
2836  /// must set this value based on the cost threshold for that target. Targets
2837  /// should assume that the memmove will be done using as many of the largest
2838  /// store operations first, followed by smaller ones, if necessary, per
2839  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2840  /// with 8-bit alignment would result in nine 1-byte stores. This only
2841  /// applies to copying a constant array of constant size.
2843 
2844  /// Maximum number of store instructions that may be substituted for a call to
2845  /// memmove, used for functions with OptSize attribute.
2847 
2848  /// Tells the code generator that select is more expensive than a branch if
2849  /// the branch is usually predicted right.
2851 
2852  /// \see enableExtLdPromotion.
2854 
2855  /// Return true if the value types that can be represented by the specified
2856  /// register class are all legal.
2857  bool isLegalRC(const TargetRegisterInfo &TRI,
2858  const TargetRegisterClass &RC) const;
2859 
2860  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2861  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2862  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2863  MachineBasicBlock *MBB) const;
2864 
2865  /// Replace/modify the XRay custom event operands with target-dependent
2866  /// details.
2867  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2868  MachineBasicBlock *MBB) const;
2869 
2870  /// Replace/modify the XRay typed event operands with target-dependent
2871  /// details.
2872  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2873  MachineBasicBlock *MBB) const;
2874 };
2875 
2876 /// This class defines information used to lower LLVM code to legal SelectionDAG
2877 /// operators that the target instruction selector can accept natively.
2878 ///
2879 /// This class also defines callbacks that targets must implement to lower
2880 /// target-specific constructs to SelectionDAG operators.
2882 public:
2883  struct DAGCombinerInfo;
2884 
2885  TargetLowering(const TargetLowering &) = delete;
2886  TargetLowering &operator=(const TargetLowering &) = delete;
2887 
2888  /// NOTE: The TargetMachine owns TLOF.
2889  explicit TargetLowering(const TargetMachine &TM);
2890 
2891  bool isPositionIndependent() const;
2892 
2893  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2894  FunctionLoweringInfo *FLI,
2895  LegacyDivergenceAnalysis *DA) const {
2896  return false;
2897  }
2898 
2899  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2900  return false;
2901  }
2902 
2903  /// Returns true by value, base pointer and offset pointer and addressing mode
2904  /// by reference if the node's address can be legally represented as
2905  /// pre-indexed load / store address.
2906  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2907  SDValue &/*Offset*/,
2908  ISD::MemIndexedMode &/*AM*/,
2909  SelectionDAG &/*DAG*/) const {
2910  return false;
2911  }
2912 
2913  /// Returns true by value, base pointer and offset pointer and addressing mode
2914  /// by reference if this node can be combined with a load / store to form a
2915  /// post-indexed load / store.
2916  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2917  SDValue &/*Base*/,
2918  SDValue &/*Offset*/,
2919  ISD::MemIndexedMode &/*AM*/,
2920  SelectionDAG &/*DAG*/) const {
2921  return false;
2922  }
2923 
2924  /// Return the entry encoding for a jump table in the current function. The
2925  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2926  virtual unsigned getJumpTableEncoding() const;
2927 
2928  virtual const MCExpr *
2930  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2931  MCContext &/*Ctx*/) const {
2932  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2933  }
2934 
2935  /// Returns relocation base for the given PIC jumptable.
2936  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2937  SelectionDAG &DAG) const;
2938 
2939  /// This returns the relocation base for the given PIC jumptable, the same as
2940  /// getPICJumpTableRelocBase, but as an MCExpr.
2941  virtual const MCExpr *
2942  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2943  unsigned JTI, MCContext &Ctx) const;
2944 
2945  /// Return true if folding a constant offset with the given GlobalAddress is
2946  /// legal. It is frequently not legal in PIC relocation models.
2947  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2948 
2950  SDValue &Chain) const;
2951 
2952  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2953  SDValue &NewRHS, ISD::CondCode &CCCode,
2954  const SDLoc &DL) const;
2955 
2956  /// Returns a pair of (return value, chain).
2957  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2958  std::pair<SDValue, SDValue> makeLibCall(
2959  SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops,
2960  bool isSigned, const SDLoc &dl, bool doesNotReturn = false,
2961  bool isReturnValueUsed = true, bool isPostTypeLegalization = false) const;
2962 
2963  /// Check whether parameters to a call that are passed in callee saved
2964  /// registers are the same as from the calling function. This needs to be
2965  /// checked for tail call eligibility.
2966  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2967  const uint32_t *CallerPreservedMask,
2968  const SmallVectorImpl<CCValAssign> &ArgLocs,
2969  const SmallVectorImpl<SDValue> &OutVals) const;
2970 
2971  //===--------------------------------------------------------------------===//
2972  // TargetLowering Optimization Methods
2973  //
2974 
2975  /// A convenience struct that encapsulates a DAG, and two SDValues for
2976  /// returning information from TargetLowering to its clients that want to
2977  /// combine.
2980  bool LegalTys;
2981  bool LegalOps;
2984 
2986  bool LT, bool LO) :
2987  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2988 
2989  bool LegalTypes() const { return LegalTys; }
2990  bool LegalOperations() const { return LegalOps; }
2991 
2993  Old = O;
2994  New = N;
2995  return true;
2996  }
2997  };
2998 
2999  /// Determines the optimal series of memory ops to replace the memset / memcpy.
3000  /// Return true if the number of memory ops is below the threshold (Limit).
3001  /// It returns the types of the sequence of memory ops to perform
3002  /// memset / memcpy by reference.
3003  bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
3004  unsigned Limit, uint64_t Size,
3005  unsigned DstAlign, unsigned SrcAlign,
3006  bool IsMemset,
3007  bool ZeroMemset,
3008  bool MemcpyStrSrc,
3009  bool AllowOverlap,
3010  unsigned DstAS, unsigned SrcAS,
3011  const AttributeList &FuncAttributes) const;
3012 
3013  /// Check to see if the specified operand of the specified instruction is a
3014  /// constant integer. If so, check to see if there are any bits set in the
3015  /// constant that are not demanded. If so, shrink the constant and return
3016  /// true.
3017  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3018  TargetLoweringOpt &TLO) const;
3019 
3020  // Target hook to do target-specific const optimization, which is called by
3021  // ShrinkDemandedConstant. This function should return true if the target
3022  // doesn't want ShrinkDemandedConstant to further optimize the constant.
3023  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3024  TargetLoweringOpt &TLO) const {
3025  return false;
3026  }
3027 
3028  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3029  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3030  /// generalized for targets with other types of implicit widening casts.
3031  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3032  TargetLoweringOpt &TLO) const;
3033 
3034  /// Look at Op. At this point, we know that only the DemandedBits bits of the
3035  /// result of Op are ever used downstream. If we can use this information to
3036  /// simplify Op, create a new simplified DAG node and return true, returning
3037  /// the original and new nodes in Old and New. Otherwise, analyze the
3038  /// expression and return a mask of KnownOne and KnownZero bits for the
3039  /// expression (used to simplify the caller). The KnownZero/One bits may only
3040  /// be accurate for those bits in the Demanded masks.
3041  /// \p AssumeSingleUse When this parameter is true, this function will
3042  /// attempt to simplify \p Op even if there are multiple uses.
3043  /// Callers are responsible for correctly updating the DAG based on the
3044  /// results of this function, because simply replacing replacing TLO.Old
3045  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3046  /// has multiple uses.
3047  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3048  const APInt &DemandedElts, KnownBits &Known,
3049  TargetLoweringOpt &TLO, unsigned Depth = 0,
3050  bool AssumeSingleUse = false) const;
3051 
3052  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3053  /// Adds Op back to the worklist upon success.
3054  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3055  KnownBits &Known, TargetLoweringOpt &TLO,
3056  unsigned Depth = 0,
3057  bool AssumeSingleUse = false) const;
3058 
3059  /// Helper wrapper around SimplifyDemandedBits.
3060  /// Adds Op back to the worklist upon success.
3061  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
3062  DAGCombinerInfo &DCI) const;
3063 
3064  /// Look at Vector Op. At this point, we know that only the DemandedElts
3065  /// elements of the result of Op are ever used downstream. If we can use
3066  /// this information to simplify Op, create a new simplified DAG node and
3067  /// return true, storing the original and new nodes in TLO.
3068  /// Otherwise, analyze the expression and return a mask of KnownUndef and
3069  /// KnownZero elements for the expression (used to simplify the caller).
3070  /// The KnownUndef/Zero elements may only be accurate for those bits
3071  /// in the DemandedMask.
3072  /// \p AssumeSingleUse When this parameter is true, this function will
3073  /// attempt to simplify \p Op even if there are multiple uses.
3074  /// Callers are responsible for correctly updating the DAG based on the
3075  /// results of this function, because simply replacing replacing TLO.Old
3076  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3077  /// has multiple uses.
3078  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3079  APInt &KnownUndef, APInt &KnownZero,
3080  TargetLoweringOpt &TLO, unsigned Depth = 0,
3081  bool AssumeSingleUse = false) const;
3082 
3083  /// Helper wrapper around SimplifyDemandedVectorElts.
3084  /// Adds Op back to the worklist upon success.
3085  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3086  APInt &KnownUndef, APInt &KnownZero,
3087  DAGCombinerInfo &DCI) const;
3088 
3089  /// Determine which of the bits specified in Mask are known to be either zero
3090  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3091  /// argument allows us to only collect the known bits that are shared by the
3092  /// requested vector elements.
3093  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3094  KnownBits &Known,
3095  const APInt &DemandedElts,
3096  const SelectionDAG &DAG,
3097  unsigned Depth = 0) const;
3098 
3099  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3100  /// Default implementation computes low bits based on alignment
3101  /// information. This should preserve known bits passed into it.
3102  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3103  KnownBits &Known,
3104  const APInt &DemandedElts,
3105  const SelectionDAG &DAG,
3106  unsigned Depth = 0) const;
3107 
3108  /// This method can be implemented by targets that want to expose additional
3109  /// information about sign bits to the DAG Combiner. The DemandedElts
3110  /// argument allows us to only collect the minimum sign bits that are shared
3111  /// by the requested vector elements.
3112  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3113  const APInt &DemandedElts,
3114  const SelectionDAG &DAG,
3115  unsigned Depth = 0) const;
3116 
3117  /// Attempt to simplify any target nodes based on the demanded vector
3118  /// elements, returning true on success. Otherwise, analyze the expression and
3119  /// return a mask of KnownUndef and KnownZero elements for the expression
3120  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3121  /// accurate for those bits in the DemandedMask.
3122  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3123  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3124  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3125 
3126  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3127  /// returning true on success. Otherwise, analyze the
3128  /// expression and return a mask of KnownOne and KnownZero bits for the
3129  /// expression (used to simplify the caller). The KnownZero/One bits may only
3130  /// be accurate for those bits in the Demanded masks.
3131  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3132  const APInt &DemandedBits,
3133  const APInt &DemandedElts,
3134  KnownBits &Known,
3135  TargetLoweringOpt &TLO,
3136  unsigned Depth = 0) const;
3137 
3138  /// This method returns the constant pool value that will be loaded by LD.
3139  /// NOTE: You must check for implicit extensions of the constant by LD.
3140  virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
3141 
3142  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3143  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3144  /// NaN.
3145  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3146  const SelectionDAG &DAG,
3147  bool SNaN = false,
3148  unsigned Depth = 0) const;
3150  void *DC; // The DAG Combiner object.
3153 
3154  public:
3156 
3157  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3158  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3159 
3160  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3161  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3162  bool isAfterLegalizeDAG() const {
3163  return Level == AfterLegalizeDAG;
3164  }
3166  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3167 
3168  void AddToWorklist(SDNode *N);
3169  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3170  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3171  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3172 
3173  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3174  };
3175 
3176  /// Return if the N is a constant or constant vector equal to the true value
3177  /// from getBooleanContents().
3178  bool isConstTrueVal(const SDNode *N) const;
3179 
3180  /// Return if the N is a constant or constant vector equal to the false value
3181  /// from getBooleanContents().
3182  bool isConstFalseVal(const SDNode *N) const;
3183 
3184  /// Return if \p N is a True value when extended to \p VT.
3185  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3186 
3187  /// Try to simplify a setcc built with the specified operands and cc. If it is
3188  /// unable to simplify it, return a null SDValue.
3189  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3190  bool foldBooleans, DAGCombinerInfo &DCI,
3191  const SDLoc &dl) const;
3192 
3193  // For targets which wrap address, unwrap for analysis.
3194  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3195 
3196  /// Returns true (and the GlobalValue and the offset) if the node is a
3197  /// GlobalAddress + offset.
3198  virtual bool
3199  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3200 
3201  /// This method will be invoked for all target nodes and for any
3202  /// target-independent nodes that the target has registered with invoke it
3203  /// for.
3204  ///
3205  /// The semantics are as follows:
3206  /// Return Value:
3207  /// SDValue.Val == 0 - No change was made
3208  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3209  /// otherwise - N should be replaced by the returned Operand.
3210  ///
3211  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3212  /// more complex transformations.
3213  ///
3214  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3215 
3216  /// Return true if it is profitable to move this shift by a constant amount
3217  /// though its operand, adjusting any immediate operands as necessary to
3218  /// preserve semantics. This transformation may not be desirable if it
3219  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3220  /// extraction in AArch64). By default, it returns true.
3221  ///
3222  /// @param N the shift node
3223  /// @param Level the current DAGCombine legalization level.
3224  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3225  CombineLevel Level) const {
3226  return true;
3227  }
3228 
3229  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3230  // to a shuffle and a truncate.
3231  // Example of such a combine:
3232  // v4i32 build_vector((extract_elt V, 1),
3233  // (extract_elt V, 3),
3234  // (extract_elt V, 5),
3235  // (extract_elt V, 7))
3236  // -->
3237  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3239  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3240  return false;
3241  }
3242 
3243  /// Return true if the target has native support for the specified value type
3244  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3245  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3246  /// and some i16 instructions are slow.
3247  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3248  // By default, assume all legal types are desirable.
3249  return isTypeLegal(VT);
3250  }
3251 
3252  /// Return true if it is profitable for dag combiner to transform a floating
3253  /// point op of specified opcode to a equivalent op of an integer
3254  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3255  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3256  EVT /*VT*/) const {
3257  return false;
3258  }
3259 
3260  /// This method query the target whether it is beneficial for dag combiner to
3261  /// promote the specified node. If true, it should return the desired
3262  /// promotion type by reference.
3263  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3264  return false;
3265  }
3266 
3267  /// Return true if the target supports swifterror attribute. It optimizes
3268  /// loads and stores to reading and writing a specific register.
3269  virtual bool supportSwiftError() const {
3270  return false;
3271  }
3272 
3273  /// Return true if the target supports that a subset of CSRs for the given
3274  /// machine function is handled explicitly via copies.
3275  virtual bool supportSplitCSR(MachineFunction *MF) const {
3276  return false;
3277  }
3278 
3279  /// Perform necessary initialization to handle a subset of CSRs explicitly
3280  /// via copies. This function is called at the beginning of instruction
3281  /// selection.
3283  llvm_unreachable("Not Implemented");
3284  }
3285 
3286  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3287  /// CSRs to virtual registers in the entry block, and copy them back to
3288  /// physical registers in the exit blocks. This function is called at the end
3289  /// of instruction selection.
3290  virtual void insertCopiesSplitCSR(
3292  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3293  llvm_unreachable("Not Implemented");
3294  }
3295 
3296  //===--------------------------------------------------------------------===//
3297  // Lowering methods - These methods must be implemented by targets so that
3298  // the SelectionDAGBuilder code knows how to lower these.
3299  //
3300 
3301  /// This hook must be implemented to lower the incoming (formal) arguments,
3302  /// described by the Ins array, into the specified DAG. The implementation
3303  /// should fill in the InVals array with legal-type argument values, and
3304  /// return the resulting token chain value.
3306  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3307  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3308  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3309  llvm_unreachable("Not Implemented");
3310  }
3311 
3312  /// This structure contains all information that is necessary for lowering
3313  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3314  /// needs to lower a call, and targets will see this struct in their LowerCall
3315  /// implementation.
3318  Type *RetTy = nullptr;
3319  bool RetSExt : 1;
3320  bool RetZExt : 1;
3321  bool IsVarArg : 1;
3322  bool IsInReg : 1;
3323  bool DoesNotReturn : 1;
3325  bool IsConvergent : 1;
3326  bool IsPatchPoint : 1;
3327 
3328  // IsTailCall should be modified by implementations of
3329  // TargetLowering::LowerCall that perform tail call conversions.
3330  bool IsTailCall = false;
3331 
3332  // Is Call lowering done post SelectionDAG type legalization.
3333  bool IsPostTypeLegalization = false;
3334 
3335  unsigned NumFixedArgs = -1;
3338  ArgListTy Args;
3346 
3348  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3349  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3350  IsPatchPoint(false), DAG(DAG) {}
3351 
3353  DL = dl;
3354  return *this;
3355  }
3356 
3358  Chain = InChain;
3359  return *this;
3360  }
3361 
3362  // setCallee with target/module-specific attributes
3364  SDValue Target, ArgListTy &&ArgsList) {
3365  RetTy = ResultType;
3366  Callee = Target;
3367  CallConv = CC;
3368  NumFixedArgs = ArgsList.size();
3369  Args = std::move(ArgsList);
3370 
3372  &(DAG.getMachineFunction()), CC, Args);
3373  return *this;
3374  }
3375 
3377  SDValue Target, ArgListTy &&ArgsList) {
3378  RetTy = ResultType;
3379  Callee = Target;
3380  CallConv = CC;
3381  NumFixedArgs = ArgsList.size();
3382  Args = std::move(ArgsList);
3383  return *this;
3384  }
3385 
3387  SDValue Target, ArgListTy &&ArgsList,
3388  ImmutableCallSite Call) {
3389  RetTy = ResultType;
3390 
3391  IsInReg = Call.hasRetAttr(Attribute::InReg);
3392  DoesNotReturn =
3393  Call.doesNotReturn() ||
3394  (!Call.isInvoke() &&
3395  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3396  IsVarArg = FTy->isVarArg();
3397  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3398  RetSExt = Call.hasRetAttr(Attribute::SExt);
3399  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3400 
3401  Callee = Target;
3402 
3403  CallConv = Call.getCallingConv();
3404  NumFixedArgs = FTy->getNumParams();
3405  Args = std::move(ArgsList);
3406 
3407  CS = Call;
3408 
3409  return *this;
3410  }
3411 
3413  IsInReg = Value;
3414  return *this;
3415  }
3416 
3418  DoesNotReturn = Value;
3419  return *this;
3420  }
3421 
3423  IsVarArg = Value;
3424  return *this;
3425  }
3426 
3428  IsTailCall = Value;
3429  return *this;
3430  }
3431 
3433  IsReturnValueUsed = !Value;
3434  return *this;
3435  }
3436 
3438  IsConvergent = Value;
3439  return *this;
3440  }
3441 
3443  RetSExt = Value;
3444  return *this;
3445  }
3446 
3448  RetZExt = Value;
3449  return *this;
3450  }
3451 
3453  IsPatchPoint = Value;
3454  return *this;
3455  }
3456 
3458  IsPostTypeLegalization = Value;
3459  return *this;
3460  }
3461 
3462  ArgListTy &getArgs() {
3463  return Args;
3464  }
3465  };
3466 
3467  /// This function lowers an abstract call to a function into an actual call.
3468  /// This returns a pair of operands. The first element is the return value
3469  /// for the function (if RetTy is not VoidTy). The second element is the
3470  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3471  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3472 
3473  /// This hook must be implemented to lower calls into the specified
3474  /// DAG. The outgoing arguments to the call are described by the Outs array,
3475  /// and the values to be returned by the call are described by the Ins
3476  /// array. The implementation should fill in the InVals array with legal-type
3477  /// return values from the call, and return the resulting token chain value.
3478  virtual SDValue
3480  SmallVectorImpl<SDValue> &/*InVals*/) const {
3481  llvm_unreachable("Not Implemented");
3482  }
3483 
3484  /// Target-specific cleanup for formal ByVal parameters.
3485  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3486 
3487  /// This hook should be implemented to check whether the return values
3488  /// described by the Outs array can fit into the return registers. If false
3489  /// is returned, an sret-demotion is performed.
3490  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3491  MachineFunction &/*MF*/, bool /*isVarArg*/,
3492  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3493  LLVMContext &/*Context*/) const
3494  {
3495  // Return true by default to get preexisting behavior.
3496  return true;
3497  }
3498 
3499  /// This hook must be implemented to lower outgoing return values, described
3500  /// by the Outs array, into the specified DAG. The implementation should
3501  /// return the resulting token chain value.
3502  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3503  bool /*isVarArg*/,
3504  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3505  const SmallVectorImpl<SDValue> & /*OutVals*/,
3506  const SDLoc & /*dl*/,
3507  SelectionDAG & /*DAG*/) const {
3508  llvm_unreachable("Not Implemented");
3509  }
3510 
3511  /// Return true if result of the specified node is used by a return node
3512  /// only. It also compute and return the input chain for the tail call.
3513  ///
3514  /// This is used to determine whether it is possible to codegen a libcall as
3515  /// tail call at legalization time.
3516  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3517  return false;
3518  }
3519 
3520  /// Return true if the target may be able emit the call instruction as a tail
3521  /// call. This is used by optimization passes to determine if it's profitable
3522  /// to duplicate return instructions to enable tailcall optimization.
3523  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3524  return false;
3525  }
3526 
3527  /// Return the builtin name for the __builtin___clear_cache intrinsic
3528  /// Default is to invoke the clear cache library call
3529  virtual const char * getClearCacheBuiltinName() const {
3530  return "__clear_cache";
3531  }
3532 
3533  /// Return the register ID of the name passed in. Used by named register
3534  /// global variables extension. There is no target-independent behaviour
3535  /// so the default action is to bail.
3536  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3537  SelectionDAG &DAG) const {
3538  report_fatal_error("Named registers not implemented for this target");
3539  }
3540 
3541  /// Return the type that should be used to zero or sign extend a
3542  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3543  /// require the return type to be promoted, but this is not true all the time,
3544  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3545  /// conventions. The frontend should handle this and include all of the
3546  /// necessary information.
3548  ISD::NodeType /*ExtendKind*/) const {
3549  EVT MinVT = getRegisterType(Context, MVT::i32);
3550  return VT.bitsLT(MinVT) ? MinVT : VT;
3551  }
3552 
3553  /// For some targets, an LLVM struct type must be broken down into multiple
3554  /// simple types, but the calling convention specifies that the entire struct
3555  /// must be passed in a block of consecutive registers.
3556  virtual bool
3558  bool isVarArg) const {
3559  return false;
3560  }
3561 
3562  /// For most targets, an LLVM type must be broken down into multiple
3563  /// smaller types. Usually the halves are ordered according to the endianness
3564  /// but for some platform that would break. So this method will default to
3565  /// matching the endianness but can be overridden.
3566  virtual bool
3568  return DL.isLittleEndian();
3569  }
3570 
3571  /// Returns a 0 terminated array of registers that can be safely used as
3572  /// scratch registers.
3573  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3574  return nullptr;
3575  }
3576 
3577  /// This callback is used to prepare for a volatile or atomic load.
3578  /// It takes a chain node as input and returns the chain for the load itself.
3579  ///
3580  /// Having a callback like this is necessary for targets like SystemZ,
3581  /// which allows a CPU to reuse the result of a previous load indefinitely,
3582  /// even if a cache-coherent store is performed by another CPU. The default
3583  /// implementation does nothing.
3585  SelectionDAG &DAG) const {
3586  return Chain;
3587  }
3588 
3589  /// This callback is used to inspect load/store instructions and add
3590  /// target-specific MachineMemOperand flags to them. The default
3591  /// implementation does nothing.
3594  }
3595 
3596  /// This callback is invoked by the type legalizer to legalize nodes with an
3597  /// illegal operand type but legal result types. It replaces the
3598  /// LowerOperation callback in the type Legalizer. The reason we can not do
3599  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3600  /// use this callback.
3601  ///
3602  /// TODO: Consider merging with ReplaceNodeResults.
3603  ///
3604  /// The target places new result values for the node in Results (their number
3605  /// and types must exactly match those of the original return values of
3606  /// the node), or leaves Results empty, which indicates that the node is not
3607  /// to be custom lowered after all.
3608  /// The default implementation calls LowerOperation.
3609  virtual void LowerOperationWrapper(SDNode *N,
3611  SelectionDAG &DAG) const;
3612 
3613  /// This callback is invoked for operations that are unsupported by the
3614  /// target, which are registered to use 'custom' lowering, and whose defined
3615  /// values are all legal. If the target has no operations that require custom
3616  /// lowering, it need not implement this. The default implementation of this
3617  /// aborts.
3618  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3619 
3620  /// This callback is invoked when a node result type is illegal for the
3621  /// target, and the operation was registered to use 'custom' lowering for that
3622  /// result type. The target places new result values for the node in Results
3623  /// (their number and types must exactly match those of the original return
3624  /// values of the node), or leaves Results empty, which indicates that the
3625  /// node is not to be custom lowered after all.
3626  ///
3627  /// If the target has no operations that require custom lowering, it need not
3628  /// implement this. The default implementation aborts.
3629  virtual void ReplaceNodeResults(SDNode * /*N*/,
3630  SmallVectorImpl<SDValue> &/*Results*/,
3631  SelectionDAG &/*DAG*/) const {
3632  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3633  }
3634 
3635  /// This method returns the name of a target specific DAG node.
3636  virtual const char *getTargetNodeName(unsigned Opcode) const;
3637 
3638  /// This method returns a target specific FastISel object, or null if the
3639  /// target does not support "fast" ISel.
3641  const TargetLibraryInfo *) const {
3642  return nullptr;
3643  }
3644 
3645  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3646  SelectionDAG &DAG) const;
3647 
3648  //===--------------------------------------------------------------------===//
3649  // Inline Asm Support hooks
3650  //
3651 
3652  /// This hook allows the target to expand an inline asm call to be explicit
3653  /// llvm code if it wants to. This is useful for turning simple inline asms
3654  /// into LLVM intrinsics, which gives the compiler more information about the
3655  /// behavior of the code.
3656  virtual bool ExpandInlineAsm(CallInst *) const {
3657  return false;
3658  }
3659 
3661  C_Register, // Constraint represents specific register(s).
3662  C_RegisterClass, // Constraint represents any of register(s) in class.
3663  C_Memory, // Memory constraint.
3664  C_Other, // Something else.
3665  C_Unknown // Unsupported constraint.
3666  };
3667 
3669  // Generic weights.
3670  CW_Invalid = -1, // No match.
3671  CW_Okay = 0, // Acceptable.
3672  CW_Good = 1, // Good weight.
3673  CW_Better = 2, // Better weight.
3674  CW_Best = 3, // Best weight.
3675 
3676  // Well-known weights.
3677  CW_SpecificReg = CW_Okay, // Specific register operands.
3678  CW_Register = CW_Good, // Register operands.
3679  CW_Memory = CW_Better, // Memory operands.
3680  CW_Constant = CW_Best, // Constant operand.
3681  CW_Default = CW_Okay // Default or don't know type.
3682  };
3683 
3684  /// This contains information for each constraint that we are lowering.
3686  /// This contains the actual string for the code, like "m". TargetLowering
3687  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3688  /// matches the operand.
3689  std::string ConstraintCode;
3690 
3691  /// Information about the constraint code, e.g. Register, RegisterClass,
3692  /// Memory, Other, Unknown.
3694 
3695  /// If this is the result output operand or a clobber, this is null,
3696  /// otherwise it is the incoming operand to the CallInst. This gets
3697  /// modified as the asm is processed.
3698  Value *CallOperandVal = nullptr;
3699 
3700  /// The ValueType for the operand value.
3701  MVT ConstraintVT = MVT::Other;
3702 
3703  /// Copy constructor for copying from a ConstraintInfo.
3705  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3706 
3707  /// Return true of this is an input operand that is a matching constraint
3708  /// like "4".
3709  bool isMatchingInputConstraint() const;
3710 
3711  /// If this is an input matching constraint, this method returns the output
3712  /// operand it matches.
3713  unsigned getMatchedOperand() const;
3714  };
3715 
3716  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3717 
3718  /// Split up the constraint string from the inline assembly value into the
3719  /// specific constraints and their prefixes, and also tie in the associated
3720  /// operand values. If this returns an empty vector, and if the constraint
3721  /// string itself isn't empty, there was an error parsing.
3722  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3723  const TargetRegisterInfo *TRI,
3724  ImmutableCallSite CS) const;
3725 
3726  /// Examine constraint type and operand type and determine a weight value.
3727  /// The operand object must already have been set up with the operand type.
3728  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3729  AsmOperandInfo &info, int maIndex) const;
3730 
3731  /// Examine constraint string and operand type and determine a weight value.
3732  /// The operand object must already have been set up with the operand type.
3733  virtual ConstraintWeight getSingleConstraintMatchWeight(
3734  AsmOperandInfo &info, const char *constraint) const;
3735 
3736  /// Determines the constraint code and constraint type to use for the specific
3737  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3738  /// If the actual operand being passed in is available, it can be passed in as
3739  /// Op, otherwise an empty SDValue can be passed.
3740  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3741  SDValue Op,
3742  SelectionDAG *DAG = nullptr) const;
3743 
3744  /// Given a constraint, return the type of constraint it is for this target.
3745  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3746 
3747  /// Given a physical register constraint (e.g. {edx}), return the register
3748  /// number and the register class for the register.
3749  ///
3750  /// Given a register class constraint, like 'r', if this corresponds directly
3751  /// to an LLVM register class, return a register of 0 and the register class
3752  /// pointer.
3753  ///
3754  /// This should only be used for C_Register constraints. On error, this
3755  /// returns a register number of 0 and a null register class pointer.
3756  virtual std::pair<unsigned, const TargetRegisterClass *>
3757  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3758  StringRef Constraint, MVT VT) const;
3759 
3760  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3761  if (ConstraintCode == "i")
3762  return InlineAsm::Constraint_i;
3763  else if (ConstraintCode == "m")
3764  return InlineAsm::Constraint_m;
3766  }
3767 
3768  /// Try to replace an X constraint, which matches anything, with another that
3769  /// has more specific requirements based on the type of the corresponding
3770  /// operand. This returns null if there is no replacement to make.
3771  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3772 
3773  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3774  /// add anything to Ops.
3775  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3776  std::vector<SDValue> &Ops,
3777  SelectionDAG &DAG) const;
3778 
3779  // Lower custom output constraints. If invalid, return SDValue().
3780  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3781  SDLoc DL,
3782  const AsmOperandInfo &OpInfo,
3783  SelectionDAG &DAG) const;
3784 
3785  //===--------------------------------------------------------------------===//
3786  // Div utility functions
3787  //
3788  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3789  SmallVectorImpl<SDNode *> &Created) const;
3790  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3791  SmallVectorImpl<SDNode *> &Created) const;
3792 
3793  /// Targets may override this function to provide custom SDIV lowering for
3794  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3795  /// assumes SDIV is expensive and replaces it with a series of other integer
3796  /// operations.
3797  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3798  SelectionDAG &DAG,
3799  SmallVectorImpl<SDNode *> &Created) const;
3800 
3801  /// Indicate whether this target prefers to combine FDIVs with the same
3802  /// divisor. If the transform should never be done, return zero. If the
3803  /// transform should be done, return the minimum number of divisor uses
3804  /// that must exist.
3805  virtual unsigned combineRepeatedFPDivisors() const {
3806  return 0;
3807  }
3808 
3809  /// Hooks for building estimates in place of slower divisions and square
3810  /// roots.
3811 
3812  /// Return either a square root or its reciprocal estimate value for the input
3813  /// operand.
3814  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3815  /// 'Enabled' as set by a potential default override attribute.
3816  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3817  /// refinement iterations required to generate a sufficient (though not
3818  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3819  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3820  /// algorithm implementation that uses either one or two constants.
3821  /// The boolean Reciprocal is used to select whether the estimate is for the
3822  /// square root of the input operand or the reciprocal of its square root.
3823  /// A target may choose to implement its own refinement within this function.
3824  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3825  /// any further refinement of the estimate.
3826  /// An empty SDValue return means no estimate sequence can be created.
3828  int Enabled, int &RefinementSteps,
3829  bool &UseOneConstNR, bool Reciprocal) const {
3830  return SDValue();
3831  }
3832 
3833  /// Return a reciprocal estimate value for the input operand.
3834  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3835  /// 'Enabled' as set by a potential default override attribute.
3836  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3837  /// refinement iterations required to generate a sufficient (though not
3838  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3839  /// A target may choose to implement its own refinement within this function.
3840  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3841  /// any further refinement of the estimate.
3842  /// An empty SDValue return means no estimate sequence can be created.
3844  int Enabled, int &RefinementSteps) const {
3845  return SDValue();
3846  }
3847 
3848  //===--------------------------------------------------------------------===//
3849  // Legalization utility functions
3850  //
3851 
3852  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3853  /// respectively, each computing an n/2-bit part of the result.
3854  /// \param Result A vector that will be filled with the parts of the result
3855  /// in little-endian order.
3856  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3857  /// if you want to control how low bits are extracted from the LHS.
3858  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3859  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3860  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3861  /// \returns true if the node has been expanded, false if it has not
3862  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3863  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3865  SDValue LL = SDValue(), SDValue LH = SDValue(),
3866  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3867 
3868  /// Expand a MUL into two nodes. One that computes the high bits of
3869  /// the result and one that computes the low bits.
3870  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3871  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3872  /// if you want to control how low bits are extracted from the LHS.
3873  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3874  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3875  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3876  /// \returns true if the node has been expanded. false if it has not
3877  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3878  SelectionDAG &DAG, MulExpansionKind Kind,
3879  SDValue LL = SDValue(), SDValue LH = SDValue(),
3880  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3881 
3882  /// Expand funnel shift.
3883  /// \param N Node to expand
3884  /// \param Result output after conversion
3885  /// \returns True, if the expansion was successful, false otherwise
3886  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3887 
3888  /// Expand rotations.
3889  /// \param N Node to expand
3890  /// \param Result output after conversion
3891  /// \returns True, if the expansion was successful, false otherwise
3892  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3893 
3894  /// Expand float(f32) to SINT(i64) conversion
3895  /// \param N Node to expand
3896  /// \param Result output after conversion
3897  /// \returns True, if the expansion was successful, false otherwise
3898  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3899 
3900  /// Expand float to UINT conversion
3901  /// \param N Node to expand
3902  /// \param Result output after conversion
3903  /// \returns True, if the expansion was successful, false otherwise
3904  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3905 
3906  /// Expand UINT(i64) to double(f64) conversion
3907  /// \param N Node to expand
3908  /// \param Result output after conversion
3909  /// \returns True, if the expansion was successful, false otherwise
3910  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3911 
3912  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3913  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3914 
3915  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3916  /// vector nodes can only succeed if all operations are legal/custom.
3917  /// \param N Node to expand
3918  /// \param Result output after conversion
3919  /// \returns True, if the expansion was successful, false otherwise
3920  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3921 
3922  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3923  /// vector nodes can only succeed if all operations are legal/custom.
3924  /// \param N Node to expand
3925  /// \param Result output after conversion
3926  /// \returns True, if the expansion was successful, false otherwise
3927  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3928 
3929  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3930  /// vector nodes can only succeed if all operations are legal/custom.
3931  /// \param N Node to expand
3932  /// \param Result output after conversion
3933  /// \returns True, if the expansion was successful, false otherwise
3934  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3935 
3936  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
3937  /// vector nodes can only succeed if all operations are legal/custom.
3938  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
3939  /// \param N Node to expand
3940  /// \param Result output after conversion
3941  /// \returns True, if the expansion was successful, false otherwise
3942  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3943 
3944  /// Turn load of vector type into a load of the individual elements.
3945  /// \param LD load to expand
3946  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3947  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3948 
3949  // Turn a store of a vector type into stores of the individual elements.
3950  /// \param ST Store with a vector value type
3951  /// \returns MERGE_VALUs of the individual store chains.
3953 
3954  /// Expands an unaligned load to 2 half-size loads for an integer, and
3955  /// possibly more for vectors.
3956  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3957  SelectionDAG &DAG) const;
3958 
3959  /// Expands an unaligned store to 2 half-size stores for integer values, and
3960  /// possibly more for vectors.
3961  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3962 
3963  /// Increments memory address \p Addr according to the type of the value
3964  /// \p DataVT that should be stored. If the data is stored in compressed
3965  /// form, the memory address should be incremented according to the number of
3966  /// the stored elements. This number is equal to the number of '1's bits
3967  /// in the \p Mask.
3968  /// \p DataVT is a vector type. \p Mask is a vector value.
3969  /// \p DataVT and \p Mask have the same number of vector elements.
3970  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3971  EVT DataVT, SelectionDAG &DAG,
3972  bool IsCompressedMemory) const;
3973 
3974  /// Get a pointer to vector element \p Idx located in memory for a vector of
3975  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3976  /// bounds the returned pointer is unspecified, but will be within the vector
3977  /// bounds.
3978  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3979  SDValue Index) const;
3980 
3981  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3982  /// method accepts integers as its arguments.
3983  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
3984 
3985  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
3986  /// integers as its arguments.
3987  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
3988 
3989  /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
3990  /// always suceeds and populates the Result and Overflow arguments.
3991  void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3992  SelectionDAG &DAG) const;
3993 
3994  /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
3995  /// always suceeds and populates the Result and Overflow arguments.
3996  void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3997  SelectionDAG &DAG) const;
3998 
3999  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4000  /// expansion was successful and populates the Result and Overflow arguments.
4001  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4002  SelectionDAG &DAG) const;
4003 
4004  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4005  /// only the first Count elements of the vector are used.
4006  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
4007 
4008  //===--------------------------------------------------------------------===//
4009  // Instruction Emitting Hooks
4010  //
4011 
4012  /// This method should be implemented by targets that mark instructions with
4013  /// the 'usesCustomInserter' flag. These instructions are special in various
4014  /// ways, which require special support to insert. The specified MachineInstr
4015  /// is created but not inserted into any basic blocks, and this method is
4016  /// called to expand it into a sequence of instructions, potentially also
4017  /// creating new basic blocks and control flow.
4018  /// As long as the returned basic block is different (i.e., we created a new
4019  /// one), the custom inserter is free to modify the rest of \p MBB.
4020  virtual MachineBasicBlock *
4021  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4022 
4023  /// This method should be implemented by targets that mark instructions with
4024  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4025  /// instruction selection by target hooks. e.g. To fill in optional defs for
4026  /// ARM 's' setting instructions.
4027  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4028  SDNode *Node) const;
4029 
4030  /// If this function returns true, SelectionDAGBuilder emits a
4031  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4032  virtual bool useLoadStackGuardNode() const {
4033  return false;
4034  }
4035 
4037  const SDLoc &DL) const {
4038  llvm_unreachable("not implemented for this target");
4039  }
4040 
4041  /// Lower TLS global address SDNode for target independent emulated TLS model.
4042  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4043  SelectionDAG &DAG) const;
4044 
4045  /// Expands target specific indirect branch for the case of JumpTable
4046  /// expanasion.
4048  SelectionDAG &DAG) const {
4049  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4050  }
4051 
4052  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4053  // If we're comparing for equality to zero and isCtlzFast is true, expose the
4054  // fact that this can be implemented as a ctlz/srl pair, so that the dag
4055  // combiner can fold the new nodes.
4056  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4057 
4058 private:
4059  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4060  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4061  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4062  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4063 
4064  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4065  SDValue N1, ISD::CondCode Cond,
4066  DAGCombinerInfo &DCI,
4067  const SDLoc &DL) const;
4068 };
4069 
4070 /// Given an LLVM IR type and return type attributes, compute the return value
4071 /// EVTs and flags, and optionally also the offsets, if the return value is
4072 /// being lowered to memory.
4075  const TargetLowering &TLI, const DataLayout &DL);
4076 
4077 } // end namespace llvm
4078 
4079 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:398
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:614
virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:380
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1100
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:269
void * PointerTy
Definition: GenericValue.h:21
bool hasOneUse() const
Return true if there is exactly one use of this node.
A description of a memory reference used in the backend.
Definition: BitVector.h:937
virtual bool decomposeMulByConstant(EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
virtual bool mergeStoresAfterLegalization(EVT MemVT) const
Allow store merging for the specified type after legalization in addition to before legalization...
SimpleValueType SimpleTy
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:62
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
InstrTy * getInstruction() const
Definition: CallSite.h:96
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
static cl::opt< unsigned > MaxLoadsPerMemcmpOptSize("max-loads-per-memcmp-opt-size", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz"))
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const
Return true if sinking I&#39;s operands to the same basic block as I is profitable, e.g.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:232
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
An instruction for storing to memory.
Definition: Instructions.h:320
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:544
This class is used to represent ISD::STORE nodes.
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx)
static cl::opt< unsigned > MaxLoadsPerMemcmp("max-loads-per-memcmp", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp"))
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT, SelectionDAG &DAG)
Scalarize a vector store, bitcasting to TargetVT to determine the scalar type.
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:41
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isFloatingPointOperation() const
Definition: Instructions.h:823
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:970
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:15
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
virtual bool isProfitableToHoist(Instruction *I) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...