LLVM  10.0.0svn
X86LegalizerInfo.cpp
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1 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for X86.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86LegalizerInfo.h"
14 #include "X86Subtarget.h"
15 #include "X86TargetMachine.h"
19 #include "llvm/IR/DerivedTypes.h"
20 #include "llvm/IR/Type.h"
21 
22 using namespace llvm;
23 using namespace TargetOpcode;
24 using namespace LegalizeActions;
25 
26 /// FIXME: The following static functions are SizeChangeStrategy functions
27 /// that are meant to temporarily mimic the behaviour of the old legalization
28 /// based on doubling/halving non-legal types as closely as possible. This is
29 /// not entirly possible as only legalizing the types that are exactly a power
30 /// of 2 times the size of the legal types would require specifying all those
31 /// sizes explicitly.
32 /// In practice, not specifying those isn't a problem, and the below functions
33 /// should disappear quickly as we add support for legalizing non-power-of-2
34 /// sized types further.
35 static void
38  for (unsigned i = 0; i < v.size(); ++i) {
39  result.push_back(v[i]);
40  if (i + 1 < v[i].first && i + 1 < v.size() &&
41  v[i + 1].first != v[i].first + 1)
42  result.push_back({v[i].first + 1, Unsupported});
43  }
44 }
45 
48  assert(v.size() >= 1);
49  assert(v[0].first > 1);
51  {2, Unsupported}};
53  auto Largest = result.back().first;
54  result.push_back({Largest + 1, Unsupported});
55  return result;
56 }
57 
59  const X86TargetMachine &TM)
60  : Subtarget(STI), TM(TM) {
61 
62  setLegalizerInfo32bit();
63  setLegalizerInfo64bit();
64  setLegalizerInfoSSE1();
65  setLegalizerInfoSSE2();
66  setLegalizerInfoSSE41();
67  setLegalizerInfoAVX();
68  setLegalizerInfoAVX2();
69  setLegalizerInfoAVX512();
70  setLegalizerInfoAVX512DQ();
71  setLegalizerInfoAVX512BW();
72 
74  for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
76  for (unsigned MemOp : {G_LOAD, G_STORE})
83 
84  computeTables();
85  verify(*STI.getInstrInfo());
86 }
87 
90  MachineIRBuilder &MIRBuilder) const {
91  switch (MI.getIntrinsicID()) {
92  case Intrinsic::memcpy:
93  case Intrinsic::memset:
94  case Intrinsic::memmove:
95  if (createMemLibcall(MIRBuilder, MRI, MI) ==
97  return false;
98  MI.eraseFromParent();
99  return true;
100  default:
101  break;
102  }
103  return true;
104 }
105 
106 void X86LegalizerInfo::setLegalizerInfo32bit() {
107 
108  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
109  const LLT s1 = LLT::scalar(1);
110  const LLT s8 = LLT::scalar(8);
111  const LLT s16 = LLT::scalar(16);
112  const LLT s32 = LLT::scalar(32);
113  const LLT s64 = LLT::scalar(64);
114  const LLT s128 = LLT::scalar(128);
115 
116  for (auto Ty : {p0, s1, s8, s16, s32})
117  setAction({G_IMPLICIT_DEF, Ty}, Legal);
118 
119  for (auto Ty : {s8, s16, s32, p0})
120  setAction({G_PHI, Ty}, Legal);
121 
122  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
123  for (auto Ty : {s8, s16, s32})
124  setAction({BinOp, Ty}, Legal);
125 
126  for (unsigned Op : {G_UADDE}) {
127  setAction({Op, s32}, Legal);
128  setAction({Op, 1, s1}, Legal);
129  }
130 
131  for (unsigned MemOp : {G_LOAD, G_STORE}) {
132  for (auto Ty : {s8, s16, s32, p0})
133  setAction({MemOp, Ty}, Legal);
134 
135  // And everything's fine in addrspace 0.
136  setAction({MemOp, 1, p0}, Legal);
137  }
138 
139  // Pointer-handling
140  setAction({G_FRAME_INDEX, p0}, Legal);
141  setAction({G_GLOBAL_VALUE, p0}, Legal);
142 
143  setAction({G_GEP, p0}, Legal);
144  setAction({G_GEP, 1, s32}, Legal);
145 
146  if (!Subtarget.is64Bit()) {
147  getActionDefinitionsBuilder(G_PTRTOINT)
148  .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
149  .maxScalar(0, s32)
150  .widenScalarToNextPow2(0, /*Min*/ 8);
151  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
152 
153  // Shifts and SDIV
155  {G_SDIV, G_SREM, G_UDIV, G_UREM})
156  .legalFor({s8, s16, s32})
157  .clampScalar(0, s8, s32);
158 
160  {G_SHL, G_LSHR, G_ASHR})
161  .legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
162  .clampScalar(0, s8, s32)
163  .clampScalar(1, s8, s8);
164  }
165 
166  // Control-flow
167  setAction({G_BRCOND, s1}, Legal);
168 
169  // Constants
170  for (auto Ty : {s8, s16, s32, p0})
171  setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
172 
173  // Extensions
174  for (auto Ty : {s8, s16, s32}) {
175  setAction({G_ZEXT, Ty}, Legal);
176  setAction({G_SEXT, Ty}, Legal);
177  setAction({G_ANYEXT, Ty}, Legal);
178  }
179  setAction({G_ANYEXT, s128}, Legal);
180 
181  // Comparison
182  setAction({G_ICMP, s1}, Legal);
183 
184  for (auto Ty : {s8, s16, s32, p0})
185  setAction({G_ICMP, 1, Ty}, Legal);
186 
187  // Merge/Unmerge
188  for (const auto &Ty : {s16, s32, s64}) {
189  setAction({G_MERGE_VALUES, Ty}, Legal);
190  setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
191  }
192  for (const auto &Ty : {s8, s16, s32}) {
193  setAction({G_MERGE_VALUES, 1, Ty}, Legal);
194  setAction({G_UNMERGE_VALUES, Ty}, Legal);
195  }
196 }
197 
198 void X86LegalizerInfo::setLegalizerInfo64bit() {
199 
200  if (!Subtarget.is64Bit())
201  return;
202 
203  const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
204  const LLT s1 = LLT::scalar(1);
205  const LLT s8 = LLT::scalar(8);
206  const LLT s16 = LLT::scalar(16);
207  const LLT s32 = LLT::scalar(32);
208  const LLT s64 = LLT::scalar(64);
209  const LLT s128 = LLT::scalar(128);
210 
211  setAction({G_IMPLICIT_DEF, s64}, Legal);
212  // Need to have that, as tryFoldImplicitDef will create this pattern:
213  // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
214  setAction({G_IMPLICIT_DEF, s128}, Legal);
215 
216  setAction({G_PHI, s64}, Legal);
217 
218  for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
219  setAction({BinOp, s64}, Legal);
220 
221  for (unsigned MemOp : {G_LOAD, G_STORE})
222  setAction({MemOp, s64}, Legal);
223 
224  // Pointer-handling
225  setAction({G_GEP, 1, s64}, Legal);
226  getActionDefinitionsBuilder(G_PTRTOINT)
227  .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
228  .maxScalar(0, s64)
229  .widenScalarToNextPow2(0, /*Min*/ 8);
230  getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s64}});
231 
232  // Constants
233  setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
234 
235  // Extensions
236  for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
237  setAction({extOp, s64}, Legal);
238  }
239 
241  .legalForCartesianProduct({s32, s64})
242  .clampScalar(1, s32, s64)
244  .clampScalar(0, s32, s64)
246 
248  .legalForCartesianProduct({s32, s64})
249  .clampScalar(1, s32, s64)
251  .clampScalar(0, s32, s64)
253 
254  // Comparison
255  setAction({G_ICMP, 1, s64}, Legal);
256 
258  .legalForCartesianProduct({s8}, {s32, s64})
259  .clampScalar(0, s8, s8)
260  .clampScalar(1, s32, s64)
262 
263  // Divisions
265  {G_SDIV, G_SREM, G_UDIV, G_UREM})
266  .legalFor({s8, s16, s32, s64})
267  .clampScalar(0, s8, s64);
268 
269  // Shifts
271  {G_SHL, G_LSHR, G_ASHR})
272  .legalFor({{s8, s8}, {s16, s8}, {s32, s8}, {s64, s8}})
273  .clampScalar(0, s8, s64)
274  .clampScalar(1, s8, s8);
275 
276  // Merge/Unmerge
277  setAction({G_MERGE_VALUES, s128}, Legal);
278  setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
279  setAction({G_MERGE_VALUES, 1, s128}, Legal);
280  setAction({G_UNMERGE_VALUES, s128}, Legal);
281 }
282 
283 void X86LegalizerInfo::setLegalizerInfoSSE1() {
284  if (!Subtarget.hasSSE1())
285  return;
286 
287  const LLT s32 = LLT::scalar(32);
288  const LLT s64 = LLT::scalar(64);
289  const LLT v4s32 = LLT::vector(4, 32);
290  const LLT v2s64 = LLT::vector(2, 64);
291 
292  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
293  for (auto Ty : {s32, v4s32})
294  setAction({BinOp, Ty}, Legal);
295 
296  for (unsigned MemOp : {G_LOAD, G_STORE})
297  for (auto Ty : {v4s32, v2s64})
298  setAction({MemOp, Ty}, Legal);
299 
300  // Constants
301  setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
302 
303  // Merge/Unmerge
304  for (const auto &Ty : {v4s32, v2s64}) {
305  setAction({G_CONCAT_VECTORS, Ty}, Legal);
306  setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
307  }
308  setAction({G_MERGE_VALUES, 1, s64}, Legal);
309  setAction({G_UNMERGE_VALUES, s64}, Legal);
310 }
311 
312 void X86LegalizerInfo::setLegalizerInfoSSE2() {
313  if (!Subtarget.hasSSE2())
314  return;
315 
316  const LLT s32 = LLT::scalar(32);
317  const LLT s64 = LLT::scalar(64);
318  const LLT v16s8 = LLT::vector(16, 8);
319  const LLT v8s16 = LLT::vector(8, 16);
320  const LLT v4s32 = LLT::vector(4, 32);
321  const LLT v2s64 = LLT::vector(2, 64);
322 
323  const LLT v32s8 = LLT::vector(32, 8);
324  const LLT v16s16 = LLT::vector(16, 16);
325  const LLT v8s32 = LLT::vector(8, 32);
326  const LLT v4s64 = LLT::vector(4, 64);
327 
328  for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
329  for (auto Ty : {s64, v2s64})
330  setAction({BinOp, Ty}, Legal);
331 
332  for (unsigned BinOp : {G_ADD, G_SUB})
333  for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
334  setAction({BinOp, Ty}, Legal);
335 
336  setAction({G_MUL, v8s16}, Legal);
337 
338  setAction({G_FPEXT, s64}, Legal);
339  setAction({G_FPEXT, 1, s32}, Legal);
340 
341  setAction({G_FPTRUNC, s32}, Legal);
342  setAction({G_FPTRUNC, 1, s64}, Legal);
343 
344  // Constants
345  setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
346 
347  // Merge/Unmerge
348  for (const auto &Ty :
349  {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
350  setAction({G_CONCAT_VECTORS, Ty}, Legal);
351  setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
352  }
353  for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
354  setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
355  setAction({G_UNMERGE_VALUES, Ty}, Legal);
356  }
357 }
358 
359 void X86LegalizerInfo::setLegalizerInfoSSE41() {
360  if (!Subtarget.hasSSE41())
361  return;
362 
363  const LLT v4s32 = LLT::vector(4, 32);
364 
365  setAction({G_MUL, v4s32}, Legal);
366 }
367 
368 void X86LegalizerInfo::setLegalizerInfoAVX() {
369  if (!Subtarget.hasAVX())
370  return;
371 
372  const LLT v16s8 = LLT::vector(16, 8);
373  const LLT v8s16 = LLT::vector(8, 16);
374  const LLT v4s32 = LLT::vector(4, 32);
375  const LLT v2s64 = LLT::vector(2, 64);
376 
377  const LLT v32s8 = LLT::vector(32, 8);
378  const LLT v64s8 = LLT::vector(64, 8);
379  const LLT v16s16 = LLT::vector(16, 16);
380  const LLT v32s16 = LLT::vector(32, 16);
381  const LLT v8s32 = LLT::vector(8, 32);
382  const LLT v16s32 = LLT::vector(16, 32);
383  const LLT v4s64 = LLT::vector(4, 64);
384  const LLT v8s64 = LLT::vector(8, 64);
385 
386  for (unsigned MemOp : {G_LOAD, G_STORE})
387  for (auto Ty : {v8s32, v4s64})
388  setAction({MemOp, Ty}, Legal);
389 
390  for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
391  setAction({G_INSERT, Ty}, Legal);
392  setAction({G_EXTRACT, 1, Ty}, Legal);
393  }
394  for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
395  setAction({G_INSERT, 1, Ty}, Legal);
396  setAction({G_EXTRACT, Ty}, Legal);
397  }
398  // Merge/Unmerge
399  for (const auto &Ty :
400  {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
401  setAction({G_CONCAT_VECTORS, Ty}, Legal);
402  setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
403  }
404  for (const auto &Ty :
405  {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
406  setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
407  setAction({G_UNMERGE_VALUES, Ty}, Legal);
408  }
409 }
410 
411 void X86LegalizerInfo::setLegalizerInfoAVX2() {
412  if (!Subtarget.hasAVX2())
413  return;
414 
415  const LLT v32s8 = LLT::vector(32, 8);
416  const LLT v16s16 = LLT::vector(16, 16);
417  const LLT v8s32 = LLT::vector(8, 32);
418  const LLT v4s64 = LLT::vector(4, 64);
419 
420  const LLT v64s8 = LLT::vector(64, 8);
421  const LLT v32s16 = LLT::vector(32, 16);
422  const LLT v16s32 = LLT::vector(16, 32);
423  const LLT v8s64 = LLT::vector(8, 64);
424 
425  for (unsigned BinOp : {G_ADD, G_SUB})
426  for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
427  setAction({BinOp, Ty}, Legal);
428 
429  for (auto Ty : {v16s16, v8s32})
430  setAction({G_MUL, Ty}, Legal);
431 
432  // Merge/Unmerge
433  for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
434  setAction({G_CONCAT_VECTORS, Ty}, Legal);
435  setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
436  }
437  for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
438  setAction({G_CONCAT_VECTORS, 1, Ty}, Legal);
439  setAction({G_UNMERGE_VALUES, Ty}, Legal);
440  }
441 }
442 
443 void X86LegalizerInfo::setLegalizerInfoAVX512() {
444  if (!Subtarget.hasAVX512())
445  return;
446 
447  const LLT v16s8 = LLT::vector(16, 8);
448  const LLT v8s16 = LLT::vector(8, 16);
449  const LLT v4s32 = LLT::vector(4, 32);
450  const LLT v2s64 = LLT::vector(2, 64);
451 
452  const LLT v32s8 = LLT::vector(32, 8);
453  const LLT v16s16 = LLT::vector(16, 16);
454  const LLT v8s32 = LLT::vector(8, 32);
455  const LLT v4s64 = LLT::vector(4, 64);
456 
457  const LLT v64s8 = LLT::vector(64, 8);
458  const LLT v32s16 = LLT::vector(32, 16);
459  const LLT v16s32 = LLT::vector(16, 32);
460  const LLT v8s64 = LLT::vector(8, 64);
461 
462  for (unsigned BinOp : {G_ADD, G_SUB})
463  for (auto Ty : {v16s32, v8s64})
464  setAction({BinOp, Ty}, Legal);
465 
466  setAction({G_MUL, v16s32}, Legal);
467 
468  for (unsigned MemOp : {G_LOAD, G_STORE})
469  for (auto Ty : {v16s32, v8s64})
470  setAction({MemOp, Ty}, Legal);
471 
472  for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
473  setAction({G_INSERT, Ty}, Legal);
474  setAction({G_EXTRACT, 1, Ty}, Legal);
475  }
476  for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
477  setAction({G_INSERT, 1, Ty}, Legal);
478  setAction({G_EXTRACT, Ty}, Legal);
479  }
480 
481  /************ VLX *******************/
482  if (!Subtarget.hasVLX())
483  return;
484 
485  for (auto Ty : {v4s32, v8s32})
486  setAction({G_MUL, Ty}, Legal);
487 }
488 
489 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
490  if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
491  return;
492 
493  const LLT v8s64 = LLT::vector(8, 64);
494 
495  setAction({G_MUL, v8s64}, Legal);
496 
497  /************ VLX *******************/
498  if (!Subtarget.hasVLX())
499  return;
500 
501  const LLT v2s64 = LLT::vector(2, 64);
502  const LLT v4s64 = LLT::vector(4, 64);
503 
504  for (auto Ty : {v2s64, v4s64})
505  setAction({G_MUL, Ty}, Legal);
506 }
507 
508 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
509  if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
510  return;
511 
512  const LLT v64s8 = LLT::vector(64, 8);
513  const LLT v32s16 = LLT::vector(32, 16);
514 
515  for (unsigned BinOp : {G_ADD, G_SUB})
516  for (auto Ty : {v64s8, v32s16})
517  setAction({BinOp, Ty}, Legal);
518 
519  setAction({G_MUL, v32s16}, Legal);
520 
521  /************ VLX *******************/
522  if (!Subtarget.hasVLX())
523  return;
524 
525  const LLT v8s16 = LLT::vector(8, 16);
526  const LLT v16s16 = LLT::vector(16, 16);
527 
528  for (auto Ty : {v8s16, v16s16})
529  setAction({G_MUL, Ty}, Legal);
530 }
bool hasAVX() const
Definition: X86Subtarget.h:581
static void addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result, const LegalizerInfo::SizeAndActionsVec &v)
FIXME: The following static functions are SizeChangeStrategy functions that are meant to temporarily ...
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:542
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
bool hasSSE41() const
Definition: X86Subtarget.h:579
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasAVX2() const
Definition: X86Subtarget.h:582
The operation should be implemented in terms of a wider scalar base-type.
Definition: LegalizerInfo.h:57
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:501
X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM)
std::vector< SizeAndAction > SizeAndActionsVec
static LegalizerInfo::SizeAndActionsVec widen_1(const LegalizerInfo::SizeAndActionsVec &v)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
static SizeAndActionsVec widenToLargerTypesUnsupportedOtherwise(const SizeAndActionsVec &v)
LegalizeRuleSet & widenScalarToNextPow2(unsigned TypeIdx, unsigned MinSize=0)
Widen the scalar to the next power of two that is at least MinSize.
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This operation is completely unsupported on the target.
Definition: LegalizerInfo.h:85
bool hasVLX() const
Definition: X86Subtarget.h:681
void verify(const MCInstrInfo &MII) const
Perform simple self-diagnostic and assert if there is anything obviously wrong with the actions set u...
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
unsigned getPointerSizeInBits(unsigned AS) const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
bool hasDQI() const
Definition: X86Subtarget.h:679
bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const override
Return true if MI is either legal or has been legalized and false if not legal.
unsigned const MachineRegisterInfo * MRI
Helper class to build MachineInstr.
LegalizerHelper::LegalizeResult createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstr &MI)
Create a libcall to memcpy et al.
LegalizeRuleSet & clampScalar(unsigned TypeIdx, const LLT &MinTy, const LLT &MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
Some kind of error has occurred and we could not legalize this instruction.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
unsigned first
static SizeAndActionsVec narrowToSmallerAndWidenToSmallest(const SizeAndActionsVec &v)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static SizeAndActionsVec widenToLargerTypesAndNarrowToLargest(const SizeAndActionsVec &v)
A SizeChangeStrategy for the common case where legalization for a particular operation consists of wi...
void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, const unsigned TypeIdx, SizeChangeStrategy S)
The setAction calls record the non-size-changing legalization actions to take on specificly-sized typ...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSSE1() const
Definition: X86Subtarget.h:575
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
This file declares the targeting of the Machinelegalizer class for X86.
bool hasAVX512() const
Definition: X86Subtarget.h:583
IRTranslator LLVM IR MI
bool hasBWI() const
Definition: X86Subtarget.h:680
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
void setAction(const InstrAspect &Aspect, LegalizeAction Action)
More friendly way to set an action for common types that have an LLT representation.
The operation is expected to be selectable directly by the target, and no transformation is necessary...
Definition: LegalizerInfo.h:47
bool hasSSE2() const
Definition: X86Subtarget.h:576