LLVM  10.0.0svn
MachineInstr.h
Go to the documentation of this file.
1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
11 // the back end.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
17 
18 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCSymbol.h"
32 #include <algorithm>
33 #include <cassert>
34 #include <cstdint>
35 #include <utility>
36 
37 namespace llvm {
38 
39 class AAResults;
40 template <typename T> class ArrayRef;
41 class DIExpression;
42 class DILocalVariable;
43 class MachineBasicBlock;
44 class MachineFunction;
45 class MachineMemOperand;
46 class MachineRegisterInfo;
47 class ModuleSlotTracker;
48 class raw_ostream;
49 template <typename T> class SmallVectorImpl;
50 class SmallBitVector;
51 class StringRef;
52 class TargetInstrInfo;
53 class TargetRegisterClass;
54 class TargetRegisterInfo;
55 
56 //===----------------------------------------------------------------------===//
57 /// Representation of each machine instruction.
58 ///
59 /// This class isn't a POD type, but it must have a trivial destructor. When a
60 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
61 /// without having their destructor called.
62 ///
64  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
65  ilist_sentinel_tracking<true>> {
66 public:
68 
69  /// Flags to specify different kinds of comments to output in
70  /// assembly code. These flags carry semantic information not
71  /// otherwise easily derivable from the IR text.
72  ///
73  enum CommentFlag {
74  ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
76  TAsmComments = 0x4 // Target Asm comments should start from this value.
77  };
78 
79  enum MIFlag {
80  NoFlags = 0,
81  FrameSetup = 1 << 0, // Instruction is used as a part of
82  // function frame setup code.
83  FrameDestroy = 1 << 1, // Instruction is used as a part of
84  // function frame destruction code.
85  BundledPred = 1 << 2, // Instruction has bundled predecessors.
86  BundledSucc = 1 << 3, // Instruction has bundled successors.
87  FmNoNans = 1 << 4, // Instruction does not support Fast
88  // math nan values.
89  FmNoInfs = 1 << 5, // Instruction does not support Fast
90  // math infinity values.
91  FmNsz = 1 << 6, // Instruction is not required to retain
92  // signed zero values.
93  FmArcp = 1 << 7, // Instruction supports Fast math
94  // reciprocal approximations.
95  FmContract = 1 << 8, // Instruction supports Fast math
96  // contraction operations like fma.
97  FmAfn = 1 << 9, // Instruction may map to Fast math
98  // instrinsic approximation.
99  FmReassoc = 1 << 10, // Instruction supports Fast math
100  // reassociation of operand order.
101  NoUWrap = 1 << 11, // Instruction supports binary operator
102  // no unsigned wrap.
103  NoSWrap = 1 << 12, // Instruction supports binary operator
104  // no signed wrap.
105  IsExact = 1 << 13, // Instruction supports division is
106  // known to be exact.
107  FPExcept = 1 << 14, // Instruction may raise floating-point
108  // exceptions.
109  };
110 
111 private:
112  const MCInstrDesc *MCID; // Instruction descriptor.
113  MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
114 
115  // Operands are allocated by an ArrayRecycler.
116  MachineOperand *Operands = nullptr; // Pointer to the first operand.
117  unsigned NumOperands = 0; // Number of operands on instruction.
118  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
119  OperandCapacity CapOperands; // Capacity of the Operands array.
120 
121  uint16_t Flags = 0; // Various bits of additional
122  // information about machine
123  // instruction.
124 
125  uint8_t AsmPrinterFlags = 0; // Various bits of information used by
126  // the AsmPrinter to emit helpful
127  // comments. This is *not* semantic
128  // information. Do not use this for
129  // anything other than to convey comment
130  // information to AsmPrinter.
131 
132  /// Internal implementation detail class that provides out-of-line storage for
133  /// extra info used by the machine instruction when this info cannot be stored
134  /// in-line within the instruction itself.
135  ///
136  /// This has to be defined eagerly due to the implementation constraints of
137  /// `PointerSumType` where it is used.
138  class ExtraInfo final
139  : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
140  public:
141  static ExtraInfo *create(BumpPtrAllocator &Allocator,
143  MCSymbol *PreInstrSymbol = nullptr,
144  MCSymbol *PostInstrSymbol = nullptr) {
145  bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
146  bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
147  auto *Result = new (Allocator.Allocate(
148  totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
149  MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
150  alignof(ExtraInfo)))
151  ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
152 
153  // Copy the actual data into the trailing objects.
154  std::copy(MMOs.begin(), MMOs.end(),
155  Result->getTrailingObjects<MachineMemOperand *>());
156 
157  if (HasPreInstrSymbol)
158  Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
159  if (HasPostInstrSymbol)
160  Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
161  PostInstrSymbol;
162 
163  return Result;
164  }
165 
166  ArrayRef<MachineMemOperand *> getMMOs() const {
167  return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
168  }
169 
170  MCSymbol *getPreInstrSymbol() const {
171  return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
172  }
173 
174  MCSymbol *getPostInstrSymbol() const {
175  return HasPostInstrSymbol
176  ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
177  : nullptr;
178  }
179 
180  private:
181  friend TrailingObjects;
182 
183  // Description of the extra info, used to interpret the actual optional
184  // data appended.
185  //
186  // Note that this is not terribly space optimized. This leaves a great deal
187  // of flexibility to fit more in here later.
188  const int NumMMOs;
189  const bool HasPreInstrSymbol;
190  const bool HasPostInstrSymbol;
191 
192  // Implement the `TrailingObjects` internal API.
193  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
194  return NumMMOs;
195  }
196  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
197  return HasPreInstrSymbol + HasPostInstrSymbol;
198  }
199 
200  // Just a boring constructor to allow us to initialize the sizes. Always use
201  // the `create` routine above.
202  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
203  : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
204  HasPostInstrSymbol(HasPostInstrSymbol) {}
205  };
206 
207  /// Enumeration of the kinds of inline extra info available. It is important
208  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
209  /// it accessible as an `ArrayRef`.
210  enum ExtraInfoInlineKinds {
211  EIIK_MMO = 0,
212  EIIK_PreInstrSymbol,
213  EIIK_PostInstrSymbol,
214  EIIK_OutOfLine
215  };
216 
217  // We store extra information about the instruction here. The common case is
218  // expected to be nothing or a single pointer (typically a MMO or a symbol).
219  // We work to optimize this common case by storing it inline here rather than
220  // requiring a separate allocation, but we fall back to an allocation when
221  // multiple pointers are needed.
222  PointerSumType<ExtraInfoInlineKinds,
227  Info;
228 
229  DebugLoc debugLoc; // Source line information.
230 
231  // Intrusive list support
232  friend struct ilist_traits<MachineInstr>;
234  void setParent(MachineBasicBlock *P) { Parent = P; }
235 
236  /// This constructor creates a copy of the given
237  /// MachineInstr in the given MachineFunction.
239 
240  /// This constructor create a MachineInstr and add the implicit operands.
241  /// It reserves space for number of operands specified by
242  /// MCInstrDesc. An explicit DebugLoc is supplied.
244  bool NoImp = false);
245 
246  // MachineInstrs are pool-allocated and owned by MachineFunction.
247  friend class MachineFunction;
248 
249 public:
250  MachineInstr(const MachineInstr &) = delete;
251  MachineInstr &operator=(const MachineInstr &) = delete;
252  // Use MachineFunction::DeleteMachineInstr() instead.
253  ~MachineInstr() = delete;
254 
255  const MachineBasicBlock* getParent() const { return Parent; }
256  MachineBasicBlock* getParent() { return Parent; }
257 
258  /// Return the function that contains the basic block that this instruction
259  /// belongs to.
260  ///
261  /// Note: this is undefined behaviour if the instruction does not have a
262  /// parent.
263  const MachineFunction *getMF() const;
265  return const_cast<MachineFunction *>(
266  static_cast<const MachineInstr *>(this)->getMF());
267  }
268 
269  /// Return the asm printer flags bitvector.
270  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
271 
272  /// Clear the AsmPrinter bitvector.
273  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
274 
275  /// Return whether an AsmPrinter flag is set.
277  return AsmPrinterFlags & Flag;
278  }
279 
280  /// Set a flag for the AsmPrinter.
281  void setAsmPrinterFlag(uint8_t Flag) {
282  AsmPrinterFlags |= Flag;
283  }
284 
285  /// Clear specific AsmPrinter flags.
287  AsmPrinterFlags &= ~Flag;
288  }
289 
290  /// Return the MI flags bitvector.
291  uint16_t getFlags() const {
292  return Flags;
293  }
294 
295  /// Return whether an MI flag is set.
296  bool getFlag(MIFlag Flag) const {
297  return Flags & Flag;
298  }
299 
300  /// Set a MI flag.
302  Flags |= (uint16_t)Flag;
303  }
304 
305  void setFlags(unsigned flags) {
306  // Filter out the automatically maintained flags.
307  unsigned Mask = BundledPred | BundledSucc;
308  Flags = (Flags & Mask) | (flags & ~Mask);
309  }
310 
311  /// clearFlag - Clear a MI flag.
313  Flags &= ~((uint16_t)Flag);
314  }
315 
316  /// Return true if MI is in a bundle (but not the first MI in a bundle).
317  ///
318  /// A bundle looks like this before it's finalized:
319  /// ----------------
320  /// | MI |
321  /// ----------------
322  /// |
323  /// ----------------
324  /// | MI * |
325  /// ----------------
326  /// |
327  /// ----------------
328  /// | MI * |
329  /// ----------------
330  /// In this case, the first MI starts a bundle but is not inside a bundle, the
331  /// next 2 MIs are considered "inside" the bundle.
332  ///
333  /// After a bundle is finalized, it looks like this:
334  /// ----------------
335  /// | Bundle |
336  /// ----------------
337  /// |
338  /// ----------------
339  /// | MI * |
340  /// ----------------
341  /// |
342  /// ----------------
343  /// | MI * |
344  /// ----------------
345  /// |
346  /// ----------------
347  /// | MI * |
348  /// ----------------
349  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
350  /// a bundle, but the next three MIs are.
351  bool isInsideBundle() const {
352  return getFlag(BundledPred);
353  }
354 
355  /// Return true if this instruction part of a bundle. This is true
356  /// if either itself or its following instruction is marked "InsideBundle".
357  bool isBundled() const {
358  return isBundledWithPred() || isBundledWithSucc();
359  }
360 
361  /// Return true if this instruction is part of a bundle, and it is not the
362  /// first instruction in the bundle.
363  bool isBundledWithPred() const { return getFlag(BundledPred); }
364 
365  /// Return true if this instruction is part of a bundle, and it is not the
366  /// last instruction in the bundle.
367  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
368 
369  /// Bundle this instruction with its predecessor. This can be an unbundled
370  /// instruction, or it can be the first instruction in a bundle.
371  void bundleWithPred();
372 
373  /// Bundle this instruction with its successor. This can be an unbundled
374  /// instruction, or it can be the last instruction in a bundle.
375  void bundleWithSucc();
376 
377  /// Break bundle above this instruction.
378  void unbundleFromPred();
379 
380  /// Break bundle below this instruction.
381  void unbundleFromSucc();
382 
383  /// Returns the debug location id of this MachineInstr.
384  const DebugLoc &getDebugLoc() const { return debugLoc; }
385 
386  /// Return the debug variable referenced by
387  /// this DBG_VALUE instruction.
388  const DILocalVariable *getDebugVariable() const;
389 
390  /// Return the complex address expression referenced by
391  /// this DBG_VALUE instruction.
392  const DIExpression *getDebugExpression() const;
393 
394  /// Return the debug label referenced by
395  /// this DBG_LABEL instruction.
396  const DILabel *getDebugLabel() const;
397 
398  /// Emit an error referring to the source location of this instruction.
399  /// This should only be used for inline assembly that is somehow
400  /// impossible to compile. Other errors should have been handled much
401  /// earlier.
402  ///
403  /// If this method returns, the caller should try to recover from the error.
404  void emitError(StringRef Msg) const;
405 
406  /// Returns the target instruction descriptor of this MachineInstr.
407  const MCInstrDesc &getDesc() const { return *MCID; }
408 
409  /// Returns the opcode of this MachineInstr.
410  unsigned getOpcode() const { return MCID->Opcode; }
411 
412  /// Retuns the total number of operands.
413  unsigned getNumOperands() const { return NumOperands; }
414 
415  const MachineOperand& getOperand(unsigned i) const {
416  assert(i < getNumOperands() && "getOperand() out of range!");
417  return Operands[i];
418  }
419  MachineOperand& getOperand(unsigned i) {
420  assert(i < getNumOperands() && "getOperand() out of range!");
421  return Operands[i];
422  }
423 
424  /// Returns the total number of definitions.
425  unsigned getNumDefs() const {
426  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
427  }
428 
429  /// Returns true if the instruction has implicit definition.
430  bool hasImplicitDef() const {
431  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
432  I != E; ++I) {
433  const MachineOperand &MO = getOperand(I);
434  if (MO.isDef() && MO.isImplicit())
435  return true;
436  }
437  return false;
438  }
439 
440  /// Returns the implicit operands number.
441  unsigned getNumImplicitOperands() const {
443  }
444 
445  /// Return true if operand \p OpIdx is a subregister index.
446  bool isOperandSubregIdx(unsigned OpIdx) const {
448  "Expected MO_Immediate operand type.");
449  if (isExtractSubreg() && OpIdx == 2)
450  return true;
451  if (isInsertSubreg() && OpIdx == 3)
452  return true;
453  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
454  return true;
455  if (isSubregToReg() && OpIdx == 3)
456  return true;
457  return false;
458  }
459 
460  /// Returns the number of non-implicit operands.
461  unsigned getNumExplicitOperands() const;
462 
463  /// Returns the number of non-implicit definitions.
464  unsigned getNumExplicitDefs() const;
465 
466  /// iterator/begin/end - Iterate over all operands of a machine instruction.
469 
471  mop_iterator operands_end() { return Operands + NumOperands; }
472 
474  const_mop_iterator operands_end() const { return Operands + NumOperands; }
475 
478  }
481  }
483  return make_range(operands_begin(),
485  }
487  return make_range(operands_begin(),
489  }
492  }
495  }
496  /// Returns a range over all explicit operands that are register definitions.
497  /// Implicit definition are not included!
499  return make_range(operands_begin(),
501  }
502  /// \copydoc defs()
504  return make_range(operands_begin(),
506  }
507  /// Returns a range that includes all operands that are register uses.
508  /// This may include unrelated operands which are not register uses.
511  }
512  /// \copydoc uses()
515  }
519  }
523  }
524 
525  /// Returns the number of the operand iterator \p I points to.
527  return I - operands_begin();
528  }
529 
530  /// Access to memory operands of the instruction. If there are none, that does
531  /// not imply anything about whether the function accesses memory. Instead,
532  /// the caller must behave conservatively.
534  if (!Info)
535  return {};
536 
537  if (Info.is<EIIK_MMO>())
538  return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
539 
540  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
541  return EI->getMMOs();
542 
543  return {};
544  }
545 
546  /// Access to memory operands of the instruction.
547  ///
548  /// If `memoperands_begin() == memoperands_end()`, that does not imply
549  /// anything about whether the function accesses memory. Instead, the caller
550  /// must behave conservatively.
551  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
552 
553  /// Access to memory operands of the instruction.
554  ///
555  /// If `memoperands_begin() == memoperands_end()`, that does not imply
556  /// anything about whether the function accesses memory. Instead, the caller
557  /// must behave conservatively.
558  mmo_iterator memoperands_end() const { return memoperands().end(); }
559 
560  /// Return true if we don't have any memory operands which described the
561  /// memory access done by this instruction. If this is true, calling code
562  /// must be conservative.
563  bool memoperands_empty() const { return memoperands().empty(); }
564 
565  /// Return true if this instruction has exactly one MachineMemOperand.
566  bool hasOneMemOperand() const { return memoperands().size() == 1; }
567 
568  /// Return the number of memory operands.
569  unsigned getNumMemOperands() const { return memoperands().size(); }
570 
571  /// Helper to extract a pre-instruction symbol if one has been added.
573  if (!Info)
574  return nullptr;
575  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
576  return S;
577  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
578  return EI->getPreInstrSymbol();
579 
580  return nullptr;
581  }
582 
583  /// Helper to extract a post-instruction symbol if one has been added.
585  if (!Info)
586  return nullptr;
587  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
588  return S;
589  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
590  return EI->getPostInstrSymbol();
591 
592  return nullptr;
593  }
594 
595  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
596  /// queries but they are bundle aware.
597 
598  enum QueryType {
599  IgnoreBundle, // Ignore bundles
600  AnyInBundle, // Return true if any instruction in bundle has property
601  AllInBundle // Return true if all instructions in bundle have property
602  };
603 
604  /// Return true if the instruction (or in the case of a bundle,
605  /// the instructions inside the bundle) has the specified property.
606  /// The first argument is the property being queried.
607  /// The second argument indicates whether the query should look inside
608  /// instruction bundles.
609  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
610  assert(MCFlag < 64 &&
611  "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
612  // Inline the fast path for unbundled or bundle-internal instructions.
613  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
614  return getDesc().getFlags() & (1ULL << MCFlag);
615 
616  // If this is the first instruction in a bundle, take the slow path.
617  return hasPropertyInBundle(1ULL << MCFlag, Type);
618  }
619 
620  /// Return true if this is an instruction that should go through the usual
621  /// legalization steps.
624  }
625 
626  /// Return true if this instruction can have a variable number of operands.
627  /// In this case, the variable operands will be after the normal
628  /// operands but before the implicit definitions and uses (if any are
629  /// present).
632  }
633 
634  /// Set if this instruction has an optional definition, e.g.
635  /// ARM instructions which can set condition code if 's' bit is set.
638  }
639 
640  /// Return true if this is a pseudo instruction that doesn't
641  /// correspond to a real machine instruction.
643  return hasProperty(MCID::Pseudo, Type);
644  }
645 
647  return hasProperty(MCID::Return, Type);
648  }
649 
650  /// Return true if this is an instruction that marks the end of an EH scope,
651  /// i.e., a catchpad or a cleanuppad instruction.
654  }
655 
657  return hasProperty(MCID::Call, Type);
658  }
659 
660  /// Returns true if the specified instruction stops control flow
661  /// from executing the instruction immediately following it. Examples include
662  /// unconditional branches and return instructions.
664  return hasProperty(MCID::Barrier, Type);
665  }
666 
667  /// Returns true if this instruction part of the terminator for a basic block.
668  /// Typically this is things like return and branch instructions.
669  ///
670  /// Various passes use this to insert code into the bottom of a basic block,
671  /// but before control flow occurs.
674  }
675 
676  /// Returns true if this is a conditional, unconditional, or indirect branch.
677  /// Predicates below can be used to discriminate between
678  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
679  /// get more information.
681  return hasProperty(MCID::Branch, Type);
682  }
683 
684  /// Return true if this is an indirect branch, such as a
685  /// branch through a register.
688  }
689 
690  /// Return true if this is a branch which may fall
691  /// through to the next instruction or may transfer control flow to some other
692  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
693  /// information about this branch.
696  }
697 
698  /// Return true if this is a branch which always
699  /// transfers control flow to some other block. The
700  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
701  /// about this branch.
704  }
705 
706  /// Return true if this instruction has a predicate operand that
707  /// controls execution. It may be set to 'always', or may be set to other
708  /// values. There are various methods in TargetInstrInfo that can be used to
709  /// control and modify the predicate in this instruction.
711  // If it's a bundle than all bundled instructions must be predicable for this
712  // to return true.
714  }
715 
716  /// Return true if this instruction is a comparison.
718  return hasProperty(MCID::Compare, Type);
719  }
720 
721  /// Return true if this instruction is a move immediate
722  /// (including conditional moves) instruction.
724  return hasProperty(MCID::MoveImm, Type);
725  }
726 
727  /// Return true if this instruction is a register move.
728  /// (including moving values from subreg to reg)
730  return hasProperty(MCID::MoveReg, Type);
731  }
732 
733  /// Return true if this instruction is a bitcast instruction.
735  return hasProperty(MCID::Bitcast, Type);
736  }
737 
738  /// Return true if this instruction is a select instruction.
740  return hasProperty(MCID::Select, Type);
741  }
742 
743  /// Return true if this instruction cannot be safely duplicated.
744  /// For example, if the instruction has a unique labels attached
745  /// to it, duplicating it would cause multiple definition errors.
748  }
749 
750  /// Return true if this instruction is convergent.
751  /// Convergent instructions can not be made control-dependent on any
752  /// additional values.
754  if (isInlineAsm()) {
755  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
756  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
757  return true;
758  }
760  }
761 
762  /// Returns true if the specified instruction has a delay slot
763  /// which must be filled by the code generator.
766  }
767 
768  /// Return true for instructions that can be folded as
769  /// memory operands in other instructions. The most common use for this
770  /// is instructions that are simple loads from memory that don't modify
771  /// the loaded value in any way, but it can also be used for instructions
772  /// that can be expressed as constant-pool loads, such as V_SETALLONES
773  /// on x86, to allow them to be folded when it is beneficial.
774  /// This should only be set on instructions that return a value in their
775  /// only virtual register definition.
778  }
779 
780  /// Return true if this instruction behaves
781  /// the same way as the generic REG_SEQUENCE instructions.
782  /// E.g., on ARM,
783  /// dX VMOVDRR rY, rZ
784  /// is equivalent to
785  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
786  ///
787  /// Note that for the optimizers to be able to take advantage of
788  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
789  /// override accordingly.
792  }
793 
794  /// Return true if this instruction behaves
795  /// the same way as the generic EXTRACT_SUBREG instructions.
796  /// E.g., on ARM,
797  /// rX, rY VMOVRRD dZ
798  /// is equivalent to two EXTRACT_SUBREG:
799  /// rX = EXTRACT_SUBREG dZ, ssub_0
800  /// rY = EXTRACT_SUBREG dZ, ssub_1
801  ///
802  /// Note that for the optimizers to be able to take advantage of
803  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
804  /// override accordingly.
807  }
808 
809  /// Return true if this instruction behaves
810  /// the same way as the generic INSERT_SUBREG instructions.
811  /// E.g., on ARM,
812  /// dX = VSETLNi32 dY, rZ, Imm
813  /// is equivalent to a INSERT_SUBREG:
814  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
815  ///
816  /// Note that for the optimizers to be able to take advantage of
817  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
818  /// override accordingly.
821  }
822 
823  //===--------------------------------------------------------------------===//
824  // Side Effect Analysis
825  //===--------------------------------------------------------------------===//
826 
827  /// Return true if this instruction could possibly read memory.
828  /// Instructions with this flag set are not necessarily simple load
829  /// instructions, they may load a value and modify it, for example.
831  if (isInlineAsm()) {
832  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
833  if (ExtraInfo & InlineAsm::Extra_MayLoad)
834  return true;
835  }
836  return hasProperty(MCID::MayLoad, Type);
837  }
838 
839  /// Return true if this instruction could possibly modify memory.
840  /// Instructions with this flag set are not necessarily simple store
841  /// instructions, they may store a modified value based on their operands, or
842  /// may not actually modify anything, for example.
844  if (isInlineAsm()) {
845  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
846  if (ExtraInfo & InlineAsm::Extra_MayStore)
847  return true;
848  }
850  }
851 
852  /// Return true if this instruction could possibly read or modify memory.
854  return mayLoad(Type) || mayStore(Type);
855  }
856 
857  /// Return true if this instruction could possibly raise a floating-point
858  /// exception. This is the case if the instruction is a floating-point
859  /// instruction that can in principle raise an exception, as indicated
860  /// by the MCID::MayRaiseFPException property, *and* at the same time,
861  /// the instruction is used in a context where we expect floating-point
862  /// exceptions might be enabled, as indicated by the FPExcept MI flag.
863  bool mayRaiseFPException() const {
865  getFlag(MachineInstr::MIFlag::FPExcept);
866  }
867 
868  //===--------------------------------------------------------------------===//
869  // Flags that indicate whether an instruction can be modified by a method.
870  //===--------------------------------------------------------------------===//
871 
872  /// Return true if this may be a 2- or 3-address
873  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
874  /// result if Y and Z are exchanged. If this flag is set, then the
875  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
876  /// instruction.
877  ///
878  /// Note that this flag may be set on instructions that are only commutable
879  /// sometimes. In these cases, the call to commuteInstruction will fail.
880  /// Also note that some instructions require non-trivial modification to
881  /// commute them.
884  }
885 
886  /// Return true if this is a 2-address instruction
887  /// which can be changed into a 3-address instruction if needed. Doing this
888  /// transformation can be profitable in the register allocator, because it
889  /// means that the instruction can use a 2-address form if possible, but
890  /// degrade into a less efficient form if the source and dest register cannot
891  /// be assigned to the same register. For example, this allows the x86
892  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
893  /// is the same speed as the shift but has bigger code size.
894  ///
895  /// If this returns true, then the target must implement the
896  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
897  /// is allowed to fail if the transformation isn't valid for this specific
898  /// instruction (e.g. shl reg, 4 on x86).
899  ///
902  }
903 
904  /// Return true if this instruction requires
905  /// custom insertion support when the DAG scheduler is inserting it into a
906  /// machine basic block. If this is true for the instruction, it basically
907  /// means that it is a pseudo instruction used at SelectionDAG time that is
908  /// expanded out into magic code by the target when MachineInstrs are formed.
909  ///
910  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
911  /// is used to insert this into the MachineBasicBlock.
914  }
915 
916  /// Return true if this instruction requires *adjustment*
917  /// after instruction selection by calling a target hook. For example, this
918  /// can be used to fill in ARM 's' optional operand depending on whether
919  /// the conditional flag register is used.
922  }
923 
924  /// Returns true if this instruction is a candidate for remat.
925  /// This flag is deprecated, please don't use it anymore. If this
926  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
927  /// verify the instruction is really rematable.
929  // It's only possible to re-mat a bundle if all bundled instructions are
930  // re-materializable.
932  }
933 
934  /// Returns true if this instruction has the same cost (or less) than a move
935  /// instruction. This is useful during certain types of optimizations
936  /// (e.g., remat during two-address conversion or machine licm)
937  /// where we would like to remat or hoist the instruction, but not if it costs
938  /// more than moving the instruction into the appropriate register. Note, we
939  /// are not marking copies from and to the same register class with this flag.
941  // Only returns true for a bundle if all bundled instructions are cheap.
943  }
944 
945  /// Returns true if this instruction source operands
946  /// have special register allocation requirements that are not captured by the
947  /// operand register classes. e.g. ARM::STRD's two source registers must be an
948  /// even / odd pair, ARM::STM registers have to be in ascending order.
949  /// Post-register allocation passes should not attempt to change allocations
950  /// for sources of instructions with this flag.
953  }
954 
955  /// Returns true if this instruction def operands
956  /// have special register allocation requirements that are not captured by the
957  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
958  /// even / odd pair, ARM::LDM registers have to be in ascending order.
959  /// Post-register allocation passes should not attempt to change allocations
960  /// for definitions of instructions with this flag.
963  }
964 
965  enum MICheckType {
966  CheckDefs, // Check all operands for equality
967  CheckKillDead, // Check all operands including kill / dead markers
968  IgnoreDefs, // Ignore all definitions
969  IgnoreVRegDefs // Ignore virtual register definitions
970  };
971 
972  /// Return true if this instruction is identical to \p Other.
973  /// Two instructions are identical if they have the same opcode and all their
974  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
975  /// Note that this means liveness related flags (dead, undef, kill) do not
976  /// affect the notion of identical.
977  bool isIdenticalTo(const MachineInstr &Other,
978  MICheckType Check = CheckDefs) const;
979 
980  /// Unlink 'this' from the containing basic block, and return it without
981  /// deleting it.
982  ///
983  /// This function can not be used on bundled instructions, use
984  /// removeFromBundle() to remove individual instructions from a bundle.
986 
987  /// Unlink this instruction from its basic block and return it without
988  /// deleting it.
989  ///
990  /// If the instruction is part of a bundle, the other instructions in the
991  /// bundle remain bundled.
993 
994  /// Unlink 'this' from the containing basic block and delete it.
995  ///
996  /// If this instruction is the header of a bundle, the whole bundle is erased.
997  /// This function can not be used for instructions inside a bundle, use
998  /// eraseFromBundle() to erase individual bundled instructions.
999  void eraseFromParent();
1000 
1001  /// Unlink 'this' from the containing basic block and delete it.
1002  ///
1003  /// For all definitions mark their uses in DBG_VALUE nodes
1004  /// as undefined. Otherwise like eraseFromParent().
1006 
1007  /// Unlink 'this' form its basic block and delete it.
1008  ///
1009  /// If the instruction is part of a bundle, the other instructions in the
1010  /// bundle remain bundled.
1011  void eraseFromBundle();
1012 
1013  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1014  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1015  bool isAnnotationLabel() const {
1017  }
1018 
1019  /// Returns true if the MachineInstr represents a label.
1020  bool isLabel() const {
1021  return isEHLabel() || isGCLabel() || isAnnotationLabel();
1022  }
1023 
1024  bool isCFIInstruction() const {
1025  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1026  }
1027 
1028  // True if the instruction represents a position in the function.
1029  bool isPosition() const { return isLabel() || isCFIInstruction(); }
1030 
1031  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1032  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1033  bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
1034 
1035  /// A DBG_VALUE is indirect iff the first operand is a register and
1036  /// the second operand is an immediate.
1037  bool isIndirectDebugValue() const {
1038  return isDebugValue()
1039  && getOperand(0).isReg()
1040  && getOperand(1).isImm();
1041  }
1042 
1043  /// A DBG_VALUE is an entry value iff its debug expression contains the
1044  /// DW_OP_LLVM_entry_value operation.
1045  bool isDebugEntryValue() const;
1046 
1047  /// Return true if the instruction is a debug value which describes a part of
1048  /// a variable as unavailable.
1049  bool isUndefDebugValue() const {
1050  return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1051  }
1052 
1053  bool isPHI() const {
1054  return getOpcode() == TargetOpcode::PHI ||
1055  getOpcode() == TargetOpcode::G_PHI;
1056  }
1057  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1058  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1059  bool isInlineAsm() const {
1060  return getOpcode() == TargetOpcode::INLINEASM ||
1062  }
1063 
1064  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1065  /// specific, be attached to a generic MachineInstr.
1066  bool isMSInlineAsm() const {
1068  }
1069 
1070  bool isStackAligningInlineAsm() const;
1072 
1073  bool isInsertSubreg() const {
1074  return getOpcode() == TargetOpcode::INSERT_SUBREG;
1075  }
1076 
1077  bool isSubregToReg() const {
1078  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1079  }
1080 
1081  bool isRegSequence() const {
1082  return getOpcode() == TargetOpcode::REG_SEQUENCE;
1083  }
1084 
1085  bool isBundle() const {
1086  return getOpcode() == TargetOpcode::BUNDLE;
1087  }
1088 
1089  bool isCopy() const {
1090  return getOpcode() == TargetOpcode::COPY;
1091  }
1092 
1093  bool isFullCopy() const {
1094  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1095  }
1096 
1097  bool isExtractSubreg() const {
1098  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1099  }
1100 
1101  /// Return true if the instruction behaves like a copy.
1102  /// This does not include native copy instructions.
1103  bool isCopyLike() const {
1104  return isCopy() || isSubregToReg();
1105  }
1106 
1107  /// Return true is the instruction is an identity copy.
1108  bool isIdentityCopy() const {
1109  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1111  }
1112 
1113  /// Return true if this instruction doesn't produce any output in the form of
1114  /// executable instructions.
1115  bool isMetaInstruction() const {
1116  switch (getOpcode()) {
1117  default:
1118  return false;
1119  case TargetOpcode::IMPLICIT_DEF:
1120  case TargetOpcode::KILL:
1121  case TargetOpcode::CFI_INSTRUCTION:
1123  case TargetOpcode::GC_LABEL:
1124  case TargetOpcode::DBG_VALUE:
1125  case TargetOpcode::DBG_LABEL:
1128  return true;
1129  }
1130  }
1131 
1132  /// Return true if this is a transient instruction that is either very likely
1133  /// to be eliminated during register allocation (such as copy-like
1134  /// instructions), or if this instruction doesn't have an execution-time cost.
1135  bool isTransient() const {
1136  switch (getOpcode()) {
1137  default:
1138  return isMetaInstruction();
1139  // Copy-like instructions are usually eliminated during register allocation.
1140  case TargetOpcode::PHI:
1141  case TargetOpcode::G_PHI:
1142  case TargetOpcode::COPY:
1143  case TargetOpcode::INSERT_SUBREG:
1144  case TargetOpcode::SUBREG_TO_REG:
1145  case TargetOpcode::REG_SEQUENCE:
1146  return true;
1147  }
1148  }
1149 
1150  /// Return the number of instructions inside the MI bundle, excluding the
1151  /// bundle header.
1152  ///
1153  /// This is the number of instructions that MachineBasicBlock::iterator
1154  /// skips, 0 for unbundled instructions.
1155  unsigned getBundleSize() const;
1156 
1157  /// Return true if the MachineInstr reads the specified register.
1158  /// If TargetRegisterInfo is passed, then it also checks if there
1159  /// is a read of a super-register.
1160  /// This does not count partial redefines of virtual registers as reads:
1161  /// %reg1024:6 = OP.
1163  const TargetRegisterInfo *TRI = nullptr) const {
1164  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1165  }
1166 
1167  /// Return true if the MachineInstr reads the specified virtual register.
1168  /// Take into account that a partial define is a
1169  /// read-modify-write operation.
1171  return readsWritesVirtualRegister(Reg).first;
1172  }
1173 
1174  /// Return a pair of bools (reads, writes) indicating if this instruction
1175  /// reads or writes Reg. This also considers partial defines.
1176  /// If Ops is not null, all operand indices for Reg are added.
1177  std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1178  SmallVectorImpl<unsigned> *Ops = nullptr) const;
1179 
1180  /// Return true if the MachineInstr kills the specified register.
1181  /// If TargetRegisterInfo is passed, then it also checks if there is
1182  /// a kill of a super-register.
1184  const TargetRegisterInfo *TRI = nullptr) const {
1185  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1186  }
1187 
1188  /// Return true if the MachineInstr fully defines the specified register.
1189  /// If TargetRegisterInfo is passed, then it also checks
1190  /// if there is a def of a super-register.
1191  /// NOTE: It's ignoring subreg indices on virtual registers.
1193  const TargetRegisterInfo *TRI = nullptr) const {
1194  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1195  }
1196 
1197  /// Return true if the MachineInstr modifies (fully define or partially
1198  /// define) the specified register.
1199  /// NOTE: It's ignoring subreg indices on virtual registers.
1201  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1202  }
1203 
1204  /// Returns true if the register is dead in this machine instruction.
1205  /// If TargetRegisterInfo is passed, then it also checks
1206  /// if there is a dead def of a super-register.
1208  const TargetRegisterInfo *TRI = nullptr) const {
1209  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1210  }
1211 
1212  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1213  /// the given register (not considering sub/super-registers).
1214  bool hasRegisterImplicitUseOperand(Register Reg) const;
1215 
1216  /// Returns the operand index that is a use of the specific register or -1
1217  /// if it is not found. It further tightens the search criteria to a use
1218  /// that kills the register if isKill is true.
1219  int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1220  const TargetRegisterInfo *TRI = nullptr) const;
1221 
1222  /// Wrapper for findRegisterUseOperandIdx, it returns
1223  /// a pointer to the MachineOperand rather than an index.
1225  const TargetRegisterInfo *TRI = nullptr) {
1226  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1227  return (Idx == -1) ? nullptr : &getOperand(Idx);
1228  }
1229 
1231  Register Reg, bool isKill = false,
1232  const TargetRegisterInfo *TRI = nullptr) const {
1233  return const_cast<MachineInstr *>(this)->
1235  }
1236 
1237  /// Returns the operand index that is a def of the specified register or
1238  /// -1 if it is not found. If isDead is true, defs that are not dead are
1239  /// skipped. If Overlap is true, then it also looks for defs that merely
1240  /// overlap the specified register. If TargetRegisterInfo is non-null,
1241  /// then it also checks if there is a def of a super-register.
1242  /// This may also return a register mask operand when Overlap is true.
1244  bool isDead = false, bool Overlap = false,
1245  const TargetRegisterInfo *TRI = nullptr) const;
1246 
1247  /// Wrapper for findRegisterDefOperandIdx, it returns
1248  /// a pointer to the MachineOperand rather than an index.
1249  MachineOperand *
1250  findRegisterDefOperand(Register Reg, bool isDead = false,
1251  bool Overlap = false,
1252  const TargetRegisterInfo *TRI = nullptr) {
1253  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1254  return (Idx == -1) ? nullptr : &getOperand(Idx);
1255  }
1256 
1257  const MachineOperand *
1258  findRegisterDefOperand(Register Reg, bool isDead = false,
1259  bool Overlap = false,
1260  const TargetRegisterInfo *TRI = nullptr) const {
1261  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1262  Reg, isDead, Overlap, TRI);
1263  }
1264 
1265  /// Find the index of the first operand in the
1266  /// operand list that is used to represent the predicate. It returns -1 if
1267  /// none is found.
1268  int findFirstPredOperandIdx() const;
1269 
1270  /// Find the index of the flag word operand that
1271  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1272  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1273  ///
1274  /// If GroupNo is not NULL, it will receive the number of the operand group
1275  /// containing OpIdx.
1276  ///
1277  /// The flag operand is an immediate that can be decoded with methods like
1278  /// InlineAsm::hasRegClassConstraint().
1279  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1280 
1281  /// Compute the static register class constraint for operand OpIdx.
1282  /// For normal instructions, this is derived from the MCInstrDesc.
1283  /// For inline assembly it is derived from the flag words.
1284  ///
1285  /// Returns NULL if the static register class constraint cannot be
1286  /// determined.
1287  const TargetRegisterClass*
1288  getRegClassConstraint(unsigned OpIdx,
1289  const TargetInstrInfo *TII,
1290  const TargetRegisterInfo *TRI) const;
1291 
1292  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1293  /// the given \p CurRC.
1294  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1295  /// instructions inside the bundle will be taken into account. In other words,
1296  /// this method accumulates all the constraints of the operand of this MI and
1297  /// the related bundle if MI is a bundle or inside a bundle.
1298  ///
1299  /// Returns the register class that satisfies both \p CurRC and the
1300  /// constraints set by MI. Returns NULL if such a register class does not
1301  /// exist.
1302  ///
1303  /// \pre CurRC must not be NULL.
1305  Register Reg, const TargetRegisterClass *CurRC,
1306  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1307  bool ExploreBundle = false) const;
1308 
1309  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1310  /// to the given \p CurRC.
1311  ///
1312  /// Returns the register class that satisfies both \p CurRC and the
1313  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1314  /// does not exist.
1315  ///
1316  /// \pre CurRC must not be NULL.
1317  /// \pre The operand at \p OpIdx must be a register.
1318  const TargetRegisterClass *
1319  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1320  const TargetInstrInfo *TII,
1321  const TargetRegisterInfo *TRI) const;
1322 
1323  /// Add a tie between the register operands at DefIdx and UseIdx.
1324  /// The tie will cause the register allocator to ensure that the two
1325  /// operands are assigned the same physical register.
1326  ///
1327  /// Tied operands are managed automatically for explicit operands in the
1328  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1329  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1330 
1331  /// Given the index of a tied register operand, find the
1332  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1333  /// index of the tied operand which must exist.
1334  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1335 
1336  /// Given the index of a register def operand,
1337  /// check if the register def is tied to a source operand, due to either
1338  /// two-address elimination or inline assembly constraints. Returns the
1339  /// first tied use operand index by reference if UseOpIdx is not null.
1340  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1341  unsigned *UseOpIdx = nullptr) const {
1342  const MachineOperand &MO = getOperand(DefOpIdx);
1343  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1344  return false;
1345  if (UseOpIdx)
1346  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1347  return true;
1348  }
1349 
1350  /// Return true if the use operand of the specified index is tied to a def
1351  /// operand. It also returns the def operand index by reference if DefOpIdx
1352  /// is not null.
1353  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1354  unsigned *DefOpIdx = nullptr) const {
1355  const MachineOperand &MO = getOperand(UseOpIdx);
1356  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1357  return false;
1358  if (DefOpIdx)
1359  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1360  return true;
1361  }
1362 
1363  /// Clears kill flags on all operands.
1364  void clearKillInfo();
1365 
1366  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1367  /// properly composing subreg indices where necessary.
1368  void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1369  const TargetRegisterInfo &RegInfo);
1370 
1371  /// We have determined MI kills a register. Look for the
1372  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1373  /// add a implicit operand if it's not found. Returns true if the operand
1374  /// exists / is added.
1375  bool addRegisterKilled(Register IncomingReg,
1376  const TargetRegisterInfo *RegInfo,
1377  bool AddIfNotFound = false);
1378 
1379  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1380  /// all aliasing registers.
1381  void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1382 
1383  /// We have determined MI defined a register without a use.
1384  /// Look for the operand that defines it and mark it as IsDead. If
1385  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1386  /// true if the operand exists / is added.
1387  bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1388  bool AddIfNotFound = false);
1389 
1390  /// Clear all dead flags on operands defining register @p Reg.
1391  void clearRegisterDeads(Register Reg);
1392 
1393  /// Mark all subregister defs of register @p Reg with the undef flag.
1394  /// This function is used when we determined to have a subregister def in an
1395  /// otherwise undefined super register.
1396  void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1397 
1398  /// We have determined MI defines a register. Make sure there is an operand
1399  /// defining Reg.
1400  void addRegisterDefined(Register Reg,
1401  const TargetRegisterInfo *RegInfo = nullptr);
1402 
1403  /// Mark every physreg used by this instruction as
1404  /// dead except those in the UsedRegs list.
1405  ///
1406  /// On instructions with register mask operands, also add implicit-def
1407  /// operands for all registers in UsedRegs.
1409  const TargetRegisterInfo &TRI);
1410 
1411  /// Return true if it is safe to move this instruction. If
1412  /// SawStore is set to true, it means that there is a store (or call) between
1413  /// the instruction's location and its intended destination.
1414  bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1415 
1416  /// Returns true if this instruction's memory access aliases the memory
1417  /// access of Other.
1418  //
1419  /// Assumes any physical registers used to compute addresses
1420  /// have the same value for both instructions. Returns false if neither
1421  /// instruction writes to memory.
1422  ///
1423  /// @param AA Optional alias analysis, used to compare memory operands.
1424  /// @param Other MachineInstr to check aliasing against.
1425  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1426  bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1427 
1428  /// Return true if this instruction may have an ordered
1429  /// or volatile memory reference, or if the information describing the memory
1430  /// reference is not available. Return false if it is known to have no
1431  /// ordered or volatile memory references.
1432  bool hasOrderedMemoryRef() const;
1433 
1434  /// Return true if this load instruction never traps and points to a memory
1435  /// location whose value doesn't change during the execution of this function.
1436  ///
1437  /// Examples include loading a value from the constant pool or from the
1438  /// argument area of a function (if it does not change). If the instruction
1439  /// does multiple loads, this returns true only if all of the loads are
1440  /// dereferenceable and invariant.
1441  bool isDereferenceableInvariantLoad(AAResults *AA) const;
1442 
1443  /// If the specified instruction is a PHI that always merges together the
1444  /// same virtual register, return the register, otherwise return 0.
1445  unsigned isConstantValuePHI() const;
1446 
1447  /// Return true if this instruction has side effects that are not modeled
1448  /// by mayLoad / mayStore, etc.
1449  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1450  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1451  /// INLINEASM instruction, in which case the side effect property is encoded
1452  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1453  ///
1454  bool hasUnmodeledSideEffects() const;
1455 
1456  /// Returns true if it is illegal to fold a load across this instruction.
1457  bool isLoadFoldBarrier() const;
1458 
1459  /// Return true if all the defs of this instruction are dead.
1460  bool allDefsAreDead() const;
1461 
1462  /// Return a valid size if the instruction is a spill instruction.
1464 
1465  /// Return a valid size if the instruction is a folded spill instruction.
1467 
1468  /// Return a valid size if the instruction is a restore instruction.
1470 
1471  /// Return a valid size if the instruction is a folded restore instruction.
1473  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1474 
1475  /// Copy implicit register operands from specified
1476  /// instruction to this instruction.
1477  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1478 
1479  /// Debugging support
1480  /// @{
1481  /// Determine the generic type to be printed (if needed) on uses and defs.
1482  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1483  const MachineRegisterInfo &MRI) const;
1484 
1485  /// Return true when an instruction has tied register that can't be determined
1486  /// by the instruction's descriptor. This is useful for MIR printing, to
1487  /// determine whether we need to print the ties or not.
1488  bool hasComplexRegisterTies() const;
1489 
1490  /// Print this MI to \p OS.
1491  /// Don't print information that can be inferred from other instructions if
1492  /// \p IsStandalone is false. It is usually true when only a fragment of the
1493  /// function is printed.
1494  /// Only print the defs and the opcode if \p SkipOpers is true.
1495  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1496  /// Otherwise, also print the debug loc, with a terminating newline.
1497  /// \p TII is used to print the opcode name. If it's not present, but the
1498  /// MI is in a function, the opcode will be printed using the function's TII.
1499  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1500  bool SkipDebugLoc = false, bool AddNewLine = true,
1501  const TargetInstrInfo *TII = nullptr) const;
1502  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1503  bool SkipOpers = false, bool SkipDebugLoc = false,
1504  bool AddNewLine = true,
1505  const TargetInstrInfo *TII = nullptr) const;
1506  void dump() const;
1507  /// @}
1508 
1509  //===--------------------------------------------------------------------===//
1510  // Accessors used to build up machine instructions.
1511 
1512  /// Add the specified operand to the instruction. If it is an implicit
1513  /// operand, it is added to the end of the operand list. If it is an
1514  /// explicit operand it is added at the end of the explicit operand list
1515  /// (before the first implicit operand).
1516  ///
1517  /// MF must be the machine function that was used to allocate this
1518  /// instruction.
1519  ///
1520  /// MachineInstrBuilder provides a more convenient interface for creating
1521  /// instructions and adding operands.
1522  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1523 
1524  /// Add an operand without providing an MF reference. This only works for
1525  /// instructions that are inserted in a basic block.
1526  ///
1527  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1528  /// preferred.
1529  void addOperand(const MachineOperand &Op);
1530 
1531  /// Replace the instruction descriptor (thus opcode) of
1532  /// the current instruction with a new one.
1533  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1534 
1535  /// Replace current source information with new such.
1536  /// Avoid using this, the constructor argument is preferable.
1538  debugLoc = std::move(dl);
1539  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1540  }
1541 
1542  /// Erase an operand from an instruction, leaving it with one
1543  /// fewer operand than it started with.
1544  void RemoveOperand(unsigned OpNo);
1545 
1546  /// Clear this MachineInstr's memory reference descriptor list. This resets
1547  /// the memrefs to their most conservative state. This should be used only
1548  /// as a last resort since it greatly pessimizes our knowledge of the memory
1549  /// access performed by the instruction.
1550  void dropMemRefs(MachineFunction &MF);
1551 
1552  /// Assign this MachineInstr's memory reference descriptor list.
1553  ///
1554  /// Unlike other methods, this *will* allocate them into a new array
1555  /// associated with the provided `MachineFunction`.
1557 
1558  /// Add a MachineMemOperand to the machine instruction.
1559  /// This function should be used only occasionally. The setMemRefs function
1560  /// is the primary method for setting up a MachineInstr's MemRefs list.
1562 
1563  /// Clone another MachineInstr's memory reference descriptor list and replace
1564  /// ours with it.
1565  ///
1566  /// Note that `*this` may be the incoming MI!
1567  ///
1568  /// Prefer this API whenever possible as it can avoid allocations in common
1569  /// cases.
1570  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1571 
1572  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1573  /// list and replace ours with it.
1574  ///
1575  /// Note that `*this` may be one of the incoming MIs!
1576  ///
1577  /// Prefer this API whenever possible as it can avoid allocations in common
1578  /// cases.
1581 
1582  /// Set a symbol that will be emitted just prior to the instruction itself.
1583  ///
1584  /// Setting this to a null pointer will remove any such symbol.
1585  ///
1586  /// FIXME: This is not fully implemented yet.
1588 
1589  /// Set a symbol that will be emitted just after the instruction itself.
1590  ///
1591  /// Setting this to a null pointer will remove any such symbol.
1592  ///
1593  /// FIXME: This is not fully implemented yet.
1594  void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1595 
1596  /// Clone another MachineInstr's pre- and post- instruction symbols and
1597  /// replace ours with it.
1598  void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1599 
1600  /// Return the MIFlags which represent both MachineInstrs. This
1601  /// should be used when merging two MachineInstrs into one. This routine does
1602  /// not modify the MIFlags of this MachineInstr.
1603  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1604 
1605  static uint16_t copyFlagsFromInstruction(const Instruction &I);
1606 
1607  /// Copy all flags to MachineInst MIFlags
1608  void copyIRFlags(const Instruction &I);
1609 
1610  /// Break any tie involving OpIdx.
1611  void untieRegOperand(unsigned OpIdx) {
1612  MachineOperand &MO = getOperand(OpIdx);
1613  if (MO.isReg() && MO.isTied()) {
1614  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1615  MO.TiedTo = 0;
1616  }
1617  }
1618 
1619  /// Add all implicit def and use operands to this instruction.
1621 
1622  /// Scan instructions following MI and collect any matching DBG_VALUEs.
1624 
1625  /// Find all DBG_VALUEs that point to the register def in this instruction
1626  /// and point them to \p Reg instead.
1628 
1629  /// Returns the Intrinsic::ID for this instruction.
1630  /// \pre Must have an intrinsic ID operand.
1631  unsigned getIntrinsicID() const {
1633  }
1634 
1635 private:
1636  /// If this instruction is embedded into a MachineFunction, return the
1637  /// MachineRegisterInfo object for the current function, otherwise
1638  /// return null.
1639  MachineRegisterInfo *getRegInfo();
1640 
1641  /// Unlink all of the register operands in this instruction from their
1642  /// respective use lists. This requires that the operands already be on their
1643  /// use lists.
1644  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1645 
1646  /// Add all of the register operands in this instruction from their
1647  /// respective use lists. This requires that the operands not be on their
1648  /// use lists yet.
1649  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1650 
1651  /// Slow path for hasProperty when we're dealing with a bundle.
1652  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1653 
1654  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1655  /// this MI and the given operand index \p OpIdx.
1656  /// If the related operand does not constrained Reg, this returns CurRC.
1657  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1658  unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1659  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1660 };
1661 
1662 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1663 /// instruction rather than by pointer value.
1664 /// The hashing and equality testing functions ignore definitions so this is
1665 /// useful for CSE, etc.
1667  static inline MachineInstr *getEmptyKey() {
1668  return nullptr;
1669  }
1670 
1671  static inline MachineInstr *getTombstoneKey() {
1672  return reinterpret_cast<MachineInstr*>(-1);
1673  }
1674 
1675  static unsigned getHashValue(const MachineInstr* const &MI);
1676 
1677  static bool isEqual(const MachineInstr* const &LHS,
1678  const MachineInstr* const &RHS) {
1679  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1680  LHS == getEmptyKey() || LHS == getTombstoneKey())
1681  return LHS == RHS;
1682  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1683  }
1684 };
1685 
1686 //===----------------------------------------------------------------------===//
1687 // Debugging Support
1688 
1690  MI.print(OS);
1691  return OS;
1692 }
1693 
1694 } // end namespace llvm
1695 
1696 #endif // LLVM_CODEGEN_MACHINEINSTR_H
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:717
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead...
static bool Check(DecodeStatus &Out, DecodeStatus In)
void bundleWithPred()
Bundle this instruction with its predecessor.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs...
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
mop_iterator operands_end()
Definition: MachineInstr.h:471
bool isDebugLabel() const
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:920
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:474
bool isLabel() const
Returns true if the MachineInstr represents a label.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:656
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:573
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:509
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
A compile time pair of an integer tag and the pointer-like type which it indexes within a sum type...
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:482
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:961
iterator begin() const
Definition: ArrayRef.h:136
bool isCFIInstruction() const
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:363
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:805
bool isSubregToReg() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:526
unsigned Reg
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:764
unsigned getSubReg() const
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isInlineAsm() const
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:953
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:710
bool isAnnotationLabel() const
MachineInstr & operator=(const MachineInstr &)=delete
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
bool isRegSequence() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:853
Template traits for intrusive list.
Definition: ilist.h:89
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:286
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:28
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction&#39;s memory access aliases the memory access of Other.
Manage lifetime of a slot tracker for printing IR.
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:419
bool isMetaInstruction() const
Return true if this instruction doesn&#39;t produce any output in the form of executable instructions...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:476
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:723
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:734
void clearKillInfo()
Clears kill flags on all operands.
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:367
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:503
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:672
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
void bundleWithSucc()
Bundle this instruction with its successor.
mir Rename Register Operands
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:703
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
Optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:473
void unbundleFromPred()
Break bundle above this instruction.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:686
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:652
bool isFullCopy() const
bool isBundle() const
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
Definition: MachineInstr.h:863
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
static MachineInstr * getEmptyKey()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isMSInlineAsm() const
FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific, be attached to a generic MachineInstr.
MachineBasicBlock * getParent()
Definition: MachineInstr.h:256
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:351
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:680
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:572
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr&#39;s memory reference descriptor list.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
TargetInstrInfo - Interface to description of machine instruction set.
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:885
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:646
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:513
Optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
static MachineInstr * getTombstoneKey()
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:843
#define P(N)
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:900
An ilist node that can access its parent list.
Definition: ilist_node.h:256
unsigned const MachineRegisterInfo * MRI
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s pre- and post- instruction symbols and replace ours with it...
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps...
Definition: MachineInstr.h:622
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:276
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:533
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:717
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:141
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:642
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:357
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:446
~MachineInstr()=delete
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:301
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:312
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:739
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:566
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:520
See the file comment for details on the usage of the TrailingObjects type.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:498
bool isEHLabel() const
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can&#39;t be determined by the instruction&#39;s descr...
const MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:928
bool isStackAligningInlineAsm() const
bool isCopy() const
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:819
bool isImplicitDef() const
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:753
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static wasm::ValType getType(const TargetRegisterClass *RC)
Optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
bool isDebugInstr() const
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:584
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:711
void eraseFromBundle()
Unlink &#39;this&#39; form its basic block and delete it.
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:516
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
Basic Register Allocator
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:694
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr&#39;s memory reference descriptor list and replace ours with it...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
InlineAsm::AsmDialect getInlineAsmDialect() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:551
void setFlags(unsigned flags)
Definition: MachineInstr.h:305
bool isDereferenceableInvariantLoad(AAResults *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Intrinsic::ID getIntrinsicID() const
iterator end() const
Definition: ArrayRef.h:137
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:630
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:486
int64_t getImm() const
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:181
A range adaptor for a pair of iterators.
LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
Definition: Allocator.h:215
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:609
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:490
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:702
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:598
A sum type over pointer-like types.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isValid() const
Definition: Register.h:115
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:790
Representation of each machine instruction.
Definition: MachineInstr.h:63
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
Definition: MachineInstr.h:729
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
const MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:776
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
Clone the merge of multiple MachineInstrs&#39; memory reference descriptors list and replace ours with it...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable...
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:479
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:951
bool isGCLabel() const
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:425
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isKill() const
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2047
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation...
MachineInstr * removeFromParent()
Unlink &#39;this&#39; from the containing basic block, and return it without deleting it. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:636
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:291
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:830
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:563
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:912
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr&#39;s memory reference descriptor list.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:273
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:706
void unbundleFromSucc()
Break bundle below this instruction.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:441
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
mop_iterator operands_begin()
Definition: MachineInstr.h:470
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
bool isPosition() const
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
This header defines support for implementing classes that have some trailing object (or arrays of obj...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:64
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:493
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
MachineFunction * getMF()
Definition: MachineInstr.h:264
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:663
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:281
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:73
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:430
Register getReg() const
getReg - Returns the register number.
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:569
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:244
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1217
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
bool isExtractSubreg() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:296
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:940
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:882
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:270
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:746
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:558
bool isImplicit() const
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.