LLVM 24.0.0git
AVRRegisterInfo.h
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1//===-- AVRRegisterInfo.h - AVR Register Information Impl -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_REGISTER_INFO_H
14#define LLVM_AVR_REGISTER_INFO_H
15
17
18#define GET_REGINFO_HEADER
19#include "AVRGenRegisterInfo.inc"
20
21namespace llvm {
22
23/// Utilities relating to AVR registers.
25public:
27
28public:
29 const uint16_t *
30 getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
32 CallingConv::ID CC) const override;
33 BitVector getReservedRegs(const MachineFunction &MF) const override;
34
37 const MachineFunction &MF) const override;
38
39 /// Stack Frame Processing Methods
41 unsigned FIOperandNum,
42 RegScavenger *RS = nullptr) const override;
43
44 Register getFrameRegister(const MachineFunction &MF) const override;
45
46 /// Splits a 16-bit `DREGS` register into the lo/hi register pair.
47 /// \param Reg A 16-bit register to split.
48 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
49
51 unsigned SubReg, const TargetRegisterClass *DstRC,
52 unsigned DstSubReg, const TargetRegisterClass *NewRC,
53 LiveIntervals &LIS) const override;
54};
55
56} // end namespace llvm
57
58#endif // LLVM_AVR_REGISTER_INFO_H
IRTranslator LLVM IR MI
Register Reg
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Register getFrameRegister(const MachineFunction &MF) const override
void splitReg(Register Reg, Register &LoReg, Register &HiReg) const
Splits a 16-bit DREGS register into the lo/hi register pair.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
Definition Register.h:20
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58