LoongArchRegisterInfo.cpp

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//===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the LoongArch implementation of the TargetRegisterInfo
// class.
//
//===----------------------------------------------------------------------===//
 
#include "LoongArchRegisterInfo.h"
#include "LoongArch.h"
#include "LoongArchInstrInfo.h"
#include "LoongArchSubtarget.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/ErrorHandling.h"
 
using namespace llvm;
 
#define GET_REGINFO_TARGET_DESC
#include "LoongArchGenRegisterInfo.inc"
 
LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
    : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
                               /*EHFlavor*/ 0,
                               /*PC*/ 0, HwMode) {}
 
const MCPhysReg *
LoongArchRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  auto &Subtarget = MF->getSubtarget<LoongArchSubtarget>();
  auto CC = MF->getFunction().getCallingConv();
 
  if (CC == CallingConv::GHC)
    return CSR_NoRegs_SaveList;
  if (CC == CallingConv::PreserveNone)
    return CSR_NoneRegs_SaveList;
  if (CC == CallingConv::PreserveMost)
    return CSR_MostRegs_SaveList;
  switch (Subtarget.getTargetABI()) {
  default:
    llvm_unreachable("Unrecognized ABI");
  case LoongArchABI::ABI_ILP32S:
  case LoongArchABI::ABI_LP64S:
    return CSR_ILP32S_LP64S_SaveList;
  case LoongArchABI::ABI_ILP32F:
  case LoongArchABI::ABI_LP64F:
    return CSR_ILP32F_LP64F_SaveList;
  case LoongArchABI::ABI_ILP32D:
  case LoongArchABI::ABI_LP64D:
    return CSR_ILP32D_LP64D_SaveList;
  }
}
 
const uint32_t *
LoongArchRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                            CallingConv::ID CC) const {
  auto &Subtarget = MF.getSubtarget<LoongArchSubtarget>();
 
  if (CC == CallingConv::GHC)
    return CSR_NoRegs_RegMask;
  if (CC == CallingConv::PreserveNone)
    return CSR_NoneRegs_RegMask;
  if (CC == CallingConv::PreserveMost)
    return CSR_MostRegs_RegMask;
  switch (Subtarget.getTargetABI()) {
  default:
    llvm_unreachable("Unrecognized ABI");
  case LoongArchABI::ABI_ILP32S:
  case LoongArchABI::ABI_LP64S:
    return CSR_ILP32S_LP64S_RegMask;
  case LoongArchABI::ABI_ILP32F:
  case LoongArchABI::ABI_LP64F:
    return CSR_ILP32F_LP64F_RegMask;
  case LoongArchABI::ABI_ILP32D:
  case LoongArchABI::ABI_LP64D:
    return CSR_ILP32D_LP64D_RegMask;
  }
}
 
const uint32_t *LoongArchRegisterInfo::getNoPreservedMask() const {
  return CSR_NoRegs_RegMask;
}
 
BitVector
LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  const LoongArchFrameLowering *TFI = getFrameLowering(MF);
  BitVector Reserved(getNumRegs());
 
  // Use markSuperRegs to ensure any register aliases are also reserved
  markSuperRegs(Reserved, LoongArch::R0);  // zero
  markSuperRegs(Reserved, LoongArch::R2);  // tp
  markSuperRegs(Reserved, LoongArch::R3);  // sp
  markSuperRegs(Reserved, LoongArch::R21); // non-allocatable
  if (TFI->hasFP(MF))
    markSuperRegs(Reserved, LoongArch::R22); // fp
  // Reserve the base register if we need to realign the stack and allocate
  // variable-sized objects at runtime.
  if (TFI->hasBP(MF))
    markSuperRegs(Reserved, LoongArchABI::getBPReg()); // bp
 
  assert(checkAllSuperRegsMarked(Reserved));
  return Reserved;
}
 
Register
LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
  const TargetFrameLowering *TFI = getFrameLowering(MF);
  return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
}
 
bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                                int SPAdj,
                                                unsigned FIOperandNum,
                                                RegScavenger *RS) const {
  // TODO: this implementation is a temporary placeholder which does just
  // enough to allow other aspects of code generation to be tested.
 
  assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
 
  MachineInstr &MI = *II;
  assert(MI.getOperand(FIOperandNum + 1).isImm() &&
         "Unexpected FI-consuming insn");
 
  MachineBasicBlock &MBB = *MI.getParent();
  MachineFunction &MF = *MI.getParent()->getParent();
  MachineRegisterInfo &MRI = MF.getRegInfo();
  const LoongArchSubtarget &STI = MF.getSubtarget<LoongArchSubtarget>();
  const LoongArchInstrInfo *TII = STI.getInstrInfo();
  const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
  DebugLoc DL = MI.getDebugLoc();
  bool IsLA64 = STI.is64Bit();
  unsigned MIOpc = MI.getOpcode();
 
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
  Register FrameReg;
  StackOffset Offset =
      TFI->getFrameIndexReference(MF, FrameIndex, FrameReg) +
      StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
 
  bool FrameRegIsKill = false;
 
  int FixedOffset = Offset.getFixed();
  bool OffsetLegal = true;
  // True only when the instruction's immediate field is si12.
  bool HasSimm12Field = false;
  // Replace ld/st with ldptr/stptr if possible.
  unsigned PtrOpc = 0;
 
  switch (MIOpc) {
  case LoongArch::LDPTR_W:
  case LoongArch::LDPTR_D:
  case LoongArch::STPTR_W:
  case LoongArch::STPTR_D:
    PtrOpc = MIOpc;
    break;
  case LoongArch::LD_W:
    HasSimm12Field = true;
    PtrOpc = LoongArch::LDPTR_W;
    break;
  case LoongArch::LD_D:
    HasSimm12Field = true;
    PtrOpc = LoongArch::LDPTR_D;
    break;
  case LoongArch::ST_W:
    HasSimm12Field = true;
    PtrOpc = LoongArch::STPTR_W;
    break;
  case LoongArch::ST_D:
    HasSimm12Field = true;
    PtrOpc = LoongArch::STPTR_D;
    break;
  case LoongArch::LD_B:
  case LoongArch::LD_H:
  case LoongArch::LD_BU:
  case LoongArch::LD_HU:
  case LoongArch::LD_WU:
  case LoongArch::ST_B:
  case LoongArch::ST_H:
  case LoongArch::FLD_S:
  case LoongArch::FLD_D:
  case LoongArch::FST_S:
  case LoongArch::FST_D:
  case LoongArch::VLD:
  case LoongArch::VST:
  case LoongArch::XVLD:
  case LoongArch::XVST:
  case LoongArch::VLDREPL_B:
  case LoongArch::XVLDREPL_B:
    HasSimm12Field = true;
    break;
  }
 
  // Handle offsets that exceed the immediate range of the instruction.
  switch (MIOpc) {
  case LoongArch::VSTELM_B:
  case LoongArch::XVSTELM_B:
    OffsetLegal = isInt<8>(FixedOffset);
    break;
  case LoongArch::VSTELM_H:
  case LoongArch::XVSTELM_H:
    OffsetLegal = isShiftedInt<8, 1>(FixedOffset);
    break;
  case LoongArch::VSTELM_W:
  case LoongArch::XVSTELM_W:
    OffsetLegal = isShiftedInt<8, 2>(FixedOffset);
    break;
  case LoongArch::VSTELM_D:
  case LoongArch::XVSTELM_D:
    OffsetLegal = isShiftedInt<8, 3>(FixedOffset);
    break;
  }
 
  if (!OffsetLegal && isInt<12>(FixedOffset)) {
    unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
 
    // The offset fits in si12 but is not legal for the instruction,
    // so use only one scratch register instead.
    Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
    BuildMI(MBB, II, DL, TII->get(Addi), ScratchReg)
        .addReg(FrameReg)
        .addImm(FixedOffset);
    Offset = StackOffset::getFixed(0);
    FrameReg = ScratchReg;
    FrameRegIsKill = true;
  }
 
  // If the offset doesn't fit the si12 field of ld/st but does fit
  // the si14 << 2 field of ldptr/stptr, replace with the latter one.
  if (IsLA64 && !isInt<12>(FixedOffset) && isShiftedInt<14, 2>(FixedOffset)) {
    if (PtrOpc) {
      MI.setDesc(TII->get(PtrOpc));
      MI.getOperand(FIOperandNum)
          .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FixedOffset);
      return false;
    }
  }
 
  if (!isInt<12>(FixedOffset)) {
    unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
    unsigned Add = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
    int64_t Val = FixedOffset;
    // Keep the old behaviour of materializing the whole offset for instructions
    // do not have simm12 field or ADDI due to it will be replaced.
    int64_t Lo12 = !HasSimm12Field ? 0 : SignExtend64<12>(Val);
    uint64_t HiVal = (uint64_t)Val - (uint64_t)Lo12;
 
    // The offset won't fit in an immediate, so use a scratch register instead.
    // Modify Offset and FrameReg appropriately.
    Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
    // Move lower 12-bit of offset into original instruction.
    Offset = StackOffset::getFixed(Lo12);
 
    if (HasSimm12Field && isShiftedInt<20, 12>(HiVal)) {
      BuildMI(MBB, II, DL, TII->get(LoongArch::PseudoAddUpperImm), ScratchReg)
          .addReg(FrameReg)
          .addImm(static_cast<int64_t>(HiVal) >> 12);
    } else {
      TII->movImm(MBB, II, DL, ScratchReg, HiVal);
      if (MIOpc == Addi) {
        BuildMI(MBB, II, DL, TII->get(Add), MI.getOperand(0).getReg())
            .addReg(FrameReg)
            .addReg(ScratchReg, RegState::Kill);
        MI.eraseFromParent();
        return true;
      }
      BuildMI(MBB, II, DL, TII->get(Add), ScratchReg)
          .addReg(FrameReg)
          .addReg(ScratchReg, RegState::Kill);
    }
    FrameReg = ScratchReg;
    FrameRegIsKill = true;
  }
 
  // Spill CFRs.
  if (MIOpc == LoongArch::PseudoST_CFR) {
    Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
    BuildMI(MBB, II, DL, TII->get(LoongArch::MOVCF2GR), ScratchReg)
        .add(MI.getOperand(0));
    BuildMI(MBB, II, DL, TII->get(IsLA64 ? LoongArch::ST_D : LoongArch::ST_W))
        .addReg(ScratchReg, RegState::Kill)
        .addReg(FrameReg)
        .addImm(Offset.getFixed());
    MI.eraseFromParent();
    return true;
  }
 
  // Reload CFRs.
  if (MIOpc == LoongArch::PseudoLD_CFR) {
    Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
    BuildMI(MBB, II, DL, TII->get(IsLA64 ? LoongArch::LD_D : LoongArch::LD_W),
            ScratchReg)
        .addReg(FrameReg)
        .addImm(Offset.getFixed());
    BuildMI(MBB, II, DL, TII->get(LoongArch::MOVGR2CF))
        .add(MI.getOperand(0))
        .addReg(ScratchReg, RegState::Kill);
    MI.eraseFromParent();
    return true;
  }
 
  MI.getOperand(FIOperandNum)
      .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
  return false;
}
 
bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
  if (!TargetRegisterInfo::canRealignStack(MF))
    return false;
 
  const MachineRegisterInfo *MRI = &MF.getRegInfo();
  const LoongArchFrameLowering *TFI = getFrameLowering(MF);
 
  // Stack realignment requires a frame pointer.  If we already started
  // register allocation with frame pointer elimination, it is too late now.
  if (!MRI->canReserveReg(LoongArch::R22))
    return false;
 
  // We may also need a base pointer if there are dynamic allocas or stack
  // pointer adjustments around calls.
  if (TFI->hasReservedCallFrame(MF))
    return true;
 
  // A base pointer is required and allowed.  Check that it isn't too late to
  // reserve it.
  return MRI->canReserveReg(LoongArchABI::getBPReg());
}