35 if (Preheader ==
Loop)
36 Preheader = *std::next(
Loop->pred_begin());
39 Exit = *std::next(
Loop->succ_begin());
45 MF.
insert(std::next(
Loop->getIterator()), NewBB);
48 auto InsertPt = NewBB->
end();
51 NewBB->
insert(InsertPt, NewMI);
57 R =
MRI.createVirtualRegister(
MRI.getRegClass(OrigR));
65 for (
auto &
Use :
MRI.use_operands(OrigR))
66 if (
Use.getParent()->getParent() !=
Loop)
70 MRI.constrainRegClass(R,
MRI.getRegClass(
Use->getReg()));
71 assert(ConstrainRegClass &&
72 "Expected a valid constrained register class!");
73 (void)ConstrainRegClass;
83 if (
auto It = Remaps.
find(MO.getReg()); It != Remaps.
end())
84 MO.setReg(It->second);
86 for (
auto I = NewBB->
begin();
I->isPHI(); ++
I) {
88 unsigned LoopRegIdx = 3, InitRegIdx = 1;
89 if (
MI.getOperand(2).getMBB() != Preheader)
96 Register R =
MI.getOperand(LoopRegIdx).getReg();
97 if (
auto It = Remaps.
find(R); It != Remaps.
end())
100 MI.removeOperand(LoopRegIdx + 1);
101 MI.removeOperand(LoopRegIdx + 0);
106 MI.getOperand(LoopRegIdx).setReg(LoopReg);
107 MI.removeOperand(InitRegIdx + 1);
108 MI.removeOperand(InitRegIdx + 0);
118 Loop->replacePhiUsesWith(Preheader, NewBB);
119 if (
auto PreheaderLayoutSuccessor = std::next(Preheader->
getIterator());
120 PreheaderLayoutSuccessor != Preheader->
getParent()->
end())
122 TII->removeBranch(*NewBB);
123 TII->insertBranch(*NewBB,
Loop,
nullptr, {},
DL);
125 Loop->replaceSuccessor(Exit, NewBB);
126 Exit->replacePhiUsesWith(
Loop, NewBB);
135 assert(CanAnalyzeBr &&
"Must be able to analyze the loop branch!");
138 FBB == Exit ? NewBB : FBB,
Cond,
DL);
139 if (
TII->removeBranch(*NewBB) > 0)
140 TII->insertBranch(*NewBB, Exit,
nullptr, {},
DL);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
PassBuilder PB(Mod->getContext(), Machine, PassOpts->PTO, std::nullopt, &PIC)
SmallVector< MachineOperand, 4 > Cond
MachineRegisterInfo & MRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Remove Loads Into Fake Uses
iterator find(const_arg_type_t< KeyT > Val)
void splitCriticalEdge(BasicBlockT *FromBB, BasicBlockT *ToBB, BasicBlockT *NewBB)
Apply updates that the critical edge (FromBB, ToBB) has been split with NewBB.
Represents a single loop in the control flow graph.
instr_iterator instr_begin()
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LLVM_ABI void updateTerminator(MachineBasicBlock *PreviousLayoutSuccessor)
Update the terminator instructions in block to account for changes to block layout which may have bee...
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
LLVM_ABI iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Instructions::iterator instr_iterator
LLVM_ABI void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
void insert(iterator MBBI, MachineBasicBlock *MBB)
Representation of each machine instruction.
mop_range defs()
Returns all explicit operands that are register definitions.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
A Use represents the edge between a Value definition and its users.
self_iterator getIterator()
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI MachineBasicBlock * PeelSingleBlockLoop(LoopPeelDirection Direction, MachineBasicBlock *Loop, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineDomTreeUpdater *MDTU=nullptr)
Peels a single block loop.
@ LPD_Back
Peel the last iteration of the loop.
@ LPD_Front
Peel the first iteration of the loop.
MCRegisterClass TargetRegisterClass
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.