LLVM 24.0.0git
ProcessImplicitDefs.cpp
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1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/ADT/SetVector.h"
18#include "llvm/Pass.h"
19#include "llvm/Support/Debug.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "processimpdefs"
25
26namespace {
27/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
28/// for each use. Add isUndef marker to implicit_def defs and their uses.
29class ProcessImplicitDefsLegacy : public MachineFunctionPass {
30public:
31 static char ID;
32
33 ProcessImplicitDefsLegacy() : MachineFunctionPass(ID) {}
34
35 void getAnalysisUsage(AnalysisUsage &AU) const override;
36
37 bool runOnMachineFunction(MachineFunction &MF) override;
38
39 MachineFunctionProperties getRequiredProperties() const override {
40 return MachineFunctionProperties().setIsSSA();
41 }
42};
43
44class ProcessImplicitDefs {
45 const TargetInstrInfo *TII = nullptr;
46 const TargetRegisterInfo *TRI = nullptr;
47 MachineRegisterInfo *MRI = nullptr;
48
50
51 void processImplicitDef(MachineInstr *MI);
52 bool canTurnIntoImplicitDef(MachineInstr *MI);
53
54public:
55 bool run(MachineFunction &MF);
56};
57} // end anonymous namespace
58
59char ProcessImplicitDefsLegacy::ID = 0;
60char &llvm::ProcessImplicitDefsID = ProcessImplicitDefsLegacy::ID;
61
62INITIALIZE_PASS(ProcessImplicitDefsLegacy, DEBUG_TYPE,
63 "Process Implicit Definitions", false, false)
64
65void ProcessImplicitDefsLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
66 AU.setPreservesCFG();
67 AU.addPreserved<AAResultsWrapperPass>();
69}
70
71bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
72 if (!MI->isCopyLike() &&
73 !MI->isInsertSubreg() &&
74 !MI->isRegSequence() &&
75 !MI->isPHI())
76 return false;
77 for (const MachineOperand &MO : MI->all_uses())
78 if (MO.readsReg())
79 return false;
80 return true;
81}
82
83void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
84 LLVM_DEBUG(dbgs() << "Processing " << *MI);
85 Register Reg = MI->getOperand(0).getReg();
86 // Trim any extra operands.
87 for (unsigned i = MI->getNumOperands() - 1; i; --i)
88 MI->removeOperand(i);
89
90 if (Reg.isVirtual()) {
91 // For virtual registers, mark all uses as <undef>, and convert users to
92 // implicit-def when possible.
93 bool AllUsesUndef = true;
94 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
95 MachineInstr *UserMI = MO.getParent();
96 if (UserMI->hasTiedAndOtherReadOf(Reg, MO.getSubReg())) {
97 AllUsesUndef = false;
98 continue;
99 }
100 MO.setIsUndef();
101 if (!canTurnIntoImplicitDef(UserMI))
102 continue;
103 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
104 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
105 WorkList.insert(UserMI);
106 }
107 if (AllUsesUndef) {
108 MI->eraseFromParent();
109 return;
110 }
111 // A kept PHI, now an IMPLICIT_DEF, leaves the PHI block.
112 MachineBasicBlock *MBB = MI->getParent();
113 MachineBasicBlock::iterator Next = std::next(MI->getIterator());
114 if (Next != MBB->end() && Next->isPHI())
116 return;
117 }
118
119 // This is a physreg implicit-def.
120 // Try to add undef flag to all uses. If all uses are updated remove
121 // implicit-def.
122 MachineBasicBlock::instr_iterator SearchMI = MI->getIterator();
123 MachineBasicBlock::instr_iterator SearchE = MI->getParent()->instr_end();
124 bool ImplicitDefIsDead = false;
125 bool SearchedWholeBlock = true;
126 constexpr unsigned SearchLimit = 35;
127 unsigned Count = 0;
128 for (++SearchMI; SearchMI != SearchE; ++SearchMI) {
129 if (SearchMI->isDebugInstr())
130 continue;
131 if (++Count > SearchLimit) {
132 SearchedWholeBlock = false;
133 break;
134 }
135 for (MachineOperand &MO : SearchMI->operands()) {
136 if (!MO.isReg())
137 continue;
138 Register SearchReg = MO.getReg();
139 if (!SearchReg.isPhysical() || !TRI->regsOverlap(Reg, SearchReg))
140 continue;
141 // SearchMI uses or redefines Reg. Set <undef> flags on all uses.
142 if (MO.isUse()) {
143 if (TRI->isSubRegisterEq(Reg, SearchReg)) {
144 MO.setIsUndef();
145 } else {
146 // Use is larger than Reg. It is not safe to add undef to this use.
147 return;
148 }
149 }
150 if (MO.isDef()) {
151 if (TRI->isSubRegisterEq(SearchReg, Reg)) {
152 ImplicitDefIsDead = true;
153 } else {
154 // Reg is larger than definition. It is not safe to add undef to any
155 // subsequent uses of Reg.
156 return;
157 }
158 }
159 }
160 if (ImplicitDefIsDead) {
161 LLVM_DEBUG(dbgs() << "Physreg redefine: " << *SearchMI);
162 break;
163 }
164 }
165
166 // If we have added an undef flag to all uses (i.e. we have found a redefining
167 // MI or there are no successors), we can erase the IMPLICIT_DEF.
168 if (ImplicitDefIsDead ||
169 (SearchedWholeBlock && MI->getParent()->succ_empty())) {
170 MI->eraseFromParent();
171 LLVM_DEBUG(dbgs() << "Deleting implicit-def: " << *MI);
172 }
173}
174
175bool ProcessImplicitDefsLegacy::runOnMachineFunction(MachineFunction &MF) {
176 return ProcessImplicitDefs().run(MF);
177}
178
179PreservedAnalyses
182 if (!ProcessImplicitDefs().run(MF))
183 return PreservedAnalyses::all();
184
187 .preserve<AAManager>();
188}
189
190/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
191/// <undef> operands.
192bool ProcessImplicitDefs::run(MachineFunction &MF) {
193
194 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
195 << "********** Function: " << MF.getName() << '\n');
196
197 bool Changed = false;
198
201 MRI = &MF.getRegInfo();
202 assert(WorkList.empty() && "Inconsistent worklist state");
203
204 for (MachineBasicBlock &MBB : MF) {
205 // Scan the basic block for implicit defs.
206 for (MachineInstr &MI : MBB)
207 if (MI.isImplicitDef())
208 WorkList.insert(&MI);
209
210 if (WorkList.empty())
211 continue;
212
213 LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
214 << " implicit defs.\n");
215 Changed = true;
216
217 // Drain the WorkList to recursively process any new implicit defs.
218 do processImplicitDef(WorkList.pop_back_val());
219 while (!WorkList.empty());
220 }
221 return Changed;
222}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
#define DEBUG_TYPE
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
This file implements a set that has insertion order iteration characteristics.
#define LLVM_DEBUG(...)
Definition Debug.h:119
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
Represents analyses that only rely on functions' control flow.
Definition Analysis.h:73
LLVM_ABI iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
Instructions::iterator instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Properties which a MachineFunction may have at a given point in time.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
LLVM_ABI void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
LLVM_ABI bool hasTiedAndOtherReadOf(Register Reg, unsigned SubReg) const
Return true if two operands read (Reg, SubReg) and one is tied to a def of another register.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
PreservedAnalyses & preserveSet()
Mark an analysis set as preserved.
Definition Analysis.h:151
LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition Register.h:79
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:83
A SetVector that performs no allocations if smaller than a certain size.
Definition SetVector.h:345
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Changed
This is an optimization pass for GlobalISel generic memory operations.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
LLVM_ABI char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Count
Definition InstrProf.h:145
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Next
Definition InstrProf.h:147
LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.