24#define DEBUG_TYPE "processimpdefs"
44class ProcessImplicitDefs {
59char ProcessImplicitDefsLegacy::ID = 0;
63 "Process Implicit Definitions",
false,
false)
65void ProcessImplicitDefsLegacy::getAnalysisUsage(
AnalysisUsage &AU)
const {
71bool ProcessImplicitDefs::canTurnIntoImplicitDef(
MachineInstr *
MI) {
72 if (!
MI->isCopyLike() &&
73 !
MI->isInsertSubreg() &&
74 !
MI->isRegSequence() &&
77 for (
const MachineOperand &MO :
MI->all_uses())
83void ProcessImplicitDefs::processImplicitDef(MachineInstr *
MI) {
87 for (
unsigned i =
MI->getNumOperands() - 1; i; --i)
93 bool AllUsesUndef =
true;
95 MachineInstr *UserMI = MO.getParent();
101 if (!canTurnIntoImplicitDef(UserMI))
104 UserMI->
setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
105 WorkList.insert(UserMI);
108 MI->eraseFromParent();
124 bool ImplicitDefIsDead =
false;
125 bool SearchedWholeBlock =
true;
126 constexpr unsigned SearchLimit = 35;
128 for (++SearchMI; SearchMI != SearchE; ++SearchMI) {
129 if (SearchMI->isDebugInstr())
131 if (++
Count > SearchLimit) {
132 SearchedWholeBlock =
false;
135 for (MachineOperand &MO : SearchMI->operands()) {
143 if (
TRI->isSubRegisterEq(
Reg, SearchReg)) {
151 if (
TRI->isSubRegisterEq(SearchReg,
Reg)) {
152 ImplicitDefIsDead =
true;
160 if (ImplicitDefIsDead) {
168 if (ImplicitDefIsDead ||
169 (SearchedWholeBlock &&
MI->getParent()->succ_empty())) {
170 MI->eraseFromParent();
175bool ProcessImplicitDefsLegacy::runOnMachineFunction(
MachineFunction &MF) {
176 return ProcessImplicitDefs().run(MF);
182 if (!ProcessImplicitDefs().
run(MF))
187 .preserve<AAManager>();
194 LLVM_DEBUG(
dbgs() <<
"********** PROCESS IMPLICIT DEFS **********\n"
195 <<
"********** Function: " << MF.
getName() <<
'\n');
202 assert(WorkList.empty() &&
"Inconsistent worklist state");
207 if (
MI.isImplicitDef())
208 WorkList.insert(&
MI);
210 if (WorkList.empty())
214 <<
" implicit defs.\n");
218 do processImplicitDef(WorkList.pop_back_val());
219 while (!WorkList.empty());
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const HexagonInstrInfo * TII
Register const TargetRegisterInfo * TRI
Promote Memory to Register
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file implements a set that has insertion order iteration characteristics.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
Represents analyses that only rely on functions' control flow.
LLVM_ABI iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
Instructions::iterator instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Properties which a MachineFunction may have at a given point in time.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
LLVM_ABI void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
LLVM_ABI bool hasTiedAndOtherReadOf(Register Reg, unsigned SubReg) const
Return true if two operands read (Reg, SubReg) and one is tied to a def of another register.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
PreservedAnalyses & preserveSet()
Mark an analysis set as preserved.
LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
A SetVector that performs no allocations if smaller than a certain size.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
This is an optimization pass for GlobalISel generic memory operations.
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Count
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Next
LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.