LLVM 24.0.0git
VERegisterInfo.cpp
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1//===-- VERegisterInfo.cpp - VE Register Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the VE implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "VERegisterInfo.h"
14#include "VE.h"
15#include "VESubtarget.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/IR/Type.h"
22#include "llvm/Support/Debug.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "ve-register-info"
27
28#define GET_REGINFO_TARGET_DESC
29#include "VEGenRegisterInfo.inc"
30
31// VE uses %s10 == %lp to keep return address
32VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {}
33
34const MCPhysReg *
35VERegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36 switch (MF->getFunction().getCallingConv()) {
37 case CallingConv::Fast:
38 // Being explicit (same as standard CC).
39 default:
40 return CSR_SaveList;
41 case CallingConv::PreserveAll:
42 return CSR_preserve_all_SaveList;
43 }
44}
45
46const uint32_t *VERegisterInfo::getCallPreservedMask(const MachineFunction &MF,
47 CallingConv::ID CC) const {
48 switch (CC) {
49 case CallingConv::Fast:
50 // Being explicit (same as standard CC).
51 default:
52 return CSR_RegMask;
53 case CallingConv::PreserveAll:
54 return CSR_preserve_all_RegMask;
55 }
56}
57
58const uint32_t *VERegisterInfo::getNoPreservedMask() const {
59 return CSR_NoRegs_RegMask;
60}
61
62BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63 BitVector Reserved(getNumRegs());
64
65 const Register ReservedRegs[] = {
66 VE::SX8, // Stack limit
67 VE::SX9, // Frame pointer
68 VE::SX10, // Link register (return address)
69 VE::SX11, // Stack pointer
70
71 // FIXME: maybe not need to be reserved
72 VE::SX12, // Outer register
73 VE::SX13, // Id register for dynamic linker
74
75 VE::SX14, // Thread pointer
76 VE::SX15, // Global offset table register
77 VE::SX16, // Procedure linkage table register
78 VE::SX17, // Linkage-area register
79 // sx18-sx33 are callee-saved registers
80 // sx34-sx63 are temporary registers
81 };
82
83 for (auto R : ReservedRegs)
84 for (MCRegAliasIterator ItAlias(R, this, true); ItAlias.isValid();
85 ++ItAlias)
86 Reserved.set(*ItAlias);
87
88 // Reserve constant registers.
89 Reserved.set(VE::VM0);
90 Reserved.set(VE::VMP0);
91
92 return Reserved;
93}
94
95static unsigned offsetToDisp(MachineInstr &MI) {
96 // Default offset in instruction's operands (reg+reg+imm).
97 unsigned OffDisp = 2;
98
99#define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii
100
101 {
102 using namespace llvm::VE;
103 switch (MI.getOpcode()) {
104 case INLINEASM:
105 case RRCAS_multi_cases(TS1AML):
106 case RRCAS_multi_cases(TS1AMW):
107 case RRCAS_multi_cases(CASL):
108 case RRCAS_multi_cases(CASW):
109 // These instructions use AS format (reg+imm).
110 OffDisp = 1;
111 break;
112 }
113 }
114#undef RRCAS_multi_cases
115
116 return OffDisp;
117}
118
119namespace {
120class EliminateFrameIndex {
121 const TargetInstrInfo &TII;
122 const TargetRegisterInfo &TRI;
123 const DebugLoc &DL;
124 MachineBasicBlock &MBB;
125 MachineBasicBlock::iterator II;
126 Register clobber;
127
128 // Some helper functions for the ease of instruction building.
129 MachineFunction &getFunc() const { return *MBB.getParent(); }
130 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
131 return TRI.getSubReg(Reg, Idx);
132 }
133 inline const MCInstrDesc &get(unsigned Opcode) const {
134 return TII.get(Opcode);
135 }
136 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) {
137 return BuildMI(MBB, II, DL, MCID, DestReg);
138 }
139 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) {
140 return build(get(InstOpc), DestReg);
141 }
142 inline MachineInstrBuilder build(const MCInstrDesc &MCID) {
143 return BuildMI(MBB, II, DL, MCID);
144 }
145 inline MachineInstrBuilder build(unsigned InstOpc) {
146 return build(get(InstOpc));
147 }
148
149 // Calculate an address of frame index from a frame register and a given
150 // offset if the offset doesn't fit in the immediate field. Use a clobber
151 // register to hold calculated address.
152 void prepareReplaceFI(MachineInstr &MI, Register &FrameReg, int64_t &Offset,
153 int64_t Bytes = 0);
154 // Replace the frame index in \p MI with a frame register and a given offset
155 // if it fits in the immediate field. Otherwise, use pre-calculated address
156 // in a clobber register.
157 void replaceFI(MachineInstr &MI, Register FrameReg, int64_t Offset,
158 int FIOperandNum);
159
160 // Expand and eliminate Frame Index of pseudo STQrii and LDQrii.
161 void processSTQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
162 int FIOperandNum);
163 void processLDQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
164 int FIOperandNum);
165 // Expand and eliminate Frame Index of pseudo STVMrii and LDVMrii.
166 void processSTVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
167 int FIOperandNum);
168 void processLDVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
169 int FIOperandNum);
170 // Expand and eliminate Frame Index of pseudo STVM512rii and LDVM512rii.
171 void processSTVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,
172 int FIOperandNum);
173 void processLDVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,
174 int FIOperandNum);
175
176public:
177 EliminateFrameIndex(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
178 const DebugLoc &DL, MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator II)
180 : TII(TII), TRI(TRI), DL(DL), MBB(MBB), II(II), clobber(VE::SX13) {}
181
182 // Expand and eliminate Frame Index from MI
183 void processMI(MachineInstr &MI, Register FrameReg, int64_t Offset,
184 int FIOperandNum);
185};
186} // namespace
187
188// Prepare the frame index if it doesn't fit in the immediate field. Use
189// clobber register to hold calculated address.
190void EliminateFrameIndex::prepareReplaceFI(MachineInstr &MI, Register &FrameReg,
191 int64_t &Offset, int64_t Bytes) {
192 if (isInt<32>(Offset) && isInt<32>(Offset + Bytes)) {
193 // If the offset is small enough to fit in the immediate field, directly
194 // encode it. So, nothing to prepare here.
195 return;
196 }
197
198 // If the offset doesn't fit, emit following codes. This clobbers SX13
199 // which we always know is available here.
200 // lea %clobber, Offset@lo
201 // and %clobber, %clobber, (32)0
202 // lea.sl %clobber, Offset@hi(FrameReg, %clobber)
203 build(VE::LEAzii, clobber).addImm(0).addImm(0).addImm(Lo_32(Offset));
204 build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32));
205 build(VE::LEASLrri, clobber)
206 .addReg(clobber)
207 .addReg(FrameReg)
208 .addImm(Hi_32(Offset));
209
210 // Use clobber register as a frame register and 0 offset
211 FrameReg = clobber;
212 Offset = 0;
213}
214
215// Replace the frame index in \p MI with a proper byte and framereg offset.
216void EliminateFrameIndex::replaceFI(MachineInstr &MI, Register FrameReg,
217 int64_t Offset, int FIOperandNum) {
218 assert(isInt<32>(Offset));
219
220 // The offset must be small enough to fit in the immediate field after
221 // call of prepareReplaceFI. Therefore, we directly encode it.
222 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
223 MI.getOperand(FIOperandNum + offsetToDisp(MI)).ChangeToImmediate(Offset);
224}
225
226void EliminateFrameIndex::processSTQ(MachineInstr &MI, Register FrameReg,
227 int64_t Offset, int FIOperandNum) {
228 assert(MI.getOpcode() == VE::STQrii);
229 LLVM_DEBUG(dbgs() << "processSTQ: "; MI.dump());
230
231 prepareReplaceFI(MI, FrameReg, Offset, 8);
232
233 Register SrcReg = MI.getOperand(3).getReg();
234 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);
235 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);
236 // VE stores HiReg to 8(addr) and LoReg to 0(addr)
237 MachineInstr *StMI =
238 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg);
239 replaceFI(*StMI, FrameReg, Offset, 0);
240 // Mutate to 'hi' store.
241 MI.setDesc(get(VE::STrii));
242 MI.getOperand(3).setReg(SrcHiReg);
243 Offset += 8;
244 replaceFI(MI, FrameReg, Offset, FIOperandNum);
245}
246
247void EliminateFrameIndex::processLDQ(MachineInstr &MI, Register FrameReg,
248 int64_t Offset, int FIOperandNum) {
249 assert(MI.getOpcode() == VE::LDQrii);
250 LLVM_DEBUG(dbgs() << "processLDQ: "; MI.dump());
251
252 prepareReplaceFI(MI, FrameReg, Offset, 8);
253
254 Register DestReg = MI.getOperand(0).getReg();
255 Register DestHiReg = getSubReg(DestReg, VE::sub_even);
256 Register DestLoReg = getSubReg(DestReg, VE::sub_odd);
257 // VE loads HiReg from 8(addr) and LoReg from 0(addr)
258 MachineInstr *StMI =
259 build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0);
260 replaceFI(*StMI, FrameReg, Offset, 1);
261 MI.setDesc(get(VE::LDrii));
262 MI.getOperand(0).setReg(DestHiReg);
263 Offset += 8;
264 replaceFI(MI, FrameReg, Offset, FIOperandNum);
265}
266
267void EliminateFrameIndex::processSTVM(MachineInstr &MI, Register FrameReg,
268 int64_t Offset, int FIOperandNum) {
269 assert(MI.getOpcode() == VE::STVMrii);
270 LLVM_DEBUG(dbgs() << "processSTVM: "; MI.dump());
271
272 // Original MI is:
273 // STVMrii frame-index, 0, offset, reg (, memory operand)
274 // Convert it to:
275 // SVMi tmp-reg, reg, 0
276 // STrii frame-reg, 0, offset, tmp-reg
277 // SVMi tmp-reg, reg, 1
278 // STrii frame-reg, 0, offset+8, tmp-reg
279 // SVMi tmp-reg, reg, 2
280 // STrii frame-reg, 0, offset+16, tmp-reg
281 // SVMi tmp-reg, reg, 3
282 // STrii frame-reg, 0, offset+24, tmp-reg
283
284 prepareReplaceFI(MI, FrameReg, Offset, 24);
285
286 Register SrcReg = MI.getOperand(3).getReg();
287 bool isKill = MI.getOperand(3).isKill();
288 // FIXME: it would be better to scavenge a register here instead of
289 // reserving SX16 all of the time.
290 Register TmpReg = VE::SX16;
291 for (int i = 0; i < 3; ++i) {
292 build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i);
293 MachineInstr *StMI =
294 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
295 TmpReg, getKillRegState(true));
296 replaceFI(*StMI, FrameReg, Offset, 0);
297 Offset += 8;
298 }
299 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3);
300 MI.setDesc(get(VE::STrii));
301 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);
302 replaceFI(MI, FrameReg, Offset, FIOperandNum);
303}
304
305void EliminateFrameIndex::processLDVM(MachineInstr &MI, Register FrameReg,
306 int64_t Offset, int FIOperandNum) {
307 assert(MI.getOpcode() == VE::LDVMrii);
308 LLVM_DEBUG(dbgs() << "processLDVM: "; MI.dump());
309
310 // Original MI is:
311 // LDVMri reg, frame-index, 0, offset (, memory operand)
312 // Convert it to:
313 // LDrii tmp-reg, frame-reg, 0, offset
314 // LVMir vm, 0, tmp-reg
315 // LDrii tmp-reg, frame-reg, 0, offset+8
316 // LVMir_m vm, 1, tmp-reg, vm
317 // LDrii tmp-reg, frame-reg, 0, offset+16
318 // LVMir_m vm, 2, tmp-reg, vm
319 // LDrii tmp-reg, frame-reg, 0, offset+24
320 // LVMir_m vm, 3, tmp-reg, vm
321
322 prepareReplaceFI(MI, FrameReg, Offset, 24);
323
324 Register DestReg = MI.getOperand(0).getReg();
325 // FIXME: it would be better to scavenge a register here instead of
326 // reserving SX16 all of the time.
327 unsigned TmpReg = VE::SX16;
328 for (int i = 0; i < 4; ++i) {
329 if (i != 3) {
330 MachineInstr *StMI =
331 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
332 replaceFI(*StMI, FrameReg, Offset, 1);
333 Offset += 8;
334 } else {
335 // Last LDrii replace the target instruction.
336 MI.setDesc(get(VE::LDrii));
337 MI.getOperand(0).ChangeToRegister(TmpReg, true);
338 }
339 // First LVM is LVMir. Others are LVMir_m. Last LVM places at the
340 // next of the target instruction.
341 if (i == 0)
342 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true));
343 else if (i != 3)
344 build(VE::LVMir_m, DestReg)
345 .addImm(i)
346 .addReg(TmpReg, getKillRegState(true))
347 .addReg(DestReg);
348 else
349 BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestReg)
350 .addImm(3)
351 .addReg(TmpReg, getKillRegState(true))
352 .addReg(DestReg);
353 }
354 replaceFI(MI, FrameReg, Offset, FIOperandNum);
355}
356
357void EliminateFrameIndex::processSTVM512(MachineInstr &MI, Register FrameReg,
358 int64_t Offset, int FIOperandNum) {
359 assert(MI.getOpcode() == VE::STVM512rii);
360 LLVM_DEBUG(dbgs() << "processSTVM512: "; MI.dump());
361
362 prepareReplaceFI(MI, FrameReg, Offset, 56);
363
364 Register SrcReg = MI.getOperand(3).getReg();
365 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd);
366 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even);
367 bool isKill = MI.getOperand(3).isKill();
368 // FIXME: it would be better to scavenge a register here instead of
369 // reserving SX16 all of the time.
370 Register TmpReg = VE::SX16;
371 // store low part of VMP
372 MachineInstr *LastMI = nullptr;
373 for (int i = 0; i < 4; ++i) {
374 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcLoReg).addImm(i);
375 MachineInstr *StMI =
376 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
377 TmpReg, getKillRegState(true));
378 replaceFI(*StMI, FrameReg, Offset, 0);
379 Offset += 8;
380 }
381 if (isKill)
382 LastMI->addRegisterKilled(SrcLoReg, &TRI, true);
383 // store high part of VMP
384 for (int i = 0; i < 3; ++i) {
385 build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(i);
386 MachineInstr *StMI =
387 build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
388 TmpReg, getKillRegState(true));
389 replaceFI(*StMI, FrameReg, Offset, 0);
390 Offset += 8;
391 }
392 LastMI = build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(3);
393 if (isKill) {
394 LastMI->addRegisterKilled(SrcHiReg, &TRI, true);
395 // Add implicit super-register kills to the particular MI.
396 LastMI->addRegisterKilled(SrcReg, &TRI, true);
397 }
398 MI.setDesc(get(VE::STrii));
399 MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);
400 replaceFI(MI, FrameReg, Offset, FIOperandNum);
401}
402
403void EliminateFrameIndex::processLDVM512(MachineInstr &MI, Register FrameReg,
404 int64_t Offset, int FIOperandNum) {
405 assert(MI.getOpcode() == VE::LDVM512rii);
406 LLVM_DEBUG(dbgs() << "processLDVM512: "; MI.dump());
407
408 prepareReplaceFI(MI, FrameReg, Offset, 56);
409
410 Register DestReg = MI.getOperand(0).getReg();
411 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd);
412 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even);
413 // FIXME: it would be better to scavenge a register here instead of
414 // reserving SX16 all of the time.
415 Register TmpReg = VE::SX16;
416 build(VE::IMPLICIT_DEF, DestReg);
417 for (int i = 0; i < 4; ++i) {
418 MachineInstr *LdMI =
419 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
420 replaceFI(*LdMI, FrameReg, Offset, 1);
421 build(VE::LVMir_m, DestLoReg)
422 .addImm(i)
423 .addReg(TmpReg, getKillRegState(true))
424 .addReg(DestLoReg);
425 Offset += 8;
426 }
427 for (int i = 0; i < 3; ++i) {
428 MachineInstr *LdMI =
429 build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
430 replaceFI(*LdMI, FrameReg, Offset, 1);
431 build(VE::LVMir_m, DestHiReg)
432 .addImm(i)
433 .addReg(TmpReg, getKillRegState(true))
434 .addReg(DestHiReg);
435 Offset += 8;
436 }
437 MI.setDesc(get(VE::LDrii));
438 MI.getOperand(0).ChangeToRegister(TmpReg, true);
439 BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestHiReg)
440 .addImm(3)
441 .addReg(TmpReg, getKillRegState(true))
442 .addReg(DestHiReg);
443 replaceFI(MI, FrameReg, Offset, FIOperandNum);
444}
445
446void EliminateFrameIndex::processMI(MachineInstr &MI, Register FrameReg,
447 int64_t Offset, int FIOperandNum) {
448 switch (MI.getOpcode()) {
449 case VE::STQrii:
450 processSTQ(MI, FrameReg, Offset, FIOperandNum);
451 return;
452 case VE::LDQrii:
453 processLDQ(MI, FrameReg, Offset, FIOperandNum);
454 return;
455 case VE::STVMrii:
456 processSTVM(MI, FrameReg, Offset, FIOperandNum);
457 return;
458 case VE::LDVMrii:
459 processLDVM(MI, FrameReg, Offset, FIOperandNum);
460 return;
461 case VE::STVM512rii:
462 processSTVM512(MI, FrameReg, Offset, FIOperandNum);
463 return;
464 case VE::LDVM512rii:
465 processLDVM512(MI, FrameReg, Offset, FIOperandNum);
466 return;
467 }
468 prepareReplaceFI(MI, FrameReg, Offset);
469 replaceFI(MI, FrameReg, Offset, FIOperandNum);
470}
471
472bool VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
473 int SPAdj, unsigned FIOperandNum,
474 RegScavenger *RS) const {
475 assert(SPAdj == 0 && "Unexpected");
476
477 MachineInstr &MI = *II;
478 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
479
480 MachineFunction &MF = *MI.getParent()->getParent();
481 const VESubtarget &Subtarget = MF.getSubtarget<VESubtarget>();
482 const VEFrameLowering &TFI = *getFrameLowering(MF);
483 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
484 const VERegisterInfo &TRI = *Subtarget.getRegisterInfo();
485 DebugLoc DL = MI.getDebugLoc();
486 EliminateFrameIndex EFI(TII, TRI, DL, *MI.getParent(), II);
487
488 // Retrieve FrameReg and byte offset for stack slot.
489 Register FrameReg;
490 int64_t Offset =
491 TFI.getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
492 Offset += MI.getOperand(FIOperandNum + offsetToDisp(MI)).getImm();
493
494 EFI.processMI(MI, FrameReg, Offset, FIOperandNum);
495 return false;
496}
497
498Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const {
499 return VE::SX9;
500}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
BitVector.h
This file implements the BitVector class.
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:855
Reg
Register Reg
Definition MachineSink.cpp:2127
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
II
uint64_t IntrinsicInst * II
Definition NVVMIntrRange.cpp:46
replaceFI
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr)
Definition SparcRegisterInfo.cpp:115
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:119
offsetToDisp
static unsigned offsetToDisp(MachineInstr &MI)
Definition VERegisterInfo.cpp:95
RRCAS_multi_cases
#define RRCAS_multi_cases(NAME)
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition Function.h:273
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition MCRegisterInfo.h:890
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:323
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:341
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:778
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition MachineFunction.h:739
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineInstr::addRegisterKilled
LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition MachineInstr.cpp:2166
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition TargetInstrInfo.h:116
llvm::VESubtarget::getInstrInfo
const VEInstrInfo * getInstrInfo() const override
Definition VESubtarget.h:52
llvm::VESubtarget::getRegisterInfo
const VERegisterInfo * getRegisterInfo() const override
Definition VESubtarget.h:56
uint32_t
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::CallingConv::PreserveAll
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition CallingConv.h:66
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition CallingConv.h:41
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:35
llvm::irsymtab::build
LLVM_ABI Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
Definition IRSymtab.cpp:348
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::get
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Definition PointerIntPair.h:256
llvm::Hi_32
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition MathExtras.h:151
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
llvm::Lo_32
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition MathExtras.h:156
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::M0
unsigned M0(unsigned Val)
Definition VE.h:376
llvm::VERegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition VERegisterInfo.cpp:62
llvm::VERegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition VERegisterInfo.cpp:58
llvm::VERegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition VERegisterInfo.cpp:35
llvm::VERegisterInfo::eliminateFrameIndex
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition VERegisterInfo.cpp:472
llvm::VERegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition VERegisterInfo.cpp:46
llvm::VERegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition VERegisterInfo.cpp:498
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