LLVM 24.0.0git
XtensaDisassembler.cpp
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1//===-- XtensaDisassembler.cpp - Disassembler for Xtensa ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file implements the XtensaDisassembler class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/XtensaMCTargetDesc.h"
16#include "TargetInfo/XtensaTargetInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCDecoder.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCDisassembler.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Endian.h"
26
27using namespace llvm;
28using namespace llvm::MCD;
29
30#define DEBUG_TYPE "Xtensa-disassembler"
31
32using DecodeStatus = MCDisassembler::DecodeStatus;
33
34namespace {
35
36class XtensaDisassembler : public MCDisassembler {
37 bool IsLittleEndian;
38
39public:
40 XtensaDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool isLE)
41 : MCDisassembler(STI, Ctx), IsLittleEndian(isLE) {}
42
43 bool hasDensity() const { return STI.hasFeature(Xtensa::FeatureDensity); }
44
45 bool hasESP32S3Ops() const {
46 return STI.getFeatureBits()[Xtensa::FeatureESP32S3Ops];
47 }
48
49 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const override;
52};
53} // end anonymous namespace
54
55static MCDisassembler *createXtensaDisassembler(const Target &T,
56 const MCSubtargetInfo &STI,
57 MCContext &Ctx) {
58 return new XtensaDisassembler(STI, Ctx, true);
59}
60
65
66const MCPhysReg ARDecoderTable[] = {
67 Xtensa::A0, Xtensa::SP, Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5,
68 Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11,
69 Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};
70
71static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
72 uint64_t Address,
73 const void *Decoder) {
74 if (RegNo >= std::size(ARDecoderTable))
75 return MCDisassembler::Fail;
76
77 MCPhysReg Reg = ARDecoderTable[RegNo];
78 Inst.addOperand(MCOperand::createReg(Reg));
79 return MCDisassembler::Success;
80}
81
82static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
83 uint64_t Address,
84 const void *Decoder) {
85 if (RegNo > 3)
86 return MCDisassembler::Fail;
87
88 MCPhysReg Reg = Xtensa::M0 + RegNo;
89 Inst.addOperand(MCOperand::createReg(Reg));
90 return MCDisassembler::Success;
91}
92
93static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo,
94 uint64_t Address,
95 const void *Decoder) {
96 if (RegNo > 1)
97 return MCDisassembler::Fail;
98
99 MCPhysReg Reg = Xtensa::M0 + RegNo;
100 Inst.addOperand(MCOperand::createReg(Reg));
101 return MCDisassembler::Success;
102}
103
104static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
105 uint64_t Address,
106 const void *Decoder) {
107 if (RegNo > 1)
108 return MCDisassembler::Fail;
109
110 MCPhysReg Reg = Xtensa::M2 + RegNo;
111 Inst.addOperand(MCOperand::createReg(Reg));
112 return MCDisassembler::Success;
113}
114
115static const unsigned QRDecoderTable[] = {Xtensa::Q0, Xtensa::Q1, Xtensa::Q2,
116 Xtensa::Q3, Xtensa::Q4, Xtensa::Q5,
117 Xtensa::Q6, Xtensa::Q7};
118
119static DecodeStatus DecodeQRRegisterClass(MCInst &Inst, uint64_t RegNo,
120 uint64_t Address,
121 const void *Decoder) {
122 if (RegNo >= std::size(QRDecoderTable))
123 return MCDisassembler::Fail;
124
125 unsigned Reg = QRDecoderTable[RegNo];
126 Inst.addOperand(MCOperand::createReg(Reg));
127 return MCDisassembler::Success;
128}
129
130static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo,
131 uint64_t Address,
132 const void *Decoder) {
133 if (RegNo > 15)
134 return MCDisassembler::Fail;
135
136 MCPhysReg Reg = Xtensa::F0 + RegNo;
137 Inst.addOperand(MCOperand::createReg(Reg));
138 return MCDisassembler::Success;
139}
140
141static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo,
142 uint64_t Address,
143 const MCDisassembler *Decoder) {
144 if (RegNo > 255)
145 return MCDisassembler::Fail;
146
147 Xtensa::RegisterAccessType RAType = Inst.getOpcode() == Xtensa::WUR
148 ? Xtensa::REGISTER_WRITE
149 : Xtensa::REGISTER_READ;
150
151 const XtensaDisassembler *Dis =
152 static_cast<const XtensaDisassembler *>(Decoder);
153 const MCRegisterInfo *MRI = Dis->getContext().getRegisterInfo();
154 MCPhysReg Reg = Xtensa::getUserRegister(RegNo, *MRI);
155 if (!Xtensa::checkRegister(Reg, Decoder->getSubtargetInfo().getFeatureBits(),
156 RAType))
157 return MCDisassembler::Fail;
158
159 Inst.addOperand(MCOperand::createReg(Reg));
160 return MCDisassembler::Success;
161}
162
167
168const DecodeRegister SRDecoderTable[] = {
169 {Xtensa::LBEG, 0}, {Xtensa::LEND, 1},
170 {Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3},
171 {Xtensa::BREG, 4}, {Xtensa::LITBASE, 5},
172 {Xtensa::SCOMPARE1, 12}, {Xtensa::ACCLO, 16},
173 {Xtensa::ACCHI, 17}, {Xtensa::M0, 32},
174 {Xtensa::M1, 33}, {Xtensa::M2, 34},
175 {Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72},
176 {Xtensa::WINDOWSTART, 73}, {Xtensa::IBREAKENABLE, 96},
177 {Xtensa::MEMCTL, 97}, {Xtensa::ATOMCTL, 99},
178 {Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128},
179 {Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144},
180 {Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160},
181 {Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176},
182 {Xtensa::EPC1, 177}, {Xtensa::EPC2, 178},
183 {Xtensa::EPC3, 179}, {Xtensa::EPC4, 180},
184 {Xtensa::EPC5, 181}, {Xtensa::EPC6, 182},
185 {Xtensa::EPC7, 183}, {Xtensa::DEPC, 192},
186 {Xtensa::EPS2, 194}, {Xtensa::EPS3, 195},
187 {Xtensa::EPS4, 196}, {Xtensa::EPS5, 197},
188 {Xtensa::EPS6, 198}, {Xtensa::EPS7, 199},
189 {Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209},
190 {Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211},
191 {Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213},
192 {Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215},
193 {Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226},
194 {Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228},
195 {Xtensa::PS, 230}, {Xtensa::VECBASE, 231},
196 {Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233},
197 {Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235},
198 {Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237},
199 {Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240},
200 {Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242},
201 {Xtensa::MISC0, 244}, {Xtensa::MISC1, 245},
202 {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
203
204static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
205 uint64_t Address,
206 const MCDisassembler *Decoder) {
207 if (RegNo > 255)
208 return MCDisassembler::Fail;
209
210 Xtensa::RegisterAccessType RAType =
211 Inst.getOpcode() == Xtensa::WSR
212 ? Xtensa::REGISTER_WRITE
213 : (Inst.getOpcode() == Xtensa::RSR ? Xtensa::REGISTER_READ
214 : Xtensa::REGISTER_EXCHANGE);
215
216 for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
217 if (SRDecoderTable[i].RegNo == RegNo) {
218 MCPhysReg Reg = SRDecoderTable[i].Reg;
219
220 // Handle special case. The INTERRUPT/INTSET registers use the same
221 // encoding, but INTERRUPT used for read and INTSET for write.
222 if (Reg == Xtensa::INTERRUPT && RAType == Xtensa::REGISTER_WRITE) {
223 Reg = Xtensa::INTSET;
224 }
225
226 if (!Xtensa::checkRegister(
227 Reg, Decoder->getSubtargetInfo().getFeatureBits(), RAType))
228 return MCDisassembler::Fail;
229
230 Inst.addOperand(MCOperand::createReg(Reg));
231 return MCDisassembler::Success;
232 }
233 }
234
235 return MCDisassembler::Fail;
236}
237
238static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo,
239 uint64_t Address,
240 const void *Decoder) {
241 if (RegNo > 15)
242 return MCDisassembler::Fail;
243
244 MCPhysReg Reg = Xtensa::B0 + RegNo;
245 Inst.addOperand(MCOperand::createReg(Reg));
246 return MCDisassembler::Success;
247}
248
249static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
250 uint64_t Address, uint64_t Offset,
251 uint64_t InstSize, MCInst &MI,
252 const void *Decoder) {
253 const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
254 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
255 /*OpSize=*/0, InstSize);
256}
257
258static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm,
259 int64_t Address, const void *Decoder) {
260 assert(isUInt<18>(Imm) && "Invalid immediate");
261 Inst.addOperand(
262 MCOperand::createImm(SignExtend64<20>(Imm << 2) + (Address & 0x3)));
263 return MCDisassembler::Success;
264}
265
266static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm,
267 int64_t Address, const void *Decoder) {
268 assert(isUInt<18>(Imm) && "Invalid immediate");
269 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm)));
270 return MCDisassembler::Success;
271}
272
273static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm,
274 int64_t Address, const void *Decoder) {
275 switch (Inst.getOpcode()) {
276 case Xtensa::BEQZ:
277 case Xtensa::BGEZ:
278 case Xtensa::BLTZ:
279 case Xtensa::BNEZ:
280 assert(isUInt<12>(Imm) && "Invalid immediate");
281 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true,
282 Address, 0, 3, Inst, Decoder))
283 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
284 break;
285 default:
286 assert(isUInt<8>(Imm) && "Invalid immediate");
287 if (!tryAddingSymbolicOperand(SignExtend64<8>(Imm) + 4 + Address, true,
288 Address, 0, 3, Inst, Decoder))
289 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
290 }
291 return MCDisassembler::Success;
292}
293
294static DecodeStatus decodeLoopOperand(MCInst &Inst, uint64_t Imm,
295 int64_t Address, const void *Decoder) {
296
297 assert(isUInt<8>(Imm) && "Invalid immediate");
298 if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3, Inst,
299 Decoder))
300 Inst.addOperand(MCOperand::createImm(Imm));
301 return MCDisassembler::Success;
302}
303
304static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm,
305 int64_t Address, const void *Decoder) {
306
307 assert(isUInt<16>(Imm) && "Invalid immediate");
308 Inst.addOperand(MCOperand::createImm(
309 SignExtend64<17>((Imm << 2) + 0x40000 + (Address & 0x3))));
310 return MCDisassembler::Success;
311}
312
313static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
314 int64_t Address, const void *Decoder) {
315 assert(isUInt<8>(Imm) && "Invalid immediate");
316 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
317 return MCDisassembler::Success;
318}
319
320static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm,
321 int64_t Address,
322 const void *Decoder) {
323 assert(isUInt<8>(Imm) && "Invalid immediate");
324 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8)));
325 return MCDisassembler::Success;
326}
327
328static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm,
329 int64_t Address, const void *Decoder) {
330 assert(isUInt<12>(Imm) && "Invalid immediate");
331 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
332 return MCDisassembler::Success;
333}
334
335static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm,
336 int64_t Address, const void *Decoder) {
337 assert(isUInt<4>(Imm) && "Invalid immediate");
338 Inst.addOperand(MCOperand::createImm(Imm));
339 return MCDisassembler::Success;
340}
341
342static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm,
343 int64_t Address, const void *Decoder) {
344 assert(isUInt<5>(Imm) && "Invalid immediate");
345 Inst.addOperand(MCOperand::createImm(Imm));
346 return MCDisassembler::Success;
347}
348
349static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm,
350 int64_t Address, const void *Decoder) {
351 assert(isUInt<4>(Imm) && "Invalid immediate");
352 Inst.addOperand(MCOperand::createImm(Imm + 1));
353 return MCDisassembler::Success;
354}
355
356static DecodeStatus decodeImm1n_15Operand(MCInst &Inst, uint64_t Imm,
357 int64_t Address,
358 const void *Decoder) {
359 assert(isUInt<4>(Imm) && "Invalid immediate");
360 if (!Imm)
361 Inst.addOperand(MCOperand::createImm(-1));
362 else
363 Inst.addOperand(MCOperand::createImm(Imm));
364 return MCDisassembler::Success;
365}
366
367static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm,
368 int64_t Address,
369 const void *Decoder) {
370 assert(isUInt<7>(Imm) && "Invalid immediate");
371 if ((Imm & 0x60) == 0x60)
372 Inst.addOperand(MCOperand::createImm((~0x1f) | Imm));
373 else
374 Inst.addOperand(MCOperand::createImm(Imm));
375 return MCDisassembler::Success;
376}
377
378static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm,
379 int64_t Address, const void *Decoder) {
380 assert(isUInt<4>(Imm) && "Invalid immediate");
381 Inst.addOperand(MCOperand::createImm(Imm > 7 ? Imm - 16 : Imm));
382 return MCDisassembler::Success;
383}
384
385static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm,
386 int64_t Address,
387 const void *Decoder) {
388 assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");
389 Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm)));
390 return MCDisassembler::Success;
391}
392
393static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm,
394 int64_t Address,
395 const void *Decoder) {
396 assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate");
397 Inst.addOperand(MCOperand::createImm(Imm));
398 return MCDisassembler::Success;
399}
400
401static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
402 int64_t Address,
403 const void *Decoder) {
404 assert(isUInt<5>(Imm) && "Invalid immediate");
405 Inst.addOperand(MCOperand::createImm(32 - Imm));
406 return MCDisassembler::Success;
407}
408
409static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7,
410 8, 10, 12, 16, 32, 64, 128, 256};
411static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm,
412 int64_t Address, const void *Decoder) {
413 assert(isUInt<4>(Imm) && "Invalid immediate");
414
415 Inst.addOperand(MCOperand::createImm(TableB4const[Imm]));
416 return MCDisassembler::Success;
417}
418
419static int64_t TableB4constu[16] = {32768, 65536, 2, 3, 4, 5, 6, 7,
420 8, 10, 12, 16, 32, 64, 128, 256};
421static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm,
422 int64_t Address,
423 const void *Decoder) {
424 assert(isUInt<4>(Imm) && "Invalid immediate");
425
426 Inst.addOperand(MCOperand::createImm(TableB4constu[Imm]));
427 return MCDisassembler::Success;
428}
429
430static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm,
431 int64_t Address, const void *Decoder) {
432 assert(isUInt<4>(Imm) && "Invalid immediate");
433 Inst.addOperand(MCOperand::createImm(Imm + 7));
434 return MCDisassembler::Success;
435}
436
437static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm,
438 int64_t Address,
439 const void *Decoder) {
440 assert(isUInt<8>(Imm) && "Invalid immediate");
441 Inst.addOperand(MCOperand::createImm(Imm));
442 return MCDisassembler::Success;
443}
444
445static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm,
446 int64_t Address,
447 const void *Decoder) {
448 assert(isUInt<8>(Imm) && "Invalid immediate");
449 Inst.addOperand(MCOperand::createImm(Imm));
450 return MCDisassembler::Success;
451}
452
453static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm,
454 int64_t Address,
455 const void *Decoder) {
456 assert(isUInt<8>(Imm) && "Invalid immediate");
457 Inst.addOperand(MCOperand::createImm(Imm));
458 return MCDisassembler::Success;
459}
460
461static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm,
462 int64_t Address,
463 const void *Decoder) {
464 assert(isUInt<8>(Imm) && "Invalid immediate");
465 Inst.addOperand(MCOperand::createImm(Imm));
466 return MCDisassembler::Success;
467}
468
469static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm,
470 int64_t Address,
471 const void *Decoder) {
472 assert(isUInt<8>(Imm) && "Invalid immediate");
473 Inst.addOperand(MCOperand::createImm(Imm));
474 return MCDisassembler::Success;
475}
476
477static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, uint64_t Imm,
478 int64_t Address,
479 const void *Decoder) {
480 assert(isInt<8>(Imm) && "Invalid immediate");
481 if ((Imm & 0xf) != 0)
482 Inst.addOperand(MCOperand::createImm(Imm << 4));
483 else
484 Inst.addOperand(MCOperand::createImm(Imm));
485 return MCDisassembler::Success;
486}
487
488static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, uint64_t Imm,
489 int64_t Address,
490 const void *Decoder) {
491 assert(isInt<16>(Imm) && "Invalid immediate");
492 if ((Imm & 0x7) != 0)
493 Inst.addOperand(MCOperand::createImm(Imm << 3));
494 else
495 Inst.addOperand(MCOperand::createImm(Imm));
496 return MCDisassembler::Success;
497}
498
499static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, uint64_t Imm,
500 int64_t Address,
501 const void *Decoder) {
502 assert(isInt<16>(Imm) && "Invalid immediate");
503 if ((Imm & 0xf) != 0)
504 Inst.addOperand(MCOperand::createImm(Imm << 4));
505 else
506 Inst.addOperand(MCOperand::createImm(Imm));
507 return MCDisassembler::Success;
508}
509
510static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, uint64_t Imm,
511 int64_t Address,
512 const void *Decoder) {
513 assert(isInt<16>(Imm) && "Invalid immediate");
514 if ((Imm & 0x2) != 0)
515 Inst.addOperand(MCOperand::createImm(Imm << 2));
516 else
517 Inst.addOperand(MCOperand::createImm(Imm));
518 return MCDisassembler::Success;
519}
520
521static DecodeStatus decodeOffset_128_2Operand(MCInst &Inst, uint64_t Imm,
522 int64_t Address,
523 const void *Decoder) {
524 assert(isUInt<8>(Imm) && "Invalid immediate");
525 if ((Imm & 0x1) != 0)
526 Inst.addOperand(MCOperand::createImm(Imm << 1));
527 else
528 Inst.addOperand(MCOperand::createImm(Imm));
529 return MCDisassembler::Success;
530}
531
532static DecodeStatus decodeOffset_128_1Operand(MCInst &Inst, uint64_t Imm,
533 int64_t Address,
534 const void *Decoder) {
535 assert(isUInt<8>(Imm) && "Invalid immediate");
536 Inst.addOperand(MCOperand::createImm(Imm));
537 return MCDisassembler::Success;
538}
539
540static DecodeStatus decodeOffset_64_16Operand(MCInst &Inst, uint64_t Imm,
541 int64_t Address,
542 const void *Decoder) {
543 assert(isInt<16>(Imm) && "Invalid immediate");
544 if ((Imm & 0xf) != 0)
545 Inst.addOperand(MCOperand::createImm(Imm << 4));
546 else
547 Inst.addOperand(MCOperand::createImm(Imm));
548 return MCDisassembler::Success;
549}
550
551static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm,
552 int64_t Address, const void *Decoder) {
553 assert(isUInt<12>(Imm) && "Invalid immediate");
554 DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
555 Inst.addOperand(MCOperand::createImm((Imm >> 4) & 0xff));
556 return MCDisassembler::Success;
557}
558
559static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm,
560 int64_t Address, const void *Decoder) {
561 assert(isUInt<12>(Imm) && "Invalid immediate");
562 DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
563 Inst.addOperand(MCOperand::createImm((Imm >> 3) & 0x1fe));
564 return MCDisassembler::Success;
565}
566
567static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm,
568 int64_t Address, const void *Decoder) {
569 assert(isUInt<12>(Imm) && "Invalid immediate");
570 DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
571 Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3fc));
572 return MCDisassembler::Success;
573}
574
575static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm,
576 int64_t Address, const void *Decoder) {
577 assert(isUInt<8>(Imm) && "Invalid immediate");
578 DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
579 Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3c));
580 return MCDisassembler::Success;
581}
582
583/// Read two bytes from the ArrayRef and return 16 bit data sorted
584/// according to the given endianness.
585static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
586 uint64_t &Size, uint64_t &Insn,
587 bool IsLittleEndian) {
588 // We want to read exactly 2 Bytes of data.
589 if (Bytes.size() < 2) {
590 Size = 0;
591 return MCDisassembler::Fail;
592 }
593
594 if (!IsLittleEndian) {
595 report_fatal_error("Big-endian mode currently is not supported!");
596 } else {
597 Insn = (Bytes[1] << 8) | Bytes[0];
598 }
599
600 return MCDisassembler::Success;
601}
602
603/// Read three bytes from the ArrayRef and return 24 bit data
604static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
605 uint64_t &Size, uint64_t &Insn,
606 bool IsLittleEndian,
607 bool CheckTIE = false) {
608 // We want to read exactly 3 Bytes of data.
609 if (Bytes.size() < 3) {
610 Size = 0;
611 return MCDisassembler::Fail;
612 }
613
614 if (!IsLittleEndian) {
615 report_fatal_error("Big-endian mode currently is not supported!");
616 } else {
617 if (CheckTIE && (Bytes[0] & 0x8) != 0)
618 return MCDisassembler::Fail;
619 Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
620 }
621
622 return MCDisassembler::Success;
623}
624
625/// Read four bytes from the ArrayRef and return 32 bit data
626static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
627 uint64_t &Size, uint64_t &Insn,
628 bool IsLittleEndian) {
629 // We want to read exactly 4 Bytes of data.
630 if (Bytes.size() < 4) {
631 Size = 0;
632 return MCDisassembler::Fail;
633 }
634
635 if (!IsLittleEndian) {
636 report_fatal_error("Big-endian mode currently is not supported!");
637 } else {
638 if ((Bytes[0] & 0x8) == 0)
639 return MCDisassembler::Fail;
640 Insn =
641 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
642 }
643
644 return MCDisassembler::Success;
645}
646
647#include "XtensaGenDisassemblerTables.inc"
648
649DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
650 ArrayRef<uint8_t> Bytes,
651 uint64_t Address,
652 raw_ostream &CS) const {
653 uint64_t Insn;
654 DecodeStatus Result;
655
656 // Parse 16-bit instructions
657 if (hasDensity()) {
658 Result = readInstruction16(Bytes, Address, Size, Insn, IsLittleEndian);
659 if (Result == MCDisassembler::Fail)
660 return MCDisassembler::Fail;
661 LLVM_DEBUG(dbgs() << "Trying Xtensa 16-bit instruction table :\n");
662 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
663 if (Result != MCDisassembler::Fail) {
664 Size = 2;
665 return Result;
666 }
667 }
668
669 // Parse Core 24-bit instructions
670 Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian);
671 if (Result == MCDisassembler::Fail)
672 return MCDisassembler::Fail;
673 LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n");
674 Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI);
675 if (Result != MCDisassembler::Fail) {
676 Size = 3;
677 return Result;
678 }
679
680 if (hasESP32S3Ops()) {
681 // Parse ESP32S3 24-bit instructions
682 Result =
683 readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian, true);
684 if (Result != MCDisassembler::Fail) {
685 LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (24-bit opcodes):\n");
686 Result = decodeInstruction(DecoderTableESP32S324, MI, Insn, Address, this,
687 STI);
688 if (Result != MCDisassembler::Fail) {
689 Size = 3;
690 return Result;
691 }
692 }
693
694 // Parse ESP32S3 32-bit instructions
695 Result = readInstruction32(Bytes, Address, Size, Insn, IsLittleEndian);
696 if (Result == MCDisassembler::Fail)
697 return MCDisassembler::Fail;
698 LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (32-bit opcodes):\n");
699 Result =
700 decodeInstruction(DecoderTableESP32S332, MI, Insn, Address, this, STI);
701 if (Result != MCDisassembler::Fail) {
702 Size = 4;
703 return Result;
704 }
705 }
706
707 return Result;
708}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:534
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:535
Decoder
unsigned const MCDisassembler * Decoder
Definition AMDGPUDisassembler.cpp:536
readInstruction16
static bool readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:80
readInstruction32
static bool readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn)
Definition ARCDisassembler.cpp:52
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:855
Reg
Register Reg
Definition MachineSink.cpp:2127
T
#define T
Definition Mips16ISelLowering.cpp:282
isBranch
static bool isBranch(unsigned Opcode)
Definition R600InstrInfo.cpp:631
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:119
decodeMem16Operand
static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:559
decodeOffset_16_16Operand
static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:477
decodeOffset_128_2Operand
static DecodeStatus decodeOffset_128_2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:521
decodeSelect_2Operand
static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:437
DecodeMR23RegisterClass
static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:104
DecodeMRRegisterClass
static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:82
QRDecoderTable
static const unsigned QRDecoderTable[]
Definition XtensaDisassembler.cpp:115
decodeOffset_256_16Operand
static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:499
TableB4const
static int64_t TableB4const[16]
Definition XtensaDisassembler.cpp:409
decodeImm1n_15Operand
static DecodeStatus decodeImm1n_15Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:356
decodeOffset_128_1Operand
static DecodeStatus decodeOffset_128_1Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:532
decodeSelect_16Operand
static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:461
decodeOffset_256_4Operand
static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:510
DecodeFPRRegisterClass
static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:130
LLVMInitializeXtensaDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler()
Definition XtensaDisassembler.cpp:61
DecodeMR01RegisterClass
static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:93
decodeImm8_sh8Operand
static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:320
decodeImm8Operand
static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:313
decodeL32ROperand
static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:304
decodeEntry_Imm12OpValue
static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:393
decodeMem32nOperand
static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:575
decodeImm12Operand
static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:328
DecodeARRegisterClass
static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:71
tryAddingSymbolicOperand
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t InstSize, MCInst &MI, const void *Decoder)
Definition XtensaDisassembler.cpp:249
ARDecoderTable
const MCPhysReg ARDecoderTable[]
Definition XtensaDisassembler.cpp:66
decodeMem32Operand
static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:567
decodeUimm4Operand
static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:335
DecodeURRegisterClass
static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition XtensaDisassembler.cpp:141
decodeSelect_256Operand
static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:469
decodeImm64n_4nOperand
static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:385
decodeImm1_16Operand
static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:349
readInstruction24
static DecodeStatus readInstruction24(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian, bool CheckTIE=false)
Read three bytes from the ArrayRef and return 24 bit data.
Definition XtensaDisassembler.cpp:604
decodeMem8Operand
static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:551
DecodeQRRegisterClass
static DecodeStatus DecodeQRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:119
decodeImm7_22Operand
static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:430
decodeUimm5Operand
static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:342
decodeImm32n_95Operand
static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:367
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)
Read two bytes from the ArrayRef and return 16 bit data sorted according to the given endianness.
Definition XtensaDisassembler.cpp:585
decodeSelect_4Operand
static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:445
createXtensaDisassembler
static MCDisassembler * createXtensaDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition XtensaDisassembler.cpp:55
decodeOffset_256_8Operand
static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:488
decodeCallOperand
static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:258
decodeB4constuOperand
static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:421
decodeB4constOperand
static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:411
decodeImm8n_7Operand
static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:378
TableB4constu
static int64_t TableB4constu[16]
Definition XtensaDisassembler.cpp:419
DecodeSRRegisterClass
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition XtensaDisassembler.cpp:204
decodeOffset_64_16Operand
static DecodeStatus decodeOffset_64_16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:540
DecodeBRRegisterClass
static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:238
decodeShimm1_31Operand
static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:401
decodeSelect_8Operand
static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:453
decodeLoopOperand
static DecodeStatus decodeLoopOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:294
decodeJumpOperand
static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:266
decodeBranchOperand
static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition XtensaDisassembler.cpp:273
SRDecoderTable
const DecodeRegister SRDecoderTable[]
Definition XtensaDisassembler.cpp:168
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint64_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit data.
Definition XtensaDisassembler.cpp:626
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition MCDisassembler.cpp:28
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:272
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:188
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition MCSubtargetInfo.h:181
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:138
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint32_t
llvm::Xtensa::checkRegister
bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits, RegisterAccessType RA)
Definition XtensaMCTargetDesc.cpp:78
llvm::Xtensa::getUserRegister
MCRegister getUserRegister(unsigned Code, const MCRegisterInfo &MRI)
Definition XtensaMCTargetDesc.cpp:236
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::getTheXtensaTarget
Target & getTheXtensaTarget()
Definition XtensaTargetInfo.cpp:15
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:567
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:900
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