LLVM
15.0.0git
lib
Target
Hexagon
MCTargetDesc
HexagonBaseInfo.h
Go to the documentation of this file.
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//===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Hexagon target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#include "
HexagonDepITypes.h
"
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#include "
MCTargetDesc/HexagonMCTargetDesc.h
"
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namespace
llvm
{
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/// HexagonII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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namespace
HexagonII {
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unsigned
const
TypeCVI_FIRST
=
TypeCVI_4SLOT_MPY
;
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unsigned
const
TypeCVI_LAST
=
TypeCVI_ZW
;
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enum
AddrMode
{
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NoAddrMode
= 0,
// No addressing mode
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Absolute
= 1,
// Absolute addressing mode
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AbsoluteSet
= 2,
// Absolute set addressing mode
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BaseImmOffset
= 3,
// Indirect with offset
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BaseLongOffset
= 4,
// Indirect with long offset
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BaseRegOffset
= 5,
// Indirect with register offset
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PostInc
= 6
// Post increment addressing mode
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};
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enum
MemAccessSize
{
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NoMemAccess
= 0,
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ByteAccess
,
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HalfWordAccess
,
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WordAccess
,
45
DoubleWordAccess
,
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HVXVectorAccess
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};
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// MCInstrDesc TSFlags
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// *** Must match HexagonInstrFormat*.td ***
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enum
{
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// This 7-bit field describes the insn type.
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TypePos
= 0,
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TypeMask
= 0x7f,
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// Solo instructions.
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SoloPos
= 7,
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SoloMask
= 0x1,
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// Packed only with A or X-type instructions.
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SoloAXPos
= 8,
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SoloAXMask
= 0x1,
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// Only A-type instruction in first slot or nothing.
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RestrictSlot1AOKPos
= 9,
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RestrictSlot1AOKMask
= 0x1,
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// Predicated instructions.
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PredicatedPos
= 10,
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PredicatedMask
= 0x1,
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PredicatedFalsePos
= 11,
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PredicatedFalseMask
= 0x1,
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PredicatedNewPos
= 12,
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PredicatedNewMask
= 0x1,
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PredicateLatePos
= 13,
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PredicateLateMask
= 0x1,
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// New-Value consumer instructions.
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NewValuePos
= 14,
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NewValueMask
= 0x1,
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// New-Value producer instructions.
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hasNewValuePos
= 15,
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hasNewValueMask
= 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos
= 16,
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NewValueOpMask
= 0x7,
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// Stores that can become new-value stores.
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mayNVStorePos
= 19,
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mayNVStoreMask
= 0x1,
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// New-value store instructions.
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NVStorePos
= 20,
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NVStoreMask
= 0x1,
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// Loads that can become current-value loads.
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mayCVLoadPos
= 21,
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mayCVLoadMask
= 0x1,
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// Current-value load instructions.
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CVLoadPos
= 22,
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CVLoadMask
= 0x1,
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// Extendable insns.
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ExtendablePos
= 23,
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ExtendableMask
= 0x1,
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// Insns must be extended.
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ExtendedPos
= 24,
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ExtendedMask
= 0x1,
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// Which operand may be extended.
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ExtendableOpPos
= 25,
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ExtendableOpMask
= 0x7,
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// Signed or unsigned range.
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ExtentSignedPos
= 28,
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ExtentSignedMask
= 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos
= 29,
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ExtentBitsMask
= 0x1f,
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// Alignment power-of-two before extending operand.
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ExtentAlignPos
= 34,
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ExtentAlignMask
= 0x3,
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CofMax1Pos
= 36,
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CofMax1Mask
= 0x1,
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CofRelax1Pos
= 37,
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CofRelax1Mask
= 0x1,
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CofRelax2Pos
= 38,
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CofRelax2Mask
= 0x1,
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RestrictNoSlot1StorePos
= 39,
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RestrictNoSlot1StoreMask
= 0x1,
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// Addressing mode for load/store instructions.
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AddrModePos
= 42,
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AddrModeMask
= 0x7,
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// Access size for load/store instructions.
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MemAccessSizePos
= 45,
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MemAccesSizeMask
= 0xf,
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// Branch predicted taken.
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TakenPos
= 49,
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TakenMask
= 0x1,
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// Floating-point instructions.
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FPPos
= 50,
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FPMask
= 0x1,
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// New-Value producer-2 instructions.
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hasNewValuePos2
= 52,
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hasNewValueMask2
= 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos2
= 53,
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NewValueOpMask2
= 0x7,
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// Accumulator instructions.
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AccumulatorPos
= 56,
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AccumulatorMask
= 0x1,
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// Complex XU, prevent xu competition by preferring slot3
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PrefersSlot3Pos
= 57,
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PrefersSlot3Mask
= 0x1,
156
157
HasHvxTmpPos
= 60,
158
HasHvxTmpMask
= 0x1,
159
160
CVINewPos
= 62,
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CVINewMask
= 0x1,
162
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isCVIPos
= 63,
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isCVIMask
= 0x1,
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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// Hexagon specific MO operand flag mask.
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enum
HexagonMOTargetFlagVal
{
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// Hexagon-specific MachineOperand target flags.
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//
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// When changing these, make sure to update
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// getSerializableDirectMachineOperandTargetFlags and
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// getSerializableBitmaskMachineOperandTargetFlags if needed.
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MO_NO_FLAG
,
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/// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
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/// Used for computing a global address for PIC compilations
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MO_PCREL
,
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/// MO_GOT - Indicates a GOT-relative relocation
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MO_GOT
,
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// Low or high part of a symbol.
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MO_LO16
,
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MO_HI16
,
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// Offset from the base of the SDA.
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MO_GPREL
,
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192
// MO_GDGOT - indicates GOT relative relocation for TLS
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// GeneralDynamic method
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MO_GDGOT
,
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// MO_GDPLT - indicates PLT relative relocation for TLS
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// GeneralDynamic method
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MO_GDPLT
,
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200
// MO_IE - indicates non PIC relocation for TLS
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// Initial Executable method
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MO_IE
,
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// MO_IEGOT - indicates PIC relocation for TLS
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// Initial Executable method
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MO_IEGOT
,
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// MO_TPREL - indicates relocation for TLS
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// local Executable method
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MO_TPREL
,
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212
// HMOTF_ConstExtended
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// Addendum to above, indicates a const extended op
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// Can be used as a mask.
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HMOTF_ConstExtended
= 0x80,
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// Union of all bitmasks (currently only HMOTF_ConstExtended).
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MO_Bitmasks
=
HMOTF_ConstExtended
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};
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// Hexagon Sub-instruction classes.
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enum
SubInstructionGroup
{
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HSIG_None
= 0,
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HSIG_L1
,
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HSIG_L2
,
226
HSIG_S1
,
227
HSIG_S2
,
228
HSIG_A
,
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HSIG_Compound
230
};
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// Hexagon Compound classes.
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enum
CompoundGroup
{
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HCG_None
= 0,
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HCG_A
,
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HCG_B
,
237
HCG_C
238
};
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enum
InstParseBits
{
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INST_PARSE_MASK
= 0x0000c000,
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INST_PARSE_PACKET_END
= 0x0000c000,
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INST_PARSE_LOOP_END
= 0x00008000,
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INST_PARSE_NOT_END
= 0x00004000,
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INST_PARSE_DUPLEX
= 0x00000000,
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INST_PARSE_EXTENDER
= 0x00000000
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};
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enum
InstIClassBits
:
unsigned
{
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INST_ICLASS_MASK
= 0xf0000000,
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INST_ICLASS_EXTENDER
= 0x00000000,
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INST_ICLASS_J_1
= 0x10000000,
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INST_ICLASS_J_2
= 0x20000000,
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INST_ICLASS_LD_ST_1
= 0x30000000,
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INST_ICLASS_LD_ST_2
= 0x40000000,
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INST_ICLASS_J_3
= 0x50000000,
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INST_ICLASS_CR
= 0x60000000,
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INST_ICLASS_ALU32_1
= 0x70000000,
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INST_ICLASS_XTYPE_1
= 0x80000000,
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INST_ICLASS_LD
= 0x90000000,
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INST_ICLASS_ST
= 0xa0000000,
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INST_ICLASS_ALU32_2
= 0xb0000000,
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INST_ICLASS_XTYPE_2
= 0xc0000000,
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INST_ICLASS_XTYPE_3
= 0xd0000000,
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INST_ICLASS_XTYPE_4
= 0xe0000000,
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INST_ICLASS_ALU32_3
= 0xf0000000
267
};
268
269
LLVM_ATTRIBUTE_UNUSED
270
static
unsigned
getMemAccessSizeInBytes
(
MemAccessSize
S
) {
271
switch
(
S
) {
272
case
ByteAccess
:
return
1;
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case
HalfWordAccess
:
return
2;
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case
WordAccess
:
return
4;
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case
DoubleWordAccess
:
return
8;
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default
:
return
0;
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}
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}
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}
// end namespace HexagonII
280
281
}
// end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
llvm::HexagonII::INST_PARSE_PACKET_END
@ INST_PARSE_PACKET_END
Definition:
HexagonBaseInfo.h:242
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition:
HexagonBaseInfo.h:233
llvm::HexagonII::ExtentSignedMask
@ ExtentSignedMask
Definition:
HexagonBaseInfo.h:109
HexagonMCTargetDesc.h
llvm::HexagonII::RestrictSlot1AOKMask
@ RestrictSlot1AOKMask
Definition:
HexagonBaseInfo.h:64
llvm::HexagonII::CofRelax2Mask
@ CofRelax2Mask
Definition:
HexagonBaseInfo.h:122
llvm::HexagonII::HSIG_Compound
@ HSIG_Compound
Definition:
HexagonBaseInfo.h:229
llvm::HexagonII::HSIG_S2
@ HSIG_S2
Definition:
HexagonBaseInfo.h:227
llvm::HexagonII::MO_HI16
@ MO_HI16
Definition:
HexagonBaseInfo.h:187
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:17
llvm::HexagonII::SoloMask
@ SoloMask
Definition:
HexagonBaseInfo.h:58
llvm::HexagonII::INST_ICLASS_J_3
@ INST_ICLASS_J_3
Definition:
HexagonBaseInfo.h:256
llvm::HexagonII::PredicatedPos
@ PredicatedPos
Definition:
HexagonBaseInfo.h:67
llvm::HexagonII::hasNewValueMask2
@ hasNewValueMask2
Definition:
HexagonBaseInfo.h:144
llvm::HexagonII::MO_GDGOT
@ MO_GDGOT
Definition:
HexagonBaseInfo.h:194
llvm::HexagonII::HCG_C
@ HCG_C
Definition:
HexagonBaseInfo.h:237
llvm::HexagonII::CofRelax1Mask
@ CofRelax1Mask
Definition:
HexagonBaseInfo.h:120
llvm::HexagonII::INST_ICLASS_XTYPE_1
@ INST_ICLASS_XTYPE_1
Definition:
HexagonBaseInfo.h:259
llvm::HexagonII::MO_LO16
@ MO_LO16
Definition:
HexagonBaseInfo.h:186
llvm::HexagonII::mayNVStorePos
@ mayNVStorePos
Definition:
HexagonBaseInfo.h:86
llvm::HexagonII::INST_ICLASS_LD_ST_1
@ INST_ICLASS_LD_ST_1
Definition:
HexagonBaseInfo.h:254
llvm::HexagonII::hasNewValueMask
@ hasNewValueMask
Definition:
HexagonBaseInfo.h:81
llvm::HexagonII::InstIClassBits
InstIClassBits
Definition:
HexagonBaseInfo.h:249
llvm::HexagonII::NewValueOpMask
@ NewValueOpMask
Definition:
HexagonBaseInfo.h:84
llvm::HexagonII::HSIG_None
@ HSIG_None
Definition:
HexagonBaseInfo.h:223
llvm::HexagonII::AccumulatorMask
@ AccumulatorMask
Definition:
HexagonBaseInfo.h:151
llvm::HexagonII::PostInc
@ PostInc
Definition:
HexagonBaseInfo.h:37
llvm::HexagonII::INST_ICLASS_ALU32_1
@ INST_ICLASS_ALU32_1
Definition:
HexagonBaseInfo.h:258
llvm::HexagonII::CVLoadMask
@ CVLoadMask
Definition:
HexagonBaseInfo.h:96
llvm::HexagonII::ExtentBitsPos
@ ExtentBitsPos
Definition:
HexagonBaseInfo.h:111
llvm::HexagonII::TypeCVI_ZW
@ TypeCVI_ZW
Definition:
HexagonDepITypes.h:49
llvm::HexagonII::HCG_None
@ HCG_None
Definition:
HexagonBaseInfo.h:234
llvm::HexagonII::getMemAccessSizeInBytes
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
Definition:
HexagonBaseInfo.h:270
llvm::HexagonII::hasNewValuePos2
@ hasNewValuePos2
Definition:
HexagonBaseInfo.h:143
llvm::HexagonII::ExtentAlignPos
@ ExtentAlignPos
Definition:
HexagonBaseInfo.h:114
llvm::HexagonII::Absolute
@ Absolute
Definition:
HexagonBaseInfo.h:32
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition:
Compiler.h:182
llvm::HexagonII::AbsoluteSet
@ AbsoluteSet
Definition:
HexagonBaseInfo.h:33
llvm::HexagonII::HCG_A
@ HCG_A
Definition:
HexagonBaseInfo.h:235
llvm::HexagonII::MO_GOT
@ MO_GOT
MO_GOT - Indicates a GOT-relative relocation.
Definition:
HexagonBaseInfo.h:183
llvm::HexagonII::INST_ICLASS_XTYPE_2
@ INST_ICLASS_XTYPE_2
Definition:
HexagonBaseInfo.h:263
llvm::HexagonII::SoloAXMask
@ SoloAXMask
Definition:
HexagonBaseInfo.h:61
llvm::HexagonII::NVStorePos
@ NVStorePos
Definition:
HexagonBaseInfo.h:89
llvm::HexagonII::TypeMask
@ TypeMask
Definition:
HexagonBaseInfo.h:54
llvm::HexagonII::MemAccessSize
MemAccessSize
Definition:
HexagonBaseInfo.h:40
llvm::HexagonII::INST_ICLASS_LD_ST_2
@ INST_ICLASS_LD_ST_2
Definition:
HexagonBaseInfo.h:255
llvm::HexagonII::RestrictSlot1AOKPos
@ RestrictSlot1AOKPos
Definition:
HexagonBaseInfo.h:63
llvm::HexagonII::NoMemAccess
@ NoMemAccess
Definition:
HexagonBaseInfo.h:41
llvm::HexagonII::MO_IEGOT
@ MO_IEGOT
Definition:
HexagonBaseInfo.h:206
llvm::HexagonII::CofRelax1Pos
@ CofRelax1Pos
Definition:
HexagonBaseInfo.h:119
llvm::HexagonII::NVStoreMask
@ NVStoreMask
Definition:
HexagonBaseInfo.h:90
llvm::HexagonII::ByteAccess
@ ByteAccess
Definition:
HexagonBaseInfo.h:42
llvm::HexagonII::CofRelax2Pos
@ CofRelax2Pos
Definition:
HexagonBaseInfo.h:121
llvm::HexagonII::SubInstructionGroup
SubInstructionGroup
Definition:
HexagonBaseInfo.h:222
llvm::HexagonII::INST_PARSE_DUPLEX
@ INST_PARSE_DUPLEX
Definition:
HexagonBaseInfo.h:245
llvm::HexagonII::TakenMask
@ TakenMask
Definition:
HexagonBaseInfo.h:136
llvm::HexagonII::mayNVStoreMask
@ mayNVStoreMask
Definition:
HexagonBaseInfo.h:87
llvm::HexagonII::MemAccesSizeMask
@ MemAccesSizeMask
Definition:
HexagonBaseInfo.h:132
llvm::HexagonII::HCG_B
@ HCG_B
Definition:
HexagonBaseInfo.h:236
llvm::HexagonII::INST_ICLASS_ALU32_2
@ INST_ICLASS_ALU32_2
Definition:
HexagonBaseInfo.h:262
llvm::HexagonII::hasNewValuePos
@ hasNewValuePos
Definition:
HexagonBaseInfo.h:80
llvm::HexagonII::HalfWordAccess
@ HalfWordAccess
Definition:
HexagonBaseInfo.h:43
llvm::HexagonII::INST_ICLASS_ALU32_3
@ INST_ICLASS_ALU32_3
Definition:
HexagonBaseInfo.h:266
llvm::HexagonII::CVINewPos
@ CVINewPos
Definition:
HexagonBaseInfo.h:160
llvm::HexagonII::ExtendedMask
@ ExtendedMask
Definition:
HexagonBaseInfo.h:103
llvm::HexagonII::PrefersSlot3Pos
@ PrefersSlot3Pos
Definition:
HexagonBaseInfo.h:154
llvm::HexagonII::HSIG_S1
@ HSIG_S1
Definition:
HexagonBaseInfo.h:226
llvm::HexagonII::BaseLongOffset
@ BaseLongOffset
Definition:
HexagonBaseInfo.h:35
llvm::HexagonII::MO_PCREL
@ MO_PCREL
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
Definition:
HexagonBaseInfo.h:180
llvm::HexagonII::PredicatedNewPos
@ PredicatedNewPos
Definition:
HexagonBaseInfo.h:71
llvm::HexagonII::INST_ICLASS_CR
@ INST_ICLASS_CR
Definition:
HexagonBaseInfo.h:257
llvm::HexagonII::PrefersSlot3Mask
@ PrefersSlot3Mask
Definition:
HexagonBaseInfo.h:155
llvm::HexagonII::HasHvxTmpPos
@ HasHvxTmpPos
Definition:
HexagonBaseInfo.h:157
llvm::HexagonII::MO_NO_FLAG
@ MO_NO_FLAG
Definition:
HexagonBaseInfo.h:176
llvm::HexagonII::INST_ICLASS_MASK
@ INST_ICLASS_MASK
Definition:
HexagonBaseInfo.h:250
llvm::HexagonII::RestrictNoSlot1StorePos
@ RestrictNoSlot1StorePos
Definition:
HexagonBaseInfo.h:124
llvm::HexagonII::INST_PARSE_EXTENDER
@ INST_PARSE_EXTENDER
Definition:
HexagonBaseInfo.h:246
llvm::HexagonII::ExtentAlignMask
@ ExtentAlignMask
Definition:
HexagonBaseInfo.h:115
llvm::HexagonII::MO_TPREL
@ MO_TPREL
Definition:
HexagonBaseInfo.h:210
llvm::HexagonII::ExtendedPos
@ ExtendedPos
Definition:
HexagonBaseInfo.h:102
llvm::HexagonII::PredicatedFalsePos
@ PredicatedFalsePos
Definition:
HexagonBaseInfo.h:69
llvm::HexagonII::PredicateLateMask
@ PredicateLateMask
Definition:
HexagonBaseInfo.h:74
llvm::HexagonII::PredicatedFalseMask
@ PredicatedFalseMask
Definition:
HexagonBaseInfo.h:70
llvm::HexagonII::BaseRegOffset
@ BaseRegOffset
Definition:
HexagonBaseInfo.h:36
llvm::HexagonII::INST_ICLASS_XTYPE_4
@ INST_ICLASS_XTYPE_4
Definition:
HexagonBaseInfo.h:265
llvm::HexagonII::PredicatedNewMask
@ PredicatedNewMask
Definition:
HexagonBaseInfo.h:72
llvm::HexagonII::mayCVLoadMask
@ mayCVLoadMask
Definition:
HexagonBaseInfo.h:93
llvm::HexagonII::HexagonMOTargetFlagVal
HexagonMOTargetFlagVal
Definition:
HexagonBaseInfo.h:170
llvm::HexagonII::SoloPos
@ SoloPos
Definition:
HexagonBaseInfo.h:57
llvm::HexagonII::INST_PARSE_MASK
@ INST_PARSE_MASK
Definition:
HexagonBaseInfo.h:241
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition:
HexagonBaseInfo.h:34
llvm::HexagonII::RestrictNoSlot1StoreMask
@ RestrictNoSlot1StoreMask
Definition:
HexagonBaseInfo.h:125
llvm::HexagonII::DoubleWordAccess
@ DoubleWordAccess
Definition:
HexagonBaseInfo.h:45
llvm::HexagonII::MemAccessSizePos
@ MemAccessSizePos
Definition:
HexagonBaseInfo.h:131
llvm::HexagonII::HSIG_L1
@ HSIG_L1
Definition:
HexagonBaseInfo.h:224
HexagonDepITypes.h
llvm::HexagonII::HMOTF_ConstExtended
@ HMOTF_ConstExtended
Definition:
HexagonBaseInfo.h:215
llvm::HexagonII::CofMax1Pos
@ CofMax1Pos
Definition:
HexagonBaseInfo.h:117
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition:
README.txt:210
llvm::HexagonII::FPMask
@ FPMask
Definition:
HexagonBaseInfo.h:140
llvm::HexagonII::AddrMode
AddrMode
Definition:
HexagonBaseInfo.h:30
llvm::HexagonII::TypeCVI_4SLOT_MPY
@ TypeCVI_4SLOT_MPY
Definition:
HexagonDepITypes.h:24
llvm::HexagonII::CVLoadPos
@ CVLoadPos
Definition:
HexagonBaseInfo.h:95
llvm::HexagonII::HSIG_L2
@ HSIG_L2
Definition:
HexagonBaseInfo.h:225
llvm::HexagonII::PredicateLatePos
@ PredicateLatePos
Definition:
HexagonBaseInfo.h:73
llvm::HexagonII::isCVIPos
@ isCVIPos
Definition:
HexagonBaseInfo.h:163
llvm::HexagonII::NewValueOpPos2
@ NewValueOpPos2
Definition:
HexagonBaseInfo.h:146
llvm::HexagonII::TypeCVI_FIRST
const unsigned TypeCVI_FIRST
Definition:
HexagonBaseInfo.h:27
llvm::HexagonII::CofMax1Mask
@ CofMax1Mask
Definition:
HexagonBaseInfo.h:118
llvm::HexagonII::ExtentBitsMask
@ ExtentBitsMask
Definition:
HexagonBaseInfo.h:112
llvm::HexagonII::HasHvxTmpMask
@ HasHvxTmpMask
Definition:
HexagonBaseInfo.h:158
llvm::HexagonII::ExtendablePos
@ ExtendablePos
Definition:
HexagonBaseInfo.h:99
llvm::HexagonII::ExtendableOpPos
@ ExtendableOpPos
Definition:
HexagonBaseInfo.h:105
llvm::HexagonII::INST_PARSE_NOT_END
@ INST_PARSE_NOT_END
Definition:
HexagonBaseInfo.h:244
llvm::HexagonII::INST_ICLASS_EXTENDER
@ INST_ICLASS_EXTENDER
Definition:
HexagonBaseInfo.h:251
llvm::HexagonII::MO_IE
@ MO_IE
Definition:
HexagonBaseInfo.h:202
llvm::HexagonII::NoAddrMode
@ NoAddrMode
Definition:
HexagonBaseInfo.h:31
llvm::HexagonII::MO_Bitmasks
@ MO_Bitmasks
Definition:
HexagonBaseInfo.h:218
llvm::HexagonII::ExtentSignedPos
@ ExtentSignedPos
Definition:
HexagonBaseInfo.h:108
llvm::HexagonII::CVINewMask
@ CVINewMask
Definition:
HexagonBaseInfo.h:161
llvm::HexagonII::AddrModePos
@ AddrModePos
Definition:
HexagonBaseInfo.h:128
llvm::HexagonII::AddrModeMask
@ AddrModeMask
Definition:
HexagonBaseInfo.h:129
llvm::HexagonII::TakenPos
@ TakenPos
Definition:
HexagonBaseInfo.h:135
llvm::HexagonII::INST_ICLASS_LD
@ INST_ICLASS_LD
Definition:
HexagonBaseInfo.h:260
llvm::HexagonII::MO_GDPLT
@ MO_GDPLT
Definition:
HexagonBaseInfo.h:198
llvm::HexagonII::NewValuePos
@ NewValuePos
Definition:
HexagonBaseInfo.h:77
llvm::HexagonII::INST_ICLASS_J_1
@ INST_ICLASS_J_1
Definition:
HexagonBaseInfo.h:252
llvm::HexagonII::isCVIMask
@ isCVIMask
Definition:
HexagonBaseInfo.h:164
llvm::HexagonII::INST_PARSE_LOOP_END
@ INST_PARSE_LOOP_END
Definition:
HexagonBaseInfo.h:243
llvm::HexagonII::ExtendableMask
@ ExtendableMask
Definition:
HexagonBaseInfo.h:100
llvm::HexagonII::WordAccess
@ WordAccess
Definition:
HexagonBaseInfo.h:44
llvm::HexagonII::AccumulatorPos
@ AccumulatorPos
Definition:
HexagonBaseInfo.h:150
llvm::HexagonII::HSIG_A
@ HSIG_A
Definition:
HexagonBaseInfo.h:228
llvm::HexagonII::INST_ICLASS_XTYPE_3
@ INST_ICLASS_XTYPE_3
Definition:
HexagonBaseInfo.h:264
llvm::HexagonII::ExtendableOpMask
@ ExtendableOpMask
Definition:
HexagonBaseInfo.h:106
llvm::HexagonII::SoloAXPos
@ SoloAXPos
Definition:
HexagonBaseInfo.h:60
llvm::HexagonII::TypeCVI_LAST
const unsigned TypeCVI_LAST
Definition:
HexagonBaseInfo.h:28
llvm::HexagonII::PredicatedMask
@ PredicatedMask
Definition:
HexagonBaseInfo.h:68
llvm::HexagonII::FPPos
@ FPPos
Definition:
HexagonBaseInfo.h:139
llvm::HexagonII::NewValueOpPos
@ NewValueOpPos
Definition:
HexagonBaseInfo.h:83
llvm::HexagonII::TypePos
@ TypePos
Definition:
HexagonBaseInfo.h:53
llvm::HexagonII::INST_ICLASS_J_2
@ INST_ICLASS_J_2
Definition:
HexagonBaseInfo.h:253
llvm::HexagonII::MO_GPREL
@ MO_GPREL
Definition:
HexagonBaseInfo.h:190
llvm::HexagonII::mayCVLoadPos
@ mayCVLoadPos
Definition:
HexagonBaseInfo.h:92
llvm::HexagonII::NewValueMask
@ NewValueMask
Definition:
HexagonBaseInfo.h:78
llvm::HexagonII::INST_ICLASS_ST
@ INST_ICLASS_ST
Definition:
HexagonBaseInfo.h:261
llvm::HexagonII::NewValueOpMask2
@ NewValueOpMask2
Definition:
HexagonBaseInfo.h:147
llvm::HexagonII::InstParseBits
InstParseBits
Definition:
HexagonBaseInfo.h:240
llvm::HexagonII::HVXVectorAccess
@ HVXVectorAccess
Definition:
HexagonBaseInfo.h:46
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