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27 #define DEBUG_TYPE "instructionselector"
32 : Renderers(MaxRenderers), MIs() {}
41 return VRegVal->Value.getSExtValue() ==
Value;
51 if (RootI->
getOpcode() != TargetOpcode::G_PTR_ADD)
56 if (RHSI->
getOpcode() != TargetOpcode::G_CONSTANT)
69 return !
MI.mayLoadOrStore() && !
MI.mayRaiseFPException() &&
70 !
MI.hasUnmodeledSideEffects() &&
MI.implicit_operands().empty();
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
Register getReg() const
getReg - Returns the register number.
MatcherState(unsigned MaxRenderers)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
self_iterator getIterator()
const MachineBasicBlock * getParent() const
unsigned const MachineRegisterInfo * MRI
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
LLVM Value Representation.
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...