LLVM  14.0.0git
MachineCombinerPattern.h
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1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
2 // combiner ------*- C++ -*-===//
3 //
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines instruction pattern supported by combiner
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
16 
17 namespace llvm {
18 
19 /// These are instruction patterns matched by the machine combiner pass.
21  // These are commutative variants for reassociating a computation chain. See
22  // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
27 
28  // These are patterns matched by the PowerPC to reassociate FMA chains.
31 
32  // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
33  // reduce register pressure.
36 
37  // These are multiply-add patterns matched by the AArch64 machine combiner.
50  // NEON integers vectors
63 
76 
85 
94 
95  // Floating Point
100  FMULADDS_OP1,
101  FMULADDS_OP2,
102  FMULSUBS_OP1,
103  FMULSUBS_OP2,
104  FMULADDD_OP1,
105  FMULADDD_OP2,
106  FMULSUBD_OP1,
107  FMULSUBD_OP2,
157 };
158 
159 } // end namespace llvm
160 
161 #endif
llvm::MachineCombinerPattern::MULSUBv2i32_indexed_OP2
@ MULSUBv2i32_indexed_OP2
llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP1
@ FMLAv4i32_indexed_OP1
llvm::MachineCombinerPattern::FMLAv8i16_indexed_OP1
@ FMLAv8i16_indexed_OP1
llvm::MachineCombinerPattern::MULSUBv8i8_OP2
@ MULSUBv8i8_OP2
llvm::MachineCombinerPattern::MULSUBv4i32_indexed_OP1
@ MULSUBv4i32_indexed_OP1
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineCombinerPattern::MULADDv4i16_indexed_OP1
@ MULADDv4i16_indexed_OP1
llvm::MachineCombinerPattern::FMULADDD_OP2
@ FMULADDD_OP2
llvm::MachineCombinerPattern::MULADDv4i32_OP2
@ MULADDv4i32_OP2
llvm::MachineCombinerPattern::FMULSUBH_OP1
@ FMULSUBH_OP1
llvm::MachineCombinerPattern::MULSUBv8i8_OP1
@ MULSUBv8i8_OP1
llvm::MachineCombinerPattern::MULADDv4i16_indexed_OP2
@ MULADDv4i16_indexed_OP2
llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP2
@ FMLAv1i32_indexed_OP2
llvm::MachineCombinerPattern::FMULSUBS_OP1
@ FMULSUBS_OP1
llvm::MachineCombinerPattern::MULADDv2i32_OP1
@ MULADDv2i32_OP1
llvm::MachineCombinerPattern::MULADDX_OP1
@ MULADDX_OP1
llvm::MachineCombinerPattern::FMULADDS_OP2
@ FMULADDS_OP2
llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP2
@ FMLAv4i32_indexed_OP2
llvm::MachineCombinerPattern::MULSUBW_OP1
@ MULSUBW_OP1
llvm::MachineCombinerPattern::MULSUBv16i8_OP2
@ MULSUBv16i8_OP2
llvm::MachineCombinerPattern::FMLSv2f64_OP2
@ FMLSv2f64_OP2
llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP2
@ FMLAv2i32_indexed_OP2
llvm::MachineCombinerPattern::FMLSv2f64_OP1
@ FMLSv2f64_OP1
llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP1
@ FMLSv4i32_indexed_OP1
llvm::MachineCombinerPattern::REASSOC_XY_BAC
@ REASSOC_XY_BAC
llvm::MachineCombinerPattern::FMLSv2f32_OP2
@ FMLSv2f32_OP2
llvm::MachineCombinerPattern::MULADDv8i16_OP1
@ MULADDv8i16_OP1
llvm::MachineCombinerPattern::MULSUBv2i32_indexed_OP1
@ MULSUBv2i32_indexed_OP1
llvm::MachineCombinerPattern::FMLSv2f32_OP1
@ FMLSv2f32_OP1
llvm::MachineCombinerPattern::MULADDv8i8_OP1
@ MULADDv8i8_OP1
llvm::MachineCombinerPattern::FMLSv4f16_OP1
@ FMLSv4f16_OP1
llvm::MachineCombinerPattern::MULADDv8i8_OP2
@ MULADDv8i8_OP2
llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP1
@ FMLAv1i32_indexed_OP1
llvm::MachineCombinerPattern::FMLAv8f16_OP2
@ FMLAv8f16_OP2
llvm::MachineCombinerPattern::FMLAv2f64_OP2
@ FMLAv2f64_OP2
llvm::MachineCombinerPattern::REASSOC_AX_YB
@ REASSOC_AX_YB
llvm::MachineCombinerPattern::MULSUBXI_OP1
@ MULSUBXI_OP1
llvm::MachineCombinerPattern::FMLAv4f16_OP2
@ FMLAv4f16_OP2
llvm::MachineCombinerPattern::MULSUBv2i32_OP2
@ MULSUBv2i32_OP2
llvm::MachineCombinerPattern::FMULADDH_OP1
@ FMULADDH_OP1
llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP2
@ FMLSv4i32_indexed_OP2
llvm::MachineCombinerPattern::FMLSv4f32_OP2
@ FMLSv4f32_OP2
llvm::MachineCombinerPattern::REASSOC_XMM_AMM_BMM
@ REASSOC_XMM_AMM_BMM
llvm::MachineCombinerPattern::FMLAv8i16_indexed_OP2
@ FMLAv8i16_indexed_OP2
llvm::MachineCombinerPattern::MULADDv2i32_OP2
@ MULADDv2i32_OP2
llvm::MachineCombinerPattern::MULSUBv4i32_indexed_OP2
@ MULSUBv4i32_indexed_OP2
llvm::MachineCombinerPattern::FMLSv4f32_OP1
@ FMLSv4f32_OP1
llvm::MachineCombinerPattern::MULSUBW_OP2
@ MULSUBW_OP2
llvm::MachineCombinerPattern::MULSUBWI_OP1
@ MULSUBWI_OP1
llvm::MachineCombinerPattern::FMLSv8i16_indexed_OP2
@ FMLSv8i16_indexed_OP2
llvm::MachineCombinerPattern::MULADDv4i32_indexed_OP2
@ MULADDv4i32_indexed_OP2
llvm::MachineCombinerPattern::FNMULSUBH_OP1
@ FNMULSUBH_OP1
llvm::MachineCombinerPattern::MULSUBv4i32_OP1
@ MULSUBv4i32_OP1
llvm::MachineCombinerPattern::MULSUBv4i16_indexed_OP2
@ MULSUBv4i16_indexed_OP2
llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP2
@ FMLAv1i64_indexed_OP2
llvm::MachineCombinerPattern::FMLAv4f16_OP1
@ FMLAv4f16_OP1
llvm::MachineCombinerPattern::FMULSUBD_OP2
@ FMULSUBD_OP2
llvm::MachineCombinerPattern::MULADDv4i16_OP2
@ MULADDv4i16_OP2
llvm::MachineCombinerPattern::FMLSv8f16_OP1
@ FMLSv8f16_OP1
llvm::MachineCombinerPattern::FMLSv8f16_OP2
@ FMLSv8f16_OP2
llvm::MachineCombinerPattern::MULSUBX_OP2
@ MULSUBX_OP2
llvm::MachineCombinerPattern::FMLAv4f32_OP2
@ FMLAv4f32_OP2
llvm::MachineCombinerPattern::FMLAv2f32_OP1
@ FMLAv2f32_OP1
llvm::MachineCombinerPattern::MULADDv4i32_indexed_OP1
@ MULADDv4i32_indexed_OP1
llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP1
@ FMLSv2i32_indexed_OP1
llvm::MachineCombinerPattern::MULSUBv2i32_OP1
@ MULSUBv2i32_OP1
llvm::MachineCombinerPattern::FMLAv8f16_OP1
@ FMLAv8f16_OP1
llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP2
@ FMLSv2i32_indexed_OP2
llvm::MachineCombinerPattern::FMLAv4i16_indexed_OP2
@ FMLAv4i16_indexed_OP2
llvm::MachineCombinerPattern::FMULSUBD_OP1
@ FMULSUBD_OP1
llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP1
@ FMLAv2i32_indexed_OP1
llvm::MachineCombinerPattern::MULADDv4i16_OP1
@ MULADDv4i16_OP1
llvm::MachineCombinerPattern::FNMULSUBS_OP1
@ FNMULSUBS_OP1
llvm::MachineCombinerPattern::FMLAv4f32_OP1
@ FMLAv4f32_OP1
llvm::MachineCombinerPattern::MULADDv16i8_OP1
@ MULADDv16i8_OP1
llvm::MachineCombinerPattern::MULSUBv4i16_indexed_OP1
@ MULSUBv4i16_indexed_OP1
llvm::MachineCombinerPattern::FMULADDD_OP1
@ FMULADDD_OP1
llvm::MachineCombinerPattern::FMLSv4f16_OP2
@ FMLSv4f16_OP2
llvm::MachineCombinerPattern::FMULSUBH_OP2
@ FMULSUBH_OP2
llvm::MachineCombinerPattern::MULSUBv4i16_OP2
@ MULSUBv4i16_OP2
llvm::MachineCombinerPattern::REASSOC_AX_BY
@ REASSOC_AX_BY
llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP1
@ FMLAv1i64_indexed_OP1
llvm::MachineCombinerPattern::REASSOC_XY_BCA
@ REASSOC_XY_BCA
llvm::MachineCombinerPattern::MULSUBv8i16_OP2
@ MULSUBv8i16_OP2
llvm::MachineCombinerPattern::MULSUBv4i16_OP1
@ MULSUBv4i16_OP1
llvm::MachineCombinerPattern::FMLAv4i16_indexed_OP1
@ FMLAv4i16_indexed_OP1
llvm::MachineCombinerPattern::MULADDv8i16_indexed_OP1
@ MULADDv8i16_indexed_OP1
llvm::MachineCombinerPattern::MULADDv8i16_indexed_OP2
@ MULADDv8i16_indexed_OP2
llvm::MachineCombinerPattern::FMULADDS_OP1
@ FMULADDS_OP1
llvm::MachineCombinerPattern::MULADDv2i32_indexed_OP2
@ MULADDv2i32_indexed_OP2
llvm::MachineCombinerPattern::MULSUBv8i16_OP1
@ MULSUBv8i16_OP1
llvm::MachineCombinerPattern::REASSOC_XY_AMM_BMM
@ REASSOC_XY_AMM_BMM
llvm::MachineCombinerPattern::MULADDv2i32_indexed_OP1
@ MULADDv2i32_indexed_OP1
llvm::MachineCombinerPattern::MULSUBv8i16_indexed_OP1
@ MULSUBv8i16_indexed_OP1
llvm::MachineCombinerPattern::FMULADDH_OP2
@ FMULADDH_OP2
llvm::MachineCombinerPattern::FMLSv8i16_indexed_OP1
@ FMLSv8i16_indexed_OP1
llvm::MachineCombinerPattern::MULADDv4i32_OP1
@ MULADDv4i32_OP1
llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP2
@ FMLAv2i64_indexed_OP2
llvm::MachineCombinerPattern::MULSUBv8i16_indexed_OP2
@ MULSUBv8i16_indexed_OP2
llvm::MachineCombinerPattern::MULSUBv16i8_OP1
@ MULSUBv16i8_OP1
llvm::MachineCombinerPattern::FMLAv2f64_OP1
@ FMLAv2f64_OP1
llvm::MachineCombinerPattern::MULADDW_OP2
@ MULADDW_OP2
llvm::MachineCombinerPattern::FMLAv2f32_OP2
@ FMLAv2f32_OP2
llvm::MachineCombinerPattern::REASSOC_XA_BY
@ REASSOC_XA_BY
llvm::MachineCombinerPattern::FMLSv1i64_indexed_OP2
@ FMLSv1i64_indexed_OP2
llvm::MachineCombinerPattern::FNMULSUBD_OP1
@ FNMULSUBD_OP1
llvm::MachineCombinerPattern::MULSUBX_OP1
@ MULSUBX_OP1
llvm::MachineCombinerPattern::MULSUBv4i32_OP2
@ MULSUBv4i32_OP2
llvm::MachineCombinerPattern::FMLSv4i16_indexed_OP1
@ FMLSv4i16_indexed_OP1
llvm::MachineCombinerPattern::REASSOC_XA_YB
@ REASSOC_XA_YB
llvm::MachineCombinerPattern::MULADDX_OP2
@ MULADDX_OP2
llvm::MachineCombinerPattern::MULADDv16i8_OP2
@ MULADDv16i8_OP2
llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP1
@ FMLSv2i64_indexed_OP1
llvm::MachineCombinerPattern::MULADDXI_OP1
@ MULADDXI_OP1
llvm::MachineCombinerPattern::FMLSv1i32_indexed_OP2
@ FMLSv1i32_indexed_OP2
llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP1
@ FMLAv2i64_indexed_OP1
llvm::MachineCombinerPattern::MULADDW_OP1
@ MULADDW_OP1
llvm::MachineCombinerPattern::FMLSv4i16_indexed_OP2
@ FMLSv4i16_indexed_OP2
llvm::MachineCombinerPattern::MULADDv8i16_OP2
@ MULADDv8i16_OP2
llvm::MachineCombinerPattern::FMULSUBS_OP2
@ FMULSUBS_OP2
llvm::MachineCombinerPattern::MULADDWI_OP1
@ MULADDWI_OP1
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP2
@ FMLSv2i64_indexed_OP2