#include "NVPTX.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/AtomicOrdering.h"

Classes
class	llvm::NVPTXTargetLowering

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::NVPTXISD

Enumerations

enum llvm::NVPTXISD::NodeType : unsigned {
llvm::NVPTXISD::FIRST_NUMBER = ISD::BUILTIN_OP_END , llvm::NVPTXISD::RET_GLUE , llvm::NVPTXISD::DeclareScalarParam , llvm::NVPTXISD::DeclareArrayParam ,
llvm::NVPTXISD::CALL , llvm::NVPTXISD::MoveParam , llvm::NVPTXISD::CallPrototype , llvm::NVPTXISD::ProxyReg ,
llvm::NVPTXISD::FSHL_CLAMP , llvm::NVPTXISD::FSHR_CLAMP , llvm::NVPTXISD::MUL_WIDE_SIGNED , llvm::NVPTXISD::MUL_WIDE_UNSIGNED ,
llvm::NVPTXISD::SETP_F16X2 , llvm::NVPTXISD::SETP_BF16X2 , llvm::NVPTXISD::BFI , llvm::NVPTXISD::PRMT ,
llvm::NVPTXISD::BUILD_VECTOR , llvm::NVPTXISD::UNPACK_VECTOR , llvm::NVPTXISD::FCOPYSIGN , llvm::NVPTXISD::FMAXNUM3 ,
llvm::NVPTXISD::FMINNUM3 , llvm::NVPTXISD::FMAXIMUM3 , llvm::NVPTXISD::FMINIMUM3 , llvm::NVPTXISD::DYNAMIC_STACKALLOC ,
llvm::NVPTXISD::STACKRESTORE , llvm::NVPTXISD::STACKSAVE , llvm::NVPTXISD::BrxStart , llvm::NVPTXISD::BrxItem ,
llvm::NVPTXISD::BrxEnd , llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED , llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X , llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y ,
llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z , llvm::NVPTXISD::FIRST_MEMORY_OPCODE , llvm::NVPTXISD::ATOMIC_CMP_SWAP_B128 = FIRST_MEMORY_OPCODE , llvm::NVPTXISD::ATOMIC_SWAP_B128 ,
llvm::NVPTXISD::LoadV2 , llvm::NVPTXISD::LoadV4 , llvm::NVPTXISD::LoadV8 , llvm::NVPTXISD::LDUV2 ,
llvm::NVPTXISD::LDUV4 , llvm::NVPTXISD::StoreV2 , llvm::NVPTXISD::StoreV4 , llvm::NVPTXISD::StoreV8 ,
llvm::NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2 , llvm::NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2 ,
llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2 , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2 ,
llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT , llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT ,
llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2 , llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2 ,
llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2 , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT ,
llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1 , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2 , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT , llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT ,
llvm::NVPTXISD::LAST_MEMORY_OPCODE
}

Classes

Namespaces

Enumerations