LLVM 17.0.0git
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1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
17#include "NVPTX.h"
21namespace llvm {
22namespace NVPTXISD {
23enum NodeType : unsigned {
24 // Start the numbering from where ISD NodeType finishes.
64 LDGV2, // LDG.v2
65 LDGV4, // LDG.v4
66 LDUV2, // LDU.v2
67 LDUV4, // LDU.v4
76 StoreParamS32, // to sext and store a <32bit value, not used currently
77 StoreParamU32, // to zext and store a <32bit value, not used currently
82 // Texture intrinsics
252 // Surface intrinsics
435class NVPTXSubtarget;
438// TargetLowering Implementation
443 const NVPTXSubtarget &STI);
444 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
448 const char *getTargetNodeName(unsigned Opcode) const override;
451 MachineFunction &MF,
452 unsigned Intrinsic) const override;
454 /// getFunctionParamOptimizedAlign - since function arguments are passed via
455 /// .param space, we may want to increase their alignment in a way that
456 /// ensures that we can effectively vectorize their loads & stores. We can
457 /// increase alignment only if the function has internal or has private
458 /// linkage as for other linkage types callers may already rely on default
459 /// alignment. To allow using 128-bit vectorized loads/stores, this function
460 /// ensures that alignment is 16 or greater.
462 const DataLayout &DL) const;
464 /// Helper for computing alignment of a device function byval parameter.
466 Align InitialAlign,
467 const DataLayout &DL) const;
469 /// isLegalAddressingMode - Return true if the addressing mode represented
470 /// by AM is legal for this target, for a load/store of the specified type
471 /// Used to guide target specific optimizations, like loop strength
472 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
473 /// address mode (CodeGenPrepare.cpp)
474 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
475 unsigned AS,
476 Instruction *I = nullptr) const override;
478 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
479 // Truncating 64-bit to 32-bit is free in SASS.
480 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
481 return false;
482 return SrcTy->getPrimitiveSizeInBits() == 64 &&
483 DstTy->getPrimitiveSizeInBits() == 32;
484 }
487 EVT VT) const override {
488 if (VT.isVector())
490 return MVT::i1;
491 }
493 ConstraintType getConstraintType(StringRef Constraint) const override;
494 std::pair<unsigned, const TargetRegisterClass *>
496 StringRef Constraint, MVT VT) const override;
499 bool isVarArg,
501 const SDLoc &dl, SelectionDAG &DAG,
502 SmallVectorImpl<SDValue> &InVals) const override;
504 SDValue LowerCall(CallLoweringInfo &CLI,
505 SmallVectorImpl<SDValue> &InVals) const override;
507 std::string
508 getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
509 const SmallVectorImpl<ISD::OutputArg> &, MaybeAlign retAlignment,
510 std::optional<std::pair<unsigned, const APInt &>> VAInfo,
511 const CallBase &CB, unsigned UniqueCallSite) const;
513 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
515 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
516 SelectionDAG &DAG) const override;
518 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
519 std::vector<SDValue> &Ops,
520 SelectionDAG &DAG) const override;
524 // PTX always uses 32-bit shift amounts
525 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
526 return MVT::i32;
527 }
530 getPreferredVectorAction(MVT VT) const override;
532 // Get the degree of precision we want from 32-bit floating point division
533 // operations.
534 //
535 // 0 - Use ptx div.approx
536 // 1 - Use ptx.div.full (approximate, but less so than div.approx)
537 // 2 - Use IEEE-compliant div instructions, if available.
538 int getDivF32Level() const;
540 // Get whether we should use a precise or approximate 32-bit floating point
541 // sqrt instruction.
542 bool usePrecSqrtF32() const;
544 // Get whether we should use instructions that flush floating-point denormals
545 // to sign-preserving zero.
546 bool useF32FTZ(const MachineFunction &MF) const;
549 int &ExtraSteps, bool &UseOneConst,
550 bool Reciprocal) const override;
552 unsigned combineRepeatedFPDivisors() const override { return 2; }
554 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
555 bool allowUnsafeFPMath(MachineFunction &MF) const;
558 EVT) const override {
559 return true;
560 }
562 bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
564 // The default is to transform llvm.ctlz(x, false) (where false indicates that
565 // x == 0 is not undefined behavior) into a branch that checks whether x is 0
566 // and avoids calling ctlz in that case. We have a dedicated ctlz
567 // instruction, so we say that ctlz is cheap to speculate.
568 bool isCheapToSpeculateCtlz(Type *Ty) const override { return true; }
572 }
576 }
579 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
582 const NVPTXSubtarget &STI; // cache the subtarget here
583 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
585 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
586 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
589 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
590 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
591 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
596 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
597 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
598 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
600 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
601 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
603 SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
605 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
606 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
608 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
609 SelectionDAG &DAG) const override;
610 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
612 Align getArgumentAlignment(SDValue Callee, const CallBase *CB, Type *Ty,
613 unsigned Idx, const DataLayout &DL) const;
615} // namespace llvm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1184
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
Machine Value Type.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const NVPTXTargetMachine * nvTM
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
bool useF32FTZ(const MachineFunction &MF) const
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, std::optional< std::pair< unsigned, const APInt & > > VAInfo, const CallBase &CB, unsigned UniqueCallSite) const
Align getFunctionParamOptimizedAlign(const Function *F, Type *ArgTy, const DataLayout &DL) const
getFunctionParamOptimizedAlign - since function arguments are passed via .param space,...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Align getFunctionByValParamAlign(const Function *F, Type *ArgTy, Align InitialAlign, const DataLayout &DL) const
Helper for computing alignment of a device function byval parameter.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool allowUnsafeFPMath(MachineFunction &MF) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:222
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Code generation optimization level.
Definition: CodeGen.h:57
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1323
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...