LLVM 20.0.0git
NVPTXISelLowering.h
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1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
16
17#include "NVPTX.h"
20
21namespace llvm {
22namespace NVPTXISD {
23enum NodeType : unsigned {
24 // Start the numbering from where ISD NodeType finishes.
71
75 LDUV2, // LDU.v2
76 LDUV4, // LDU.v4
85 StoreParamS32, // to sext and store a <32bit value, not used currently
86 StoreParamU32, // to zext and store a <32bit value, not used currently
91};
92}
93
94class NVPTXSubtarget;
95
96//===--------------------------------------------------------------------===//
97// TargetLowering Implementation
98//===--------------------------------------------------------------------===//
100public:
101 explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
102 const NVPTXSubtarget &STI);
103 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
104
106
107 const char *getTargetNodeName(unsigned Opcode) const override;
108
110 MachineFunction &MF,
111 unsigned Intrinsic) const override;
112
113 Align getFunctionArgumentAlignment(const Function *F, Type *Ty, unsigned Idx,
114 const DataLayout &DL) const;
115
116 /// getFunctionParamOptimizedAlign - since function arguments are passed via
117 /// .param space, we may want to increase their alignment in a way that
118 /// ensures that we can effectively vectorize their loads & stores. We can
119 /// increase alignment only if the function has internal or has private
120 /// linkage as for other linkage types callers may already rely on default
121 /// alignment. To allow using 128-bit vectorized loads/stores, this function
122 /// ensures that alignment is 16 or greater.
124 const DataLayout &DL) const;
125
126 /// Helper for computing alignment of a device function byval parameter.
128 Align InitialAlign,
129 const DataLayout &DL) const;
130
131 // Helper for getting a function parameter name. Name is composed from
132 // its index and the function name. Negative index corresponds to special
133 // parameter (unsized array) used for passing variable arguments.
134 std::string getParamName(const Function *F, int Idx) const;
135
136 /// isLegalAddressingMode - Return true if the addressing mode represented
137 /// by AM is legal for this target, for a load/store of the specified type
138 /// Used to guide target specific optimizations, like loop strength
139 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
140 /// address mode (CodeGenPrepare.cpp)
141 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
142 unsigned AS,
143 Instruction *I = nullptr) const override;
144
145 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
146 // Truncating 64-bit to 32-bit is free in SASS.
147 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
148 return false;
149 return SrcTy->getPrimitiveSizeInBits() == 64 &&
150 DstTy->getPrimitiveSizeInBits() == 32;
151 }
152
154 EVT VT) const override {
155 if (VT.isVector())
156 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
157 return MVT::i1;
158 }
159
160 ConstraintType getConstraintType(StringRef Constraint) const override;
161 std::pair<unsigned, const TargetRegisterClass *>
163 StringRef Constraint, MVT VT) const override;
164
166 bool isVarArg,
168 const SDLoc &dl, SelectionDAG &DAG,
169 SmallVectorImpl<SDValue> &InVals) const override;
170
171 SDValue LowerCall(CallLoweringInfo &CLI,
172 SmallVectorImpl<SDValue> &InVals) const override;
173
177
178 std::string
179 getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
180 const SmallVectorImpl<ISD::OutputArg> &, MaybeAlign retAlignment,
181 std::optional<std::pair<unsigned, const APInt &>> VAInfo,
182 const CallBase &CB, unsigned UniqueCallSite) const;
183
184 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
186 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
187 SelectionDAG &DAG) const override;
188
190 std::vector<SDValue> &Ops,
191 SelectionDAG &DAG) const override;
192
194
195 // PTX always uses 32-bit shift amounts
196 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
197 return MVT::i32;
198 }
199
201 getPreferredVectorAction(MVT VT) const override;
202
203 // Get the degree of precision we want from 32-bit floating point division
204 // operations.
205 //
206 // 0 - Use ptx div.approx
207 // 1 - Use ptx.div.full (approximate, but less so than div.approx)
208 // 2 - Use IEEE-compliant div instructions, if available.
209 int getDivF32Level() const;
210
211 // Get whether we should use a precise or approximate 32-bit floating point
212 // sqrt instruction.
213 bool usePrecSqrtF32() const;
214
215 // Get whether we should use instructions that flush floating-point denormals
216 // to sign-preserving zero.
217 bool useF32FTZ(const MachineFunction &MF) const;
218
220 int &ExtraSteps, bool &UseOneConst,
221 bool Reciprocal) const override;
222
223 unsigned combineRepeatedFPDivisors() const override { return 2; }
224
225 bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const;
226 bool allowUnsafeFPMath(MachineFunction &MF) const;
227
229 EVT) const override {
230 return true;
231 }
232
233 // The default is the same as pointer type, but brx.idx only accepts i32
234 MVT getJumpTableRegTy(const DataLayout &) const override { return MVT::i32; }
235
236 unsigned getJumpTableEncoding() const override;
237
238 bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
239
240 // The default is to transform llvm.ctlz(x, false) (where false indicates that
241 // x == 0 is not undefined behavior) into a branch that checks whether x is 0
242 // and avoids calling ctlz in that case. We have a dedicated ctlz
243 // instruction, so we say that ctlz is cheap to speculate.
244 bool isCheapToSpeculateCtlz(Type *Ty) const override { return true; }
245
248 }
249
252 }
253
255 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
256
257 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override {
258 // There's rarely any point of packing something into a vector type if we
259 // already have the source data.
260 return true;
261 }
262
263private:
264 const NVPTXSubtarget &STI; // cache the subtarget here
265 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
266
267 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
268
269 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
270 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
271 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
272 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
273 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
274
275 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
276
277 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
278 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
279 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
280
281 SDValue PromoteBinOpIfF32FTZ(SDValue Op, SelectionDAG &DAG) const;
282
283 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
284 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
285
286 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
287 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
288
289 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
290 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
291
292 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
293 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
294 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
295
296 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
297 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
298
299 SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
300
301 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
302
303 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
304 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
305
306 SDValue LowerCopyToReg_128(SDValue Op, SelectionDAG &DAG) const;
307 unsigned getNumRegisters(LLVMContext &Context, EVT VT,
308 std::optional<MVT> RegisterVT) const override;
309 bool
310 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
311 SDValue *Parts, unsigned NumParts, MVT PartVT,
312 std::optional<CallingConv::ID> CC) const override;
313
314 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
315 SelectionDAG &DAG) const override;
316 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
317
318 Align getArgumentAlignment(const CallBase *CB, Type *Ty, unsigned Idx,
319 const DataLayout &DL) const;
320};
321
322} // namespace llvm
323
324#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file describes how to lower LLVM code to machine code.
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:704
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1112
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:176
Machine Value Type.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const NVPTXTargetMachine * nvTM
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MVT getJumpTableRegTy(const DataLayout &) const override
bool useF32FTZ(const MachineFunction &MF) const
SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
Align getFunctionArgumentAlignment(const Function *F, Type *Ty, unsigned Idx, const DataLayout &DL) const
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
std::string getParamName(const Function *F, int Idx) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, std::optional< std::pair< unsigned, const APInt & > > VAInfo, const CallBase &CB, unsigned UniqueCallSite) const
Align getFunctionParamOptimizedAlign(const Function *F, Type *ArgTy, const DataLayout &DL) const
getFunctionParamOptimizedAlign - since function arguments are passed via .param space,...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Align getFunctionByValParamAlign(const Function *F, Type *ArgTy, Align InitialAlign, const DataLayout &DL) const
Helper for computing alignment of a device function byval parameter.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool allowUnsafeFPMath(MachineFunction &MF) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:228
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
An instruction for storing to memory.
Definition: Instructions.h:292
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:237
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1490
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:35
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:74
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:168
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:331
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...