LLVM 19.0.0git
NVPTXISelLowering.h
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1//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
15#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
16
17#include "NVPTX.h"
20
21namespace llvm {
22namespace NVPTXISD {
23enum NodeType : unsigned {
24 // Start the numbering from where ISD NodeType finishes.
65
68 LDGV2, // LDG.v2
69 LDGV4, // LDG.v4
70 LDUV2, // LDU.v2
71 LDUV4, // LDU.v4
80 StoreParamS32, // to sext and store a <32bit value, not used currently
81 StoreParamU32, // to zext and store a <32bit value, not used currently
85
86 // Texture intrinsics
261
262 // Surface intrinsics
274
286
298
310
322
334
346
358
370
382
394
406
418
430
443}
444
445class NVPTXSubtarget;
446
447//===--------------------------------------------------------------------===//
448// TargetLowering Implementation
449//===--------------------------------------------------------------------===//
451public:
453 const NVPTXSubtarget &STI);
454 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
455
457
458 const char *getTargetNodeName(unsigned Opcode) const override;
459
461 MachineFunction &MF,
462 unsigned Intrinsic) const override;
463
464 /// getFunctionParamOptimizedAlign - since function arguments are passed via
465 /// .param space, we may want to increase their alignment in a way that
466 /// ensures that we can effectively vectorize their loads & stores. We can
467 /// increase alignment only if the function has internal or has private
468 /// linkage as for other linkage types callers may already rely on default
469 /// alignment. To allow using 128-bit vectorized loads/stores, this function
470 /// ensures that alignment is 16 or greater.
472 const DataLayout &DL) const;
473
474 /// Helper for computing alignment of a device function byval parameter.
476 Align InitialAlign,
477 const DataLayout &DL) const;
478
479 // Helper for getting a function parameter name. Name is composed from
480 // its index and the function name. Negative index corresponds to special
481 // parameter (unsized array) used for passing variable arguments.
482 std::string getParamName(const Function *F, int Idx) const;
483
484 /// isLegalAddressingMode - Return true if the addressing mode represented
485 /// by AM is legal for this target, for a load/store of the specified type
486 /// Used to guide target specific optimizations, like loop strength
487 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
488 /// address mode (CodeGenPrepare.cpp)
489 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
490 unsigned AS,
491 Instruction *I = nullptr) const override;
492
493 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
494 // Truncating 64-bit to 32-bit is free in SASS.
495 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
496 return false;
497 return SrcTy->getPrimitiveSizeInBits() == 64 &&
498 DstTy->getPrimitiveSizeInBits() == 32;
499 }
500
502 EVT VT) const override {
503 if (VT.isVector())
504 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
505 return MVT::i1;
506 }
507
508 ConstraintType getConstraintType(StringRef Constraint) const override;
509 std::pair<unsigned, const TargetRegisterClass *>
511 StringRef Constraint, MVT VT) const override;
512
514 bool isVarArg,
516 const SDLoc &dl, SelectionDAG &DAG,
517 SmallVectorImpl<SDValue> &InVals) const override;
518
519 SDValue LowerCall(CallLoweringInfo &CLI,
520 SmallVectorImpl<SDValue> &InVals) const override;
521
523
524 std::string
525 getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
526 const SmallVectorImpl<ISD::OutputArg> &, MaybeAlign retAlignment,
527 std::optional<std::pair<unsigned, const APInt &>> VAInfo,
528 const CallBase &CB, unsigned UniqueCallSite) const;
529
530 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
532 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
533 SelectionDAG &DAG) const override;
534
536 std::vector<SDValue> &Ops,
537 SelectionDAG &DAG) const override;
538
540
541 // PTX always uses 32-bit shift amounts
542 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
543 return MVT::i32;
544 }
545
547 getPreferredVectorAction(MVT VT) const override;
548
549 // Get the degree of precision we want from 32-bit floating point division
550 // operations.
551 //
552 // 0 - Use ptx div.approx
553 // 1 - Use ptx.div.full (approximate, but less so than div.approx)
554 // 2 - Use IEEE-compliant div instructions, if available.
555 int getDivF32Level() const;
556
557 // Get whether we should use a precise or approximate 32-bit floating point
558 // sqrt instruction.
559 bool usePrecSqrtF32() const;
560
561 // Get whether we should use instructions that flush floating-point denormals
562 // to sign-preserving zero.
563 bool useF32FTZ(const MachineFunction &MF) const;
564
566 int &ExtraSteps, bool &UseOneConst,
567 bool Reciprocal) const override;
568
569 unsigned combineRepeatedFPDivisors() const override { return 2; }
570
571 bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const;
572 bool allowUnsafeFPMath(MachineFunction &MF) const;
573
575 EVT) const override {
576 return true;
577 }
578
579 bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
580
581 // The default is to transform llvm.ctlz(x, false) (where false indicates that
582 // x == 0 is not undefined behavior) into a branch that checks whether x is 0
583 // and avoids calling ctlz in that case. We have a dedicated ctlz
584 // instruction, so we say that ctlz is cheap to speculate.
585 bool isCheapToSpeculateCtlz(Type *Ty) const override { return true; }
586
589 }
590
593 }
594
596 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
597
598 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override {
599 // There's rarely any point of packing something into a vector type if we
600 // already have the source data.
601 return true;
602 }
603
604private:
605 const NVPTXSubtarget &STI; // cache the subtarget here
606 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
607
608 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
612 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
613
614 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
616 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
617
618 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
619 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
620
621 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
622 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
623
624 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
625 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
626 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
627
628 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
629 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
630
631 SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
632
633 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
634 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
635
636 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
637 SelectionDAG &DAG) const override;
638 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
639
640 Align getArgumentAlignment(const CallBase *CB, Type *Ty, unsigned Idx,
641 const DataLayout &DL) const;
642};
643
644} // namespace llvm
645
646#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1259
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:178
Machine Value Type.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const NVPTXTargetMachine * nvTM
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
bool useF32FTZ(const MachineFunction &MF) const
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
std::string getParamName(const Function *F, int Idx) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, std::optional< std::pair< unsigned, const APInt & > > VAInfo, const CallBase &CB, unsigned UniqueCallSite) const
Align getFunctionParamOptimizedAlign(const Function *F, Type *ArgTy, const DataLayout &DL) const
getFunctionParamOptimizedAlign - since function arguments are passed via .param space,...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Align getFunctionByValParamAlign(const Function *F, Type *ArgTy, Align InitialAlign, const DataLayout &DL) const
Helper for computing alignment of a device function byval parameter.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool allowUnsafeFPMath(MachineFunction &MF) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
An instruction for storing to memory.
Definition: Instructions.h:302
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1389
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1401
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:319
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...