LLVM  14.0.0git
llvm::TargetRegisterInfo Member List

This is the complete list of members for llvm::TargetRegisterInfo, including all inherited members.

adjustStackMapLiveOutMask(uint32_t *Mask) constllvm::TargetRegisterInfoinlinevirtual
canRealignStack(const MachineFunction &MF) constllvm::TargetRegisterInfovirtual
checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) constllvm::TargetRegisterInfo
composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) constllvm::TargetRegisterInfoinline
composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) constllvm::TargetRegisterInfoinlineprotectedvirtual
composeSubRegIndices(unsigned a, unsigned b) constllvm::TargetRegisterInfoinline
composeSubRegIndicesImpl(unsigned, unsigned) constllvm::TargetRegisterInfoinlineprotectedvirtual
dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)llvm::TargetRegisterInfostatic
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0llvm::TargetRegisterInfopure virtual
get(MCRegister RegNo) constllvm::MCRegisterInfoinline
getAllocatableClass(const TargetRegisterClass *RC) constllvm::TargetRegisterInfo
getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) constllvm::TargetRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF) const =0llvm::TargetRegisterInfopure virtual
getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) constllvm::TargetRegisterInfoinlinevirtual
getCodeViewRegNum(MCRegister RegNum) constllvm::MCRegisterInfo
getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) constllvm::TargetRegisterInfo
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) constllvm::TargetRegisterInfo
getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) constllvm::TargetRegisterInfoinlinevirtual
getCoveringLanes() constllvm::TargetRegisterInfoinline
getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) constllvm::TargetRegisterInfo
getCrossCopyRegClass(const TargetRegisterClass *RC) constllvm::TargetRegisterInfoinlinevirtual
getCSRFirstUseCost() constllvm::TargetRegisterInfoinlinevirtual
getCustomEHPadPreservedMask(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
getDwarfRegNum(MCRegister RegNum, bool isEH) constllvm::MCRegisterInfo
getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) constllvm::MCRegisterInfo
getEncodingValue(MCRegister RegNo) constllvm::MCRegisterInfoinline
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) constllvm::TargetRegisterInfoinlinevirtual
getFrameRegister(const MachineFunction &MF) const =0llvm::TargetRegisterInfopure virtual
getIntraCallClobberedRegs(const MachineFunction *MF) constllvm::TargetRegisterInfoinlinevirtual
getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) constllvm::TargetRegisterInfoinlinevirtual
getLLVMRegNum(unsigned RegNum, bool isEH) constllvm::MCRegisterInfo
getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) constllvm::TargetRegisterInfoinline
llvm::MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) constllvm::MCRegisterInfo
getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) constllvm::TargetRegisterInfovirtual
getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) constllvm::TargetRegisterInfo
getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) constllvm::TargetRegisterInfo
getName(MCRegister RegNo) constllvm::MCRegisterInfoinline
getNoPreservedMask() constllvm::TargetRegisterInfoinlinevirtual
getNumRegClasses() constllvm::TargetRegisterInfoinline
getNumRegPressureSets() const =0llvm::TargetRegisterInfopure virtual
getNumRegs() constllvm::MCRegisterInfoinline
getNumRegUnits() constllvm::MCRegisterInfoinline
getNumSubRegIndices() constllvm::MCRegisterInfoinline
getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) constllvm::TargetRegisterInfovirtual
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) constllvm::TargetRegisterInfoinlinevirtual
getProgramCounter() constllvm::MCRegisterInfoinline
getRARegister() constllvm::MCRegisterInfoinline
getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) constllvm::TargetRegisterInfovirtual
getRegAsmName(MCRegister Reg) constllvm::TargetRegisterInfoinlinevirtual
getRegClass(unsigned i) constllvm::TargetRegisterInfoinline
getRegClassInfo(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinlineprotected
getRegClassName(const TargetRegisterClass *Class) constllvm::TargetRegisterInfoinline
llvm::MCRegisterInfo::getRegClassName(const MCRegisterClass *Class) constllvm::MCRegisterInfoinline
getRegClassPressureSets(const TargetRegisterClass *RC) const =0llvm::TargetRegisterInfopure virtual
getRegClassWeight(const TargetRegisterClass *RC) const =0llvm::TargetRegisterInfopure virtual
getRegisterCosts(const MachineFunction &MF) constllvm::TargetRegisterInfoinline
getRegisterCostTableIndex(const MachineFunction &MF) constllvm::TargetRegisterInfoinlineprotectedvirtual
getRegMaskNames() const =0llvm::TargetRegisterInfopure virtual
getRegMasks() const =0llvm::TargetRegisterInfopure virtual
getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0llvm::TargetRegisterInfopure virtual
getRegPressureSetName(unsigned Idx) const =0llvm::TargetRegisterInfopure virtual
getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) constllvm::TargetRegisterInfoinlinevirtual
getRegSizeInBits(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinline
getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) constllvm::TargetRegisterInfo
getRegUnitPressureSets(unsigned RegUnit) const =0llvm::TargetRegisterInfopure virtual
getRegUnitWeight(unsigned RegUnit) const =0llvm::TargetRegisterInfopure virtual
getReservedRegs(const MachineFunction &MF) const =0llvm::TargetRegisterInfopure virtual
getSEHRegNum(MCRegister RegNum) constllvm::MCRegisterInfo
getSpillAlign(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinline
getSpillSize(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinline
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) constllvm::TargetRegisterInfoinlinevirtual
getSubReg(MCRegister Reg, unsigned Idx) constllvm::TargetRegisterInfoinline
getSubRegIdxOffset(unsigned Idx) constllvm::MCRegisterInfo
getSubRegIdxSize(unsigned Idx) constllvm::MCRegisterInfo
getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) constllvm::MCRegisterInfo
getSubRegIndexLaneMask(unsigned SubIdx) constllvm::TargetRegisterInfoinline
getSubRegIndexName(unsigned SubIdx) constllvm::TargetRegisterInfoinline
hasRegUnit(MCRegister Reg, Register RegUnit) constllvm::TargetRegisterInfoinline
hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) constllvm::TargetRegisterInfoinlinevirtual
hasStackRealignment(const MachineFunction &MF) constllvm::TargetRegisterInfoinline
InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)llvm::MCRegisterInfoinline
isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) constllvm::TargetRegisterInfoinlinevirtual
isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) constllvm::TargetRegisterInfovirtual
isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
isConstantPhysReg(MCRegister PhysReg) constllvm::TargetRegisterInfoinlinevirtual
isDivergentRegClass(const TargetRegisterClass *RC) constllvm::TargetRegisterInfoinlinevirtual
isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) constllvm::TargetRegisterInfoinlinevirtual
isInAllocatableClass(MCRegister RegNo) constllvm::TargetRegisterInfoinline
isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) constllvm::TargetRegisterInfoinlinevirtual
isSubRegister(MCRegister RegA, MCRegister RegB) constllvm::MCRegisterInfoinline
isSubRegisterEq(MCRegister RegA, MCRegister RegB) constllvm::MCRegisterInfoinline
isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) constllvm::MCRegisterInfoinline
isSuperRegister(MCRegister RegA, MCRegister RegB) constllvm::MCRegisterInfoinline
isSuperRegisterEq(MCRegister RegA, MCRegister RegB) constllvm::MCRegisterInfoinline
isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) constllvm::TargetRegisterInfoinline
isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) constllvm::TargetRegisterInfoinline
legalclasstypes_begin(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinline
legalclasstypes_end(const TargetRegisterClass &RC) constllvm::TargetRegisterInfoinline
lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) constllvm::TargetRegisterInfovirtual
lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) constllvm::TargetRegisterInfovirtual
mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)llvm::MCRegisterInfoinline
mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)llvm::MCRegisterInfoinline
mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)llvm::MCRegisterInfoinline
mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg)llvm::MCRegisterInfoinline
markSuperRegs(BitVector &RegisterSet, MCRegister Reg) constllvm::TargetRegisterInfo
materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) constllvm::TargetRegisterInfoinlinevirtual
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) constllvm::TargetRegisterInfoinlinevirtual
operator[](MCRegister RegNo) constllvm::MCRegisterInfoinline
prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) constllvm::TargetRegisterInfo
regclass_begin() constllvm::TargetRegisterInfoinline
regclass_end() constllvm::TargetRegisterInfoinline
regclass_iterator typedefllvm::TargetRegisterInfo
regclasses() constllvm::TargetRegisterInfoinline
regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) constllvm::TargetRegisterInfo
regsOverlap(Register regA, Register regB) constllvm::TargetRegisterInfoinline
requiresFrameIndexReplacementScavenging(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
requiresFrameIndexScavenging(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
requiresRegisterScavenging(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
requiresVirtualBaseRegisters(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) constllvm::TargetRegisterInfoinlinevirtual
reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) constllvm::TargetRegisterInfoinline
reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) constllvm::TargetRegisterInfoinlineprotectedvirtual
reverseLocalAssignment() constllvm::TargetRegisterInfoinlinevirtual
saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) constllvm::TargetRegisterInfoinlinevirtual
shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) constllvm::TargetRegisterInfoinlinevirtual
shouldRealignStack(const MachineFunction &MF) constllvm::TargetRegisterInfovirtual
shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) constllvm::TargetRegisterInfovirtual
shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) constllvm::TargetRegisterInfovirtual
shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) constllvm::TargetRegisterInfoinlinevirtual
shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) constllvm::TargetRegisterInfoinlinevirtual
sub_and_superregs_inclusive(MCRegister Reg) constllvm::MCRegisterInfoinline
subregs(MCRegister Reg) constllvm::MCRegisterInfoinline
subregs_inclusive(MCRegister Reg) constllvm::MCRegisterInfoinline
superregs(MCRegister Reg) constllvm::MCRegisterInfoinline
superregs_inclusive(MCRegister Reg) constllvm::MCRegisterInfoinline
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)llvm::TargetRegisterInfoprotected
trackLivenessAfterRegAlloc(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
useFPForScavengingIndex(const MachineFunction &MF) constllvm::TargetRegisterInfoinlinevirtual
vt_iterator typedefllvm::TargetRegisterInfo
~TargetRegisterInfo()llvm::TargetRegisterInfoprotectedvirtual