LLVM  14.0.0git
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llvm::TargetRegisterInfo Class Referenceabstract

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. More...

#include "llvm/CodeGen/TargetRegisterInfo.h"

Inheritance diagram for llvm::TargetRegisterInfo:
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Collaboration diagram for llvm::TargetRegisterInfo:
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Classes

struct  RegClassInfo
 

Public Types

using regclass_iterator = const TargetRegisterClass *const *
 
using vt_iterator = const MVT::SimpleValueType *
 
- Public Types inherited from llvm::MCRegisterInfo
using regclass_iterator = const MCRegisterClass *
 

Public Member Functions

unsigned getRegSizeInBits (const TargetRegisterClass &RC) const
 Return the size in bits of a register from class RC. More...
 
unsigned getSpillSize (const TargetRegisterClass &RC) const
 Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC. More...
 
Align getSpillAlign (const TargetRegisterClass &RC) const
 Return the minimum required alignment in bytes for a spill slot for a register of this class. More...
 
bool isTypeLegalForClass (const TargetRegisterClass &RC, MVT T) const
 Return true if the given TargetRegisterClass has the ValueType T. More...
 
bool isTypeLegalForClass (const TargetRegisterClass &RC, LLT T) const
 Return true if the given TargetRegisterClass is compatible with LLT T. More...
 
vt_iterator legalclasstypes_begin (const TargetRegisterClass &RC) const
 Loop over all of the value types that can be represented by values in the given register class. More...
 
vt_iterator legalclasstypes_end (const TargetRegisterClass &RC) const
 
const TargetRegisterClassgetMinimalPhysRegClass (MCRegister Reg, MVT VT=MVT::Other) const
 Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. More...
 
const TargetRegisterClassgetMinimalPhysRegClassLLT (MCRegister Reg, LLT Ty=LLT()) const
 Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. More...
 
const TargetRegisterClassgetAllocatableClass (const TargetRegisterClass *RC) const
 Return the maximal subclass of the given register class that is allocatable or NULL. More...
 
BitVector getAllocatableSet (const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
 Returns a bitset indexed by register number indicating if a register is allocatable or not. More...
 
ArrayRef< uint8_t > getRegisterCosts (const MachineFunction &MF) const
 Get a list of cost values for all registers that correspond to the index returned by RegisterCostTableIndex. More...
 
bool isInAllocatableClass (MCRegister RegNo) const
 Return true if the register is in the allocation of any register class. More...
 
const char * getSubRegIndexName (unsigned SubIdx) const
 Return the human-readable symbolic target-specific name for the specified SubRegIndex. More...
 
LaneBitmask getSubRegIndexLaneMask (unsigned SubIdx) const
 Return a bitmask representing the parts of a register that are covered by SubIdx. More...
 
bool getCoveringSubRegIndexes (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
 Try to find one or more subregister indexes to cover LaneMask. More...
 
LaneBitmask getCoveringLanes () const
 The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. More...
 
bool regsOverlap (Register regA, Register regB) const
 Returns true if the two registers are equal or alias each other. More...
 
bool hasRegUnit (MCRegister Reg, Register RegUnit) const
 Returns true if Reg contains RegUnit. More...
 
virtual Register lookThruCopyLike (Register SrcReg, const MachineRegisterInfo *MRI) const
 Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. More...
 
virtual Register lookThruSingleUseCopyChain (Register SrcReg, const MachineRegisterInfo *MRI) const
 Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. More...
 
virtual const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const =0
 Return a null-terminated list of all of the callee-saved registers on this target. More...
 
virtual const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const
 Return a mask of call-preserved registers for the given calling convention on the current function. More...
 
virtual const uint32_tgetCustomEHPadPreservedMask (const MachineFunction &MF) const
 Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is needed. More...
 
virtual const uint32_tgetNoPreservedMask () const
 Return a register mask that clobbers everything. More...
 
virtual ArrayRef< MCPhysReggetIntraCallClobberedRegs (const MachineFunction *MF) const
 Return a list of all of the registers which are clobbered "inside" a call to the given function. More...
 
bool regmaskSubsetEqual (const uint32_t *mask0, const uint32_t *mask1) const
 Return true if all bits that are set in mask mask0 are also set in mask1. More...
 
virtual ArrayRef< const uint32_t * > getRegMasks () const =0
 Return all the call-preserved register masks defined for this target. More...
 
virtual ArrayRef< const char * > getRegMaskNames () const =0
 
virtual BitVector getReservedRegs (const MachineFunction &MF) const =0
 Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. More...
 
virtual bool isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const
 Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement. More...
 
virtual bool isInlineAsmReadOnlyReg (const MachineFunction &MF, unsigned PhysReg) const
 Returns true if PhysReg cannot be written to in inline asm statements. More...
 
virtual bool isConstantPhysReg (MCRegister PhysReg) const
 Returns true if PhysReg is unallocatable and constant throughout the function. More...
 
virtual bool isDivergentRegClass (const TargetRegisterClass *RC) const
 Returns true if the register class is considered divergent. More...
 
virtual bool isCallerPreservedPhysReg (MCRegister PhysReg, const MachineFunction &MF) const
 Physical registers that may be modified within a function but are guaranteed to be restored before any uses. More...
 
virtual bool isCalleeSavedPhysReg (MCRegister PhysReg, const MachineFunction &MF) const
 This is a wrapper around getCallPreservedMask(). More...
 
virtual void adjustStackMapLiveOutMask (uint32_t *Mask) const
 Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored). More...
 
MCRegister getMatchingSuperReg (MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
 Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
virtual const TargetRegisterClassgetMatchingSuperRegClass (const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
 Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. More...
 
virtual bool shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
 
virtual const TargetRegisterClassgetSubClassWithSubReg (const TargetRegisterClass *RC, unsigned Idx) const
 Returns the largest legal sub-class of RC that supports the sub-register index Idx. More...
 
unsigned composeSubRegIndices (unsigned a, unsigned b) const
 Return the subregister index you get from composing two subregister indices. More...
 
LaneBitmask composeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask Mask) const
 Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first. More...
 
LaneBitmask reverseComposeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask LaneMask) const
 Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA. More...
 
const TargetRegisterClassgetCommonSuperRegClass (const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
 Find a common super-register class if it exists. More...
 
regclass_iterator regclass_begin () const
 Register class iterators. More...
 
regclass_iterator regclass_end () const
 
iterator_range< regclass_iteratorregclasses () const
 
unsigned getNumRegClasses () const
 
const TargetRegisterClassgetRegClass (unsigned i) const
 Returns the register class associated with the enumeration value. More...
 
const char * getRegClassName (const TargetRegisterClass *Class) const
 Returns the name of the register class. More...
 
const TargetRegisterClassgetCommonSubClass (const TargetRegisterClass *A, const TargetRegisterClass *B) const
 Find the largest common subclass of A and B. More...
 
virtual const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const
 Returns a TargetRegisterClass used for pointer values. More...
 
virtual const TargetRegisterClassgetCrossCopyRegClass (const TargetRegisterClass *RC) const
 Returns a legal register class to copy a register in the specified class to or from. More...
 
virtual const TargetRegisterClassgetLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const
 Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. More...
 
virtual unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const
 Return the register pressure "high water mark" for the specific register class. More...
 
virtual unsigned getRegPressureSetScore (const MachineFunction &MF, unsigned PSetID) const
 Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another. More...
 
virtual const RegClassWeightgetRegClassWeight (const TargetRegisterClass *RC) const =0
 Get the weight in units of pressure for this register class. More...
 
unsigned getRegSizeInBits (Register Reg, const MachineRegisterInfo &MRI) const
 Returns size in bits of a phys/virtual/generic register. More...
 
virtual unsigned getRegUnitWeight (unsigned RegUnit) const =0
 Get the weight in units of pressure for this register unit. More...
 
virtual unsigned getNumRegPressureSets () const =0
 Get the number of dimensions of register pressure. More...
 
virtual const char * getRegPressureSetName (unsigned Idx) const =0
 Get the name of this register unit pressure set. More...
 
virtual unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const =0
 Get the register unit pressure limit for this dimension. More...
 
virtual const intgetRegClassPressureSets (const TargetRegisterClass *RC) const =0
 Get the dimensions of register pressure impacted by this register class. More...
 
virtual const intgetRegUnitPressureSets (unsigned RegUnit) const =0
 Get the dimensions of register pressure impacted by this register unit. More...
 
virtual bool getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
 Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. More...
 
virtual void updateRegAllocHint (Register Reg, Register NewReg, MachineFunction &MF) const
 A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. More...
 
virtual bool reverseLocalAssignment () const
 Allow the target to reverse allocation order of local live ranges. More...
 
virtual bool addAllocPriorityToGlobalRanges () const
 Add the allocation priority to global and split ranges as well as the local ranges when registers are added to the queue. More...
 
virtual unsigned getCSRFirstUseCost () const
 Allow the target to override the cost of using a callee-saved register for the first time. More...
 
virtual bool requiresRegisterScavenging (const MachineFunction &MF) const
 Returns true if the target requires (and can make use of) the register scavenger. More...
 
virtual bool useFPForScavengingIndex (const MachineFunction &MF) const
 Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot. More...
 
virtual bool requiresFrameIndexScavenging (const MachineFunction &MF) const
 Returns true if the target requires post PEI scavenging of registers for materializing frame index constants. More...
 
virtual bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const
 Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging. More...
 
virtual bool requiresVirtualBaseRegisters (const MachineFunction &MF) const
 Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access. More...
 
virtual bool hasReservedSpillSlot (const MachineFunction &MF, Register Reg, int &FrameIdx) const
 Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. More...
 
virtual bool trackLivenessAfterRegAlloc (const MachineFunction &MF) const
 Returns true if the live-ins should be tracked after register allocation. More...
 
virtual bool canRealignStack (const MachineFunction &MF) const
 True if the stack can be realigned for the target. More...
 
virtual bool shouldRealignStack (const MachineFunction &MF) const
 True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for. More...
 
bool hasStackRealignment (const MachineFunction &MF) const
 True if stack realignment is required and still possible. More...
 
virtual int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const
 Get the offset from the referenced frame index in the instruction, if there is one. More...
 
virtual bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const
 Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More...
 
virtual Register materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
 Insert defining instruction(s) for a pointer to FrameIdx before insertion point I. More...
 
virtual void resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const
 Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead. More...
 
virtual bool isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const
 Determine whether a given base register plus offset immediate is encodable to resolve a frame index. More...
 
virtual void getOffsetOpcodes (const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
 Gets the DWARF expression opcodes for Offset. More...
 
DIExpressionprependOffsetExpression (const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
 Prepends a DWARF expression for Offset to DIExpression Expr. More...
 
virtual bool saveScavengerRegister (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
 Spill the register so it can be used by the register scavenger. More...
 
virtual void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
 This method must be overriden to eliminate abstract frame indices from instructions which may use them. More...
 
virtual StringRef getRegAsmName (MCRegister Reg) const
 Return the assembly name for Reg. More...
 
virtual bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
 Subtarget Hooks. More...
 
virtual bool shouldRegionSplitForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const
 Region split has a high compile time cost especially for large live range. More...
 
virtual bool shouldUseLastChanceRecoloringForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const
 Last chance recoloring has a high compile time cost especially for targets with a lot of registers. More...
 
virtual bool shouldUseDeferredSpillingForVirtReg (const MachineFunction &MF, const LiveInterval &VirtReg) const
 Deferred spilling delays the spill insertion of a virtual register after every other allocation. More...
 
virtual Register getFrameRegister (const MachineFunction &MF) const =0
 Debug information queries. More...
 
void markSuperRegs (BitVector &RegisterSet, MCRegister Reg) const
 Mark a register and all its aliases as reserved in the given set. More...
 
bool checkAllSuperRegsMarked (const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
 Returns true if for every register in the set all super registers are part of the set as well. More...
 
virtual const TargetRegisterClassgetConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const
 
MCRegister getSubReg (MCRegister Reg, unsigned Idx) const
 Returns the physical register number of sub-register "Index" for physical register RegNo. More...
 
- Public Member Functions inherited from llvm::MCRegisterInfo
iterator_range< mc_subreg_iteratorsubregs (MCRegister Reg) const
 Return an iterator range over all sub-registers of Reg, excluding Reg. More...
 
iterator_range< mc_subreg_iteratorsubregs_inclusive (MCRegister Reg) const
 Return an iterator range over all sub-registers of Reg, including Reg. More...
 
iterator_range< mc_superreg_iteratorsuperregs (MCRegister Reg) const
 Return an iterator range over all super-registers of Reg, excluding Reg. More...
 
iterator_range< mc_superreg_iteratorsuperregs_inclusive (MCRegister Reg) const
 Return an iterator range over all super-registers of Reg, including Reg. More...
 
detail::concat_range< const MCPhysReg, iterator_range< mc_subreg_iterator >, iterator_range< mc_superreg_iterator > > sub_and_superregs_inclusive (MCRegister Reg) const
 Return an iterator range over all sub- and super-registers of Reg, including Reg. More...
 
void InitMCRegisterInfo (const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET)
 Initialize MCRegisterInfo, called by TableGen auto-generated routines. More...
 
void mapLLVMRegsToDwarfRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize LLVM register to Dwarf register number mapping. More...
 
void mapDwarfRegsToLLVMRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH)
 Used to initialize Dwarf register to LLVM register number mapping. More...
 
void mapLLVMRegToSEHReg (MCRegister LLVMReg, int SEHReg)
 mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping. More...
 
void mapLLVMRegToCVReg (MCRegister LLVMReg, int CVReg)
 
MCRegister getRARegister () const
 This method should return the register where the return address can be found. More...
 
MCRegister getProgramCounter () const
 Return the register which is the program counter. More...
 
const MCRegisterDescoperator[] (MCRegister RegNo) const
 
const MCRegisterDescget (MCRegister RegNo) const
 Provide a get method, equivalent to [], but more useful with a pointer to this object. More...
 
MCRegister getSubReg (MCRegister Reg, unsigned Idx) const
 Returns the physical register number of sub-register "Index" for physical register RegNo. More...
 
MCRegister getMatchingSuperReg (MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
 Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More...
 
unsigned getSubRegIndex (MCRegister RegNo, MCRegister SubRegNo) const
 For a given register pair, return the sub-register index if the second register is a sub-register of the first. More...
 
unsigned getSubRegIdxSize (unsigned Idx) const
 Get the size of the bit range covered by a sub-register index. More...
 
unsigned getSubRegIdxOffset (unsigned Idx) const
 Get the offset of the bit range covered by a sub-register index. More...
 
const char * getName (MCRegister RegNo) const
 Return the human-readable symbolic target-specific name for the specified physical register. More...
 
unsigned getNumRegs () const
 Return the number of registers this target has (useful for sizing arrays holding per register information) More...
 
unsigned getNumSubRegIndices () const
 Return the number of sub-register indices understood by the target. More...
 
unsigned getNumRegUnits () const
 Return the number of (native) register units in the target. More...
 
int getDwarfRegNum (MCRegister RegNum, bool isEH) const
 Map a target register to an equivalent dwarf register number. More...
 
Optional< unsigned > getLLVMRegNum (unsigned RegNum, bool isEH) const
 Map a dwarf register back to a target register. More...
 
int getDwarfRegNumFromDwarfEHRegNum (unsigned RegNum) const
 Map a target EH register number to an equivalent DWARF register number. More...
 
int getSEHRegNum (MCRegister RegNum) const
 Map a target register to an equivalent SEH register number. More...
 
int getCodeViewRegNum (MCRegister RegNum) const
 Map a target register to an equivalent CodeView register number. More...
 
regclass_iterator regclass_begin () const
 
regclass_iterator regclass_end () const
 
iterator_range< regclass_iteratorregclasses () const
 
unsigned getNumRegClasses () const
 
const MCRegisterClassgetRegClass (unsigned i) const
 Returns the register class associated with the enumeration value. More...
 
const char * getRegClassName (const MCRegisterClass *Class) const
 
uint16_t getEncodingValue (MCRegister RegNo) const
 Returns the encoding for RegNo. More...
 
bool isSubRegister (MCRegister RegA, MCRegister RegB) const
 Returns true if RegB is a sub-register of RegA. More...
 
bool isSuperRegister (MCRegister RegA, MCRegister RegB) const
 Returns true if RegB is a super-register of RegA. More...
 
bool isSubRegisterEq (MCRegister RegA, MCRegister RegB) const
 Returns true if RegB is a sub-register of RegA or if RegB == RegA. More...
 
bool isSuperRegisterEq (MCRegister RegA, MCRegister RegB) const
 Returns true if RegB is a super-register of RegA or if RegB == RegA. More...
 
bool isSuperOrSubRegisterEq (MCRegister RegA, MCRegister RegB) const
 Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA. More...
 

Static Public Member Functions

static void dumpReg (Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
 Debugging helper: dump register in human readable form to dbgs() stream. More...
 

Protected Member Functions

 TargetRegisterInfo (const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
 
virtual ~TargetRegisterInfo ()
 
virtual unsigned composeSubRegIndicesImpl (unsigned, unsigned) const
 Overridden by TableGen in targets that have sub-registers. More...
 
virtual LaneBitmask composeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const
 Overridden by TableGen in targets that have sub-registers. More...
 
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const
 
virtual unsigned getRegisterCostTableIndex (const MachineFunction &MF) const
 Return the register cost table index. More...
 
const RegClassInfogetRegClassInfo (const TargetRegisterClass &RC) const
 

Detailed Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has.

As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Definition at line 231 of file TargetRegisterInfo.h.

Member Typedef Documentation

◆ regclass_iterator

Definition at line 233 of file TargetRegisterInfo.h.

◆ vt_iterator

Definition at line 234 of file TargetRegisterInfo.h.

Constructor & Destructor Documentation

◆ TargetRegisterInfo()

TargetRegisterInfo::TargetRegisterInfo ( const TargetRegisterInfoDesc ID,
regclass_iterator  RCB,
regclass_iterator  RCE,
const char *const SRINames,
const LaneBitmask SRILaneMasks,
LaneBitmask  CoveringLanes,
const RegClassInfo *const  RCIs,
unsigned  Mode = 0 
)
protected

Definition at line 52 of file TargetRegisterInfo.cpp.

◆ ~TargetRegisterInfo()

TargetRegisterInfo::~TargetRegisterInfo ( )
protectedvirtualdefault

Member Function Documentation

◆ addAllocPriorityToGlobalRanges()

virtual bool llvm::TargetRegisterInfo::addAllocPriorityToGlobalRanges ( ) const
inlinevirtual

Add the allocation priority to global and split ranges as well as the local ranges when registers are added to the queue.

Definition at line 876 of file TargetRegisterInfo.h.

◆ adjustStackMapLiveOutMask()

virtual void llvm::TargetRegisterInfo::adjustStackMapLiveOutMask ( uint32_t Mask) const
inlinevirtual

Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).

Definition at line 571 of file TargetRegisterInfo.h.

◆ canRealignStack()

bool TargetRegisterInfo::canRealignStack ( const MachineFunction MF) const
virtual

◆ checkAllSuperRegsMarked()

bool TargetRegisterInfo::checkAllSuperRegsMarked ( const BitVector RegisterSet,
ArrayRef< MCPhysReg Exceptions = ArrayRef<MCPhysReg>() 
) const

Returns true if for every register in the set all super registers are part of the set as well.

Definition at line 85 of file TargetRegisterInfo.cpp.

References llvm::dbgs(), llvm::MCRegisterInfo::getNumRegs(), llvm::is_contained(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::printReg(), Reg, and llvm::BitVector::set().

◆ composeSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::composeSubRegIndexLaneMask ( unsigned  IdxA,
LaneBitmask  Mask 
) const
inline

Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.

See also
composeSubRegIndices()

Definition at line 638 of file TargetRegisterInfo.h.

References composeSubRegIndexLaneMaskImpl(), and llvm::BitmaskEnumDetail::Mask().

Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo(), and stripValuesNotDefiningMask().

◆ composeSubRegIndexLaneMaskImpl()

virtual LaneBitmask llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl ( unsigned  ,
LaneBitmask   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 671 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by composeSubRegIndexLaneMask().

◆ composeSubRegIndices()

unsigned llvm::TargetRegisterInfo::composeSubRegIndices ( unsigned  a,
unsigned  b 
) const
inline

Return the subregister index you get from composing two subregister indices.

The special null sub-register index composes as the identity.

If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.

The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.

Definition at line 629 of file TargetRegisterInfo.h.

References b, and composeSubRegIndicesImpl().

Referenced by llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCommonSuperRegClass(), llvm::CoalescerPair::isCoalescable(), isCrossCopy(), and llvm::MachineOperand::substVirtReg().

◆ composeSubRegIndicesImpl()

virtual unsigned llvm::TargetRegisterInfo::composeSubRegIndicesImpl ( unsigned  ,
unsigned   
) const
inlineprotectedvirtual

Overridden by TableGen in targets that have sub-registers.

Definition at line 665 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by composeSubRegIndices().

◆ dumpReg()

LLVM_DUMP_METHOD void TargetRegisterInfo::dumpReg ( Register  Reg,
unsigned  SubRegIndex = 0,
const TargetRegisterInfo TRI = nullptr 
)
static

Debugging helper: dump register in human readable form to dbgs() stream.

Definition at line 669 of file TargetRegisterInfo.cpp.

References llvm::dbgs(), llvm::printReg(), Reg, and TRI.

◆ eliminateFrameIndex()

virtual void llvm::TargetRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS = nullptr 
) const
pure virtual

This method must be overriden to eliminate abstract frame indices from instructions which may use them.

The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ getAllocatableClass()

const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass ( const TargetRegisterClass RC) const

Return the maximal subclass of the given register class that is allocatable or NULL.

getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.

Definition at line 194 of file TargetRegisterInfo.cpp.

References getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), llvm::TargetRegisterClass::isAllocatable(), and llvm::BitMaskClassIterator::isValid().

Referenced by getAllocatableSet().

◆ getAllocatableSet()

BitVector TargetRegisterInfo::getAllocatableSet ( const MachineFunction MF,
const TargetRegisterClass RC = nullptr 
) const

◆ getCalleeSavedRegs()

virtual const MCPhysReg* llvm::TargetRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
pure virtual

Return a null-terminated list of all of the callee-saved registers on this target.

The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa. Notice: This function does not take into account disabled CSRs. In most cases you will want to use instead the function getCalleeSavedRegs that is implemented in MachineRegisterInfo.

Referenced by llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::MachineRegisterInfo::disableCalleeSavedRegister(), doesModifyCalleeSavedReg(), llvm::MipsFrameLowering::estimateStackSize(), llvm::MachineRegisterInfo::getCalleeSavedRegs(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ getCallPreservedMask()

virtual const uint32_t* llvm::TargetRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID   
) const
inlinevirtual

Return a mask of call-preserved registers for the given calling convention on the current function.

The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.

The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.

Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.

A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.

Definition at line 485 of file TargetRegisterInfo.h.

Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable(), buildCallOperands(), llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(), getMaskForArgs(), llvm::MipsTargetLowering::getOpndList(), isCalleeSavedPhysReg(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::MipsCallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::VETargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::AMDGPUCallLowering::lowerTailCall(), and llvm::FastISel::selectPatchpoint().

◆ getCommonSubClass()

const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass ( const TargetRegisterClass A,
const TargetRegisterClass B 
) const

◆ getCommonSuperRegClass()

const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass ( const TargetRegisterClass RCA,
unsigned  SubA,
const TargetRegisterClass RCB,
unsigned  SubB,
unsigned &  PreA,
unsigned &  PreB 
) const

Find a common super-register class if it exists.

Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:

  1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
  2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
  3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).

SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.

SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.

Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.

The function returns NULL if no register class can be found.

Definition at line 318 of file TargetRegisterInfo.cpp.

References assert(), composeSubRegIndices(), firstCommonClass(), getRegSizeInBits(), llvm::SuperRegClassIterator::isValid(), and std::swap().

Referenced by isCrossCopy(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

◆ getConstrainedRegClassForOperand()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand MO,
const MachineRegisterInfo MRI 
) const
inlinevirtual

Definition at line 1088 of file TargetRegisterInfo.h.

Referenced by llvm::constrainOperandRegClass().

◆ getCoveringLanes()

LaneBitmask llvm::TargetRegisterInfo::getCoveringLanes ( ) const
inline

The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.

The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.

On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.

This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:

Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);

If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.

Definition at line 412 of file TargetRegisterInfo.h.

◆ getCoveringSubRegIndexes()

bool TargetRegisterInfo::getCoveringSubRegIndexes ( const MachineRegisterInfo MRI,
const TargetRegisterClass RC,
LaneBitmask  LaneMask,
SmallVectorImpl< unsigned > &  Indexes 
) const

Try to find one or more subregister indexes to cover LaneMask.

If this is possible, returns true and appends the best matching set of indexes to Indexes. If this is not possible, returns false.

Definition at line 523 of file TargetRegisterInfo.cpp.

References llvm::LaneBitmask::any(), llvm::LegalityPredicates::any(), E, llvm::LaneBitmask::getNumLanes(), llvm::MCRegisterInfo::getNumSubRegIndices(), getSubClassWithSubReg(), getSubRegIndexLaneMask(), and llvm::min().

◆ getCrossCopyRegClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass RC) const
inlinevirtual

Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Definition at line 766 of file TargetRegisterInfo.h.

◆ getCSRFirstUseCost()

virtual unsigned llvm::TargetRegisterInfo::getCSRFirstUseCost ( ) const
inlinevirtual

Allow the target to override the cost of using a callee-saved register for the first time.

Default value of 0 means we will use a callee-saved register if it is available.

Definition at line 881 of file TargetRegisterInfo.h.

◆ getCustomEHPadPreservedMask()

virtual const uint32_t* llvm::TargetRegisterInfo::getCustomEHPadPreservedMask ( const MachineFunction MF) const
inlinevirtual

Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is needed.

Definition at line 494 of file TargetRegisterInfo.h.

Referenced by llvm::MIRParserImpl::setupRegisterInfo().

◆ getFrameIndexInstrOffset()

virtual int64_t llvm::TargetRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
inlinevirtual

Get the offset from the referenced frame index in the instruction, if there is one.

Definition at line 944 of file TargetRegisterInfo.h.

◆ getFrameRegister()

virtual Register llvm::TargetRegisterInfo::getFrameRegister ( const MachineFunction MF) const
pure virtual

◆ getIntraCallClobberedRegs()

virtual ArrayRef<MCPhysReg> llvm::TargetRegisterInfo::getIntraCallClobberedRegs ( const MachineFunction MF) const
inlinevirtual

Return a list of all of the registers which are clobbered "inside" a call to the given function.

For example, these might be needed for PLT sequences of long-branch veneers.

Definition at line 507 of file TargetRegisterInfo.h.

◆ getLargestLegalSuperClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass RC,
const MachineFunction  
) const
inlinevirtual

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size.

The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.

The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.

Definition at line 775 of file TargetRegisterInfo.h.

Referenced by llvm::PPCRegisterInfo::getLargestLegalSuperClass(), and llvm::MachineRegisterInfo::recomputeRegClass().

◆ getMatchingSuperReg()

MCRegister llvm::TargetRegisterInfo::getMatchingSuperReg ( MCRegister  Reg,
unsigned  SubIdx,
const TargetRegisterClass RC 
) const
inline

◆ getMatchingSuperRegClass()

const TargetRegisterClass * TargetRegisterInfo::getMatchingSuperRegClass ( const TargetRegisterClass A,
const TargetRegisterClass B,
unsigned  Idx 
) const
virtual

Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.

TableGen will synthesize missing A sub-classes.

Definition at line 302 of file TargetRegisterInfo.cpp.

References assert(), B, firstCommonClass(), and llvm::SuperRegClassIterator::isValid().

Referenced by llvm::MachineInstr::getRegClassConstraintEffect(), isCrossCopy(), llvm::isOfRegClass(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().

◆ getMinimalPhysRegClass()

const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass ( MCRegister  Reg,
MVT  VT = MVT::Other 
) const

Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

Definition at line 211 of file TargetRegisterInfo.cpp.

References assert(), llvm::TargetRegisterClass::hasSubClass(), llvm::Register::isPhysicalRegister(), isTypeLegalForClass(), llvm::MVT::Other, and regclasses().

Referenced by llvm::DwarfExpression::addMachineReg(), llvm::SystemZFrameLowering::assignCalleeSavedSpillSlots(), llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), canRenameUpToDef(), CheckForPhysRegDependency(), llvm::WebAssemblyInstrInfo::copyPhysReg(), llvm::MipsFrameLowering::estimateStackSize(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), getRegisterSize(), getRegSizeInBits(), insertCSRRestores(), insertCSRSaves(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::SITargetLowering::LowerFormalArguments(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::rdf::CopyPropagation::run(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), and tryToFindRegisterToRename().

◆ getMinimalPhysRegClassLLT()

const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClassLLT ( MCRegister  Reg,
LLT  Ty = LLT() 
) const

Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

If there is no register class compatible with the given type, returns nullptr.

Definition at line 229 of file TargetRegisterInfo.cpp.

References assert(), llvm::TargetRegisterClass::hasSubClass(), llvm::Register::isPhysicalRegister(), isTypeLegalForClass(), llvm::LLT::isValid(), and regclasses().

◆ getNoPreservedMask()

virtual const uint32_t* llvm::TargetRegisterInfo::getNoPreservedMask ( ) const
inlinevirtual

Return a register mask that clobbers everything.

Definition at line 499 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::MachineBasicBlock::getBeginClobberMask(), and llvm::MachineBasicBlock::getEndClobberMask().

◆ getNumRegClasses()

unsigned llvm::TargetRegisterInfo::getNumRegClasses ( ) const
inline

◆ getNumRegPressureSets()

virtual unsigned llvm::TargetRegisterInfo::getNumRegPressureSets ( ) const
pure virtual

◆ getOffsetOpcodes()

void TargetRegisterInfo::getOffsetOpcodes ( const StackOffset Offset,
SmallVectorImpl< uint64_t > &  Ops 
) const
virtual

Gets the DWARF expression opcodes for Offset.

Definition at line 642 of file TargetRegisterInfo.cpp.

References llvm::DIExpression::appendOffset(), assert(), and Offset.

Referenced by prependOffsetExpression().

◆ getPointerRegClass()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
inlinevirtual

Returns a TargetRegisterClass used for pointer values.

If a target supports multiple different pointer register classes, kind specifies which one is indicated.

Definition at line 757 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyFrameLowering::emitEpilogue(), llvm::WebAssemblyFrameLowering::emitPrologue(), llvm::TargetInstrInfo::getRegClass(), and llvm::MachineInstr::getRegClassConstraint().

◆ getRegAllocationHints()

bool TargetRegisterInfo::getRegAllocationHints ( Register  VirtReg,
ArrayRef< MCPhysReg Order,
SmallVectorImpl< MCPhysReg > &  Hints,
const MachineFunction MF,
const VirtRegMap VRM = nullptr,
const LiveRegMatrix Matrix = nullptr 
) const
virtual

Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg.

These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling.

The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.

The default implementation of this function will only add target independent register allocation hints. Targets that override this function should typically call this default implementation as well and expect to see generic copy hints added.

Definition at line 421 of file TargetRegisterInfo.cpp.

References llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::SmallSet< T, N, C >::insert(), llvm::is_contained(), llvm::Register::isPhysical(), llvm::MachineRegisterInfo::isReserved(), llvm::Register::isVirtual(), MRI, and Reg.

Referenced by llvm::AllocationOrder::create(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), and llvm::ARMBaseRegisterInfo::getRegAllocationHints().

◆ getRegAsmName()

virtual StringRef llvm::TargetRegisterInfo::getRegAsmName ( MCRegister  Reg) const
inlinevirtual

Return the assembly name for Reg.

Definition at line 1013 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::getName(), and Reg.

Referenced by llvm::AArch64InstrInfo::copyPhysReg(), and llvm::TargetLowering::getRegForInlineAsmConstraint().

◆ getRegClass()

const TargetRegisterClass* llvm::TargetRegisterInfo::getRegClass ( unsigned  i) const
inline

◆ getRegClassInfo()

const RegClassInfo& llvm::TargetRegisterInfo::getRegClassInfo ( const TargetRegisterClass RC) const
inlineprotected

◆ getRegClassName()

const char* llvm::TargetRegisterInfo::getRegClassName ( const TargetRegisterClass Class) const
inline

◆ getRegClassPressureSets()

virtual const int* llvm::TargetRegisterInfo::getRegClassPressureSets ( const TargetRegisterClass RC) const
pure virtual

Get the dimensions of register pressure impacted by this register class.

Returns a -1 terminated array of pressure set IDs.

Referenced by llvm::RegisterClassInfo::computePSetLimit().

◆ getRegClassWeight()

virtual const RegClassWeight& llvm::TargetRegisterInfo::getRegClassWeight ( const TargetRegisterClass RC) const
pure virtual

Get the weight in units of pressure for this register class.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), and llvm::ARMBaseRegisterInfo::shouldCoalesce().

◆ getRegisterCosts()

ArrayRef<uint8_t> llvm::TargetRegisterInfo::getRegisterCosts ( const MachineFunction MF) const
inline

Get a list of cost values for all registers that correspond to the index returned by RegisterCostTableIndex.

Definition at line 350 of file TargetRegisterInfo.h.

References assert(), llvm::TargetRegisterInfoDesc::CostPerUse, llvm::MCRegisterInfo::getNumRegs(), getRegisterCostTableIndex(), and llvm::makeArrayRef().

Referenced by llvm::RegisterClassInfo::runOnMachineFunction().

◆ getRegisterCostTableIndex()

virtual unsigned llvm::TargetRegisterInfo::getRegisterCostTableIndex ( const MachineFunction MF) const
inlineprotectedvirtual

Return the register cost table index.

This implementation is sufficient for most architectures and can be overriden by targets in case there are multiple cost values associated with each register.

Definition at line 683 of file TargetRegisterInfo.h.

Referenced by getRegisterCosts().

◆ getRegMaskNames()

virtual ArrayRef<const char *> llvm::TargetRegisterInfo::getRegMaskNames ( ) const
pure virtual

Referenced by llvm::MIPrinter::print().

◆ getRegMasks()

virtual ArrayRef<const uint32_t *> llvm::TargetRegisterInfo::getRegMasks ( ) const
pure virtual

Return all the call-preserved register masks defined for this target.

Referenced by llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo().

◆ getRegPressureLimit()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
inlinevirtual

Return the register pressure "high water mark" for the specific register class.

The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.

Note: this is the old register pressure model that relies on a manually specified representative register class per value type.

Definition at line 788 of file TargetRegisterInfo.h.

Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue().

◆ getRegPressureSetLimit()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
pure virtual

Get the register unit pressure limit for this dimension.

This limit must be adjusted dynamically for reserved registers.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), and llvm::PPCInstrInfo::shouldReduceRegisterPressure().

◆ getRegPressureSetName()

virtual const char* llvm::TargetRegisterInfo::getRegPressureSetName ( unsigned  Idx) const
pure virtual

◆ getRegPressureSetScore()

virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetScore ( const MachineFunction MF,
unsigned  PSetID 
) const
inlinevirtual

Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another.

The scheduler will prefer increasing the register pressure of the set which returns the largest value for this function.

Definition at line 797 of file TargetRegisterInfo.h.

Referenced by llvm::tryPressure().

◆ getRegSizeInBits() [1/2]

unsigned llvm::TargetRegisterInfo::getRegSizeInBits ( const TargetRegisterClass RC) const
inline

◆ getRegSizeInBits() [2/2]

unsigned TargetRegisterInfo::getRegSizeInBits ( Register  Reg,
const MachineRegisterInfo MRI 
) const

◆ getRegUnitPressureSets()

virtual const int* llvm::TargetRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
pure virtual

Get the dimensions of register pressure impacted by this register unit.

Returns a -1 terminated array of pressure set IDs.

◆ getRegUnitWeight()

virtual unsigned llvm::TargetRegisterInfo::getRegUnitWeight ( unsigned  RegUnit) const
pure virtual

Get the weight in units of pressure for this register unit.

◆ getReservedRegs()

virtual BitVector llvm::TargetRegisterInfo::getReservedRegs ( const MachineFunction MF) const
pure virtual

Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g.

stack pointer, return address. A reserved register:

  • is not allocatable
  • is considered always live
  • is ignored by liveness tracking It is often necessary to reserve the super registers of a reserved register as well, to avoid them getting allocated indirectly. You may use markSuperRegs() and checkAllSuperRegsMarked() in this case.

Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), and llvm::MachineRegisterInfo::freezeReservedRegs().

◆ getSpillAlign()

Align llvm::TargetRegisterInfo::getSpillAlign ( const TargetRegisterClass RC) const
inline

◆ getSpillSize()

unsigned llvm::TargetRegisterInfo::getSpillSize ( const TargetRegisterClass RC) const
inline

Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC.

Definition at line 280 of file TargetRegisterInfo.h.

References getRegClassInfo(), and llvm::TargetRegisterInfo::RegClassInfo::SpillSize.

Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::SystemZFrameLowering::assignCalleeSavedSpillSlots(), llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), getRegisterSize(), llvm::SIMachineFunctionInfo::getScavengeFI(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::HexagonInstrInfo::isValidOffset(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::SITargetLowering::passSpecialInputs(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getSubClassWithSubReg()

virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getSubClassWithSubReg ( const TargetRegisterClass RC,
unsigned  Idx 
) const
inlinevirtual

Returns the largest legal sub-class of RC that supports the sub-register index Idx.

If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.

TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.

TableGen will synthesize missing RC sub-classes.

Definition at line 611 of file TargetRegisterInfo.h.

References assert().

Referenced by llvm::FastISel::fastEmitInst_extractsubreg(), getCoveringSubRegIndexes(), and llvm::MachineInstr::getRegClassConstraintEffect().

◆ getSubReg()

MCRegister llvm::TargetRegisterInfo::getSubReg ( MCRegister  Reg,
unsigned  Idx 
) const
inline

◆ getSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::getSubRegIndexLaneMask ( unsigned  SubIdx) const
inline

◆ getSubRegIndexName()

const char* llvm::TargetRegisterInfo::getSubRegIndexName ( unsigned  SubIdx) const
inline

Return the human-readable symbolic target-specific name for the specified SubRegIndex.

Definition at line 365 of file TargetRegisterInfo.h.

References assert(), and llvm::MCRegisterInfo::getNumSubRegIndices().

Referenced by llvm::MachineOperand::print(), llvm::printReg(), and llvm::MachineOperand::printSubRegIdx().

◆ hasRegUnit()

bool llvm::TargetRegisterInfo::hasRegUnit ( MCRegister  Reg,
Register  RegUnit 
) const
inline

Returns true if Reg contains RegUnit.

Definition at line 433 of file TargetRegisterInfo.h.

References llvm::MCRegisterInfo::DiffListIterator::isValid(), and Reg.

◆ hasReservedSpillSlot()

virtual bool llvm::TargetRegisterInfo::hasReservedSpillSlot ( const MachineFunction MF,
Register  Reg,
int FrameIdx 
) const
inlinevirtual

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register.

e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after determineCalleeSaves().

Definition at line 920 of file TargetRegisterInfo.h.

Referenced by assignCalleeSavedSpillSlots().

◆ hasStackRealignment()

bool llvm::TargetRegisterInfo::hasStackRealignment ( const MachineFunction MF) const
inline

◆ isAsmClobberable()

virtual bool llvm::TargetRegisterInfo::isAsmClobberable ( const MachineFunction MF,
MCRegister  PhysReg 
) const
inlinevirtual

Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement.

Definition at line 533 of file TargetRegisterInfo.h.

◆ isCalleeSavedPhysReg()

bool TargetRegisterInfo::isCalleeSavedPhysReg ( MCRegister  PhysReg,
const MachineFunction MF 
) const
virtual

This is a wrapper around getCallPreservedMask().

Return true if the register is preserved after the call.

Definition at line 464 of file TargetRegisterInfo.cpp.

References assert(), llvm::Function::getCallingConv(), getCallPreservedMask(), llvm::MachineFunction::getFunction(), and llvm::Register::isPhysicalRegister().

Referenced by interpretValues().

◆ isCallerPreservedPhysReg()

virtual bool llvm::TargetRegisterInfo::isCallerPreservedPhysReg ( MCRegister  PhysReg,
const MachineFunction MF 
) const
inlinevirtual

Physical registers that may be modified within a function but are guaranteed to be restored before any uses.

This is useful for targets that have call sequences where a GOT register may be updated by the caller prior to a call and is guaranteed to be restored (also by the caller) after the call.

Definition at line 558 of file TargetRegisterInfo.h.

Referenced by isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), isInvariantStore(), and llvm::MachineLoop::isLoopInvariant().

◆ isConstantPhysReg()

virtual bool llvm::TargetRegisterInfo::isConstantPhysReg ( MCRegister  PhysReg) const
inlinevirtual

Returns true if PhysReg is unallocatable and constant throughout the function.

Used by MachineRegisterInfo::isConstantPhysReg().

Definition at line 546 of file TargetRegisterInfo.h.

Referenced by llvm::MachineRegisterInfo::isConstantPhysReg(), and llvm::MachineFunction::salvageCopySSA().

◆ isDivergentRegClass()

virtual bool llvm::TargetRegisterInfo::isDivergentRegClass ( const TargetRegisterClass RC) const
inlinevirtual

Returns true if the register class is considered divergent.

Definition at line 549 of file TargetRegisterInfo.h.

◆ isFrameOffsetLegal()

virtual bool llvm::TargetRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
inlinevirtual

Determine whether a given base register plus offset immediate is encodable to resolve a frame index.

Definition at line 975 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by lookupCandidateBaseReg().

◆ isInAllocatableClass()

bool llvm::TargetRegisterInfo::isInAllocatableClass ( MCRegister  RegNo) const
inline

Return true if the register is in the allocation of any register class.

Definition at line 359 of file TargetRegisterInfo.h.

References llvm::TargetRegisterInfoDesc::InAllocatableClass.

Referenced by llvm::MachineRegisterInfo::isAllocatable().

◆ isInlineAsmReadOnlyReg()

virtual bool llvm::TargetRegisterInfo::isInlineAsmReadOnlyReg ( const MachineFunction MF,
unsigned  PhysReg 
) const
inlinevirtual

Returns true if PhysReg cannot be written to in inline asm statements.

Definition at line 539 of file TargetRegisterInfo.h.

◆ isTypeLegalForClass() [1/2]

bool llvm::TargetRegisterInfo::isTypeLegalForClass ( const TargetRegisterClass RC,
LLT  T 
) const
inline

Return true if the given TargetRegisterClass is compatible with LLT T.

Definition at line 299 of file TargetRegisterInfo.h.

References I, legalclasstypes_begin(), llvm::MVT::Other, T, and llvm::MVT::Untyped.

◆ isTypeLegalForClass() [2/2]

bool llvm::TargetRegisterInfo::isTypeLegalForClass ( const TargetRegisterClass RC,
MVT  T 
) const
inline

◆ legalclasstypes_begin()

vt_iterator llvm::TargetRegisterInfo::legalclasstypes_begin ( const TargetRegisterClass RC) const
inline

Loop over all of the value types that can be represented by values in the given register class.

Definition at line 313 of file TargetRegisterInfo.h.

References getRegClassInfo(), and llvm::TargetRegisterInfo::RegClassInfo::VTList.

Referenced by GetRegistersForValue(), getRegTy(), llvm::TargetLoweringBase::isLegalRC(), isTypeLegalForClass(), legalclasstypes_end(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ legalclasstypes_end()

vt_iterator llvm::TargetRegisterInfo::legalclasstypes_end ( const TargetRegisterClass RC) const
inline

Definition at line 317 of file TargetRegisterInfo.h.

References I, legalclasstypes_begin(), and llvm::MVT::Other.

Referenced by getRegTy().

◆ lookThruCopyLike()

Register TargetRegisterInfo::lookThruCopyLike ( Register  SrcReg,
const MachineRegisterInfo MRI 
) const
virtual

Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register.

If a physical register is encountered, we stop the search.

Definition at line 595 of file TargetRegisterInfo.cpp.

References assert(), llvm::MachineRegisterInfo::getVRegDef(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::PPCInstrInfo::getFMAPatterns(), isInvariantStore(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ lookThruSingleUseCopyChain()

Register TargetRegisterInfo::lookThruSingleUseCopyChain ( Register  SrcReg,
const MachineRegisterInfo MRI 
) const
virtual

Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register.

If a physical register is encountered, we stop the search. Return the original SrcReg if all the definitions in the chain only have one user and not a physical register.

Definition at line 617 of file TargetRegisterInfo.cpp.

References assert(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by llvm::PPCInstrInfo::getFMAPatterns().

◆ markSuperRegs()

void TargetRegisterInfo::markSuperRegs ( BitVector RegisterSet,
MCRegister  Reg 
) const

Mark a register and all its aliases as reserved in the given set.

Definition at line 79 of file TargetRegisterInfo.cpp.

References llvm::MCRegisterInfo::DiffListIterator::isValid(), and Reg.

◆ materializeFrameBaseRegister()

virtual Register llvm::TargetRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
int  FrameIdx,
int64_t  Offset 
) const
inlinevirtual

Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.

Return materialized frame pointer.

Definition at line 959 of file TargetRegisterInfo.h.

References llvm_unreachable.

◆ needsFrameBaseReg()

virtual bool llvm::TargetRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
inlinevirtual

Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Definition at line 953 of file TargetRegisterInfo.h.

◆ prependOffsetExpression()

DIExpression * TargetRegisterInfo::prependOffsetExpression ( const DIExpression Expr,
unsigned  PrependFlags,
const StackOffset Offset 
) const

◆ regclass_begin()

regclass_iterator llvm::TargetRegisterInfo::regclass_begin ( ) const
inline

Register class iterators.

Definition at line 725 of file TargetRegisterInfo.h.

Referenced by getNumRegClasses(), and regclasses().

◆ regclass_end()

regclass_iterator llvm::TargetRegisterInfo::regclass_end ( ) const
inline

Definition at line 726 of file TargetRegisterInfo.h.

Referenced by getNumRegClasses(), and regclasses().

◆ regclasses()

iterator_range<regclass_iterator> llvm::TargetRegisterInfo::regclasses ( ) const
inline

◆ regmaskSubsetEqual()

bool TargetRegisterInfo::regmaskSubsetEqual ( const uint32_t mask0,
const uint32_t mask1 
) const

Return true if all bits that are set in mask mask0 are also set in mask1.

Definition at line 491 of file TargetRegisterInfo.cpp.

References llvm::MCRegisterInfo::getNumRegs(), I, and N.

Referenced by llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(), and llvm::SITargetLowering::isEligibleForTailCallOptimization().

◆ regsOverlap()

bool llvm::TargetRegisterInfo::regsOverlap ( Register  regA,
Register  regB 
) const
inline

◆ requiresFrameIndexReplacementScavenging()

virtual bool llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging.

Definition at line 903 of file TargetRegisterInfo.h.

◆ requiresFrameIndexScavenging()

virtual bool llvm::TargetRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants.

Definition at line 897 of file TargetRegisterInfo.h.

◆ requiresRegisterScavenging()

virtual bool llvm::TargetRegisterInfo::requiresRegisterScavenging ( const MachineFunction MF) const
inlinevirtual

Returns true if the target requires (and can make use of) the register scavenger.

Definition at line 885 of file TargetRegisterInfo.h.

◆ requiresVirtualBaseRegisters()

virtual bool llvm::TargetRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction MF) const
inlinevirtual

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.

Definition at line 910 of file TargetRegisterInfo.h.

Referenced by INITIALIZE_PASS().

◆ resolveFrameIndex()

virtual void llvm::TargetRegisterInfo::resolveFrameIndex ( MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
inlinevirtual

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.

Definition at line 968 of file TargetRegisterInfo.h.

References llvm_unreachable.

◆ reverseComposeSubRegIndexLaneMask()

LaneBitmask llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask ( unsigned  IdxA,
LaneBitmask  LaneMask 
) const
inline

Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA.

This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a valie lane mask (no invalid bits set) the following holds: X0 = composeSubRegIndexLaneMask(Idx, Mask) X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) => X1 == Mask

Definition at line 652 of file TargetRegisterInfo.h.

References reverseComposeSubRegIndexLaneMaskImpl().

Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo().

◆ reverseComposeSubRegIndexLaneMaskImpl()

virtual LaneBitmask llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl ( unsigned  ,
LaneBitmask   
) const
inlineprotectedvirtual

Definition at line 675 of file TargetRegisterInfo.h.

References llvm_unreachable.

Referenced by reverseComposeSubRegIndexLaneMask().

◆ reverseLocalAssignment()

virtual bool llvm::TargetRegisterInfo::reverseLocalAssignment ( ) const
inlinevirtual

Allow the target to reverse allocation order of local live ranges.

This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.

Definition at line 872 of file TargetRegisterInfo.h.

◆ saveScavengerRegister()

virtual bool llvm::TargetRegisterInfo::saveScavengerRegister ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock::iterator UseMI,
const TargetRegisterClass RC,
Register  Reg 
) const
inlinevirtual

Spill the register so it can be used by the register scavenger.

Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.

Definition at line 993 of file TargetRegisterInfo.h.

◆ shouldCoalesce()

virtual bool llvm::TargetRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
inlinevirtual

Subtarget Hooks.

SrcRC and DstRC will be morphed into NewRC if this returns true.

Definition at line 1027 of file TargetRegisterInfo.h.

Referenced by llvm::AVRRegisterInfo::shouldCoalesce().

◆ shouldRealignStack()

bool TargetRegisterInfo::shouldRealignStack ( const MachineFunction MF) const
virtual

◆ shouldRegionSplitForVirtReg()

bool TargetRegisterInfo::shouldRegionSplitForVirtReg ( const MachineFunction MF,
const LiveInterval VirtReg 
) const
virtual

Region split has a high compile time cost especially for large live range.

This method is used to decide whether or not VirtReg should go through this expensive splitting heuristic.

Definition at line 68 of file TargetRegisterInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), HugeSizeForSplit, MI, MRI, llvm::LiveInterval::reg(), llvm::LiveRange::size(), and TII.

◆ shouldRewriteCopySrc()

bool TargetRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass DefRC,
unsigned  DefSubReg,
const TargetRegisterClass SrcRC,
unsigned  SrcSubReg 
) const
virtual

◆ shouldUseDeferredSpillingForVirtReg()

virtual bool llvm::TargetRegisterInfo::shouldUseDeferredSpillingForVirtReg ( const MachineFunction MF,
const LiveInterval VirtReg 
) const
inlinevirtual

Deferred spilling delays the spill insertion of a virtual register after every other allocation.

By deferring the spilling, it is sometimes possible to eliminate that spilling altogether because something else could have been eliminated, thus leaving some space for the virtual register. However, this comes with a compile time impact because it adds one more stage to the greedy register allocator. This method is used to decide whether VirtReg should use the deferred spilling stage instead of being spilled right away.

Definition at line 1067 of file TargetRegisterInfo.h.

◆ shouldUseLastChanceRecoloringForVirtReg()

virtual bool llvm::TargetRegisterInfo::shouldUseLastChanceRecoloringForVirtReg ( const MachineFunction MF,
const LiveInterval VirtReg 
) const
inlinevirtual

Last chance recoloring has a high compile time cost especially for targets with a lot of registers.

This method is used to decide whether or not VirtReg should go through this expensive heuristic. When this target hook is hit, by returning false, there is a high chance that the register allocation will fail altogether (usually with "ran out of registers"). That said, this error usually points to another problem in the optimization pipeline.

Definition at line 1052 of file TargetRegisterInfo.h.

◆ trackLivenessAfterRegAlloc()

virtual bool llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction MF) const
inlinevirtual

Returns true if the live-ins should be tracked after register allocation.

Definition at line 926 of file TargetRegisterInfo.h.

Referenced by llvm::BranchFolder::OptimizeFunction().

◆ updateRegAllocHint()

virtual void llvm::TargetRegisterInfo::updateRegAllocHint ( Register  Reg,
Register  NewReg,
MachineFunction MF 
) const
inlinevirtual

A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g.

coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.

Definition at line 858 of file TargetRegisterInfo.h.

◆ useFPForScavengingIndex()

virtual bool llvm::TargetRegisterInfo::useFPForScavengingIndex ( const MachineFunction MF) const
inlinevirtual

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.

Definition at line 891 of file TargetRegisterInfo.h.


The documentation for this class was generated from the following files: